4326 results about "Bit line" patented technology

The invention discloses a FeFET-based XNOR calculation unit, an array and a working method of the FeFET-based XNOR calculation unit. The unit comprises a FeFET transistor F1, a FeFET transistor F2 and an NMOS transistor M0. The source electrode of the F1 is connected to a bit line BL, the source electrode of the F2 is connected to a bit line BLB, the grid electrode of the F2 and the grid electrode of the F1 are jointly connected to a word line WL, and the drain electrode of the F2 and the drain electrode of the F1 are jointly connected to a node X. The grid electrode of the M0 is connected with the node X, the drain electrode is grounded, and the source electrode is connected to the shared charge line Scl. F1 and F2 are configured to store a weight bit, and by applying a read voltage to WL and applying a voltage corresponding to an input bit to BL and BLB, a voltage level of Scl outputs an XNOR logic calculation result. The array includes a plurality of XNOR computing units arranged in m rows * n columns. WL and Scl ends of each unit are shared in each column, and BL and BLB are shared in each row. According to the invention, the control peripheral circuit of the array word line is simplified, the variability of current is effectively avoided, and the problems of hardware overhead and the like are effectively solved.

A non-volatile memory device for performing compute in memory operations for a neural network uses a three dimensional NAND architecture. Multi-bit weight values are stored encoded as sets of threshold voltages for sets of memory cells. A weight value is stored in multiple memory cells on the same word line and connected between a bit line and a source line, each of the memory cells programmed to one of multiple threshold voltages. When multiplying an input value with the weight value, the word line is biased so that, for at least one of the threshold voltages, the memory cell will be in the linear operation region. Input values are encoded as a set of one or more voltage levels applied to a corresponding set of bit lines, each bit line connected memory cells also storing the weight value, connected to the word line, and connected to the source line.

A high-density ferroelectric memory, and a preparation method therefor and an application thereof, belonging to the field of semiconductor memories. In the memory, multiple memory cells are arranged in an array, and the two sides of the array of the memory cells are connected to substantially orthogonal word lines and bit lines, the memory cell of the present invention adopts a stacked structure of a top electrode, a resistive switching dielectric layer, an intermediate metal layer, a ferroelectric dielectric layer, and a bottom electrode, which is electrically equivalent to a ferroelectric capacitor and a resistive switching selector connected in series; the voltage division of the distributed ferroelectric capacitor in the unselected cells is reduced by regulating the RC delay of the memory cell, so that its disturbance is reduced; and the capacitance value of the ferroelectric capacitor is stable, and the influence of the disturbance voltage can be effectively reduced by RC regulation. The storage window of the memory is improved and the bit error rate is reduced, without increasing additional area overhead.

Embodiments of the present disclosure relates to an integrated circuit including an array of memory cells having the word lines and high-voltage power lines positioned on one side of the transistors and the bit lines and low voltage power lines positioned on the other side of the transistor. The memory cells according to the present disclosure also improve routing efficiency, thus, removing bottleneck of further scaling both SRAM cell.

The invention discloses a 10T-SRAM (10 T-Static Random Access Memory) in-memory multiplication unit, an in-memory operation unit and a circuit, and relates to the technical field of integrated circuit design. The invention provides a 10T-SRAM in-memory multiplication unit consisting of a 6T-SRAM part and an MAC (Media Access Control) calculation part consisting of four NMOS (N-channel Metal Oxide Semiconductor) tubes, on one hand, a 1bit weight is stored in the 6T-SRAM part, on the other hand, a 4bit unsigned number is divided into high 2bit input X [3: 2] and low 2bit input X [1: 0], and the high 2bit input X [3: 2] and the low 2bit input X [1: 0] are respectively input into the MAC calculation part, so that the multiplication of the 4bit unsigned number and the 1bit weight is realized in an in-memory calculation mode, and the calculation efficiency is improved. And the voltage drop is reflected through bit lines RBLN and RBLP. The in-memory multiplication circuit solves the problem that the existing in-memory multiplication circuit has few input bits and cannot meet the calculation requirement.

Three-dimensional (3D) memory devices and fabricating methods are provided. In some implementations, a disclosed semiconductor device is a memory device and comprises an array of memory cells in an array region, word lines extending parallel in a first lateral direction, bit lines extending parallel in a second lateral direction different from the first lateral direction, and interconnection structures located within the array region and coupled with the bit lines, and arranged in staggered rows along the first lateral direction.

A data storage device includes a bad block management system. The bad block management system detects a grown bad block of the data storage device. When a grown bad block is detected, the bad block management system initiates a manual block write process on the wordlines associated with the grown bad block. The manual block write process includes programming the wordlines of the grown bad block in a particular state and with a voltage that closes a leakage path between a bit line associated with the grown bad block and a ground line or a ground path associated with the grown bad block.

The invention relates to the technical field of semiconductors, and provides a semiconductor device and a manufacturing method thereof. The method is used for solving the technical problem of how to reduce bit line manufacturing difficulty. The manufacturing method comprises the following steps: providing a substrate, wherein the substrate comprises a plurality of active layers and accommodating spaces for separating the active layers; the active layer comprises a first part and a second part; the size of the second part in the first direction is gradually reduced along the direction from the first part to the second part; forming a filling structure surrounding the first part and a first sacrificial layer covering the filling structure in the accommodating space; the first sacrificial layer protrudes from the surface of the filling structure; the rest accommodating space exposes a plurality of second parts arranged along the second direction; and forming a bit line structure in the remaining accommodating space. Therefore, a self-aligned bit line can be formed, a high-difficulty and high-aspect-ratio bit line etching process is avoided, and the bit line manufacturing difficulty is reduced.

The utility model provides a semiconductor device, which is applied to the technical field of semiconductors. According to the utility model, by changing the width of the interval between the adjacent bit line structures, the widths of the connecting pad structures formed between the different adjacent bit line structures are different in the horizontal direction, so that the positions of part of the second isolation structures are shifted, and the purpose of communicating part of the adjacent connecting pad structures is achieved.

The invention discloses a semiconductor structure and a preparation method thereof, and electronic equipment. The semiconductor structure comprises a substrate; the storage array is arranged on the substrate and comprises a plurality of storage units arranged in an array mode, each storage unit comprises a reading transistor and a writing transistor which are electrically connected with each other, and the reading transistor and the writing transistor are stacked in the first direction perpendicular to the surface of the substrate; the writing word line extends along the second direction and is electrically connected with the writing transistors in the plurality of storage units arranged along the second direction; the read word line extends along a second direction parallel to the surface of the substrate and is electrically connected with the read transistors in the plurality of memory cells arranged along the second direction; and the bit line extends along a third direction parallel to the surface of the substrate, the read transistors and the write transistors in the plurality of memory cells arranged along the third direction are electrically connected to the bit line together, and the third direction and the second direction intersect. The semiconductor structure can improve the integration density of the memory.

A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a substrate, a first bit line disposed on the substrate and extending along a first direction, a first word line disposed on the first bit line and extending along a second direction perpendicular to the first direction, a channel structure disposed on the first bit line and penetrating the first word line, and a trench capacitor disposed on the channel structure. The channel structure is separated from the first word line by a gate dielectric layer.

A semiconductor device may include a semiconductor substrate including a horizontal portion and a vertical portion protruding upward from the horizontal portion, a bit line on the semiconductor substrate and extending in a first direction parallel to a bottom surface of the semiconductor substrate, a word line on the bit line and extending in a second direction parallel to the bottom surface of the semiconductor substrate that is different from the first direction, a semiconductor pattern on the vertical portion of the semiconductor substrate and extending in a third direction perpendicular to the bottom surface of the semiconductor substrate, and a metal silicide pattern between the semiconductor pattern and the bit line. The semiconductor pattern may include a source / drain region adjacent to the bit line and a channel region on the source / drain region, and the metal silicide pattern may be in contact with the source / drain region and the bit line.

The present disclosure relates integrated chip structure. The integrated chip structure includes a memory array having a plurality of memory devices arranged in a plurality of rows and a plurality of columns. A word-line is coupled to a first set of the plurality of memory devices disposed within a first row of the plurality of rows. A bit-line is coupled to a second set of the plurality of memory devices disposed within a first column of the plurality of columns. A local interconnect extends in parallel to the bit-line and is coupled to the bit-line and two or more of the second set of the plurality of memory devices. The local interconnect is coupled to the bit-line by a plurality of interconnect vias that are between the local interconnect and the bit-line.

A three-dimensional semiconductor device includes a semiconductor pattern spaced apart from a substrate, and extending along a first direction parallel to a lower surface of the substrate, a word line surrounding the semiconductor pattern, and extending along a second direction parallel to the lower surface of the substrate, and crossing the first direction, and a bit line extending along a first side surface of the semiconductor pattern along a third direction perpendicular to the lower surface of the substrate, wherein the word line includes a first gate electrode, a second gate electrode on a first side surface of the first gate electrode, and a third gate electrode on a second surface opposite to the first side surface of the first gate electrode, and a work function of each of the second and third gate electrodes is smaller than a work function of the first gate electrode.

The invention discloses a floating-point number index maximum value searching circuit and an in-memory computing chip. The searching circuit comprises an SRAM (Static Random Access Memory) unit matrix which comprises a plurality of rows and columns of SRAM units, wherein each unit comprises NMOS (N-channel Metal Oxide Semiconductor) tubes N1-N5 and PMOS (P-channel Metal Oxide Semiconductor) tubes P1 and P2; n1, N2, P1 and P2 are in reverse cross coupling to form a pair of storage nodes Q and QB; the grid electrode of the N5 is connected with a node QB; the grid electrode of the N3 in the ith row is connected with a word line WLLlt; igt; the grid electrode of the N4 is connected with a word line WLRlt; igt; ; the drain electrode of each column of N5 is connected in series with the source electrode of the next column of N5, and the source electrode of the first column of N5 is connected with a signal SELlt; igt; the N5 drain electrode of the last column is connected with a signal PRE; in the jth column, N3 is a corresponding node Q and a bit line BLlt; jgt; the transmission tube N4 is a corresponding node QB and a bit line BLBlt; jgt; and a transmission tube. According to the invention, the number of searching cycles is saved, the calculation time is shortened, the subsequent calculation amount is reduced, the efficiency is improved, the power consumption is reduced, and the defects of relatively high power consumption, complex hardware implementation, relatively long calculation delay and the like of an existing circuit are overcome.

The invention provides a storage and calculation integrated circuit which can be applied to the technical field of storage and calculation. The storage and calculation integrated circuit comprises a storage and calculation array which comprises a plurality of storage and calculation units; each storage and calculation unit is configured to receive an initial data signal through a connected complementary bit line, receive a weight signal through a weight line, and calculate the received initial data signal and the weight signal by using a voltage stored in the storage and calculation unit to obtain an intermediate data signal; a calculation circuit connected to the plurality of storage units and connected to a calculation line via a node; the calculation circuit is configured to apply the intermediate data signals output by the plurality of storage and calculation units to the calculation line through the node, and adjust the value of current flowing through the calculation line to obtain a target analog signal; and the quantization reading circuit is connected to the calculation line and is configured to convert the target analog signal into the target digital signal according to the quantization precision indicated by the quantization control signal under the control of the quantization control signal output by the quantization control end.

A data storage circuit includes a first memory array comprising a plurality of FeRAM memory units; a second memory array comprising a plurality of OxRAM memory units; each of the first and second memory arrays comprising: a plurality of word lines, a plurality of source lines and a plurality of bit lines; for each column each memory unit comprising: a memory cell having a first electrode and a second electrode connected to the source line associated to the memory unit; a selection transistor having a gate connected to the word line associated to the memory unit and placed in series with the memory cell between the source line and a bit line associated to of the memory unit; the data storage circuit comprising further: a data transfer stage configured to transfer data from a set of source FeRAM memory units having a common bit line to a target OxRAM unit by converting a read signal from the common bit line to a transfer voltage applied on a target line of the target OxRAM unit; the target line corresponding to the word line or the source line and having the same direction as the common bit line.

Systems, apparatuses, and methods are provided for forming air gaps between bit lines in a semiconductor device. In one aspect, a semiconductor device includes a memory array of memory cells and a bit line coupled to the memory array. Adjacent ones of the bit lines are separated by isolation regions in a first direction. The isolation region extends in a second direction perpendicular to the first direction. The isolation region includes an air gap. In the second direction, an end of the air gap is over an adjacent end of a bit line of the adjacent bit lines.

A semiconductor device includes a substrate, a shallow trench isolation, and a plurality of bit line structures. The substrate includes a plurality of active regions. The shallow trench isolation is arranged in the substrate and comprises a first insulating layer higher than the surface of the substrate and a second insulating layer lower than the surface of the substrate. The bit line structure is arranged on the substrate and at least comprises a conductive layer. At least one bit line structure crosses the active region and the first insulating layer and the second insulating layer of the shallow trench isolation, and is respectively provided with a first insulating stack structure, a second insulating stack structure and a third insulating stack structure. The first insulating stack structure, the second insulating stack structure, and the third insulating stack structure include top surfaces coplanar with each other and different stack materials. Therefore, the assembly efficiency of the bit line structure is improved, and the operation performance of the semiconductor device is optimized.

A semiconductor device may include a plurality of gate electrodes apart from each other in a vertical direction on a substrate; a plurality of channel structures penetrating the plurality of gate electrodes and extending in the vertical direction; and a plurality of bit lines arranged on and connected to the plurality of channel structures. The plurality of bit lines may include a plurality of lower bit lines and a plurality of upper bit lines at different vertical levels from each other to constitute at least two layers. The plurality of upper bit lines may be apart from each other in a first horizontal direction and extend in parallel with each other in a second horizontal direction perpendicular to the first horizontal direction. A lower expansion space may be defined between two lower bit lines adjacent to each other among the plurality of lower bit lines.

A three-dimensional (3D) memory device and a method of fabricating the same are provided. In some embodiments, the disclosed semiconductor device is a memory device and includes an array of memory cells in an array region, word lines extending in parallel in a first lateral direction, bit lines extending in parallel in a second lateral direction different from the first lateral direction; and interconnect structures in the array region and coupled with the bit lines, and arranged in staggered rows along the first lateral direction.

The embodiment of the invention relates to the field of memories, and provides a memory which comprises a first phase decoder, a first memory segment and a second memory segment, the first memory segment and the second memory segment are sequentially arranged along a first direction, and the first direction is a bit line extension direction; the first phase decoder is connected with a first storage section and outputs a plurality of first phase signals to the first storage section; the first phase decoder also outputs the plurality of first phase signals to the second memory segment. At least the area of the memory can be reduced.

The invention relates to a semiconductor device and a method of operating the same. A memory device includes a bit line control circuit and a row decoder. The bit line control circuit applies a verify pre-charge voltage to a program prohibition bit line after a program pulse period, the program prohibition bit line holding the program prohibition voltage during the program pulse period. The row decoder forms a channel in a string coupled between a program-prohibition bit line and a source line. A program prohibition voltage of the program prohibition bit line is discharged to the verification pre-charge voltage through the channel.

A three-dimensional (3D) memory device and a method of fabricating the same are provided. In some embodiments, the disclosed semiconductor device is a memory device and includes an array of memory cells in an array region, word lines extending in parallel in a first lateral direction, bit lines extending in parallel in a second lateral direction; and interconnect structures in the array region and coupled with the word lines, and arranged in staggered columns along the second lateral direction.

The invention discloses a semiconductor structure and a preparation method thereof, the semiconductor structure comprises bit lines, the bit lines extend in a first direction and are arranged at intervals in a second direction, and the first direction intersects with the second direction; the shielding lines are located between every two adjacent bit lines, extend in the first direction and are alternately arranged with the bit lines in the second direction; the active columns are located on the bit lines and are arranged in an array mode in the first direction and the second direction; the bit line contact structure is located between the bit line and the active column and is connected with the bit line and the active column, and the width of the bit line contact structure in the second direction is smaller than that of the bit line and the active column in the second direction. The shielding line can be connected with a direct-current power supply to form a conductive barrier, so that when one of the two adjacent bit lines 3 is powered on or powered off, the other bit line is less influenced or is not influenced.

A semiconductor memory device includes a bit line, a channel pattern including a horizontal channel portion on the bit line and a vertical channel portion vertically protruding from the horizontal channel portion, a word line on the horizontal channel portion and on a sidewall of the vertical channel portion, and a gate insulating pattern between the word line and the channel pattern. The channel pattern includes an oxide semiconductor and includes first, second, and third channel layers sequentially stacked. The first to third channel layers include a first metal, and the second channel layer further includes a second metal different from the first metal. At least a portion of the first channel layer contacts the bit line.

The invention relates to a multi-threshold 16T anti-radiation SRAM (Static Random Access Memory) storage unit circuit and a memory, a storage module in the circuit is of a bistable structure formed by two cross-coupled phase inverters formed by PMOS (P-channel Metal Oxide Semiconductor) transistors, and two storage nodes are formed; the redundant storage module adopts NMOS (N-channel metal oxide semiconductor) transistors to form a bistable structure, and two redundant nodes are formed to serve as redundant backups of the storage module; when the read-write operation control module reads or writes data, a word line is activated, and the data is read from the storage node and the redundant node or written into the storage node and the redundant node through the switched-on transistor; and the bit line driving module is used for driving the bit lines during reading and writing operations. According to the circuit, by introducing redundant nodes and a feedback mechanism, efficient resistance and recovery of single-particle and multi-node upset are achieved, the anti-radiation capacity is improved, the static noise margin, the read-write speed and the power consumption performance are optimized, and the circuit is suitable for the reliable data storage requirement in the high-radiation environment.

A memory device includes a memory cell array including ferroelectric memory cells, respectively disposed at intersections of wordlines and bitlines, and an analog-to-digital converter that is selectively connected to the bitlines and that outputs a digital value corresponding to charges applied through a bitline of the bitlines. The charges correspond to a piece of multi-bit data having digits stored in a portion of the ferroelectric memory cells that are connected to the bitline.

A semiconductor device may include: a plurality of word lines extending in a first direction; a plurality of bit lines extending in a second direction, a plurality of memory cells disposed at intersections of the plurality of word lines and the plurality of bit lines, respectively, each memory cell structured to include a variable resistance element configured to store data by exhibiting different resistance values and a selection element connected to the variable resistance element in series to selectively connect or disconnect the variable resistance element to the pair of the corresponding bit line and word line; and a boosting line connected to a portion of the selection element that is between one end of the selection element, which is connected to one of the word line and the bit line, and another end of the selection element, which is connected to the variable resistance element.

A memory device includes a bit line structure disposed over a semiconductor substrate, and a lower capacitor contact disposed in and extending above the semiconductor substrate. The lower capacitor contact includes polysilicon. The memory device also includes an upper capacitor contact disposed over the lower capacitor contact. The upper capacitor contact includes titanium nitride. The memory device further includes a first spacer layer disposed between the lower capacitor contact and the bit line structure and between the upper capacitor contact and the bit line structure. In addition, the memory device includes a capacitor disposed over the first spacer layer.