6159 results about "Bit line" patented technology

Apparatuses, systems, and methods for separate write enable signals for granular single pass metadata access operations. During an example write operation a memory may receive data bits and at least one metadata bit. A set of bit lines in a first column plane is selected and a first write enable signal is provided which enables writing data to each of that set of bit lines. A second set of bit lines in a second column plane is selected and a second write enable signal is provided which enables writing the at least one metadata bit to a selected subset of the second set of bit lines.

The invention discloses a FeFET-based XNOR calculation unit, an array and a working method of the FeFET-based XNOR calculation unit. The unit comprises a FeFET transistor F1, a FeFET transistor F2 and an NMOS transistor M0. The source electrode of the F1 is connected to a bit line BL, the source electrode of the F2 is connected to a bit line BLB, the grid electrode of the F2 and the grid electrode of the F1 are jointly connected to a word line WL, and the drain electrode of the F2 and the drain electrode of the F1 are jointly connected to a node X. The grid electrode of the M0 is connected with the node X, the drain electrode is grounded, and the source electrode is connected to the shared charge line Scl. F1 and F2 are configured to store a weight bit, and by applying a read voltage to WL and applying a voltage corresponding to an input bit to BL and BLB, a voltage level of Scl outputs an XNOR logic calculation result. The array includes a plurality of XNOR computing units arranged in m rows * n columns. WL and Scl ends of each unit are shared in each column, and BL and BLB are shared in each row. According to the invention, the control peripheral circuit of the array word line is simplified, the variability of current is effectively avoided, and the problems of hardware overhead and the like are effectively solved.

A non-volatile memory device for performing compute in memory operations for a neural network uses a three dimensional NOR architecture in which vertical NOR strings are formed of multiple memory cells connected in parallel between a source line and a bit line. Weights of the neural network are encoded as threshold voltages of the memory cells and activations are encoded as word line voltages applied to the memory cells of the NOR strings. The memory cells are operated in the subthreshold region, where the word line voltages are below the threshold voltages. The NOR structure naturally sums the resultant subthreshold currents of the individual memory cells to generate the product of the activations and the weights of the neural network by concurrently applying input voltages to multiple memory cells of a NOR string.

The present disclosure provides a method and an apparatus for operating an in-memory computing architecture applied to a neural network and a device, the method includes: generating a mono-pulse input signal based on discrete time coding; inputting the mono-pulse input signal into a memory array of the in-memory computing architecture to generate a bit line current signal corresponding to the memory array; and controlling a neuron circuit of the in-memory computing architecture to output a mono-pulse output signal based on discrete time coding according to the bit line current signal, wherein the mono-pulse output signal is configured as a mono-pulse input signal of a memory array of the next layer of neural network in the next in-memory computing cycle.

The present disclosure provides for transimpedance amplifiers for crossbar circuits. A crossbar circuit may include a plurality of bit lines intersecting with a plurality of word lines and a plurality of cross-point devices. Each of the plurality of the cross-point devices is connected to at least one of the word lines and at least one of the bit lines. The crossbar circuit may further include a transimpedance amplifier to generate an output voltage representative of a sum of currents flowing through a first bit line of the plurality of bit line. The transimpedance amplifier may include an operational amplifier, a current mirror circuit connected to an output of the operational amplifier, and one or more resistors connected to the current mirror circuit and a supply voltage.

In a semiconductor storage device, a first ROM cell includes a first nanosheet FET having a first nanosheet as the channel region, provided between a first bit line and a first ground power supply line. A second ROM cell includes a second nanosheet FET having a second nanosheet as the channel region, provided between a second bit line and a second ground power supply line. The face of the first nanosheet closer to the second nanosheet in the X direction is exposed from a first gate interconnect, and the face of the second nanosheet closer to the first nanosheet in the X direction is exposed from a second gate interconnect.

A memory device comprises a substrate; a first word line structure, a first dielectric layer; a dielectric liner, and a bit line structure. The first word line structure is in the substrate and comprises a first bottom conductive material and a first top conductive material, in which a top surface of the first bottom conductive material is wider than a bottom surface of the first top conductive material. The first dielectric layer is over the first word line structure. The dielectric liner lines the first word line structure. The bit line structure is over the substrate.

In a memory device including a ternary memory cell, the ternary memory cell may include: a first inverter and a second inverter cross-coupled in a first node and a second node and including a pull-up device and a pull-down device configured to have a constant current pass therethrough upon turn-off; a first read transistor and a first write transistor which are connected to each other in parallel between the first node and a first bit line; and a second read transistor and a second write transistor which are connected to each other in parallel between the second node and a second bit line, wherein the first read transistor and the second read transistor may have a read access current, which is less than or equal to the constant current, pass therethrough in response to an activated read word line.

A non-volatile memory device for performing compute in memory operations for a neural network uses a three dimensional NAND architecture. Multi-bit weight values are stored encoded as sets of threshold voltages for sets of memory cells. A weight value is stored in multiple memory cells on the same word line and connected between a bit line and a source line, each of the memory cells programmed to one of multiple threshold voltages. When multiplying an input value with the weight value, the word line is biased so that, for at least one of the threshold voltages, the memory cell will be in the linear operation region. Input values are encoded as a set of one or more voltage levels applied to a corresponding set of bit lines, each bit line connected memory cells also storing the weight value, connected to the word line, and connected to the source line.

A high-density ferroelectric memory, and a preparation method therefor and an application thereof, belonging to the field of semiconductor memories. In the memory, multiple memory cells are arranged in an array, and the two sides of the array of the memory cells are connected to substantially orthogonal word lines and bit lines, the memory cell of the present invention adopts a stacked structure of a top electrode, a resistive switching dielectric layer, an intermediate metal layer, a ferroelectric dielectric layer, and a bottom electrode, which is electrically equivalent to a ferroelectric capacitor and a resistive switching selector connected in series; the voltage division of the distributed ferroelectric capacitor in the unselected cells is reduced by regulating the RC delay of the memory cell, so that its disturbance is reduced; and the capacitance value of the ferroelectric capacitor is stable, and the influence of the disturbance voltage can be effectively reduced by RC regulation. The storage window of the memory is improved and the bit error rate is reduced, without increasing additional area overhead.

A memory device includes a plurality of memory cells including a first memory cell and a second memory cell, a first bit line connected to the first memory cell, a second bit line connected to the second memory cell, a first word line connected to the first and second memory cells, a first control transistor connected to the first bit line, a second control transistor connected to second bit line, a first mux transistor commonly connected to the first and second control transistors, and a sense amplifier connected to the first mux transistor.

A memory device includes an array comprising a plurality of one-time-programmable (OTP) memory cells; a plurality of word lines (WLs); a plurality of bit lines (BLs); and a plurality of control gate (CG) lines. Each of the OTP memory cells comprises a first fuse resistor, a second fuse resistor, a first transistor, and a second transistor. The first fuse resistor and the second fuse resistor are coupled to a corresponding one of the BLs, while the first transistor and the second transistor are gated by a first one and a second one of the CG lines, respectively.

Embodiments of the present disclosure relates to an integrated circuit including an array of memory cells having the word lines and high-voltage power lines positioned on one side of the transistors and the bit lines and low voltage power lines positioned on the other side of the transistor. The memory cells according to the present disclosure also improve routing efficiency, thus, removing bottleneck of further scaling both SRAM cell.

The invention relates to a preparation method of a memory cell and a memory, and relates to the technical field of integrated circuit design and manufacturing, the memory cell comprises an active column, a capacitor, a first grid electrode and a second grid electrode, the active column has a first end surface and a second end surface deviating from each other along a first direction, and the first end surface is used for being connected with a bit line; the active column internally comprises a first doped region, a channel region and a second doped region which are sequentially arranged along a first direction, the channel region is provided with a first outer surface and a second outer surface which are deviated from each other along a second direction, and the channel region internally comprises a stress structure which penetrates through the active column along a third direction; the first direction and the second direction intersect and are perpendicular to the third direction; the capacitor covers the second end surface and circumferentially surrounds part of the side surface of the active column; the first grid electrode is located on the first outer surface of the channel region; the second grid electrode is located on the second outer surface of the channel region, and the performance and reliability of the memory cell can be improved at least under the condition that the size of the memory cell is reduced.

A memory device includes a peripheral circuit structure and a cell array structure, in which the cell array structure overlaps the peripheral circuit structure in a first direction, in which the cell array structure includes a merged sub array in which at least four sub array regions are merged, in which the merged sub array comprises a memory cell region including: a plurality of first bit lines and a plurality of second bit lines; and a plurality of first word lines and a plurality of second word lines, in which the peripheral circuit structure comprises a merged bank in which at least four banks are merged, and in the merged bank comprises: a first bit line sense amplifier (BLSA), a second BLSA, a first sub word line driver (SWD), a second SWD, and in which a spare space is defined between the first bit lines and the second bit lines.

A memory apparatus includes memory cells and a control means configured to adjust at least one of blind program pulses applied to word lines connected to the memory cells and bit line voltages applied to bit lines coupled to the memory cells in response to determining one of the word lines connected to the memory cells being programmed is susceptible to over-programming. The control means programs non-checkpoint ones of the memory cells associated with a checkpoint state to a verify low voltage for the checkpoint state and programs the non-checkpoint ones of the memory cells to respective non-checkpoint states associated with the checkpoint state by applying the blind program pulses to each non-checkpoint one of the memory cells without verifying whether the non-checkpoint ones of the memory cells have reached their respective non-checkpoint states while applying the bit line voltages to the bit lines associated therewith.

The present inventive concepts relate to semiconductor devices and methods for fabricating the same, and a semiconductor device according to some example embodiments includes: a substrate including an active region defined by a device isolation layer; a word line that crosses and overlaps the active region; a bit line crossing the active region in a direction different from the word line; a direct contact that connects the active region and the bit line and includes a metallic material; a buried contact connected to the active region; and a bit line spacer between the bit line and the buried contact, wherein a width of the direct contact is different from that of the bit line, and the bit line spacer is on an upper surface of the direct contact.

A memory device includes pages each composed of memory cells arrayed in columns on a substrate. A page write operation of retaining a hole group formed by impact ionization inside a channel semiconductor layer, and a page erase operation of discharging the hole group from the channel semiconductor layer are performed. A first impurity layer is connected to a source line, a second impurity layer to a bit line, a first gate conductor layer to a first selection gate line, a second gate conductor layer to a plate line, a third gate conductor layer to a second selection gate line, and a bit line to a sense amplifier circuit. Page data of a memory cell group selected in at least one page is read to the bit line. Zero volts or less is applied to the plate line of the memory cell connected to an unselected page.

A semiconductor device includes a lower circuit pattern, a bit line shielding structure, a first insulating interlayer, a bit line structure, a first contact plug, a channel, and a capacitor. The lower circuit pattern is on the substrate. A bit line shielding structure is on the lower circuit pattern. A first insulating interlayer is in an opening extending through the bit line shielding structure. The bit line structure is on the bit line shielding structure and at least partially overlaps the bit line shielding structure in a vertical direction substantially perpendicular to the upper surface of the substrate. A first contact plug extends through the first insulating interlayer to contact the bit line structure and is electrically connected to the lower circuit pattern. A channel is on the bit line structure. A capacitor is on and electrically connected to the channel.

A memory device according to one embodiment includes includes bit lines, strings, first and second wirings, a word line, and a sequencer. Each of the strings has one end coupled to the bit lines. Each of the strings includes a memory cell, and first and second transistors coupled in series. The first wiring is coupled to the first transistor of each of the strings. The second wiring is coupled to the second transistor of each of the strings. The word line is coupled to the memory cell of each of the strings. The sequencer is configured to, in a read operation of N bytes in which the word line is selected, apply a first voltage to one of the first wiring line and the second wiring line, and apply a second voltage higher than the first voltage to the other of the first wiring line and the second wiring line.

The invention discloses a 10T-SRAM (10 T-Static Random Access Memory) in-memory multiplication unit, an in-memory operation unit and a circuit, and relates to the technical field of integrated circuit design. The invention provides a 10T-SRAM in-memory multiplication unit consisting of a 6T-SRAM part and an MAC (Media Access Control) calculation part consisting of four NMOS (N-channel Metal Oxide Semiconductor) tubes, on one hand, a 1bit weight is stored in the 6T-SRAM part, on the other hand, a 4bit unsigned number is divided into high 2bit input X [3: 2] and low 2bit input X [1: 0], and the high 2bit input X [3: 2] and the low 2bit input X [1: 0] are respectively input into the MAC calculation part, so that the multiplication of the 4bit unsigned number and the 1bit weight is realized in an in-memory calculation mode, and the calculation efficiency is improved. And the voltage drop is reflected through bit lines RBLN and RBLP. The in-memory multiplication circuit solves the problem that the existing in-memory multiplication circuit has few input bits and cannot meet the calculation requirement.

A circuit is provided. The circuit can include sensing circuits configured to sense differences between first and second currents on selected bit lines of an array of memory cells and produce outputs for the bit lines as a function of the difference, and a global programmable non-regular counter configured to continuously provide a count value to each of the sensing circuits in dependence on a clock signal, wherein each sensing circuit, of the sensing circuits, includes (i) a local detector circuit configured to detect a voltage (Vc) generated according to the difference and (ii) a reference voltage selector configured to receive reference voltages from a source and to select a single reference voltage (Vref), and wherein each sensing circuit produces an output according to (i) a difference between Vc and Vref and (ii) a stored count value received from the counter.

A circuit is provided. The circuit includes an array of memory cells including a plurality of bit lines and a plurality of word lines, sensing circuits configured to sense a difference between first and second currents on respective bit lines in selected bit lines and to produce outputs for the selected bit lines as a function of the difference, and a global counter configured to continuously provide a count value to each of the sensing circuits in dependence on a clock signal. Each sensing circuit, of the sensing circuits, can produce an output in dependence on (i) the difference between the first and second currents and (ii) a stored count value received from the global counter, the count value being stored in dependence on a value of the difference between the first and second currents.

A semiconductor memory device is implemented as strings of storage transistors, where the storage transistors in each string have drain terminals connected to a bit line and gate terminals connected to respective word lines. In some embodiments, the semiconductor memory device includes a reference bit line structure to provide a reference bit line signal for read operation. The reference bit line structure configures word line connections to provide a reference bit line to be used with a storage transistor being selected for read access. The reference bit line structure provides a reference bit line having the same electrical characteristics as an active bit line and is configured so that no storage transistors are selected when a word line is activated to access a selected storage transistor associated with the active bit line.

Disclosed herein are devices, methods, and systems for reading a programmed state of a memory element. The method includes setting a bit line to which the memory element is connected to a first voltage and developing to the bit line a compensation voltage different from the first voltage. The method also includes developing a modified sensing voltage to the bit line defined by the compensation voltage and a sensing voltage developed from the memory element and determining the programmed state based on the modified sensing voltage. A complementary memory element may be used to develop the compensation voltage by discharging a complementary plate line, to which the second memory element is connected, to charge a complementary bit line to which the second memory element is connected and by connecting the bit line to the complementary bit line to develop the compensation voltage to the bit line.

The embodiment of the invention discloses a semiconductor structure and a forming method thereof. The semiconductor structure comprises a semiconductor substrate, a stacking structure and a bit line structure. The stack structure and the bit line structure are located on the semiconductor substrate. The stacked structure comprises separation layers and composite layers which are alternately stacked in the vertical direction. The bit line structure extends in the vertical direction and penetrates through the stacking structure. The semiconductor substrate comprises an array region and a peripheral region; the stacked structure located in the peripheral area comprises a capacitor area. A row of bit line structures are respectively formed outside two opposite sides of the capacitor area along the first direction. Wherein the composite layer of the capacitor region comprises a first polar plate. The first polar plates are distributed on the two opposite sides of the composite layer of the capacitor area at intervals in the first direction and protrude outwards. Each first polar plate is connected to a corresponding bit line structure.

Three-dimensional (3D) memory devices and fabricating methods are provided. In some implementations, a disclosed semiconductor device is a memory device and comprises an array of memory cells in an array region, word lines extending parallel in a first lateral direction, bit lines extending parallel in a second lateral direction different from the first lateral direction, and interconnection structures located within the array region and coupled with the bit lines, and arranged in staggered rows along the first lateral direction.

A Magnetic Random Access Memory (MRAM), a method of manufacturing the same, and an electronic device including the same are provided. The MRAM includes a substrate, an array of memory cells arranged in rows and columns, bit lines, and word lines. The memory cells each include a vertical switch device and a magnetic tunnel junction on the switch device and electrically connected to a first terminal of the switch device. An active region of the switch device at least partially includes a single-crystalline semiconductor material. Each of the memory cell columns is disposed on a corresponding bit line, and a second terminal of each of the respective switch devices in the memory cell column is electrically connected to the corresponding bit line. Each of the word lines is electrically connected to a control terminal of the respective switch devices of the respective memory cells in a corresponding memory cell row.

A readout circuit includes a comparator having a first input coupled to receive a ramp signal from a ramp generator and a second input coupled to receive an analog image data signal from one of a plurality of bitlines. The comparator is configured to generate a comparator output in response to a comparison of the ramp signal and the analog image data signal. A sampling circuit has a first input coupled to receive a sampling control signal and a second input coupled to receive the comparator output. The sampling circuit is configured to generate a sampling output. A counter has a first input coupled to receive a counter control signal and a second input coupled to receive one of the comparator output and a signal from the sampling circuit. The readout circuit is configured to perform correlated multiple sampling (CMS) calculations or non-CMS calculations in response to the sampling output.

The present application discloses a cell contact structure, a semiconductor device, and a method for fabricating the semiconductor device. The cell contact structure includes a contact layer positioned on a substrate and enclosed by a plurality of bit line structures and a plurality of partition layers; and a liner layer positioned between the contact layer and the substrate, between the contact layer and the plurality of bit line structures, and between the contact layer and the plurality of partition layers. A top surface of the contact layer and a top surface of the liner layer are substantially coplanar. The liner layer includes doped polycrystalline silicon, doped polycrystalline germanium, or doped polycrystalline silicon germanium. The contact layer includes tungsten, titanium, or titanium nitride.