4821 results about "Bit line" patented technology

The invention discloses a FeFET-based XNOR calculation unit, an array and a working method of the FeFET-based XNOR calculation unit. The unit comprises a FeFET transistor F1, a FeFET transistor F2 and an NMOS transistor M0. The source electrode of the F1 is connected to a bit line BL, the source electrode of the F2 is connected to a bit line BLB, the grid electrode of the F2 and the grid electrode of the F1 are jointly connected to a word line WL, and the drain electrode of the F2 and the drain electrode of the F1 are jointly connected to a node X. The grid electrode of the M0 is connected with the node X, the drain electrode is grounded, and the source electrode is connected to the shared charge line Scl. F1 and F2 are configured to store a weight bit, and by applying a read voltage to WL and applying a voltage corresponding to an input bit to BL and BLB, a voltage level of Scl outputs an XNOR logic calculation result. The array includes a plurality of XNOR computing units arranged in m rows * n columns. WL and Scl ends of each unit are shared in each column, and BL and BLB are shared in each row. According to the invention, the control peripheral circuit of the array word line is simplified, the variability of current is effectively avoided, and the problems of hardware overhead and the like are effectively solved.

A non-volatile memory device for performing compute in memory operations for a neural network uses a three dimensional NAND architecture. Multi-bit weight values are stored encoded as sets of threshold voltages for sets of memory cells. A weight value is stored in multiple memory cells on the same word line and connected between a bit line and a source line, each of the memory cells programmed to one of multiple threshold voltages. When multiplying an input value with the weight value, the word line is biased so that, for at least one of the threshold voltages, the memory cell will be in the linear operation region. Input values are encoded as a set of one or more voltage levels applied to a corresponding set of bit lines, each bit line connected memory cells also storing the weight value, connected to the word line, and connected to the source line.

A high-density ferroelectric memory, and a preparation method therefor and an application thereof, belonging to the field of semiconductor memories. In the memory, multiple memory cells are arranged in an array, and the two sides of the array of the memory cells are connected to substantially orthogonal word lines and bit lines, the memory cell of the present invention adopts a stacked structure of a top electrode, a resistive switching dielectric layer, an intermediate metal layer, a ferroelectric dielectric layer, and a bottom electrode, which is electrically equivalent to a ferroelectric capacitor and a resistive switching selector connected in series; the voltage division of the distributed ferroelectric capacitor in the unselected cells is reduced by regulating the RC delay of the memory cell, so that its disturbance is reduced; and the capacitance value of the ferroelectric capacitor is stable, and the influence of the disturbance voltage can be effectively reduced by RC regulation. The storage window of the memory is improved and the bit error rate is reduced, without increasing additional area overhead.

Embodiments of the present disclosure relates to an integrated circuit including an array of memory cells having the word lines and high-voltage power lines positioned on one side of the transistors and the bit lines and low voltage power lines positioned on the other side of the transistor. The memory cells according to the present disclosure also improve routing efficiency, thus, removing bottleneck of further scaling both SRAM cell.

A memory device includes a peripheral circuit structure and a cell array structure, in which the cell array structure overlaps the peripheral circuit structure in a first direction, in which the cell array structure includes a merged sub array in which at least four sub array regions are merged, in which the merged sub array comprises a memory cell region including: a plurality of first bit lines and a plurality of second bit lines; and a plurality of first word lines and a plurality of second word lines, in which the peripheral circuit structure comprises a merged bank in which at least four banks are merged, and in the merged bank comprises: a first bit line sense amplifier (BLSA), a second BLSA, a first sub word line driver (SWD), a second SWD, and in which a spare space is defined between the first bit lines and the second bit lines.

The invention discloses a 10T-SRAM (10 T-Static Random Access Memory) in-memory multiplication unit, an in-memory operation unit and a circuit, and relates to the technical field of integrated circuit design. The invention provides a 10T-SRAM in-memory multiplication unit consisting of a 6T-SRAM part and an MAC (Media Access Control) calculation part consisting of four NMOS (N-channel Metal Oxide Semiconductor) tubes, on one hand, a 1bit weight is stored in the 6T-SRAM part, on the other hand, a 4bit unsigned number is divided into high 2bit input X [3: 2] and low 2bit input X [1: 0], and the high 2bit input X [3: 2] and the low 2bit input X [1: 0] are respectively input into the MAC calculation part, so that the multiplication of the 4bit unsigned number and the 1bit weight is realized in an in-memory calculation mode, and the calculation efficiency is improved. And the voltage drop is reflected through bit lines RBLN and RBLP. The in-memory multiplication circuit solves the problem that the existing in-memory multiplication circuit has few input bits and cannot meet the calculation requirement.

A circuit is provided. The circuit can include sensing circuits configured to sense differences between first and second currents on selected bit lines of an array of memory cells and produce outputs for the bit lines as a function of the difference, and a global programmable non-regular counter configured to continuously provide a count value to each of the sensing circuits in dependence on a clock signal, wherein each sensing circuit, of the sensing circuits, includes (i) a local detector circuit configured to detect a voltage (Vc) generated according to the difference and (ii) a reference voltage selector configured to receive reference voltages from a source and to select a single reference voltage (Vref), and wherein each sensing circuit produces an output according to (i) a difference between Vc and Vref and (ii) a stored count value received from the counter.

Three-dimensional (3D) memory devices and fabricating methods are provided. In some implementations, a disclosed semiconductor device is a memory device and comprises an array of memory cells in an array region, word lines extending parallel in a first lateral direction, bit lines extending parallel in a second lateral direction different from the first lateral direction, and interconnection structures located within the array region and coupled with the bit lines, and arranged in staggered rows along the first lateral direction.

The present application discloses a cell contact structure, a semiconductor device, and a method for fabricating the semiconductor device. The cell contact structure includes a contact layer positioned on a substrate and enclosed by a plurality of bit line structures and a plurality of partition layers; and a liner layer positioned between the contact layer and the substrate, between the contact layer and the plurality of bit line structures, and between the contact layer and the plurality of partition layers. A top surface of the contact layer and a top surface of the liner layer are substantially coplanar. The liner layer includes doped polycrystalline silicon, doped polycrystalline germanium, or doped polycrystalline silicon germanium. The contact layer includes tungsten, titanium, or titanium nitride.

The present disclosure provides a memory, a bit line control method and an electronic device, in a first chip of the memory, each memory array chip includes a plurality of memory layer groups stacked in sequence along a third direction, in the memory layer groups of odd numbers, each local bit line is coupled to a respective first common bit line via a respective bit line selector, and in the memory layer groups of odd numbers, each local bit line is coupled to a respective second common bit line via a respective bit line selector. Each local bit line is coupled to a respective second common bit line through a respective pre-charge switch; in the even-numbered storage layer group, each local bit line is coupled to a respective first common bit line through a respective pre-charge switch, and each local bit line is coupled to a respective second common bit line through a respective bit line selector.

A data storage device includes a bad block management system. The bad block management system detects a grown bad block of the data storage device. When a grown bad block is detected, the bad block management system initiates a manual block write process on the wordlines associated with the grown bad block. The manual block write process includes programming the wordlines of the grown bad block in a particular state and with a voltage that closes a leakage path between a bit line associated with the grown bad block and a ground line or a ground path associated with the grown bad block.

The invention relates to the technical field of semiconductors, and provides a semiconductor device and a manufacturing method thereof. The method is used for solving the technical problem of how to reduce bit line manufacturing difficulty. The manufacturing method comprises the following steps: providing a substrate, wherein the substrate comprises a plurality of active layers and accommodating spaces for separating the active layers; the active layer comprises a first part and a second part; the size of the second part in the first direction is gradually reduced along the direction from the first part to the second part; forming a filling structure surrounding the first part and a first sacrificial layer covering the filling structure in the accommodating space; the first sacrificial layer protrudes from the surface of the filling structure; the rest accommodating space exposes a plurality of second parts arranged along the second direction; and forming a bit line structure in the remaining accommodating space. Therefore, a self-aligned bit line can be formed, a high-difficulty and high-aspect-ratio bit line etching process is avoided, and the bit line manufacturing difficulty is reduced.

The utility model provides a semiconductor device, which is applied to the technical field of semiconductors. According to the utility model, by changing the width of the interval between the adjacent bit line structures, the widths of the connecting pad structures formed between the different adjacent bit line structures are different in the horizontal direction, so that the positions of part of the second isolation structures are shifted, and the purpose of communicating part of the adjacent connecting pad structures is achieved.

The invention provides a memory, in the memory, for a memory array sheet at a non-head-and-tail position, each bit line is coupled to a corresponding pressure test power supply, and the pressure test power supply corresponding to a first bit line is different from the pressure test power supply corresponding to an adjacent second bit line; for the storage array sheets at the head and tail positions, the first bit lines are coupled to the corresponding pressure test power supplies, and the pressure test power supplies corresponding to the first bit lines with odd numbers are different from the pressure test power supplies corresponding to the first bit lines with even numbers.

The invention discloses a semiconductor structure and a preparation method thereof, and electronic equipment. The semiconductor structure comprises a substrate; the storage array is arranged on the substrate and comprises a plurality of storage units arranged in an array mode, each storage unit comprises a reading transistor and a writing transistor which are electrically connected with each other, and the reading transistor and the writing transistor are stacked in the first direction perpendicular to the surface of the substrate; the writing word line extends along the second direction and is electrically connected with the writing transistors in the plurality of storage units arranged along the second direction; the read word line extends along a second direction parallel to the surface of the substrate and is electrically connected with the read transistors in the plurality of memory cells arranged along the second direction; and the bit line extends along a third direction parallel to the surface of the substrate, the read transistors and the write transistors in the plurality of memory cells arranged along the third direction are electrically connected to the bit line together, and the third direction and the second direction intersect. The semiconductor structure can improve the integration density of the memory.

A memory device includes a spin-orbit torque (“SOT”) conductor, a magnetic tunneling junction (“MTJ”) structure above the SOT conductor, a two-terminal read selector above the MTJ structure, a two-terminal write selector above the MTJ structure, and a bit line below the SOT conductor. The two-terminal read selector is conductively connected to the pinned layer in the MTJ structure. The two-terminal write selector is conductively connected to a first terminal of the SOT conductor. The bit line is conductively connected to a second terminal of the SOT conductor.

A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a substrate, a first bit line disposed on the substrate and extending along a first direction, a first word line disposed on the first bit line and extending along a second direction perpendicular to the first direction, a channel structure disposed on the first bit line and penetrating the first word line, and a trench capacitor disposed on the channel structure. The channel structure is separated from the first word line by a gate dielectric layer.

The invention provides a memory and a control method thereof, and an electronic device, in a first chip of the memory, each local bit line is coupled to a common bit line on one side through a respective bit line selector, and each local bit line is coupled to a common bit line on the other side through a respective pre-charge switch; a bit line selector configured to receive and selectively turn on the connected local bit line and the connected common bit line based on the sub word line driving signal; and a pre-charge switch configured to receive and selectively switch on the connected local bit line and the connected common bit line based on the sub word line driving complementary signal.

A semiconductor device includes a first substrate structure and a second substrate structure. The first substrate structure includes a base substrate, circuit elements disposed on the base substrate, a first substrate disposed on the circuit elements, first memory cells disposed on the first substrate and electrically connected to the circuit elements, first bit lines disposed on the first memory cells and connected to the first memory cells, and first bonding pads disposed on the first bit lines to be connected to the first bit lines, respectively. The second substrate structure is connected to the first substrate structure on the first substrate structure, and includes a second substrate, second memory cells disposed on the second substrate, second bit lines disposed on the second memory cells and connected to the second memory cells, and second bonding pads disposed on the second bit lines to be connected to the second bit lines, respectively. The first substrate structure and the second substrate structure are connected to each other by bonding the first bonding pads to the second bonding pads, and the first bonding pads and second bonding pads are vertically between the first bit lines and the second bit lines, without the first substrate or second substrate disposed vertically between the first bit lines and the second bit lines.

A semiconductor device may include a semiconductor substrate including a horizontal portion and a vertical portion protruding upward from the horizontal portion, a bit line on the semiconductor substrate and extending in a first direction parallel to a bottom surface of the semiconductor substrate, a word line on the bit line and extending in a second direction parallel to the bottom surface of the semiconductor substrate that is different from the first direction, a semiconductor pattern on the vertical portion of the semiconductor substrate and extending in a third direction perpendicular to the bottom surface of the semiconductor substrate, and a metal silicide pattern between the semiconductor pattern and the bit line. The semiconductor pattern may include a source / drain region adjacent to the bit line and a channel region on the source / drain region, and the metal silicide pattern may be in contact with the source / drain region and the bit line.

The present disclosure relates integrated chip structure. The integrated chip structure includes a memory array having a plurality of memory devices arranged in a plurality of rows and a plurality of columns. A word-line is coupled to a first set of the plurality of memory devices disposed within a first row of the plurality of rows. A bit-line is coupled to a second set of the plurality of memory devices disposed within a first column of the plurality of columns. A local interconnect extends in parallel to the bit-line and is coupled to the bit-line and two or more of the second set of the plurality of memory devices. The local interconnect is coupled to the bit-line by a plurality of interconnect vias that are between the local interconnect and the bit-line.

In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a peripheral circuit. The second semiconductor structure includes an array of memory cells and a plurality of bit lines coupled to the memory cells and each extending in a second direction perpendicular to the first direction. Each of the memory cells includes a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor. A respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the first direction. Two adjacent vertical transistors of the vertical transistors in the second direction are mirror-symmetric to one another. The array of memory cells is coupled to the peripheral circuit across the bonding interface.

A three-dimensional semiconductor device includes a semiconductor pattern spaced apart from a substrate, and extending along a first direction parallel to a lower surface of the substrate, a word line surrounding the semiconductor pattern, and extending along a second direction parallel to the lower surface of the substrate, and crossing the first direction, and a bit line extending along a first side surface of the semiconductor pattern along a third direction perpendicular to the lower surface of the substrate, wherein the word line includes a first gate electrode, a second gate electrode on a first side surface of the first gate electrode, and a third gate electrode on a second surface opposite to the first side surface of the first gate electrode, and a work function of each of the second and third gate electrodes is smaller than a work function of the first gate electrode.

The invention discloses a floating-point number index maximum value searching circuit and an in-memory computing chip. The searching circuit comprises an SRAM (Static Random Access Memory) unit matrix which comprises a plurality of rows and columns of SRAM units, wherein each unit comprises NMOS (N-channel Metal Oxide Semiconductor) tubes N1-N5 and PMOS (P-channel Metal Oxide Semiconductor) tubes P1 and P2; n1, N2, P1 and P2 are in reverse cross coupling to form a pair of storage nodes Q and QB; the grid electrode of the N5 is connected with a node QB; the grid electrode of the N3 in the ith row is connected with a word line WLLlt; igt; the grid electrode of the N4 is connected with a word line WLRlt; igt; ; the drain electrode of each column of N5 is connected in series with the source electrode of the next column of N5, and the source electrode of the first column of N5 is connected with a signal SELlt; igt; the N5 drain electrode of the last column is connected with a signal PRE; in the jth column, N3 is a corresponding node Q and a bit line BLlt; jgt; the transmission tube N4 is a corresponding node QB and a bit line BLBlt; jgt; and a transmission tube. According to the invention, the number of searching cycles is saved, the calculation time is shortened, the subsequent calculation amount is reduced, the efficiency is improved, the power consumption is reduced, and the defects of relatively high power consumption, complex hardware implementation, relatively long calculation delay and the like of an existing circuit are overcome.

The invention provides a storage and calculation integrated circuit which can be applied to the technical field of storage and calculation. The storage and calculation integrated circuit comprises a storage and calculation array which comprises a plurality of storage and calculation units; each storage and calculation unit is configured to receive an initial data signal through a connected complementary bit line, receive a weight signal through a weight line, and calculate the received initial data signal and the weight signal by using a voltage stored in the storage and calculation unit to obtain an intermediate data signal; a calculation circuit connected to the plurality of storage units and connected to a calculation line via a node; the calculation circuit is configured to apply the intermediate data signals output by the plurality of storage and calculation units to the calculation line through the node, and adjust the value of current flowing through the calculation line to obtain a target analog signal; and the quantization reading circuit is connected to the calculation line and is configured to convert the target analog signal into the target digital signal according to the quantization precision indicated by the quantization control signal under the control of the quantization control signal output by the quantization control end.

The invention relates to a memory, a preparation method thereof and electronic equipment. The memory includes a common bit line, a bit line, and a cell array. The common bit lines extend in a first direction parallel to the substrate. The bit lines are located on the first side of the common bit lines and extend in the second direction parallel to the substrate. The unit array comprises a plurality of units corresponding to the bit lines, and the units are located on the same side of the bit lines and are sequentially arranged in the second direction; wherein the plurality of units comprise at least one connecting unit, at least one gating unit positioned on one side, far away from the common bit line, of the at least one connecting unit, and a plurality of storage units positioned on one side, far away from the common bit line, of the at least one gating unit. The memory cell and the gate cell each include a transistor coupled to a bit line. A transistor included in the gating unit is a gating transistor, and the gating transistor is coupled with the common bit line through the connecting unit. The production yield and performance of the gating transistor, the memory and the electronic equipment are improved.

A semiconductor device and a method for fabricating the same may be provided. The semiconductor device may include: a first semiconductor structure including a substrate, a plurality of first word lines, a plurality of first bit lines, and a plurality of first memory cells respectively disposed in intersection regions between the first word lines and the first bit lines; and a second semiconductor structure including a plurality of second bit lines disposed over the first bit lines and respectively contacting the first bit lines, a plurality of second word lines, and a plurality of second memory cells respectively disposed in intersection regions between the second word lines and the second bit lines, wherein a first bit line and a corresponding second bit line form a metal-to-metal bonding.

A data storage circuit includes a first memory array comprising a plurality of FeRAM memory units; a second memory array comprising a plurality of OxRAM memory units; each of the first and second memory arrays comprising: a plurality of word lines, a plurality of source lines and a plurality of bit lines; for each column each memory unit comprising: a memory cell having a first electrode and a second electrode connected to the source line associated to the memory unit; a selection transistor having a gate connected to the word line associated to the memory unit and placed in series with the memory cell between the source line and a bit line associated to of the memory unit; the data storage circuit comprising further: a data transfer stage configured to transfer data from a set of source FeRAM memory units having a common bit line to a target OxRAM unit by converting a read signal from the common bit line to a transfer voltage applied on a target line of the target OxRAM unit; the target line corresponding to the word line or the source line and having the same direction as the common bit line.

A novel memory device is provided. A first cell array including a plurality of memory cells and a second cell array including a plurality of memory cells are provided to overlap with each other. Two bit lines included in the first bit line pair are electrically connected to part of the memory cells included in the first cell array and to part of the memory cells included in the second cell array. Two bit lines included in the second bit line pair are electrically connected to part of the memory cells included in the first cell array and to part of the memory cells included in the second cell array. In the first cell array, one of the bit lines included in the second bit line pair includes a region overlapping with part of the first bit line pair. In the second cell array, the other of the bit lines included in the second bit line pair includes a region overlapping with part of the first bit line pair.

Systems, apparatuses, and methods are provided for forming air gaps between bit lines in a semiconductor device. In one aspect, a semiconductor device includes a memory array of memory cells and a bit line coupled to the memory array. Adjacent ones of the bit lines are separated by isolation regions in a first direction. The isolation region extends in a second direction perpendicular to the first direction. The isolation region includes an air gap. In the second direction, an end of the air gap is over an adjacent end of a bit line of the adjacent bit lines.