913 results about "Photomask" patented technology

The invention provides an optical proximity effect correction method and system, a terminal and a medium, and the method comprises the steps: obtaining a plurality of initial parameter combinations of a photoetching mask design pattern, so as to form an initial population; wherein each initial individual in the initial population corresponds to a group of initial parameter combinations; determining a plurality of optimization indexes of the photoetching mask design graph, and determining an optical proximity effect correction function based on the plurality of optimization indexes and constraint conditions; and based on the optical proximity effect correction function, obtaining an optimal parameter combination of the photoetching mask design pattern in the iteration process of the initial population. According to the invention, the optimization algorithm is innovatively introduced into the field of optical proximity effect correction, comprehensive optical proximity effect correction is realized by introducing a plurality of optimization indexes, the manufacturing requirement of a high-precision silicon optical chip is effectively met, and the performance of the silicon optical chip is effectively improved.

The invention discloses a layout generation method for load effect compensation and a related device, which are applied to the technical field of photoetching and comprise the following steps: acquiring photomask data; carrying out grid division on the mask graph according to the photomask data, and determining layout density in each grid; comparing the layout density of each grid with a target density, and determining a density difference value corresponding to each grid; determining a virtual graph corresponding to each grid according to the density difference value; and adding a corresponding virtual graph in a layout area corresponding to the grid to form a compensated mask plate graph. By performing grid division on the mask plate graph, calculating the specific layout density in each grid and adding the corresponding virtual graph to the layout area corresponding to the grid according to the difference value between the layout density and the target density, the graph density of the layout area in each grid can be effectively compensated, so that the load effect of each area in the layout is balanced, and the performance of the mask plate is improved. And the etching uniformity is improved.

The invention provides a manufacturing method of a shallow trench isolation structure. The manufacturing method comprises the following steps: patterning a pad oxide layer-silicon nitride layer laminated structure based on a photomask to obtain a first mask opening; etching the substrate to obtain an isolation groove; carrying out a pull-back process; depositing a sacrificial layer material in the isolation trench and the first mask opening; forming a shielding layer; patterning the shielding layer based on the photomask to obtain a second mask opening; removing the sacrificial layer material in the isolation groove and obtaining a sacrificial side wall located on the side wall of the opening of the silicon nitride layer; removing the shielding layer and depositing a silicon oxide layer in the isolation groove and the first mask opening; and removing the silicon nitride layer, the liner oxide layer and the sacrificial side wall. According to the method, the first mask opening and the second mask opening are formed in different steps based on the same photomask by adopting the pull-back process, the sacrificial side wall on the side wall of the opening of the silicon nitride layer is used for protecting the trench oxide layer from being lost in the subsequent removal process of the liner oxide layer, and the problem of a sunken region at the top edge of the shallow trench isolation region can be avoided or improved.

The invention discloses an optical proximity correction method, a mask plate and a semiconductor structure forming method, and the optical proximity correction method comprises the steps: obtaining a reference layout which comprises a plurality of first metal wire patterns, a plurality of second metal wire patterns and a plurality of cutting patterns; a to-be-corrected graph is obtained from the multiple cut-off graphs, the to-be-corrected graph comprises a first to-be-corrected graph and a second to-be-corrected graph, the first to-be-corrected graph and the second to-be-corrected graph are adjacent, and the distance between the first to-be-corrected graph and the second to-be-corrected graph is smaller than a first preset size; determining a target reference pattern corresponding to the to-be-corrected pattern from the plurality of second metal wire patterns; on the basis of the target reference graph, the first to-be-corrected graph and the second to-be-corrected graph are combined and corrected, a combined graph is obtained, the combined graph is formed, and the situation that a mask design rule is violated is avoided.

The invention relates to a photomask data processing method and device, equipment, a medium and a program product. The method comprises the following steps: acquiring current photomask design data; processing the current photomask design data to obtain pattern density information and pattern size information of each target area; a thermodynamic diagram used for representing the defect degree of each target area is generated; obtaining a target area with a defect degree greater than or equal to a defect threshold value, and determining defect classification of the target area based on pattern density information and pattern size information of the target area; when the defect classification comprises pattern density classification, obtaining a target area of a target area, when the target area is greater than an area threshold value, performing functional area identification on the target area, extracting a key signal path in the functional area, determining a splitting boundary based on the functional area and the key signal path, and designing data of a current photomask based on the splitting boundary, and adjusting. By adopting the method, the photomask design data can be optimized in advance.

A method for correcting a photomask is presented that includes receiving a target design layout of a semiconductor device. The method includes inferring, by a processor, a mask bias by inputting optical feature values, geometric feature values, and resist feature values of a mask layout based on a target design layout into a first machine learning model. The processor generates a predicted pattern by incorporating the mask deviation into the mask layout, compares the predicted pattern with a target design layout, and then corrects the mask layout based on a result of the comparison between the predicted pattern and the target design layout.

The utility model relates to a photomask protective film dismounting device which comprises an object placing table, and a limiting piece, a dismounting assembly and a first temperature sensor are fixed on the object placing table; the upper surface of the storage table is coated with a teflon coating; and a cooling device is arranged in the object placing table and is used for maintaining the temperature of the upper surface of the object placing table at 5-10 DEG C, so that the adhesive between the photomask and the photomask protective film is hardened for subsequent analysis of the photomask protective film. The photomask protective film dismounting device designed by the utility model can be used for solving the problems that an adhesive is easy to splash and pollute the surface of a photomask when a heating method is used for dismounting, fogging spots are possibly caused during cleaning, and the cleanliness and the precision of the photomask are influenced; and damage is easily caused by direct tool dismounting, so that the cost is increased, and the service life of the photomask is shortened.

Systems and methods are provided for automated generation of optical proximity correction (OPC) recipes for producing photomasks for patterning semiconductor wafers, thereby improving the overall efficiency and effectiveness of computational lithography in modern semiconductor manufacturing. According to at least one embodiment, an OPC recipe is generated by a two-stage process that includes a reinforcement learning (RL) stage, for generating OPC actions for representative design patterns, and a large language model (LLM) stage, for generating an OPC recipe based on the OPC actions provided by the RL stage.

Method for particle beam-induced etching of a defect (D1) of a photomask (100) for microlithography, comprising the steps: a) Providing (S1) an activating particle beam (114) and a first gaseous component (116) activatable by the particle beam (114) at a surface (118) of the photomask (100) in a region (120) of the defect (D1) for etching the defect (D1), and subsequently b) Providing (S2) a spontaneously oxidizing oxygen-containing second gaseous component (126) at the surface (118) of the photomask (100) in a passivation area (122) encompassing the area (120) of the defect (D1) for passivation of the surface (118).

The invention discloses a photoetching method and a photoetching machine. The photoetching method comprises the following steps: acquiring flatness information of a wafer surface and bending information of a photomask; according to the flatness information, determining position information of the wafer when different positions of the surface of the wafer are located on a focusing plane of a photomask pattern under the condition that the photomask is not bent; compensating the position information based on the bending information to obtain new position information; and carrying out photoetching on the wafer at the position indicated by the new position information by utilizing the photomask. According to the method and the device, the photomask bending can be accurately compensated, so that the influence of the photomask bending on the key size uniformity and the alignment deviation compensation value uniformity in the exposure unit is eliminated.

A reticle enclosure includes a first cover having a first outer surface and a first inner surface and a second cover having a second outer surface and a second inner surface. The first cover and the second cover are joined together. The first cover and the second cover form an internal space therebetween configured to include a reticle. A catalyst layer is disposed on the first inner surface of the first cover and a dehumidification layer is disposed on the second inner surface of the second cover.

A single integrated circuit is provided, comprising a memory region and a non-memory region. The memory region comprises a first conductive structure, a memory element disposed upon the first conductive structure, and a first via disposed upon the memory element. The non-memory region comprises a second conductive structure, and a second via disposed upon the second conductive structure. The first conductive structure and the second conductive structure are formed by a first photolithography process comprising a first photomask, and the first conductive structure is configured to be a first bottom electrode in the memory region. The first via and the second via are formed by a third photolithography process comprising a third photomask. The first photomask and the third photomask comprise a same pattern.

The invention relates to the technical field of display, and provides a photomask, a metal mask plate and a preparation method, the photomask comprises a pattern definition area, the pattern definition area is used for defining a pixel opening area of the metal mask plate, the pattern definition area is a closed pattern formed by four concave arcs and fillets connected with the concave arcs, the pixel opening area is a rounded rectangle, the center of the graph definition area coincides with the center of the pixel opening area, and the area of the graph definition area is smaller than that of the pixel opening area. The pattern of the pattern definition area transferred on the metal mask can enable the liquid medicine to be more uniformly distributed on the whole surface, effectively reduce the formation of eddy current and dead zones, and avoid the retention of the liquid medicine in a local area, thereby reducing the problems of impurity accumulation and incomplete reaction, reducing inconsistent etching caused by non-uniform flow, and improving the etching quality. Therefore, the etching uniformity of the fillet and the etching uniformity of the straight edge of the pixel opening area of the metal mask plate are improved.

The invention provides a microelectronic device and a preparation method thereof, and belongs to the technical field of microelectronic manufacturing. The method comprises the following steps: depositing a dielectric film layer on a substrate; forming a first photoetching pattern on the film layer by using first photoresist, performing first etching on the dielectric film layer by taking the pattern as a mask to obtain a first pattern structure, and stripping the first photoresist; depositing a reflective film layer on the first pattern structure; and forming a second photoetching pattern on the reflecting film layer by using a second photoresist, performing second etching on the reflecting film layer by using the pattern as a mask to obtain a second pattern structure, and stripping the second photoresist to obtain the microelectronic device. The first photoetching pattern and the second photoetching pattern are formed by the same photomask, and the size of the first pattern structure is different from that of the second pattern structure. According to the method, a new photomask and an additional alignment step are not needed, multi-layer patterning and self-alignment transfer of the microelectronic device are realized, the number of photomasks and the alignment frequency are reduced, the cost is reduced, and the pattern consistency is improved.

The invention provides an off-axis illumination photoetching mask, a preparation method thereof and a photoetching system, which can be applied to the technical field of micro-nano machining and advanced photoetching, and the photoetching mask comprises a mask substrate comprising a first surface and a second surface which are oppositely arranged; the photoetching mask pattern structure is located on the second surface of the mask substrate; the light incident part is located on the first surface of the mask substrate, and the light incident part comprises a plurality of light incident units which are periodically arranged; wherein the light incident unit is provided with a V-shaped structure in the direction perpendicular to the first surface, the V-shaped structure gradually shrinks inwards from the first surface to the second surface, and each V-shaped structure comprises two slope surfaces which are connected with each other; the light incident part further comprises a band-pass filtering film which at least covers the two slope faces of the V-shaped structure.

Microlithographic projection lens with a plurality of lenses (20A-20J, 24, 25), wherein the lenses (20A-20J, 24, 25) define an imaging beam path (17) between an object plane (12) and an image plane (21), and wherein the lenses (20A-20J, 24, 25) are designed to image a photomask (13) arranged in the object plane (12) onto a lithographic object (15) arranged in the image plane (21). The projection lens comprises a frame device (23) wherein support feet (26A-26H, 46A-46H, 47A-47H) are attached to the frame device (23) and wherein the lenses (20A-20J, 24, 25) are supported by the support feet (26A-26H, 46A-46H, 47A-47H), wherein a first support foot (46A-46H) supports a first lens (24), wherein a second support foot (47A-47H) supports a second lens (25) and wherein a third support foot (26A-26H) supports a third lens (20A-20J).The first support foot (46A-46H) is attached to the frame device (23) at the same angular position (30) as the second support foot (47A-47H). The third support foot (26A-26H) is arranged at an angular position in which neither the first support foot (46A-46H) of the first lens (24) nor the second support foot (47A-47H) of the second lens (25) is located.

The invention provides a trench MOSFET and a manufacturing method thereof, and the method comprises the steps: forming a trench, a shield gate oxide layer, a control gate oxide layer, an isolation oxide layer, a shield gate, a control gate, a body region, a source region, and a dielectric layer; a first contact hole penetrating through the dielectric layer and the source region and extending into the body region and a second contact hole penetrating through the dielectric layer, the control gate and the isolation oxide layer and exposing the shield gate are formed, a subsequently formed source metal layer is electrically connected with the source region and the body region through the first contact hole, and a gate metal layer is electrically connected with the control gate and the shield gate through the second contact hole. When the trench MOSFET provided by the invention is in forward conduction, because the shield grid is connected to the control grid, an electron accumulation layer is formed on the side wall of the shield grid, so that the conduction resistance is reduced. Besides, in the manufacturing process of the trench MOSFET, the number of photomasks can be reduced, for example, only three photomasks corresponding to the trench, the contact hole and the metal layer respectively are needed, and the production cost can be reduced.

The invention discloses a photoelectric simultaneous-cutting multichannel test fixture and a battery test system, which are characterized in that components such as a photomask plate, a bottom electrode block, a top electrode down-leading circuit board and a switching slide block are integrated in a fixture body, so that when a to-be-tested sub-battery of a solar battery sample is tested, the to-be-tested sub-battery of the solar battery sample can be tested by the photomask plate, the bottom electrode block, the top electrode down-leading circuit board, the switching slide block and the like; the switching sliding block slides to enable the light transmitting opening to be aligned with the to-be-tested sub-battery, and meanwhile the connecting piece is electrically connected with the electrode of the to-be-tested sub-battery, so that synchronous switching of illumination and electric connection is achieved. According to the technical scheme, synchronous switching of the illumination channels and the electric connection channels of the multiple sub-cells in the solar cell sample can be achieved through the operation of sliding (illumination positioning and electrode conduction of the target sub-cell are completed at the same time), and the situation that in the prior art, a photomask assembly and a circuit channel switcher need to be operated separately is effectively avoided; the testing process is simplified, the misoperation risk is reduced, and the photoelectric path consistency is improved.

The invention relates to a wafer bearing platform lifting system and a method for lifting a wafer bearing platform, in particular to a system and a method for realizing accurate alignment of a wafer and a photomask in a semiconductor lithography process. The system comprises a wafer bearing table, a photomask bearing table, a plurality of linear actuators, a plurality of range finders and a controller. The wafer bearing table is used for bearing a wafer, and the photomask bearing table is used for bearing a photomask. In addition, the linear actuator is used for adjusting the wafer bearing table, and the distance measuring instrument is used for measuring the height of the surface of the wafer. The controller is configured to measure the height of multiple points on the surface of the wafer, adjust the level of the wafer, calculate the distance between the wafer and the photomask, and lift the wafer bearing table to make the wafer contact with the photomask. The invention provides a semiconductor manufacturing method which improves accuracy, efficiency and user control.

Provided is a method for fabricating a semiconductor device, the method including exposing a first pattern corresponding to a mask pattern to light in a first shot region of a substrate by using a photomask including the mask pattern, the first pattern extends in a first direction, and exposing a second pattern corresponding to the mask pattern to the light in a second shot region disposed adjacent to the first shot region of the substrate by using the photomask, the second pattern extends in a second direction, wherein the first direction crosses the second direction.

1. Name of the product in this design: Photomask enclosure. 2. Purpose of this design: for storing and transporting photomasks. 3. The key design feature of this product is its shape. 4. The image or photograph that best illustrates the design's key points: a 3D model.

Described are containers for storing, transporting, shipping or processing fragile devices such as photomasks, reticles, and semiconductor wafers, including in particular dual containment pods that include an outer pod adapted to contain an inner reticle pod, with the inner reticle pod containing a reticle.

The invention provides an adapter plate and a forming method thereof, and the adapter plate comprises a semiconductor substrate which comprises a first region, a second region, a first opening located in the first region, and a second opening located in the second region, isolation layers and DTC structures are sequentially formed on the bottoms and the side walls of the first opening and the second opening and the surface of the semiconductor substrate; the insulating layer is positioned on the surface of the DTC structure; the TSV structure is located in the second opening and fills the second opening; the partition opening is positioned on the semiconductor substrate at the adjacent part of the first region and the second region and penetrates through the DTC structure, the isolating layer and the insulating layer; and the filling layer is used for filling the partition opening and covering the DTC structure and the TSV structure. According to the adapter plate and the forming method thereof provided by the invention, the first opening and the second opening for forming the DTC structure and the TSV structure are completed under one photomask, so that the process steps and the process flow can be simplified.

The invention provides a method for monitoring the light leakage degree of an exposure machine, which comprises the following steps of: firstly, designing a special photomask with a shading area and a light-transmitting area which are arranged at intervals, then exposing a wafer coated with a photoresist layer for multiple times by using the special photomask according to a preset exposure condition, and then collecting the thickness of the photoresist layer in the shading area after each exposure to obtain the light leakage degree of the exposure machine. And finally, judging the light leakage severity of the exposure machine according to the exposure times and the thickness of the photoresist layer of the shading area collected after each exposure. According to the monitoring method provided by the invention, the severity of light leakage of the exposure machine can be timely and effectively monitored, the situation that the photoresist layer in the shading area is excessively thinned or even the dielectric layer is partially thinned, so that the subsequent etching process or ion implantation process is insufficiently withstood and the product is scrapped is avoided, and the production efficiency is improved. The effectiveness of monitoring and the smooth proceeding of the subsequent etching process or ion implantation process and the like are ensured, and the product yield is improved.

The embodiment of the invention provides an exposure system for a wafer edge and a photomask contained in the exposure system. The photomask includes a frame, an opening surrounded by the frame, a phase inversion layer underlying the frame, and an intensity attenuation layer underlying the phase inversion layer. An inner sidewall of the phase inversion layer and an inner sidewall of the intensity attenuation layer are exposed to the opening. An inner sidewall of the phase inversion layer and an inner sidewall of the intensity attenuation layer extend beyond an inner sidewall of the frame in a first direction. According to the invention, the structure with optical phase inversion and intensity adjustment is used to improve the problem of light diffraction at the edge of the wafer.

A display panel (2) and a display apparatus (100). A liquid crystal dimming module (30) of the display panel (2) is located on a light exit side of a liquid crystal display module (20), and dimming sub-pixels (SP2) on the liquid crystal dimming module (30) and display sub-pixels (SP1) on the liquid crystal display module (20) are arranged in a manner of corresponding to each other on a one-to-one basis, so as to achieve finer local dimming and improve the contrast ratio of a liquid crystal display surface; in addition, the dimming sub-pixels (SP2) on the liquid crystal dimming module (30) use a passive driving mode, such that the number of photomasks and processes can be reduced, and thus the costs can be reduced.

The invention relates to an electrical property testing device and an electrical property testing method of a silicon substrate chip. The device comprises a wafer-level chip to be tested and a test platform, the wafer-level chip to be tested comprises a plurality of core particles and a plurality of test areas; the core particles are connected based on interconnection lines; a metal interconnection structure is pre-buried on the core particle; each test area covers the crossed area of the four core particles; the crossed region comprises a part of metal interconnection structure; and the test platform is used for controlling the probe card to be in contact with the metal interconnection structures in the test areas to carry out an electrical test on the wafer-level chip to be tested. According to the electrical property testing device, a wafer level interconnection electrical property testing method based on a window translation mode can be realized, and a whole set of testing solution which can cover the whole wafer, can be reused and can be traced is designed aiming at the reliability problem of a cross-region interconnection structure in a large-scale photomask splicing process.

The present application discloses a double pattern exposure photomask correction method, a photomask correction device and a layout machine learning model training method. The double pattern exposure photomask correction method includes the following steps. A photomask layout target image is obtained. The photomask layout target image is decomposed into two photomask layout sub-images. The photomask layout sub-images overlap in a connection area. A layout machine learning model analyzes the size of the connection area according to the photomask layout target image. The layout machine learning model is established according to a three-dimensional information after etching. An optical proximity correction program is performed on the photomask layout sub-images.

A mask layout optical proximity correction (OPC) method includes determining a target pattern to be formed on a substrate, simulating a photomask layout based on the target pattern, applying a bias to the simulated photomask layout, thereby correcting the photomask layout into a first modeling layout, and selecting one of control parameters obtained through modeling using a layout of a split mask, thereby deforming the first modeling layout into a second modeling layout, and checking whether or not there is a mask rule check (MRC) violation, based on the second modeling layout.

This invention provides a photomask-based light projector, depth camera, and item picking system, comprising: a light source for projecting a linear laser array; a microlens array disposed on the light-emitting side of the light source for receiving the linear laser array and homogenizing it into a surface light; and a photomask, including a pre-set pattern structure disposed on the light-emitting side of the microlens array for receiving the surface light and projecting a structured light pattern according to the pattern structure. In this invention, a rotating mirror drives the rotation of multiple light-reflecting surfaces to reflect the linear laser projected by the light source onto the microlens array to form a linear laser array. The microlens array then homogenizes the linear laser array into a surface light, which is then projected into a structured light pattern through the photomask. This not only significantly improves the light projection power compared to VCSEL-based structured light technology but also provides a significantly denser light spot compared to galvanometer scanning devices, thereby improving the resolution of the depth camera.