2122 results about "Photomask" patented technology

The invention discloses a manufacturing method of a groove, a semiconductor device and a manufacturing method of the semiconductor device, and relates to the technical field of semiconductors, and the manufacturing method comprises the steps: providing a substrate, forming a first mask layer on the substrate, and etching the first mask layer by taking a photomask as a mask, so that the first mask layer covers the substrate of a first groove region, forming a second mask layer on the substrate, etching the second mask layer to enable the second mask layer to expose the first mask layer and the substrate in the second groove region, etching the substrate in the second groove region by taking the first mask layer and the second mask layer as masks to form a relatively shallow second groove, and etching the first mask layer to form a relatively shallow second groove; according to the method, the substrate of the first trench region and the substrate of the second trench region are exposed by the second mask layer, and the substrate of the first trench region and the substrate of the second trench region are etched by taking the second mask layer as a mask to form a deeper second trench and a shallower first trench, so that a shallow trench and a deep trench can be manufactured by adopting one photomask, and the manufacturing cost can be further reduced.

The invention discloses a process for improving surface defects of a quartz substrate of a photomask IC (integrated circuit) chip, relates to the technical field of quartz substrates, and aims to solve the problem that the surface defects of the quartz substrate cannot be effectively improved in the process from material selection to manufacturing to later quality control in the prior art. Through three methods of visual inspection, automatic optical detection and laser scanning detection, multi-dimensional detection from macroscopic to microscopic and from the surface to the structure is realized, the accuracy and comprehensiveness of defect identification are ensured, and by setting a clear defect classification standard and a maximum defect range, the defect identification accuracy is improved. Defects possibly affecting product performance can be found and treated in time, the surface laser repairing method is suitable for shallow layer defects, the internal ion implantation repairing method can effectively treat deep layer defects, the flexibility and adaptability of the technology are improved through diversified repairing strategies, and unnecessary material waste and machining cost are avoided through accurate repairing.

The invention provides a semiconductor device and a preparation method thereof, and the method comprises the following steps: providing a substrate which comprises a base layer and a spacer layer located on the base layer, and is divided into a first region for forming a BCD device and a second region for forming an SGT device, a BCD structure is arranged in the substrate layer of the first area, and a first SGT structure and a second SGT structure which are spaced from each other are arranged in the substrate layer of the second area; forming a patterned photoresist layer on the first SGT structure in the second region and the spacer layer above the BCD structure in the first region, and etching the spacer layer to expose a part of the substrate layer and the second SGT structure; and forming a control gate on the spacer layer above a part of the BCD structure and extending to a part of the exposed substrate layer, wherein the control gate is also formed on the exposed second SGT structure. On the basis of not increasing a photomask and a process, the breakdown voltage can be increased, and the electrical performance of the device is improved.

A pellicle for an EUV photo mask includes a first layer, a second layer, and a main membrane disposed between the first layer and second layer. The main membrane includes a plurality of co-axial nanotubes, each of which includes an inner tube and one or more outer tubes surrounding the inner tube, and two of the inner tube and one or more outer tubes are made of different materials from each other.

The invention provides a method for forming a photomask and a semiconductor structure, and relates to the technical field of semiconductors. The photomask is divided into four quadrant areas along two rectangular center lines, the four quadrant areas comprise three complete shading areas and one graph area, and the graph area is provided with a 1 / 4 mark graph; the photomask is used for forming the 1 / 4 mark pattern in a unit exposure area on an intermediate layer or a wafer, and the unit exposure area comprises four chip areas distributed in a 2 * 2 array and cutting channel areas among the four chip areas; the 1 / 4 mark pattern is located in the cutting channel area. Through the photomask of which the four pattern regions are positioned in different quadrant regions, four times of exposure superposition is carried out, so that a complete mark pattern can be obtained.

The invention provides an optical proximity effect correction method and system, a terminal and a medium, and the method comprises the steps: obtaining a plurality of initial parameter combinations of a photoetching mask design pattern, so as to form an initial population; wherein each initial individual in the initial population corresponds to a group of initial parameter combinations; determining a plurality of optimization indexes of the photoetching mask design graph, and determining an optical proximity effect correction function based on the plurality of optimization indexes and constraint conditions; and based on the optical proximity effect correction function, obtaining an optimal parameter combination of the photoetching mask design pattern in the iteration process of the initial population. According to the invention, the optimization algorithm is innovatively introduced into the field of optical proximity effect correction, comprehensive optical proximity effect correction is realized by introducing a plurality of optimization indexes, the manufacturing requirement of a high-precision silicon optical chip is effectively met, and the performance of the silicon optical chip is effectively improved.

The embodiment of the invention provides a defect detection device and method, a photoetching machine, equipment, a medium and a program product, the defect detection device is used for detecting defects of a thin film arranged on a photomask, and the defect detection device comprises a detection module used for bearing the photomask and scanning the thin film on the photomask, the defect information comprises the number of defects and coordinate values corresponding to the defects; the light source is used for providing illumination light for the photomask; the acquisition module is arranged along a transmission path of the illumination light through the photomask or a reflection path of the thin film, and is used for acquiring a sampling image at least comprising the thin film when the photomask is irradiated; and the processor is electrically connected with the detection module and the acquisition module and is used for determining the type of the defect according to the defect information and the sampling image. By adopting the technical scheme, the determination precision of the defect type can be improved.

The invention discloses a layout generation method for load effect compensation and a related device, which are applied to the technical field of photoetching and comprise the following steps: acquiring photomask data; carrying out grid division on the mask graph according to the photomask data, and determining layout density in each grid; comparing the layout density of each grid with a target density, and determining a density difference value corresponding to each grid; determining a virtual graph corresponding to each grid according to the density difference value; and adding a corresponding virtual graph in a layout area corresponding to the grid to form a compensated mask plate graph. By performing grid division on the mask plate graph, calculating the specific layout density in each grid and adding the corresponding virtual graph to the layout area corresponding to the grid according to the difference value between the layout density and the target density, the graph density of the layout area in each grid can be effectively compensated, so that the load effect of each area in the layout is balanced, and the performance of the mask plate is improved. And the etching uniformity is improved.

The sintering and groove sinking integrated system comprises a sintering furnace, a groove sinking furnace, a weighing mechanism, a driving mechanism and a groove sinking mold, the weighing mechanism is connected with the driving mechanism, the driving mechanism is connected with a quartz rod, the bottom end of the sintering furnace is connected with the top end of the groove sinking furnace, and inner cavities of the sintering furnace and the groove sinking furnace are communicated; and the groove sinking die is arranged in the groove sinking furnace. The sintering furnace and the groove sinking furnace are integrally arranged, and the quartz rod is directly subjected to groove sinking shaping after being sintered, so that the production time is effectively shortened, and the production cost is reduced; a driving mechanism is used for hanging and driving a quartz rod to descend, the quartz rod enters a groove sinking furnace after being densified in a sintering area, and the quartz rod is gradually melted and spread in a groove sinking mold from the bottom, so that the problems of stripes, bubbles, poor uniformity and large stress in a product caused by folding and toppling due to the fact that the length-diameter ratio of the quartz rod is too large are solved; production of large-size, low-defect, high-performance and high-purity products is achieved, and the method can be applied to development of IC photomask substrates.

The invention belongs to the technical field of projection light field regulation and control, and particularly relates to a method and a system for enhancing manufacturability of a projection type structure photomask pattern. Determining an initial mask pattern according to the target structured light field and the magnification of the projection system; calculating an initially generated structured light field by adopting a vector diffraction imaging model, calculating a numerical value of a target function, and judging whether the numerical value meets a preset threshold value or not; if the target function does not meet the preset threshold value, carrying out iterative optimization on the mask pattern by adopting an optimal gradient method until the preset threshold value of the target function is met, and outputting a continuous numerical value mask; pixel splitting or fusion is carried out on the continuous numerical mask according to the required mask manufacturing precision; local integral approximation operation is adopted, binarization processing is carried out on the mask, and the manufacturability of the mask is enhanced. According to the method, the projection type structure light field which is high in degree of freedom, high in efficiency, low in calculation power requirement and robust can be optimized, the mask pattern which can be manufactured can be obtained, and the manufacturing precision of the mask can be adjusted at will so as to adapt to different mask pattern preparation processes.

The invention provides a pattern correction method and correction system for a mask, and the method comprises the following steps: setting a plurality of main patterns and a plurality of auxiliary patterns, and collecting wafer data after photoetching of the main patterns and the auxiliary patterns; searching a main pattern with the same characteristic size as the auxiliary pattern on the mask plate as a reference pattern; acquiring a scaling ratio of the reference pattern transferred to the wafer from the mask plate, and acquiring virtual size data of the auxiliary pattern transferred to the wafer according to the scaling ratio and size information of the auxiliary pattern on the mask plate; and taking the virtual size data and the wafer data as modeling parameters of an optical proximity correction model, and iteratively establishing the optical proximity correction model until the correction error is smaller than a threshold value. The invention provides a pattern correction method and correction system for a mask plate, which can improve the pattern transfer accuracy of photoetching, thereby improving the semiconductor manufacturing yield.

To solve the problem that a conventional large-sized resin photomask storage case cannot be integrally molded by injection molding, and accordingly respective components are created by bonding.SOLUTION: A photomask storage case is composed of a lower case part made of a synthetic resin, and an upper case part blocking the lower case part, wherein the lower case part is composed of a photomask fixing frame which has a fixing part for mounting and fixing a stored photomask, and is composed of a metal frame body, and a lower case body in which the fixing frame is detachably provided. The lower case body is integrally molded by vacuum molding.SELECTED DRAWING: Figure 2

An embodiment of the present application discloses a display panel and a display panel manufacturing method. The photosensitive element and the thin film transistor device are disposed on the same side of the substrate. Some components of the photosensitive element and some components of the thin film transistor device can be manufactured by the same step, and therefore can improve integration of the photosensitive element on the array substrate. Furthermore, the photosensitive element can be integrated in the display panel with reduced photomasks and a lowered cost.

The invention relates to the technical field of semiconductor manufacturing, in particular to a photomask correction method, device and equipment and a medium, and the photomask correction method comprises the steps: obtaining a test layout with known parameters; training the initial optical proximity correction model based on known parameters until the cost evaluation function and the root-mean-square value are minimum, and obtaining an optical correction model; obtaining photochemical reaction parameters of the test layout, training an optical correction model based on the photochemical reaction parameters until the cost evaluation function and the root mean square value are minimum, and obtaining a target layout correction model; and inputting the initial layout into a target layout correction model to obtain a corrected layout, so as to obtain a target photomask based on the corrected layout, and at least ensuring that the exposed photomask pattern is consistent with a target pattern actually expected by a user.

The invention relates to the technical field of display, and provides a method for improving the straightness of a metal mask, which comprises the following steps: measuring the pixel position precision deviation of a plurality of specified point positions of a plurality of sample masks; selecting the X coordinates of the plurality of specified points as an independent variable and the sum of the Y coordinates and the Y-direction deviation as a dependent variable for fitting, or selecting the Y coordinates of the plurality of specified points as an independent variable and the sum of the X coordinates and the X-direction deviation as a dependent variable for fitting to obtain a fitting expression; when a target product is manufactured, a compensation value required by a theoretical coordinate value of a pixel opening point location of the target product is calculated, the theoretical coordinate value of the pixel opening point location in a photomask design layout of the target product is replaced by a compensated actual coordinate value, and the compensated photomask design layout is adopted to expose and manufacture a metal mask plate. The technical problems that the straightness of the metal mask plate is poor, the product yield is poor and the cost is wasted due to the fact that the raw material type is poor are solved.

The invention relates to a method for forming a semiconductor structure. The forming method comprises the following steps: after a hard mask lamination covering a gate structure and a substrate is formed, protecting an NMOS (N-channel Metal Oxide Semiconductor) forming region by using a graphical mask, and performing first anisotropic etching to expose the substrate on two sides of the gate structure in a PMOS (P-channel Metal Oxide Semiconductor) forming region; removing the patterned mask, performing second anisotropic etching, and removing a part of the nitride film in the hard mask laminated layer in the NMOS forming region while forming a source drain groove in the PMOS forming region; protecting the substrate in the NMOS forming region by using an oxide film in the hard mask lamination, forming a sigma-shaped groove in the PMOS forming region, and performing heteroepitaxy; and finally, removing the residual hard mask laminated layer and the gate upper oxide layer and the gate upper nitride layer in the gate structure by using a maskless process. According to the method, a photomask process is only used when the patterned mask is formed, so that the cost of a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) process can be reduced, the damage to the substrate can be reduced, and the performance of a device can be improved.

The invention provides a manufacturing method of a shallow trench isolation structure. The manufacturing method comprises the following steps: patterning a pad oxide layer-silicon nitride layer laminated structure based on a photomask to obtain a first mask opening; etching the substrate to obtain an isolation groove; carrying out a pull-back process; depositing a sacrificial layer material in the isolation trench and the first mask opening; forming a shielding layer; patterning the shielding layer based on the photomask to obtain a second mask opening; removing the sacrificial layer material in the isolation groove and obtaining a sacrificial side wall located on the side wall of the opening of the silicon nitride layer; removing the shielding layer and depositing a silicon oxide layer in the isolation groove and the first mask opening; and removing the silicon nitride layer, the liner oxide layer and the sacrificial side wall. According to the method, the first mask opening and the second mask opening are formed in different steps based on the same photomask by adopting the pull-back process, the sacrificial side wall on the side wall of the opening of the silicon nitride layer is used for protecting the trench oxide layer from being lost in the subsequent removal process of the liner oxide layer, and the problem of a sunken region at the top edge of the shallow trench isolation region can be avoided or improved.

The invention provides a junction field effect transistor compatible with a BCD platform and a preparation method thereof, and the preparation method comprises the steps: etching a second grid electrode of an LDMOS device region to open a part of the surface of a second drift region, etching a middle region of a first grid electrode of a JFET device region to form a first opening, opening a part of the surface of a first drift region, and forming a second opening; a first body region is then formed in the first drift region at the bottom of the first opening of the JFET device region through an ion implantation process. According to the invention, a new photomask does not need to be additionally added in the process of forming the first body region, and the middle region of the first gate, which is subsequently injected into the first body region, of the JFET device region is synchronously opened in the process of etching the second gate of the LDMOS device region and opening part of the surface of the second drift region, so that the photomask for independently opening the middle region of the first gate is saved; the preparation process is simplified, and the cost is reduced.

The invention relates to the technical field of polymer encryption materials, and discloses a stress resolution encryption material, a preparation method thereof, a structural color anti-counterfeit label and an encryption method. The stress resolution encryption material has a hard mask / flexible substrate double-layer structure, and the preparation method comprises the following steps: reacting an acrylic acid-co-acrylate copolymer solution with an anthracene derivative to obtain a hard mask material solution; the preparation method comprises the following steps: dissolving acrylate, diacetone acrylamide and an emulsifier in a solvent, and carrying out polymerization reaction under the action of an initiator to obtain an emulsion; curing and drying the emulsion to obtain a latex film; and coating the surface of the latex film with the hard film material solution. According to the stress resolution encryption material, stress programming exposure is carried out through the light source and the photomask, recording of structural color pattern information is achieved, the stress resolution encryption material has the strain resolution characteristic, and the optical performance of the surface changes along with changes of external stimulus. When the strain resolution encrypted information is read, external equipment is not needed, and the strain resolution encrypted information can be stretched by hands and identified by naked eyes.

The invention discloses a method for checking a mark pattern in photomask data. The method comprises the following steps: providing the photomask data; obtaining cutting channel photomask data from the photomask data as to-be-processed data; performing data conversion on the to-be-processed data to obtain scribe line layout data; according to the original layout data, acquiring photomask layers and position information of all the marked graphs in the scribe line layout data, and standard pattern graphs corresponding to the marked graphs; according to the photomask layers and position information of all the marked graphs in the original layout data and standard pattern graphs corresponding to all the marked graphs, a plurality of preset windows are established at the corresponding positions of the corresponding photomask layers in the scribe line layout data, and one marked graph corresponds to one preset window; in the scribe line layout data, mark graphs in all the preset windows are obtained; according to the marked graph in the preset window and the corresponding standard pattern graph, a judgment result about whether the marked graph in the preset window is correct or not is obtained, and the correctness of marked graph inspection is improved.

The invention discloses a self-aligned double-epitaxial super-junction MOSFET and a manufacturing method, the self-aligned double-epitaxial super-junction MOSFET comprises a semiconductor layer arranged on a substrate, a plurality of body regions distributed along the surface of the semiconductor layer are arranged in the semiconductor layer, and a source region located below the surface of the semiconductor layer is arranged in each body region; the pair of first side walls are arranged on the surface of the semiconductor layer above each source region in a self-aligned manner; the super junction groove is arranged in the semiconductor layer in a penetrating manner between each pair of first side walls; the first epitaxial layer of the first conductive type and the second epitaxial layer of the second conductive type are arranged in the super junction groove and are connected with the body region; and the gate oxide layer and the gate electrode are arranged on the surface of the semiconductor layer between two adjacent pairs of first side walls. According to the invention, the range of ion implantation can be accurately adjusted while the number of photomasks is reduced and self-alignment is realized, and the drift region can be directly changed into the intrinsic semiconductor layer, so that the on-resistance can be reduced while the withstand voltage is improved.

The imaging lens assembly (21) of the present application example includes an optical member (32), a lens group (33) and a light shielding member (31). The optical member (32) is configured to bend incident light incident from the object side toward the image side. The lens group (33) is arranged on the image side of the optical member (32) to image the incident light bent by the optical member (32) on the imaging surface. The light shielding member (31) partially blocks the incident light, and the light shielding member (31) includes a light shielding mask (311) and an aperture stop (312). The light shielding member (31) is provided with a first aperture (311a) that partially transmits the incident light. The aperture stop (312) partially shields the incident light on the image side of the optical member (32), and the aperture stop (312) is provided with a second aperture (312a) that partially transmits the incident light. The imaging lens assembly (21) is configured so that tan(DFOV / 2)>0.59, dm≥da.

The invention relates to a semiconductor structure preparation method and a semiconductor structure, and relates to the technical field of integrated circuits. Based on the target photomask, forming first through holes which sequentially penetrate through the supporting laminated layers in the first direction; a target lamination layer is formed on the inner side wall of the first through hole, a second through hole is defined by the target lamination layer, and the target lamination layer comprises target carbon layers and isolation layers which are alternately laminated from outside to inside; forming a dielectric stack filling the second through hole; based on the target photomask, forming a third through hole which penetrates through the dielectric lamination layer and exposes the target lamination layer; etching through the third through hole and removing the residual dielectric laminated layer in the second through hole, and over-etching the first dielectric layer to obtain a groove exposing part of the conductive layer; the target carbon layer is removed, metal barrier layers covering the inner side walls of the third through holes and the inner surfaces of the grooves are formed, and air gaps are formed between the adjacent remaining isolation layers. At least the number of used photomasks can be reduced, and the complexity and cost of the preparation process are reduced.

The invention discloses a photomask defect identification method, and belongs to the technical field of photomask detection. The method comprises the following steps: S1, acquiring a surface defect image; s2, preprocessing the surface defect image based on the imaging characteristics of the defect; s3, performing filtering algorithm correction on the preprocessed surface defect image; s4, performing colorimetric analysis on the surface defect image corrected by the filtering algorithm to obtain a particle region; s5, on the basis of morphological characteristics of defects, segmenting the particle region to obtain defect islands; and S6, performing morphological analysis on the defective island to obtain a defect type and a defect size. The photomask defect identification method provided by the invention combines morphological and colorimetric analysis methods to automatically process the surface defect image and extract the defect island, improves the accuracy of defect identification, gets rid of the constraint of the difference of different equipment imaging systems, realizes automatic batch processing, and saves the manpower and material investment in the mass production link.

The invention provides a trench gate silicon carbide transistor structure and a preparation method thereof. According to the invention, the sacrificial oxide layer with a thin film layer grows and is formed on the surface of the polycrystalline silicon layer of the trench gate structure and the surface of the polycrystalline silicon layer of the driving gate structure, so that sputtering metal can be prevented from reacting with polycrystalline silicon when an ohmic contact structure is formed; therefore, the condition that the photoetching and etching processes of the source contact hole and the gate contact hole can use the same photomask can be met; and meanwhile, the sacrificial oxide layer is thin, so that the sacrificial oxide layer can be conveniently removed together when the first metal layer which does not react is removed, and the influence on other film layers is small. The source contact hole and the gate contact hole are simultaneously formed through photoetching and etching by adopting the same photomask, so that the number of layers of the photomask is reduced, the photoetching and etching process time can be saved on one hand, the process manufacturing cost can be reduced, the parameter abnormity caused by external defects can be reduced on the other hand, the process stability is improved, and the production efficiency is improved. Therefore, the production efficiency is improved, and the productivity is increased.

The invention discloses a threshold voltage adjusting method and a manufacturing method of a semiconductor device and the semiconductor device, and relates to the technical field of semiconductor manufacturing. The threshold voltage adjusting method of the semiconductor device comprises the following steps: providing an MOS substrate, wherein the MOS substrate comprises a first MOS region and a second MOS region; pocket doping ion implantation is carried out on the first MOS region and the second MOS region, and pocket doping regions are respectively formed; thermal diffusion is carried out on the MOS substrate, so that the diffusion degree of pocket doping ions in the second MOS region is smaller than that of pocket doping ions in the first MOS region, and the threshold voltage of the second MOS region is higher than that of the first MOS region. According to the adjusting method, the threshold voltage does not need to be changed in a mode of combining homotype doping and heterotype doping, and the threshold voltage of different MOS regions can be adjusted. According to the manufacturing method, the number of used photomasks can be reduced.

The invention relates to an LED chip positioning and selecting method, which comprises the following steps of: 101, manufacturing LED semiconductor crystal grains by using a photomask plate with a fixed interval, and carrying out parameter spot measurement on the manufactured LED semiconductor crystal grains to obtain spot measurement data of the LED semiconductor crystal grains; 102, determining an actual BIN section interval to which each LED semiconductor crystal grain belongs according to spot measurement data; 103, recording the grid layout condition of each LED semiconductor crystal grain to obtain layout data; 104, sorting is carried out; the sorting device picks out the LED semiconductor crystal grains belonging to the actually same BIN section interval from the original position of the wafer and moves the LED semiconductor crystal grains to the corresponding blue film based on the layout data; wherein the sorting device comprises a plurality of sucking devices which can be independently controlled, and the spacing distance between the sucking devices is the same as the spacing distance between grids, so that the sorting device can selectively suck the corresponding LED semiconductor crystal grains according to layout data, the sorting efficiency of the LED semiconductor crystal grains in chip production can be improved, and the quality of chips is ensured; and the production cost can be reduced, and the automation level can be improved.

The embodiment of the invention relates to the field of photomasks, and provides a photomask protective film frame and a preparation method thereof, the photomask protective film frame comprises a frame main body made of a metal material and a coating formed on the surface of the frame main body, and the photomask protective film frame is characterized in that the coating is at least composed of carbon black, silicon dioxide particles and organic dye. The nanoscale carbon black in the coating has a high light absorption coefficient, fills gaps of dye molecules and forms a continuous light absorption network, the organic dye enhances absorption of light with specific wavelength through a molecular structure conjugated system, and the nanoscale carbon black and the organic dye form a composite function of broad-spectrum absorption and accurate waveband adjustment, so that more than 95% of light is absorbed in a broad-waveband range, light reflection on the surface of the frame is reduced, and the light absorption efficiency is improved. Pattern distortion caused by reflected light in the photoetching process is avoided, silicon dioxide is embedded into an organic dye matrix, silicon dioxide gaps are filled with carbon black particles, the porosity of the coating is reduced, the wear resistance of the coating is improved, and the cracking risk of the coating is reduced. Optical absorption, wear resistance and weather resistance are synchronously improved.

The invention discloses an optical proximity correction method, a mask plate and a semiconductor structure forming method, and the optical proximity correction method comprises the steps: obtaining a reference layout which comprises a plurality of first metal wire patterns, a plurality of second metal wire patterns and a plurality of cutting patterns; a to-be-corrected graph is obtained from the multiple cut-off graphs, the to-be-corrected graph comprises a first to-be-corrected graph and a second to-be-corrected graph, the first to-be-corrected graph and the second to-be-corrected graph are adjacent, and the distance between the first to-be-corrected graph and the second to-be-corrected graph is smaller than a first preset size; determining a target reference pattern corresponding to the to-be-corrected pattern from the plurality of second metal wire patterns; on the basis of the target reference graph, the first to-be-corrected graph and the second to-be-corrected graph are combined and corrected, a combined graph is obtained, the combined graph is formed, and the situation that a mask design rule is violated is avoided.

The utility model discloses a photomask box bonding glue injection device which comprises an injection pipe, a plate body and a shell, an electric control plate is arranged in the shell, a servo motor is arranged on the inner wall of the shell, the output end of the servo motor is connected with a lead screw, the lead screw is in threaded connection with a rod body, the end of the rod body is connected with a piston, and the piston is in sealed sliding connection with the injection pipe. The output end of the injection tube is in threaded connection with a needle, and a guide strip is arranged on the rod body. The servo motor is electrically connected to drive the lead screw to rotate, the lead screw is in threaded connection with the rod body, under the limitation of the guide strip and the guide opening, the piston is driven to move back, glue is sucked into the injection pipe, the servo motor rotates reversely, the piston is driven to move forwards, the glue is extruded out of the needle head, and after the piston is extruded to the bottom, the elastic piece is compressed. The device plays a role in protection, prevents the piston and the injection tube from being excessively extruded to cause breakage of the injection tube, improves safety, can be operated by a single hand, and is convenient for glue injection and plate sticking.