313results about How to "Improve routing density" patented technology

A process for producing a wiring board is provided, comprising allowing a wiring board-forming mold, which comprises a support base and a mold pattern that is formed in a protruded shape on one surface of the support base wherein the sectional width of the mold pattern on the support base side is larger than the sectional width thereof on the tip side in the same section of the mold pattern, to penetrate into a curing resin layer to transfer the mold pattern, curing the curing resin layer, releasing the laminate from the mold, depositing a conductive metal, and polishing the deposited metal layer that to form a depressed wiring pattern, and a wiring board produced by this process. Further, described is a process for producing a wiring board, comprising bringing a precision mold having a mold pattern on a surface of a mold base into contact with a surface of a metal thin film formed on an organic insulating base, pressing the mold to form a depression having a shape corresponding to the mold pattern of the precision mold in the organic insulating base, thereafter forming a metal plating layer having a thickness larger than the depth of the depression to fill the plating metal in the depression, and then polishing the metal plating layer until the organic insulating base is exposed, to form a wiring pattern, and a wiring pattern produced by this process.

Detection column wires and detection row wires are configured of thin wires made of a conductive material having light reflectivity, such as a metal or alloy including silver and aluminum. A predetermined plural number of detection column wires are electrically connected to form a plurality of column-direction bundle wires. A predetermined plural number of detection row wires are electrically connected to form a plurality of row-direction bundle wires. A reflected-light distribution pattern is further provided. When viewed in a direction vertical to the surface of the touch screen, the reflected-light distribution pattern includes a curved portion, and the normal lines of the curved portion head for all directions.

A display device includes an active area that is composed of a plurality of pixels and a plurality of signal supply wiring lines that supply driving signals to the pixels, a plurality of input sections that are disposed outside the active area and function to input the driving signals that are to be supplied to the signal supply wiring lines, and a plurality of connection wiring lines that connect the signal supply wiring lines and the input sections. Mutually neighboring first connection wiring line and second connection wiring line of the connection wiring lines are disposed in different layers via an insulating layer.

The method of manufacturing a wiring substrate comprises the steps of: performing a pattern exposure of a resin layer containing photocatalyst particles, in a shape of a desired wiring pattern so that the photocatalyst particles are exposed at a surface of the resin layer; performing irradiation of radiation to the resin layer having the exposed photocatalyst particles while the resin layer having the exposed photocatalyst particles is immersed in an aqueous solution of a metallic salt so that a photochemical reduction and precipitating of a metal film onto the exposed photocatalyst particles are performed; and forming a conducting layer on the metal film.

Provided is a substrate wherein wiring layers laminated onto the top and bottom surfaces of a core layer are connected to each other by a simple means. Also provided is a method for manufacturing said substrate. In the provided substrate (10A), a connection substrate (13) is placed in a removed region (12) which goes all the way through a part of a thick core layer (11). Said connection substrate (13) electrically connects a first wiring layer (16A) laminated onto the top surface of the core layer (11) to a second wiring layer (16B) laminated onto the bottom surface of the core layer (11). This eliminates the requirement of providing a through-hole through the core layer (11) for each connection, resulting in a small form-factor substrate (10A) with a high wiring density.

A processing method of thin core board in manufacturing of printed circuit board or integrated circuit package substrate comprises the followings: copper foil and bonding sheet, two core boards are used for laminating and thermocompression bonding to obtain a processing board with periphery being bonded, and the thickness and strength thereof can satisfy the processing requirements of conventional devices; pattern conversion processing is carried out on the bonded processing board; laminating method is carried out on newly formed conductor line pattern surface, insulating medium and conductor line are formed through laminating, laser beam drilling, plating and pattern conversion technology; the previous processes are repeated to form multilayer processing boards; when two sides of multilayer processing boards reaches certain thickness and strength, the multilayer processing boards are incised at the bonding joint to form two processing boards; conventional laminating, drilling, plating and pattern conversion technologies are adopted to process the two processing boards respectively until the manufacturing of the needed circuit board and package substrate is finished. The invention needs no special device or processing tool to process thin core board, thus greatly reducing cost and improving productivity and yield of the product.

The invention relates to the technical field of display and provides an array substrate, a display panel, a display device and a manufacturing method of the array substrate. The array substrate comprises grid lines and data lines insulated from one another on a lining substrate intersecting with each other to limit a plurality of sub pixel units. A thin film transistor and a pixel electrode are formed in each sub pixel unit. Each data line comprises a first data line body and a second data line body arranged between two columns of the corresponding adjacent sub pixel units side by side. In every two columns of the adjacent sub pixel units, the sub pixel units on the odd number line are connected with the corresponding first data line bodies, the sub pixel units on the even number line are connected with the corresponding second data line bodies, and at least part of first data line bodies and the adjacent second data line bodies are arranged on different layers between every two adjacent sub pixel units. According to the array substrate, the display panel, the display device and the manufacturing method of the array substrate, at least part of the first data lines and the adjacent corresponding second data lines are arranged on the different layers, and the short circuit between double data lines is solved.

A method of fabricating a substrate with an embedded component therein including the following steps is provided. First, a core layer having a first dielectric layer, a first patterned circuit layer, and a second patterned circuit layer is provided. The first patterned circuit layer and the second patterned circuit layer are disposed on an upper surface and a lower surface of the first dielectric layer, respectively. Then, a through hole is formed in the core layer. Next, the core layer is arranged on a supporting board and an embedded component having at least one electrode is disposed in the through hole. Afterward, a process of filling glue is carried out, such that the embedded component is fixed in the through hole. Thereafter, the supporting board is removed. Finally, the electrode of the embedded component is electrically connected to the second patterned circuit layer.

Disclosed is a method for combining two plates in the fabrication process of an enclosure baseplate of a printed circuit or an integrated circuit. The method includes the following steps: splicing two chip plates through a bonding sheet so as to make a machining plate which is big in thickness, higher in rigidity and can satisfy common equipment machining requirements; processing pattern transfer to the spliced machining plate and developing a necessary circuit diagram of a conductor on the surface of the machining plate; developing an insulating medium layer and a conducting copper layer on the surface of the newly developed circuit diagram of the conductor through the method of lamination; repeating above processes so as to form a multilayer machining plate; separating the machining plate at two sides of the splicing sheet from the splicing sheet after the machining plate reaches certain thickness and rigidity, thus forming two machining plates; and respectively processing the two machining plates through regular lamination, boring, electroplating and pattern transfer techniques until the necessary circuit board and the enclosure baseplate are finished. The method requires no special equipment or machining tools and can reduce cost by a large margin and improve production efficiency and yield.

A wiring structure includes a general signal line, a differential signal line having a pair of signal wiring lines and a reference potential layer. The signal wiring lines respectively transmit differential signals of which waveforms are inverted from each other. The reference potential layer is arranged to have a distance from the general signal line and the differential signal line, and has a non-formed portion in a region to be electromagnetically coupled to the differential signal line.

On both surfaces of an electric insulating material 1, a surface conductive layer 2A and a back surface conductive layer 2B are formed by transcription. Further, a via hole 5 penetrating through the surface conductive layer 2A and the electric insulating material 1 is provided. After forming a photosensitive plating resist pattern 14, the via hole 5 is filled with a copper plating filler 15, and the surface wiring layer 9A and the back surface wiring layer 9B are formed. Thereafter, the photosensitive plating resist pattern 14 as well as the surface conductive layer 2A and the back surface conductive layer 2B provided under the photosensitive plating resist pattern 14 are removed to fabricate a double-sided wiring board 11.

The invention discloses a four-channel microwave T/R module. The four-channel microwave T/R module has a common cavity structure consisting of the same four independent T/R channels, wherein all the components are MMICs (Monolithic Microwave Integrated Circuits) being integrally fabricated on the same multilayer circuit board. The four-channel microwave T/R module is characterized in that a microwave device is a multifunctional MMIC bare chip integrated with a phase shifter, an attenuator, a working state switch, an amplitude limiting low noise amplifier and a driver; and the multi-layer circuit board is an HTCC multi-layer circuit board. The four-channel microwave T/R module has the advantages of compact structure, small size, high wiring density, low material cost, high mechanical strength, stable chemical performance, corrosion resistance, high temperature resistance, multiple channels, high performance, high reliability, high integration degree, light weight, low power consumptionand high heat dissipation characteristic, and can monitor the transmission and reception phases of each T/R channel. Compared with an existing microwave T/R module, the four-channel microwave T/R module has the advantages that the weight and volume of the microwave T/R module are reduced by 30 percent or more under the same function and index conditions. The four-channel microwave T/R module can be widely used in airborne, shipborne, spaceborne phased array radar and communication fields.

The present invention introduces methods of creating floor plans and placements for non Manhattan integrated circuits with existing electronic design automation tools. To create a floor plan, an existing Manhattan based floor planning tool is used. The die size for the floor plan is reduced to take into account the improved wiring density of non Manhattan wiring. A non Manhattan global router is then used on the floor plan to create pin placements. The floor plan may create a floor plan having circuit modules with beveled corners to take advantage of diagonal wiring. To create a placement, an existing Manhattan based placer is first used to create an initial placement. The initial placement is then processed by a non Manhattan aware post processor. The post processor performs local optimizations on the initial placement to improve the placement for a non Manhattan routed integrated circuit.

The invention discloses a superpixel-based copper surface defect detection method for a flexible IC packaging substrate, and the method comprises the steps: carrying out the filtering and preliminarythreshold segmentation of an original color image, and obtaining a superpixel segmentation image through employing a simple linear iterative clustering method; Selecting a superpixel of the copper surface area according to the brightness characteristic, extracting the characteristic of the superpixel of the copper surface area by combining the global characteristic of the image, calculating the brightness difference degree of pixel points in the superpixel, finding out a hole in the copper surface, and oxidizing a defect area; Secondly, finding out a superpixel located at the joint of the copper surface and the background according to the gradient and neighborhood information of the pixel, obtaining boundary pixel points located at the edge of the copper surface, obtaining a continuous copper surface line by scanning the neighborhood of the boundary pixel points, and performing feature extraction and analysis on the edge pixel points on the copper surface line to find out the line sawtooth defect. Defects such as holes, oxidation and circuit sawteeth of a copper surface can be accurately positioned.

The invention relates to a method for manufacturing a package substrate without a core layer and a conductive structure of the package substrate. The structure manufactured by the method comprises a storey-adding structure which is provided with a first solder mask layer and a second solder mask layer, wherein, a plurality of openings are formed at the first solder mask layer and the second solder mask layer to expose an electric connection gasket of the storey-adding structure, and the structure also comprises a plurality of solder projections formed on the electric connection gasket and a solder layer. Therefore, the package substrate without the core layer manufactured by the invention can provide a shorter conductive path, improves the wiring density of a circuit and reduces the manufacturing procedures, and the thickness of a whole product is reduced to achieve the light, thin and small function.

A wiring board with embedded component and integrated stiffener is characterized in that an embedded semiconductor device, a first routing circuitry, an encapsulant and an array of vertical connecting elements are integrated as an electronic component disposed within a through opening of a stiffener, and a second routing circuitry is disposed beyond the through opening of the stiffener and extends over the stiffener. The mechanical robustness of the stiffener can prevent the wiring board from warping. The embedded semiconductor device is electrically coupled to the first routing circuitry and surrounded by the vertical connecting elements in electrical connection with the first and second routing circuitries. The first routing circuitry provides primary fan-out routing for another semiconductor device to be assembled on the wiring board, whereas the second routing circuitry not only provides further fan-out wiring structure, but also mechanically binds the electronic component with the stiffener.

A semiconductor device mounting board in which high density packaging and fining can be realized in response to smaller pitches while ensuring excellent reliability of package by improving a conventional wiring board, its producing method and inspecting method, and a semiconductor package. The semiconductor device mounting board in characterized by comprising a wiring structure film consisting of an insulation layer and a wiring layer, a first electrode pattern provided on one surface of the wiring structure film such that at least the side circumference thereof touches the insulation layer but at least the lower surface thereof does not touch the insulation layer and the surface of the insulation layer provided with the first electrode pattern is coplanar with the lower surface of the first electrode pattern, a second electrode pattern formed on the surface opposite to the first electrode pattern, an insulator film provided with an opening pattern being confined in the first electrode pattern, and a metal support provided on the surface of the insulator film.

The invention relates to a production method of multilayer high-density interconnection printed circuit board, wherein one or two circuit faces of the baseboard are provided with a first wiring layer, the first wiring layer is formed with a first conductive block for interconnecting the wiring layers. The production method comprises: forming an insulated medium layer covering the first wiring layer and a first conductive block on the baseboard, forming a conductive layer on the insulated medium layer, forming a first insulated layer on the conductive layer and forming a second wiring layer picture on the first insulated layer, depositing conductive material to form a second wiring layer, forming a second insulated layer on the second wiring layer and the first insulated layer, etching the second insulated layer to form an opening exposing the second wiring layer, depositing the second conductive block in the opening, deleting the second insulated layer, the first insulated layer and the conductive layer under the first insulated layer, repeating aforementioned processes to form a multilayer high-density interconnection printed circuit board. The method simplifies the production.

Provided is a method for manufacturing a printed-circuit board, which can form bumps at substantially identical heights on connection pads having different opening diameters of a solder resist. Diametrically-small bumps (78S), which are made high of solder balls (77) mounted in diametrically-small openings (71S) of a solder resist layer (70), are flattened to have the same height as that of the solder bumps (78P) of diametrically-large openings (71P). The solder bumps (78S) of the diametrically small openings (71S) and the solder bumps (78P) of the diametrically large openings (71P) are identical in the solder quantity. No connection occurs at the solder bumps (78S) of the diametrically small openings (71S) so that the connection reliability between an IC chip (90) and a multilayer printed-circuit board (10) can be retained.