Method for preparing seedless layer package substrate

A technology of packaging substrate and coreless layer, which is applied in the direction of multilayer circuit manufacturing, semiconductor/solid-state device manufacturing, electrical components, etc. Thickness etc.

Inactive Publication Date: 2009-04-15
PHOENIX PRECISION TECH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

As a result, the thickness of the final multilayer substrate cannot be reduced, which is not conducive to the miniaturization trend of semiconductor packaging substrates
When the thickness of the core substrate is less than 60 μm, the manufacture of the multilayer substrate will face severe challenges, and its producti...

Method used

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  • Method for preparing seedless layer package substrate
  • Method for preparing seedless layer package substrate
  • Method for preparing seedless layer package substrate

Examples

Experimental program
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Embodiment Construction

[0051] see Figures 2A to 2Q A schematic cross-sectional view of a coreless layer packaging substrate in a preferred embodiment of the present invention. First, if Figure 2A As shown, a carrier board 201 made of metal is provided. Next, if Figure 2B As shown, a first resist layer 202 of high photosensitive polymer material is pressed on the carrier 201 . Another example Figure 2C As shown, a plurality of first openings 202a are formed on the first resist layer 202 by means of exposure and development to expose the carrier 201 thereunder. Next, if Figure 2D ,and Figure 2E As shown, an etch stop layer 204 of nickel metal and a first metal layer 205 of copper metal are sequentially electroplated in the first openings 202a. In this embodiment, the first resist layer 202 is a dry film photoresist layer.

[0052] see Figure 2F , stripping and removing the first resistance layer 202 . Another example Figure 2G As shown, a dielectric layer 206 of an ABF (Ajinomoto Bu...

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Abstract

The invention relates to a method for manufacturing a package substrate without a core layer and a conductive structure of the package substrate. The structure manufactured by the method comprises a storey-adding structure which is provided with a first solder mask layer and a second solder mask layer, wherein, a plurality of openings are formed at the first solder mask layer and the second solder mask layer to expose an electric connection gasket of the storey-adding structure, and the structure also comprises a plurality of solder projections formed on the electric connection gasket and a solder layer. Therefore, the package substrate without the core layer manufactured by the invention can provide a shorter conductive path, improves the wiring density of a circuit and reduces the manufacturing procedures, and the thickness of a whole product is reduced to achieve the light, thin and small function.

Description

technical field [0001] The present invention relates to a manufacturing method of a seedless layer packaging substrate and a conductive structure of the packaging substrate. The manufacturing method especially refers to a seedless layer suitable for a structure without through holes, which can increase the circuit wiring density and reduce the manufacturing process. A method for manufacturing a packaging substrate. Background technique [0002] With the vigorous development of the electronic industry, electronic products are gradually entering the research and development direction of multi-function and high performance. In order to meet the packaging requirements of high integration and miniaturization of semiconductor packages, the packaging substrates provided for multiple active and passive components and circuit connections have gradually evolved from single-layer boards to multi-layer boards. In a limited space, the available wiring area on the packaging substrate can...

Claims

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Application Information

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IPC IPC(8): H01L21/48H01L23/498H05K3/46H05K1/02
CPCH01L2924/0002
Inventor 陈柏玮王仙寿许诗滨
Owner PHOENIX PRECISION TECH CORP
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