5630results about "Electrical connection printed elements" patented technology

Disclosed are appendage mountable electronic systems and related methods for covering and conforming to an appendage surface. A flexible or stretchable substrate has an inner surface for receiving an appendage, including an appendage having a curved surface, and an opposed outer surface that is accessible to external surfaces. A stretchable or flexible electronic device is supported by the substrate inner and/or outer surface, depending on the application of interest. The electronic device in combination with the substrate provides a net bending stiffness to facilitate conformal contact between the inner surface and a surface of the appendage provided within the enclosure. In an aspect, the system is capable of surface flipping without adversely impacting electronic device functionality, such as electronic devices comprising arrays of sensors, actuators, or both sensors and actuators.

A first via land of a wiring layer on a first surface of a first insulation layer that is a rigid layer and a second via land of a wiring layer on a second surface of a second insulation layer that is a flexible layer are electrically and mechanically connected with a conductive pillar pierced through a third insulation layer disposed between the first insulation layer and the second insulation layer. In such a structure, a wiring board that can mount a highly integrated semiconductor device, that is small and thin, and that has high reliability can be accomplished.

A space-efficient substantially transparent mutual capacitance touch sensor panel can be created by forming columns made of a substantially transparent conductive material on one side of a first substantially transparent substrate, forming rows made of the substantially transparent conductive material on one side of a second substantially transparent substrate, adhering the two substrates together with a substantially transparent adhesive, bringing column connections down to the second substrate using vias, and routing both the column and row connections to a single connection area on the second substrate. In addition, in some embodiments some of the row connections can be routed to a second connection area on the second substrate to minimize the size of the sensor panel.

A method of producing a chip embedded substrate is disclosed. This method comprises a first step of mounting a semiconductor chip on a first substrate on which a first wiring is formed; and a second step of joining the first substrate with a second substrate on which a second wiring is formed. In the second step, the semiconductor chip is encapsulated between the first substrate and the second substrate and electrical connection is made between the first wiring and the second wiring so as to form multilayered wirings connected to the semiconductor chip.

The present invention relates to stretchable interconnects which can be made in various geometric configurations, depending on the intended application. The stretchable interconnects can be formed of an electrically conducting film or an elastomer material to provide elastic properties in which the interconnects can be reversibly stretched in order to stretch and relax the elastomer material to its original configuration. Alternatively, stretchable interconnects can be formed of an electrically conducting film or a plastic material to provide stretching of the material to a stretched position and retaining the stretched configuration. The stretchable interconnect can be formed of a flat 2-dimensional conductive film covering an elastomeric or plastic substrate. When this structure is stretched in one or two dimensions, it retains electrical conduction in both dimensions. Alternatively, the stretchable and/or elastic interconnects can be formed of a film or stripe that is formed on an elastomeric or plastic substrate such that it is buckled randomly, or organized in waves with long-range periodicity. The buckling or waves can be induced by various techniques, including: release of built-in stress of the conductive film or conductive stripe; pre-stretching the substrate prior to the fabrication of the conductive film or conductive stripe; and patterning of the surface of the substrate prior to the fabrication of the metal film. The stretchable interconnect can be formed of a plurality of conductive films or conductive stripes embedded between a plurality of layers of a substrate formed of an elastomer or plastic.

A compact, self-contained, personal key is disclosed. The personal key comprises a USB-compliant interface releaseably coupleable to a host processing device; a memory; and a processor. The processor provides the host processing device conditional access to data storable in the memory as well as the functionality required to manage files stored in the personal key and for performing computations based on the data in the files. In one embodiment, the personal key also comprises an integral user input device and an integral user output device. The input and output devices communicate with the processor by communication paths which are independent from the USB-compliant interface, and thus allow the user to communicate with the processor without manifesting any private information external to the personal key.

A memory architecture includes a first substrate containing multiple memory devices and a first channel portion extending across the first substrate. The architecture further includes a second substrate containing multiple memory devices and a second channel portion extending across the second substrate. A connector couples the first channel portion to the second channel portion to form a single channel. The connector includes a first slot that receives an edge of the first substrate and a second slot that receives an edge of the second substrate. Another connector has a pair of slots that receive opposite edges of the first and second substrates. The channel portions extend across the substrates in a substantially linear path. Each channel portion includes multiple conductors having lengths that are approximately equal.

Embodiments of the present invention relate generally to solder bump formation and semiconductor device assemblies. One embodiment related to a method for forming a bump structure includes providing a semiconductor device (10) having a bond pad (12), and forming a first masking layer (20) overlying the bond pad (12). The first masking layer (20) is patterned to form a first opening (22) overlying at least a portion of the bond pad (12). A second masking layer (40) is formed overlying the first masking layer (20), and the second masking layer (40) is patterned to form a second opening (42) overlying at least a portion of the first opening (22). The method further includes forming a stud (30) at least within the first opening (22) and a solder bump (60) at least within the second opening (42).

Vertical holes are created in streets separating individual integrated circuit (IC) dies formed on a semiconductor wafer, the holes spanning saw-lines along which the wafer is to be later cut to separate the IC die from one another to form individual IC chips. The holes are then filled with conductive material. After the wafer is cut along the saw-lines, portions of the conductive material on opposing sides of the saw-lines remain on peripheral edges of the IC chip to form signal paths between the upper and lower surfaces of the IC chips.

A method of manufacturing a fabric article to include electronic circuitry in which a flex circuit is assembled to include conductive traces and pads on a flexible substrate, a fabric article is placed on a rigid surface, and the substrate of the flex circuit is secured to the fabric article. Also disclosed is a fabric article which includes electronic circuitry and an electrically active textile article.

A 3D interconnect structure comprising an ultra-thin interposer having a plurality of ultra-high density of through-via interconnections defined therein. The 3D interposer electrically connects first and second electronic devices in vertical dimension and has the same or similar through-via density as the first or second electronic devices it connects. The various embodiments of the interconnect structure allows 3D ICs to be stacked with or without TSVs and increases bandwidth between the two electronic devices as compared to other interconnect structures of the prior art. Further, the interconnect structure of the present invention is scalable, testable, thermal manageable, and can be manufactured at relatively low costs. Such a 3D structure can be used for a wide variety of applications that require a variety of heterogeneous ICs, such as logic, memory, graphics, power, wireless and sensors that cannot be integrated into single ICs.

A printed circuit board is disclosed. A top layer power supply pattern and a top layer ground pattern are formed. The top layer power supply pattern and the top layer ground pattern are connected to a power supply layer and a ground layer through a plurality of viaholes, respectively. A plurality of capacitors or a plurality of capacitor resistor series circuits are disposed at predetermined intervals between the top layer power supply pattern and the top layer ground pattern.

Improved termination features for multilayer electronic components are disclosed. Monolithic components are provided with plated terminations whereby the need for typical thick-film termination stripes is eliminated or greatly simplified. Such termination technology eliminates many typical termination problems and enables a higher number of terminations with finer pitch, which may be especially beneficial on smaller electronic components. The subject plated terminations are guided and anchored by exposed internal electrode tabs and additional anchor tab portions which may optionally extend to the cover layers of a multilayer component. Such anchor tabs may be positioned internally or externally relative to a chip structure to nucleate additional metallized plating material. External anchor tabs positioned on one or both of top and bottom surfaces of a monolithic structure can facilitate the formation of selective wrap-around plated terminations. The disclosed technology may be utilized with a plurality of monolithic multilayer components, including interdigitated capacitors, multilayer capacitor arrays, and integrated passive components. A variety of different plating techniques and termination materials may be employed in the formation of the subject self-determining plated terminations.

A multilayer resin wiring board includes a metal core substrate having a first main surface and a second main surface; a plurality of wiring layers located on the first and second main surfaces of the metal core substrate; a plurality of insulating resin layers, each intervening between the metal core substrate and the wiring layers and between the metal core substrate and the wiring layers and between the wiring layers; and a via formed on the wall of a through hole for connection to the metal core substrate extending through the insulating resin layers and the metal core substrate so as to establish electrical conductivity to the metal core substrate. The metal core substrate has a thin portion which is thinner than the remaining portion of the metal core substrate. The through hole for connection to the metal core substrate is formed through the thin portion by laser machining.

Disclosed is an optical printed circuit board (PCB) having a multi-channel optical waveguide, which comprises: an optical waveguide having an optical path for transmitting light beams; a groove for penetrating the optical waveguide; and an optical interconnection block inserted in the groove and connected to the optical waveguide to transmit the light beams, wherein the optical interconnection block includes an optical fiber bundle bent by the angle of 90°. The optical interconnection block connects a plurality of multi-layered optical waveguides to transmit light beams to the optical waveguides. The optical fiber bundle is installed as a medium of the multi-channel optical waveguide in the optical PCB.

A multilayer printed circuit board has an IC chip 20 included in a core substrate 30 in advance and a transition layer 38 provided on a pad 24 of the IC chip 20. Due to this, it is possible to electrically connect the IC chip to the multilayer printed circuit board without using lead members and a sealing resin. Also, by providing the transition layer 38 made of copper on the die pad 24, it is possible to prevent resin residues on the pad 24 and to improve connection characteristics between the pad 24 and a via hole 60 and reliability.

A conducting thin-film nanoprobe card fabrication method includes the steps of: (a) arranging nanotubes on a substrate in vertical; (b) covering the nanotubes with a liquid polymeric resin and then hardening the polymeric resin to form a conducting nanomembrane; (c) removing a part of the polymeric resin from the conducting nanomembrane to expose one end of each nanotube to outside; (d) removing the substrate and preparing a ceramic substrate having contacts at one side and metal bumps at the other side and plated through holes electrically respectively connected with the contacts and the metal bumps; (e) mounting the nanomembrane on the ceramic substrate to hold the nanotubes in contact with the contacts of the ceramic substrate, and (f) forming recessed holes in the nanomembrane by etching and inserting a metal rod in each recessed hole to form a respective probe.

To provide a suspension board with circuit that enables its terminals to be bonded to the other terminals with sufficient strength with simple structure, to ensure sufficient bonding reliability, the suspension board with circuit 11 includes a suspension board 12, a base layer 13 formed on the suspension board 12, and a conductive layer 14 formed on the base layer 13 and a cover layer 18 with which the conductive layer 14 is covered, wherein external connection terminals 17 to be bonded to terminals 28 of a read/write board 29 are formed without the suspension board 12 and/or the base layer 13 being formed.

A display device having a highly reliable electrostatic capacitive type touch panel which allows finger touch inputting and possesses excellent detection sensitivity is provided. With respect to X electrodes and Y electrodes which are formed on an electrostatic capacitive type touch panel, either one of the X electrodes and the Y electrodes is divided corresponding to a ratio between the number of X electrodes and the number of Y electrodes, and a floating electrode is formed in gaps formed along with the reduction of area of the electrode thus adjusting the area of the electrode. Due to the contraction of the area of the individual electrode, a noise level can be lowered more compared to lowering of a signal level and hence, an S/N ratio can be increased thus enhancing the detection sensitivity. Further, a line is branched on a flexible printed circuit board, intersecting lines are formed on a back surface of the flexible printed circuit board, and the intersecting lines are arranged to orthogonally intersect with lines formed on a front surface of the flexible printed circuit board thus lowering line capacitance.

[Object] To provide a multilayer assembly that excels in pore properties, is flexible, and is satisfactorily handled and processed; and a method of producing the multilayer assembly.

[Solving Means] A multilayer assembly includes a base and, arranged on at least one side thereof, a porous layer and has a large number of continuous micropores with an average pore diameter of 0.01 to 10 μm. The multilayer assembly suffers from no interfacial delamination between the base and the porous layer when examined in a tape peeling test according to the following procedure:

• • Tape Peeling Test

A 24-mm wide masking tape [Film Masking Tape No. 603 (#25)] supplied by Teraoka Seisakusho Co., Ltd. is applied to a surface of the porous layer of the multilayer assembly and press-bonded thereto with a roller having a diameter of 30 mm and a load of 200 gf to give a sample; and the sample is subjected to a T-peel test with a tensile tester at a peel rate of 50 mm/min.

Enclosed re-programmable non-volatile memory cards include at least two sets of electrical contacts to which the internal memory is connected. The two sets of contacts have different patterns, preferably in accordance with two different contact standards such as a memory card standard and that of the Universal Serial Bus (USB). One memory card standard that can be followed is that of the Secure Digital (SD) card. The cards can thus be used with different hosts that are compatible with one set of contacts but not the other. A sleeve that is moveable by hand may be included to expose the set of contacts being used.

A process of an embedded chip package structure includes following steps. Firstly, a metal core layer having a first surface, a second surface opposite to the first surface, an opening, and a number of through holes are provided. The opening and the through holes connect the first surface and the second surface. A chip is then disposed in the opening. Next, a dielectric layer is formed in the opening and the through holes to fix the chip in the opening. Thereafter, a number of conductive vias are respectively formed in the through holes and insulated from the metal core layer by a portion of the dielectric layer located in the through holes. A circuit structure is then formed on the first surface of the metal core layer by performing a build-up process, and the circuit structure electrically connects the chip and the conductive vias.

An apparatus for suppressing noise in an electronic device includes a multiple layer structure in which localized arrays of chip capacitors and/or patches around sources of electromagnetic waves are used. The PCB includes multiple conductive layers at different potentials, dielectric layers separating the conductive layers, conductive rods extending between at least two of the conductive layers, and a layer of patches disposed adjacent or on one or more of the conductive layers. The conductive rods are connected to one of the conductive layers and chip capacitors connect the conductive rods to another of the conductive layers. A particular location can be effectively isolated from noise using a few unit cells of an array of patches/capacitors partially or completely surrounding the particular location.

The present invention relates to an embedded chip printed circuit board in which a space required for embedding a chip is formed to a desired depth depending on various thicknesses of chips to be embedded, and thus, the circuit line for the electrical connection between the embedded chip and the circuit pattern layer can be formed to be relatively short, thereby maximizing space efficiency and decreasing inductance at high frequencies. In addition, a method of manufacturing such an embedded printed circuit board is also provided.

This specification describes techniques for fabricating connections between pairs of components. Each connection includes an array of bumps on a male component, and a matching array of wells filled with bonding material on a female component. The bump/well connections can be spaced with a pitch of less than 100 microns. One application of the invention is the attachment of electronic components to interconnection circuits or circuit assemblies to form electronic modules. The electronic components may be IC chips or high-density interconnect cables. Another application is alignment of optical components. The direct chip attachment techniques are described in the context of fabrication, assembly, test, rework, and cooling of electronic modules employing flip chip components. The preferred method is to fabricate the module on a glass carrier using a release layer so that the carrier can be removed after most of the processing is done.

A two-step masking process is disclosed for forming a ball limiting metallurgy (BLM) pad structure for a solder joint interconnection used between a support substrate and a semiconductor chip. A solder non-wettable layer and a solder wettable layer are deposited on the surface of a support substrate or semiconductor chip which are to be connected. A phased transition layer is deposited between the wettable and non-wettable layers. A thin photo-resist mask defines an area of the solder wettable and phased layers which are etched to form a raised, wettable frustum cone portion. A second mask is deposited on the surface of the support substrate or semiconductor chip, and has an opening concentrically positioned about the frustum cone. Solder is deposited in the opening and covers the frustum cone and the area about its periphery. When solidified, the solder, acting as a mask, is used to sub-etch the underlying solder non-wettable layer thereby defining the BLM pad. When reflowed, the solder beads away from the surface of the solder non-wettable layer to form a ball which securely adheres about the frustum cone.

A substrate for reducing electromagnetic emissions is provided. The substrate may include a plurality of ground layers, signal layers and power layers. All of the layers other than the ground layer are provided with a ground ring that may extend around the perimeter of the layer. The ground rings are electrically coupled together by ground stitching or vias that are randomly spaced. The random spacing of the ground stitching is based on the operating frequencies of the integrated circuit devices mounted on the substrate. Additional shielding may be provided by providing a cover assembly made of any conductive material that is coupled to the exposed ground rings on the uppermost and lowermost surfaces of the substrate. The cover assembly is coupled to the exposed ground rings in a randomized pattern. The device provides a virtual electrical ground cage in which the internal signal layers are totally enclosed, thereby reducing electromagnetic emissions.

A flex-rigid printed wiring board is proposed which includes rigid substrates each formed from an insulative base material and a conductor circuit provided on the insulative base material, and a bendably flexible substrate formed from an insulative base material, conductor circuit provided on the insulative base material and a cover lay to cover the conductor circuit, the rigid and flexible substrates being connected to each other. As the insulative base material of the flexible substrate, there is adopted a bendable base material formed by impregnating a glass cloth with a resin and drying it. An conductor circuit is formed on one side of the flexible substrate while a dummy pattern is formed on the other side near a portion thereof where the flexible substrate is to be bent. Thus, the proposed flex-rigid printed wiring board is excellent in connection reliability, permitting to prevent the base material from being easily deformed near the bending portion, conductor circuit from being broken and the flexible substrate from being waved. The similar effect can also be attained with the wiring patterns of the conductor circuit on the flexible substrate being formed wide or curved in the width direction at the bending portion.

A method and apparatus for securing a token from unauthorized use is disclosed. The method comprises the steps of receiving a first message transmitted from a host processing device and addressed to a PIN entry device according to a universal serial bus (USB) protocol; accepting a PIN entered into the PIN entry device; and transmitting a second message comprising at least a portion of the first message and the PIN from the PIN entry device to the token along a secure communication path. In another embodiment, the present invention describes an apparatus for securing a token from unauthorized use, comprising a PIN entry device, communicably coupleable to a host processing device transmitting a first message addressed to the PIN entry device, and communicatively coupleable to the token according to a universal serial bus USB protocol, the PIN entry device comprising a user input device, for accepting a user-input PIN; and a processor, communicatively coupled to the user input device, the processor for receiving the first message and combining the first message with the user-input PIN, and for producing a second message having at least a portion of the first message and the user-input PIN.

A radio frequency identification tag comprising a first substrate and a second substrate is disclosed. An antenna element is disposed on the first substrate, and a first contact pad and a second contact pad is disposed on the second substrate. A circuit is coupled to the first and second contact pads, and the first and second contact pads are designed to make electrical contact with the antenna element.