1245 results about "Redistribution layer" patented technology

The invention discloses a three-dimensional integrated packaging structure and a packaging process thereof. The three-dimensional integrated packaging structure comprises a flip or normal chip with a functional surface and an opposite back surface; the rewiring layer and the chip are vertically stacked and electrically connected with each other; electrically leading the rewiring layer out of the packaging structure; the stacking direction of the inductor and the chip is parallel to the thickness direction of the chip, the inductor and the chip, the rewiring layer and the lead-out structure are physically isolated through an insulating medium layer, the inductor is of a spiral, multi-ring layer overlapping or sectional winding structure, the inductor comprises a magnetic core, a spiral coil surrounding the surface of the magnetic core is formed through etching and electroplating processes, and the lead-out structure is arranged on the surface of the spiral coil. The spiral coil comprises a circuit A, a circuit B and a circuit C, and the magnetic core and the spiral coil are encapsulated by the insulating medium layer. The inductor and the chip are stacked in an inverted or normal mode, the three-dimensional structure saves space, reduces parasitic inductance, resistance and the like, signal transmission is stable, electromagnetic interference is small, and the three-dimensional structure is suitable for the chip packaging field of miniaturization, high integration and the like.

The invention discloses a preparation method and structure of an interposer embedded with a silicon bridge and a high-density silicon capacitor, and belongs to the field of advanced packaging of integrated circuits. The method can be used for 2.5 D advanced packaging high-density interconnection; the interposer structure comprises an interposer back RDL rewiring layer, an intermediate layer which is formed by embedding a silicon bridge and a high-density silicon capacitor by using a high-molecular epoxy resin material EMC, and an RDL rewiring layer on the front side of the interposer. High-density vertical interconnection between the upper RDL layer and the lower RDL layer is achieved through an electroplating ultrahigh copper column penetrating through the resin material, micron-level and submicron-level ultrahigh-density interconnection can be achieved through a silicon bridge embedded in the EMC resin, and high-performance packaging-level power supply decoupling can be achieved through a high-density silicon capacitor embedded in the resin. The preparation method of the structure is easy to implement, the cost is greatly reduced compared with that of the TSV silicon adapter plate interposer, and the method can be used for large-scale mass production of 2.5 D interposers.

A method of forming a semiconductor structure includes the following operations. First deep vias are formed in a first glass layer. A first redistribution layer structure is formed on a first side of the first glass layer, and the first redistribution layer structure is electrically connected to the first deep vias. A carrier is bonded to the first redistribution layer structure. The first glass layer is grinded until surfaces of the first deep vias are exposed. A second redistribution layer structure is formed on a second side of the first glass layer opposite to the first side, and the second redistribution layer structure is electrically connected to the first deep vias.

The invention provides a high-density photoelectric common connection pinboard based on a low-loss silicon nitride grating coupler. The invention aims to overcome the difficulty that the existing photoelectric heterogeneous chip is difficult to integrate, stack and package, and realizes high-density interconnection between the chip and the interposer by using a grating coupling structure and a silicon through hole technology, thereby realizing high-integration low-loss packaging of the heterogeneous chip on the interposer. According to the invention, high-efficiency optical interconnection between the heterogeneous chip and the photoelectric co-connection intermediate layer is realized through the high-efficiency grating coupler, and high-density electrical interconnection between the chip and the photoelectric co-connection intermediate layer is realized through the TSV technology and the RDL technology. Meanwhile, the optical interconnection efficiency between the interposer and the chip is improved by utilizing the electrode patterning advantage of the RDL technology, and the self-alignment between the chip and the interposer is realized. The method has extremely high compatibility to the packaging scene of the existing photoelectric heterogeneous chip, so that the method has great significance in improving the integration density and reducing the interconnection loss of a photoelectric heterogeneous integrated system and promoting the practicability of the photoelectric heterogeneous integrated system.

Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.

The embodiment of the invention provides a high-density redistribution interconnection packaging structure and a preparation method thereof, and relates to the technical field of chip packaging, and the packaging structure comprises a substrate rewiring layer, a first chip, a first plastic package body, a coating layer, an integrated rewiring layer, a first stacking rewiring layer, a second chip and a second plastic package body. Compared with the prior art, according to the high-density redistribution interconnection packaging structure provided by the embodiment of the invention, the first heat dissipation columns are additionally designed, so that the heat dissipation performance can be greatly improved, and an overheating phenomenon is slowed down. And meanwhile, the first heat dissipation column can be embedded in the first plastic package body and the coating layer at the same time, so that the binding force of each layer of the package structure is greatly improved, the structural stability is ensured, and the warping phenomenon of the package structure is relieved. Meanwhile, electrical conduction is achieved through the first conductive columns and the second conductive columns, parasitic inductance of the wiring layers is reduced, and the phenomena of short circuit, overheating and the like between the wiring layers caused by the electric leakage phenomenon are relieved.

A chip package includes a semiconductor structure and a redistribution layer. The semiconductor structure has a substrate, a first isolation layer, and a lower ground pad. The substrate has a top surface, a bottom surface opposite to the top surface, a through hole through the top surface and the bottom surface, and a sidewall surrounding the through hole. The first isolation layer is located on the top surface of the substrate, and the lower ground pad is located in the through hole. The redistribution layer extends from the bottom surface of the substrate to the lower ground pad along the sidewall. The redistribution layer covers the entire bottom surface of the substrate and electrically connects the lower ground pad.

The invention discloses a semiconductor packaging alignment mark manufacturing method and a semiconductor packaging alignment mark product. The semiconductor packaging alignment mark manufacturing method comprises the following steps that a cofferdam is manufactured at the position, corresponding to a TSV area, on light glass; the cofferdam is coated with bonding glue; bonding the wafer on the optical glass and grinding and thinning the wafer; performing etching to form a first-order groove and an alignment Mark; completing the etching of the silicon through hole; preparing a dielectric layer on the wafer; preparing a passivation layer on the dielectric layer; preparing an RDL (redistribution layer); pre-cutting a groove, and half-cutting to a cofferdam; preparing a solder mask layer; and planting or printing a solder ball, and then cutting into a final finished product. According to the invention, the alignment function of the photoetching process after pre-cutting can be realized, the overall process capability can be improved, the process steps are reduced, the product manufacturing period is shortened, the packaging cost is reduced, and the product competitiveness is improved; a special laser marking station is not needed, wafer surface pollution caused by laser marking is reduced, operators of the original laser marking station are saved, manpower and material resources are saved, one manufacturing process is saved, and the packaging cost is reduced.

Provided are a package structure and a method of forming the same. The package structure includes an interposer at least including a first die sandwiched between a first redistribution layer (RDL) structure and a second RDL structure. The first die includes: a device layer disposed on a substrate; an inductor device disposed on the device layer; an internal RDL structure disposed on the inductor device; a plurality of conductive connectors disposed on the internal RDL structure; and an inductor contact disposed aside the inductor device and electrically connecting the internal RDL structure and inductor device. The internal RDL structure is configured to redistribute an electrical signal from the inductor contact to the plurality of conductive connectors, thereby preventing the electromigration (EM) failure.

A semiconductor package includes a base substrate, an interposer package disposed on the base substrate, and first and second semiconductor chips disposed on the interposer package, the interposer package includes a first redistribution layer, a bridge chip including a bridge circuit, and a vertical connection structure including a plurality of wiring layers, and wherein each of the first semiconductor chip and the second semiconductor chip is electrically connected to the bridge circuit and the plurality of wiring layers through the first redistribution layer.

A package structure including a semiconductor die, a redistribution layer, a plurality of antenna patterns, a die attach film, and an insulating encapsulant is provided. The semiconductor die have an active surface and a backside surface opposite to the active surface. The redistribution layer is located on the active surface of the semiconductor die and electrically connected to the semiconductor die. The antenna patterns are located over the backside surface of the semiconductor die. The die attach film is located in between the semiconductor die and the antenna patterns, wherein the die attach film includes a plurality of fillers, and an average height of the die attach film is substantially equal to an average diameter of the plurality of fillers. The insulating encapsulant is located in between the redistribution layer and the antenna patterns, wherein the insulating encapsulant encapsulates the semiconductor die and the die attach film.

The invention relates to a substrate and a preparation method thereof and a chip packaging structure, the substrate comprises a core layer and a rewiring layer arranged on at least one side surface of the core layer, the core layer comprises an inorganic non-metal material layer, and the material thermal expansion coefficient of the inorganic non-metal material layer is 3 ppm / DEG C to 8 ppm / DEG C. The core layer is made of the inorganic non-metal material with a lower thermal expansion coefficient, so that the high-frequency signal loss of the substrate can be reduced, the difference between the effective thermal expansion coefficient of the core layer and the thermal expansion coefficient of the silicon chip can be reduced, the effective thermal expansion performance of the core layer is further matched with the silicon chip, and the service life of the silicon chip is prolonged. When the silicon chip is arranged on the substrate, the silicon chip is connected with the core layer through the rewiring layer, and the core layer and the silicon chip have good thermal expansion coefficient matching performance, so that the thermal stress between the substrate and the silicon chip can be reduced, the reliability is improved, and the risk of warping and layering between the substrate and the silicon chip is reduced.

Methods, systems, and devices for reconstructed semiconductor die evaluation and power delivery are described. A semiconductor device may be formed based on reconstructed wafers of operable dies and may support improved architectures for power delivery. In some examples, a first side of an interface block may be bonded with one or more volatile memory stacks. An evaluation procedure may be performed by probing one or more conductive pads in a second side of the interface block. The second side of the interface block may then be bonded to a first side of a host chip, and the host chip may be operable to control one or more functions of the interface block and the one or more volatile memory stacks. In some examples, a redistribution layer may be formed above a second side of the host chip to provide a power interface for the semiconductor device.

A method includes: forming an interposer die using a substrate, the interposer die including a plurality of conductive vias in the substrate; bonding the interposer die to a first redistribution layer (RDL); encapsulating the interposer die; forming a second RDL over the interposer die on a side opposite to the first RDL; bonding a first semiconductor die with one of the first RDL and the second RDL; and encapsulating the first semiconductor die.

A package structure and a manufacturing method thereof are provided. The package structure includes a redistribution layer, a conductive pillar, an active chip, an encapsulation layer, and another redistribution layer. The conductive pillar and the active chip are side by side disposed on the redistribution layer. The encapsulation layer surrounds the active chip and the conductive pillar, in which the encapsulation layer has a first through hole disposed between the active chip and the redistribution layer and a second through hole disposed between the conductive pillar and the redistribution layer, and a depth of the first through hole is less than a depth of the second through hole. The another redistribution layer is disposed on a side of the redistribution layer away from the redistribution layer and electrically connected to the redistribution layer through the conductive pillar.

The invention provides a semiconductor package and a method of manufacturing the same. The semiconductor package includes: a lower package including a first substrate, a first chip, and a first redistribution layer; and an upper package disposed on the lower package and including a second substrate, a second chip, and a plurality of internal connection terminals disposed on the second substrate and connected to the first redistribution layer. The first substrate comprises a concave part, the first chip is arranged in the concave part in a mode that the active surface of the first chip faces downwards, the heat conduction material fills the remaining space of the concave part, and the first redistribution layer is located on the first substrate, the heat conduction material and the first chip. The first chip includes a plurality of through silicon vias, the second chip is electrically connected to the plurality of through silicon vias via the plurality of internal connection terminals and the first redistribution layer, the first substrate further includes a signal via configured to communicate the semiconductor package with the outside, and a dummy via configured to dissipate heat of the first chip to the outside.

An electronic component device, includes: a redistribution layer, an electronic circuit chip and an optical circuit chip disposed on the redistribution layer, and a first sealing layer sealing the electronic circuit chip and the optical circuit chip, wherein the first sealing layer has an opening on an opposite side from a side of the redistribution layer, and a position of the opening at least partially overlaps with a position of the optical circuit chip.

A first die includes a first substrate and a first interconnect structure. A second die is bonded to the first die and includes a second substrate and a second interconnect structure, such that the first and second interconnect structures are arranged between the first and second substrates. A redistribution layer (RDL) stack is arranged on an outer side of the first die opposite the first interconnect structure. A heat path includes a through substrate via (TSV) extending from a conductive layer in the first interconnect structure, through the first substrate, and into the RDL stack. An RDL dielectric material is included in the RDL stack and separates the heat path from an ambient environment. A thermal conductivity of the RDL dielectric is over twenty times a thermal conductivity of an interconnect dielectric material of the first interconnect structure or of the second interconnect structure.

The preparation method of the glass-based top core plate comprises the following steps: providing a glass substrate, and forming an initial through hole in the glass substrate by adopting laser drilling; pressing a first dielectric material layer on the surface of the glass substrate and in the through hole; performing secondary laser drilling or mechanical drilling on the initial through hole to form a target through hole; electroplating the target through hole and forming a circuit; laminating the two glass substrates in the opposite directions of the dielectric material layers, and stacking a temporary substrate between the two glass substrates; performing primary layer adding of a second dielectric material on the stacked structure, wherein the layer adding number can be an odd number or an even number; removing the temporary base plate to realize plate disassembly; adding a third dielectric material on the surface of the top of the glass substrate after the glass substrate is detached; carrying out polish-brush planarization processing on the surface of the added layer to expose the circuit; forming redistribution layers on the planarized surface, wherein the number of the redistribution layers can be an odd number or an even number; according to the invention, the production yield can be improved, the warping of the substrate is reduced, the structural stability is enhanced, and the upper-layer RDL superfine circuit and the lower-layer thick circuit are conducted.

A package structure includes a circuit board, a package substrate, an electronic / photonic assembly, a film redistribution layer, a heat dissipation assembly, and an optical fiber assembly. The package substrate is disposed on the circuit board and electrically connected to the circuit board. The electronic / photonic assembly includes an ASIC assembly, an EIC assembly, and a PIC assembly. The EIC assembly and the PIC assembly are stacked and disposed on the package substrate and electrically connected to the package substrate via the film redistribution layer. An orthographic projection of the EIC assembly on the film redistribution layer is overlapped with an orthographic projection of the PIC assembly on the film redistribution layer. The heat dissipation assembly is disposed on the electronic / photonic assembly. The optical fiber assembly is disposed on the package substrate and optically connected to the PIC assembly.

A method of forming a semiconductor structure includes the following operations. First deep vias are formed in a first glass layer. A first redistribution layer structure is formed on a first side of the first glass layer, and the first redistribution layer structure is electrically connected to the first deep vias. A carrier is bonded to the first redistribution layer structure. The first glass layer is grinded until surfaces of the first deep vias are exposed. A second redistribution layer structure is formed on a second side of the first glass layer opposite to the first side, and the second redistribution layer structure is electrically connected to the first deep vias.

Methods, systems, and devices for reconstructed semiconductor die evaluation and power delivery are described. A semiconductor device may be formed based on reconstructed wafers of operable dies and may support improved architectures for power delivery. In some examples, a first side of an interface block may be bonded with one or more volatile memory stacks. An evaluation procedure may be performed by probing one or more conductive pads in a second side of the interface block. The second side of the interface block may then be bonded to a first side of a host chip, and the host chip may be operable to control one or more functions of the interface block and the one or more volatile memory stacks. In some examples, a redistribution layer may be formed above a second side of the host chip to provide a power interface for the semiconductor device.

A semiconductor device and a method for fabricating a semiconductor are described. The semiconductor device includes two modules, each module including two tiers, each tier including (i) a passive die including through-silicon vias (TSVs) arranged side-by-side laterally with a core die and (ii) bumps coupling the TSVs and an overhang portion of the core die of a second tier to the TSVs the first tier, the first module further including a bottom redistribution layer (RDL) on which the first second tier of the first module is disposed and a top RDL disposed on the second tier of the first module, the bottom RDL coupled to the bumps disposed on the first tier of the first module while the top RDL configured to couple the bumps of the first tier of the second module to the TSVs of the second tier of the first module in a one-to-one manner.

A semiconductor package includes an interposer, a lower semiconductor chip located on the interposer and including a chip through via, lower stack structures located on the interposer and spaced apart from the lower semiconductor chip in a horizontal direction, a lower molding layer located on the interposer, a redistribution layer located on the lower molding layer, the lower semiconductor chip, and the lower stack structures and electrically connected to the chip through via of the lower semiconductor chip, an upper semiconductor chip located on the redistribution layer and electrically connected to the redistribution layer, upper stack structures spaced apart from the upper semiconductor chip in the horizontal direction, located on the redistribution layer, and electrically connected to the redistribution layer, and an upper molding layer located on the redistribution layer and on side surfaces of the upper semiconductor chip and side surfaces of each of the upper stack structures.

An electronic module is provided that includes a microchannel cooler having a glass manifold contacting a first side of a microchannel chip, a plurality of functional semiconductor chips located face up on a second side of the microchannel chip. Each semiconductor chip of the plurality of functional semiconductor chips is coefficient of thermal expansion (CTE) matched, and a first redistribution layer (RDL) containing structure or organic interposer is located above and in electrical contact with the plurality of functional semiconductor chips. In either case, the first RDL containing structure and the organic imposer are not CTE matched to the functional semiconductor chips.

An embodiment semiconductor device may include a semiconductor die; one or more redistribution layers formed on a surface of the semiconductor die and electrically coupled to the semiconductor die; and an active or passive electrical device electrically coupled to the one or more redistribution layers. The active or passive electrical device may include a silicon substrate and a through-silicon-via formed in the silicon substrate. The active or passive electrical device may be configured as an integrated passive device including a deep trench capacitor or as a local silicon interconnect. The semiconductor device may further include a molding material matrix formed on a surface of the one or more redistribution layers such that the molding material matrix partially or completely surrounds the active or passive electrical device.

The invention discloses a vehicle gauge chip integrated packaging manufacturing process based on an etching technology. The vehicle gauge chip integrated packaging manufacturing process comprises the following steps: step 1, designing and preparing a substrate; step 2, preprocessing the chip; step 3, chip mounting and interconnection are carried out; step 4, plastic packaging and molding; 5, heat dissipation and reinforcement are carried out; step 6, image rotation correction and defect detection; step 7, performing post-working procedures and testing; high-density interconnection such as TSV (through silicon vias), RDL (redistribution layer) and micro bumps is realized by using an etching technology, the interconnection density is remarkably improved, the RDL wiring layer manufactured by using the etching technology has the line width less than 2 microns, high-density interconnection on the surface of a chip is realized, the integration level is further improved, the micro-channel is manufactured in the plastic package layer by using the etching technology, and the packaging efficiency is improved. And the copper radiating fins are embedded, so that the radiating efficiency is effectively improved, the problem of local heat accumulation caused by integration of the power chip and the logic chip is solved, a gap between the chip and the radiating cover plate is filled with a thermal interface material with high thermal conductivity, and the thermal resistance is reduced.

The invention discloses an integrated circuit packaging method, which comprises the following steps of: 1, constructing a thermal expansion gradual change buffer layer, and arranging a buffer transition layer with a thermal expansion coefficient changing step by step between a chip and a re-wiring layer to realize smooth transition of thermal deformation between different materials, so that interface stress concentration caused by mismatching of thermal expansion is reduced; 2, flexible stress absorption layers are introduced, and the flexible stress absorption layers with elastic deformation capacity are arranged between the chip and the rewiring layer and between the rewiring layer and the substrate. A gradual change buffer structure with a thermal expansion coefficient changing step by step is introduced between a chip and a re-wiring layer and between the re-wiring layer and a substrate, and a flexible stress absorption layer with an elastic deformation capability is combined, so that thermal expansion mismatch transits from sudden change to continuous change, and generation of thermal stress in packaging is weakened from the source.

The invention discloses a fan-out packaging structure and a preparation method thereof. The fan-out packaging structure comprises a power supply substrate; the adapter plate is located on one side of the power supply substrate and electrically connected with the power supply substrate; the redistribution layer is located on the side, away from the power supply substrate, of the adapter plate and electrically connected with the adapter plate; the functional chip layer is located on the side, away from the power supply substrate, of the redistribution layer and electrically connected with the redistribution layer; wherein the adapter plate comprises an organic plastic package layer and a plurality of conductive capacitor chips coated in the organic plastic package layer; the conductive capacitor chip is provided with a silicon through hole, and the silicon through hole in the conductive capacitor chip is used for providing a power signal of the power supply substrate to the functional chip in the functional chip layer through the redistribution layer. According to the technical scheme provided by the invention, the fan-out requirement of a large-size chip is met, the product yield and the effective DTC density are improved, and the problems of packaging warping and internal stress concentration are solved.

The invention discloses a semiconductor package and a semiconductor package assembly. The semiconductor package comprises a first interconnection structure; the first chip is arranged on the first interconnection structure and is coupled with the first interconnection structure; a first redistribution layer disposed on the first chip and coupled to the first chip; a molding compound disposed on the first interconnect structure and encapsulating the first chip and the first redistribution layer; and a through-mold via passing through the molding compound and connecting between the first redistribution layer and the first interconnect structure; the first chip comprises a first back connection structure and a second back connection structure, a first transistor layer; a first front connection structure; and a first carrier on the first interconnect structure and coupled to the first interconnect structure. Therefore, the thick power supply / ground wire and the thin signal wire are separately arranged, and mutual interference possibly existing between power supply / ground transmission and signal transmission can be avoided.