761 results about "Redistribution layer" patented technology

The invention discloses a preparation method and structure of an interposer embedded with a silicon bridge and a high-density silicon capacitor, and belongs to the field of advanced packaging of integrated circuits. The method can be used for 2.5 D advanced packaging high-density interconnection; the interposer structure comprises an interposer back RDL rewiring layer, an intermediate layer which is formed by embedding a silicon bridge and a high-density silicon capacitor by using a high-molecular epoxy resin material EMC, and an RDL rewiring layer on the front side of the interposer. High-density vertical interconnection between the upper RDL layer and the lower RDL layer is achieved through an electroplating ultrahigh copper column penetrating through the resin material, micron-level and submicron-level ultrahigh-density interconnection can be achieved through a silicon bridge embedded in the EMC resin, and high-performance packaging-level power supply decoupling can be achieved through a high-density silicon capacitor embedded in the resin. The preparation method of the structure is easy to implement, the cost is greatly reduced compared with that of the TSV silicon adapter plate interposer, and the method can be used for large-scale mass production of 2.5 D interposers.

The invention provides a high-density photoelectric common connection pinboard based on a low-loss silicon nitride grating coupler. The invention aims to overcome the difficulty that the existing photoelectric heterogeneous chip is difficult to integrate, stack and package, and realizes high-density interconnection between the chip and the interposer by using a grating coupling structure and a silicon through hole technology, thereby realizing high-integration low-loss packaging of the heterogeneous chip on the interposer. According to the invention, high-efficiency optical interconnection between the heterogeneous chip and the photoelectric co-connection intermediate layer is realized through the high-efficiency grating coupler, and high-density electrical interconnection between the chip and the photoelectric co-connection intermediate layer is realized through the TSV technology and the RDL technology. Meanwhile, the optical interconnection efficiency between the interposer and the chip is improved by utilizing the electrode patterning advantage of the RDL technology, and the self-alignment between the chip and the interposer is realized. The method has extremely high compatibility to the packaging scene of the existing photoelectric heterogeneous chip, so that the method has great significance in improving the integration density and reducing the interconnection loss of a photoelectric heterogeneous integrated system and promoting the practicability of the photoelectric heterogeneous integrated system.

A package structure including a semiconductor die, a redistribution layer, a plurality of antenna patterns, a die attach film, and an insulating encapsulant is provided. The semiconductor die have an active surface and a backside surface opposite to the active surface. The redistribution layer is located on the active surface of the semiconductor die and electrically connected to the semiconductor die. The antenna patterns are located over the backside surface of the semiconductor die. The die attach film is located in between the semiconductor die and the antenna patterns, wherein the die attach film includes a plurality of fillers, and an average height of the die attach film is substantially equal to an average diameter of the plurality of fillers. The insulating encapsulant is located in between the redistribution layer and the antenna patterns, wherein the insulating encapsulant encapsulates the semiconductor die and the die attach film.

A method includes: forming an interposer die using a substrate, the interposer die including a plurality of conductive vias in the substrate; bonding the interposer die to a first redistribution layer (RDL); encapsulating the interposer die; forming a second RDL over the interposer die on a side opposite to the first RDL; bonding a first semiconductor die with one of the first RDL and the second RDL; and encapsulating the first semiconductor die.

A package structure and a manufacturing method thereof are provided. The package structure includes a redistribution layer, a conductive pillar, an active chip, an encapsulation layer, and another redistribution layer. The conductive pillar and the active chip are side by side disposed on the redistribution layer. The encapsulation layer surrounds the active chip and the conductive pillar, in which the encapsulation layer has a first through hole disposed between the active chip and the redistribution layer and a second through hole disposed between the conductive pillar and the redistribution layer, and a depth of the first through hole is less than a depth of the second through hole. The another redistribution layer is disposed on a side of the redistribution layer away from the redistribution layer and electrically connected to the redistribution layer through the conductive pillar.

The preparation method of the glass-based top core plate comprises the following steps: providing a glass substrate, and forming an initial through hole in the glass substrate by adopting laser drilling; pressing a first dielectric material layer on the surface of the glass substrate and in the through hole; performing secondary laser drilling or mechanical drilling on the initial through hole to form a target through hole; electroplating the target through hole and forming a circuit; laminating the two glass substrates in the opposite directions of the dielectric material layers, and stacking a temporary substrate between the two glass substrates; performing primary layer adding of a second dielectric material on the stacked structure, wherein the layer adding number can be an odd number or an even number; removing the temporary base plate to realize plate disassembly; adding a third dielectric material on the surface of the top of the glass substrate after the glass substrate is detached; carrying out polish-brush planarization processing on the surface of the added layer to expose the circuit; forming redistribution layers on the planarized surface, wherein the number of the redistribution layers can be an odd number or an even number; according to the invention, the production yield can be improved, the warping of the substrate is reduced, the structural stability is enhanced, and the upper-layer RDL superfine circuit and the lower-layer thick circuit are conducted.

A semiconductor device and a method for fabricating a semiconductor are described. The semiconductor device includes two modules, each module including two tiers, each tier including (i) a passive die including through-silicon vias (TSVs) arranged side-by-side laterally with a core die and (ii) bumps coupling the TSVs and an overhang portion of the core die of a second tier to the TSVs the first tier, the first module further including a bottom redistribution layer (RDL) on which the first second tier of the first module is disposed and a top RDL disposed on the second tier of the first module, the bottom RDL coupled to the bumps disposed on the first tier of the first module while the top RDL configured to couple the bumps of the first tier of the second module to the TSVs of the second tier of the first module in a one-to-one manner.

The invention discloses a vehicle gauge chip integrated packaging manufacturing process based on an etching technology. The vehicle gauge chip integrated packaging manufacturing process comprises the following steps: step 1, designing and preparing a substrate; step 2, preprocessing the chip; step 3, chip mounting and interconnection are carried out; step 4, plastic packaging and molding; 5, heat dissipation and reinforcement are carried out; step 6, image rotation correction and defect detection; step 7, performing post-working procedures and testing; high-density interconnection such as TSV (through silicon vias), RDL (redistribution layer) and micro bumps is realized by using an etching technology, the interconnection density is remarkably improved, the RDL wiring layer manufactured by using the etching technology has the line width less than 2 microns, high-density interconnection on the surface of a chip is realized, the integration level is further improved, the micro-channel is manufactured in the plastic package layer by using the etching technology, and the packaging efficiency is improved. And the copper radiating fins are embedded, so that the radiating efficiency is effectively improved, the problem of local heat accumulation caused by integration of the power chip and the logic chip is solved, a gap between the chip and the radiating cover plate is filled with a thermal interface material with high thermal conductivity, and the thermal resistance is reduced.

The invention discloses an integrated circuit packaging method, which comprises the following steps of: 1, constructing a thermal expansion gradual change buffer layer, and arranging a buffer transition layer with a thermal expansion coefficient changing step by step between a chip and a re-wiring layer to realize smooth transition of thermal deformation between different materials, so that interface stress concentration caused by mismatching of thermal expansion is reduced; 2, flexible stress absorption layers are introduced, and the flexible stress absorption layers with elastic deformation capacity are arranged between the chip and the rewiring layer and between the rewiring layer and the substrate. A gradual change buffer structure with a thermal expansion coefficient changing step by step is introduced between a chip and a re-wiring layer and between the re-wiring layer and a substrate, and a flexible stress absorption layer with an elastic deformation capability is combined, so that thermal expansion mismatch transits from sudden change to continuous change, and generation of thermal stress in packaging is weakened from the source.

The invention discloses a semiconductor package and a semiconductor package assembly. The semiconductor package comprises a first interconnection structure; the first chip is arranged on the first interconnection structure and is coupled with the first interconnection structure; a first redistribution layer disposed on the first chip and coupled to the first chip; a molding compound disposed on the first interconnect structure and encapsulating the first chip and the first redistribution layer; and a through-mold via passing through the molding compound and connecting between the first redistribution layer and the first interconnect structure; the first chip comprises a first back connection structure and a second back connection structure, a first transistor layer; a first front connection structure; and a first carrier on the first interconnect structure and coupled to the first interconnect structure. Therefore, the thick power supply / ground wire and the thin signal wire are separately arranged, and mutual interference possibly existing between power supply / ground transmission and signal transmission can be avoided.

The invention provides a semiconductor structure and a preparation method thereof, and the semiconductor structure comprises a driving chip which comprises a first top surface and a first bottom surface which are oppositely disposed, and the first top surface is provided with a first bonding pad; the logic chip comprises a second top surface and a second bottom surface which are oppositely arranged, and the second top surface is provided with a second bonding pad; and the driving chip and the logic chip are bonded through the first bonding pad and the second bonding pad. Through bonding, the conductive columns and the rewiring layer, the bonding interfaces of the driving chip and the logic chip are in gap connection, and the transmission path between the driving chip and the logic chip is shortened.

A method for fabricating semiconductor device includes the steps of first providing a first substrate having a high-voltage (HV) region and a medium voltage (MV) region and a second substrate having a low-voltage (LV) region and a static random access memory (SRAM) region, in which the HV region includes a HV device, the MV region includes a MV device, the LV region includes a fin field-effect transistor (FinFET), and the SRAM region includes a SRAM device. Next, a bonding process is conducted by using hybrid bonding, through-silicon interposer (TSI) or redistribution layer (RDL) for bonding the first substrate and the second substrate.

A semiconductor module may include an interposer including an active local silicon interconnect (LSI) die, a first semiconductor die on the interposer, and a plurality of second semiconductor dies adjacent the first semiconductor die on the interposer and coupled to the first semiconductor die by the active LSI die. A method of forming a semiconductor module may include attaching an active local silicon interconnect (LSI) die to a carrier substrate, forming a molding material layer around the active LSI die, forming an upper redistribution layer (RDL) structure on the active LSI die and the molding material layer, attaching a first semiconductor die to the upper RDL structure; and attaching a plurality of second semiconductor dies to the upper RDL structure such that the plurality of second semiconductor dies is coupled to the first semiconductor die by the active LSI die.

The invention discloses a packaging structure, a preparation method thereof and electronic equipment. The packaging structure comprises a circuit board; the organic substrate is arranged on the circuit board and electrically connected with the circuit board, and a first groove is formed in the side, away from the circuit board, of the organic substrate; the local connection assembly is embedded into the organic substrate and is electrically connected with the organic substrate, and the local connection assembly comprises a glass substrate and a rewiring layer formed on the glass substrate; the photon integrated circuit chip is arranged in the first groove; the calculation chip is electrically connected to the rewiring layer in the local connection assembly; the electrical interface chip is located on the side, away from the circuit board, of the organic substrate, and the electrical interface chip is connected with the photon integrated circuit chip through a vertical interconnection piece and connected with the calculation chip; the optical waveguide assembly is arranged on the organic substrate and at least partially located above the photonic integrated circuit chip, and the optical waveguide assembly is connected to the photonic integrated circuit chip so as to perform optical signal coupling with the photonic integrated circuit chip.

The invention relates to a packaging structure and a preparation method thereof. The method comprises the following steps: providing a carrier plate; a dry film structure is formed on one side of the carrier plate, the dry film structure comprises a dry film layer and a conductive column, through holes are formed in the dry film layer, and at least part of the through holes are filled with the conductive column; a conductive structure is provided, the conductive structure comprises a main body part and protruding parts arranged on one side of the main body part, and the protruding parts are in one-to-one correspondence with the through holes; the conductive structure and the dry film structure are combined in a hot pressing mode, the protruding parts are embedded into the through holes to form solid-phase diffusion connection with the conductive columns, and the main body part is attached to the side, away from the carrier plate, of the dry film layer; and etching the main body part from one side, far away from the dry film layer, of the main body part to obtain a rewiring layer. According to the packaging structure and the preparation method thereof, the signal transmission efficiency and the electrical performance are improved, the material waste is reduced, the production cost is reduced, the packaging requirement of higher integration level can be met, the application scene is expanded, and the graphic precision and the product yield are greatly improved.

An integrated circuit package is provided in which a hybrid-bonded stack of memory dies couples through a plurality of through-mold vias to a redistribution layer. A logic die couples to the redistribution layer through a plurality of interconnects.

A method includes: forming a first interposer die, wherein the first interposer die comprises a first substrate and a first redistribution layer (RDL) over the first substrate; bonding the first interposer die to a second RDL; encapsulating the second RDL and the first interposer die with a first encapsulating layer; thinning the first interpose die to expose the first RDL; and bonding a first semiconductor die to the first RDL.

An integrated circuit package is provided including both an upper redistribution layer and a lower redistribution layer. A first stack of memory dies couples to the upper redistribution layer either through metal posts or through vertical wire bonds. Similarly, a second stack of memory dies couples to the lower redistribution layer either through metal posts or through vertical wire bonds. A logic die also couples to the lower redistribution layer through a plurality of interconnects.

The invention relates to a packaging structure and a preparation method thereof, and relates to the technical field of semiconductors, in the packaging structure and the preparation method thereof, a first rewiring layer comprises a wiring layer and a dielectric layer, the orthographic projection of the wiring layer on a carrier plate is not overlapped with the orthographic projection of an optical coupler on the carrier plate, namely, the wiring layer does not shield an optical window of the optical coupler, and the dielectric layer is arranged on the dielectric layer; a light-transmitting dielectric material column is formed on the side, away from the carrier plate, of the first rewiring layer, the orthographic projection of the light-transmitting dielectric material column on the carrier plate is overlapped with the orthographic projection of the optical coupler on the carrier plate, at the moment, an optical window of the optical coupler is shielded by the light-transmitting dielectric material column, and the optical window cannot be polluted when the second packaging layer is prepared subsequently; the second packaging layer exposes the light-transmitting dielectric material columns, and the optical coupler achieves vertical optical coupling through the light-transmitting dielectric material columns.

The embodiment of the invention provides a wafer-level chip packaging structure and electronic equipment, relates to the field of semiconductors, and aims to improve the transmission performance between chips. The wafer-level chip packaging structure comprises an adapter plate and a wafer-level chip. The adapter plate comprises a first rewiring layer and a second rewiring layer which are arranged in a stacked mode, the first rewiring layer comprises an optical interconnection channel, and the second rewiring layer comprises an electric interconnection channel. The wafer level chip is arranged on the adapter plate. The wafer level chip includes a plurality of device regions, each device region including at least one chip. Along a first direction parallel to the adapter plate, the chips in the two adjacent device regions are connected through an electric interconnection channel, and the chips in the two device regions at the two ends are connected through an optical interconnection channel. Along a second direction parallel to the adapter plate, the chips in the two adjacent device regions are connected through an electric interconnection channel, the chips in the two device regions at the two ends are connected through an optical interconnection channel, and the first direction and the second direction are crossed.

A semiconductor package includes a first semiconductor chip including: a first substrate, a first wiring layer on a first surface of the first substrate, a plurality of first dummy pads electrically connected to each other by a redistribution layer disposed between the first wiring layer and a first passivation layer, and a plurality of second dummy pads disposed adjacent to the plurality of first dummy pads on the first wiring layer; and a second semiconductor chip including: a second substrate, a second wiring layer on the second substrate and opposite to the first surface of the first substrate, a plurality of third dummy pads having at least a portion that overlaps the plurality of first dummy pads on the second wiring layer, and a plurality of power pads arranged adjacent to the plurality of third dummy pads and configured to provide a test voltage.

The present disclosure provides a semiconductor package structure and a semiconductor packaging method, and relates to the technical field of semiconductor. The semiconductor package structure comprises a package substrate, a random access memory chip bonded with a first connecting part on the package substrate, a package layer covering the random access memory chip on the package substrate, a redistribution layer on the package layer, a second conductive wire at least partially located in the package layer and connecting a second connecting part on the package substrate and a bottom surface of the redistribution layer, and a flash memory chip on the redistribution layer and bonded with a top surface of the redistribution layer. The redistribution layer comprises a signal line and a reference line, the signal line is used for signal transmission between the flash memory chip and the package substrate, and the reference line is used for providing a reference plane for signal transmission. The present disclosure can improve the warping, delamination and other problems of semiconductor devices, and improve signal integrity and power integrity.

This provides an improvement to the rewiring line structure of die packaging. [Solution] This invention provides an improvement to the redistribution line structure of die packaging, which mainly consists of one die, multiple redistribution lines, and multiple nickel-gold layers. Each redistribution line is formed on the surface of the die by being stretched horizontally using a redistribution layer (RDL) process. Each nickel-gold layer is formed on the surface of each redistribution line by being plated using a chemical nickel-gold (ENIG) process. Each nickel-gold layer consists of a nickel (Ni) layer and a gold (Au) layer, with the gold layer positioned on top of the nickel layer. This structure effectively solves the problems of uneven thickness and process complexity that occur in conventional die packaging when nickel-gold layers are formed using an electroplating process, and the RDL process can improve the design space and reliability of the die packaging.

A semiconductor device with first and second portions of a redistribution layer with arrays of through via elements carrying electrical ground connections that includes one or more contact pads that have one or more extensions projecting therefrom into a null space between through via elements carrying electrical signals. A method of manufacturing the semiconductor device is also disclosed.

A package device and a manufacturing method thereof are provided. The package device includes a package structure, a redistribution layer, an underfill layer, a plurality of conductive pillars, another redistribution layer, and an encapsulant. The underfill layer is disposed between the package structure and the redistribution layer, and the conductive pillars and the package structure are disposed side by side between the redistribution layers. The encapsulant is disposed between the redistribution layers and surrounds the package structure and the conductive pillars.

Embodiments of the present disclosure relate to an integrated circuit chip package that does not utilize a leadframe. An integrated circuit die includes a semiconductor substrate, an interconnect layer including bond pads, and a passivation layer covering the interconnect layer and including openings at the bond pads. The passivation layer supports a conductive redistribution layer including conductive wires and conductive vias. An insulating layer covers the conductive redistribution layer and the passivation layer. Trenches formed in an upper surface of the insulating layer define pedestal regions in the insulating layer. Vias extend from an upper surface of each pedestal region through the pedestal region and the insulating layer to reach and contact a portion of the conductive redistribution layer. Metal pads are formed at the upper surface of each pedestal region in contact with the vias associated therewith. The metal pads are used for leads of a quad flat no-lead (QFN) type package.

An electronic device is provided. The electronic device includes a redistribution layer, a component disposed on the redistribution layer, and an underfill disposed between the redistribution layer and the component. The electronic device also includes an encapsulation material covering the component. The encapsulation material or the underfill defines a sidewall adjacent to the component and a surface of the component that is substantially perpendicular to the sidewall.

The invention relates to a novel substrate designed for a packaging redistribution layer in a semiconductor device and an innovative manufacturing method thereof. The substrate aims to improve electrical and heat dissipation performance in a semiconductor package by using materials such as glass, ceramic or high-temperature polymer, so as to achieve an effect of improving heat management. One characteristic of the invention is that the redistribution layer comprises the arc angle, so that smooth transition between redistribution lines is promoted, and the filling resistance of the conductive material is effectively reduced. The redistribution layer is filled with conductive adhesive, such as copper or silver adhesive, into channels formed by selective laser etching or a 3D line printing technology. The method of manufacturing the printed circuit board ensures accurate formation of the conductive vias having arcuate angles, and involves a subsequent annealing step to cure the conductive adhesive.

A solid state drive (SSD) device includes a substrate, a first buffer chip disposed on the substrate, a second buffer chip disposed on the first buffer chip, a plurality of first non-volatile memory chips connected to the second buffer chip through wire bonding, a controller configured to send a control signal to the plurality of first non-volatile memory chips through a first channel, and a first redistribution layer disposed in the substrate and configured to electrically connect the first channel to the first buffer chip, wherein the first buffer chip is connected to the first redistribution layer through flip chip bonding, and the second buffer chip is connected to the first redistribution layer through first wires.

A semiconductor package method includes: providing a first carrier board, forming a first molding layer covering the upper surface of the first carrier board and the bridge chip after bonding an upper insulation layer of the bridge chip on the upper surface of the first carrier board; thinning the first molding layer and the lower insulation layer, and forming a first redistribution layer on the surfaces of the thinned first molding layer and lower insulation layer, the process for forming the first redistribution layer includes an electroplating process; thinning the upper insulation layer and the first molding layer, forming a second redistribution layer on the surfaces of the thinned upper insulation layer and first molding layer, and the process for forming the second redistribution layer includes an electroplating process; and providing a semiconductor chip, mounting the semiconductor chip on the upper surface of the second redistribution layer, and the semiconductor chip being electrically connected with the second redistribution layer.