1586 results about "Redistribution layer" patented technology

An optical-electrical substrate for providing electrical and optical connections to a photonic integrated circuit (PIC) includes a glass body with glass optical waveguides along an upper surface, and electrically conductive vias extending through a portion of the glass body from an intermediate surface to a lower surface. The intermediate surface is arranged at an elevation positioned between the upper and lower surfaces, and may optionally support redistribution layers and an electrical integrated circuit. An optical-electrical substrate may be fabricated by defining glass optical waveguides along an upper surface of a glass body, and forming electrically conductive vias through the glass body from the intermediate surface to the lower surface. A connection method includes registering a PIC with an optical-electrical substrate as described herein; heating bonding bumps arranged between the PIC and the intermediate surface; and providing optically transmissive paths between the PIC and glass optical waveguides of the substrate.

A package structure includes a frontside redistribution layer (RDL) structure with a recessed portion, a lower encapsulation layer on the frontside RDL structure and a plurality of through vias connected to the frontside RDL structure to an upper package, a first semiconductor die on the frontside RDL structure and in the lower encapsulation layer, and an integrated passive device (IPD) connected to the frontside RDL structure in the recessed portion that connects to the first semiconductor die. A method of forming a package structure includes forming a molded portion with a lower encapsulation layer, a plurality of through vias in the lower encapsulation layer and a first semiconductor die in the lower encapsulation layer, forming a RDL structure with a recessed portion on the molded portion, the plurality of through vias connect the frontside RDL structure to an upper package, and attaching an IPD in the recessed portion.

The invention discloses a three-dimensional integrated packaging structure and a packaging process thereof. The three-dimensional integrated packaging structure comprises a flip or normal chip with a functional surface and an opposite back surface; the rewiring layer and the chip are vertically stacked and electrically connected with each other; electrically leading the rewiring layer out of the packaging structure; the stacking direction of the inductor and the chip is parallel to the thickness direction of the chip, the inductor and the chip, the rewiring layer and the lead-out structure are physically isolated through an insulating medium layer, the inductor is of a spiral, multi-ring layer overlapping or sectional winding structure, the inductor comprises a magnetic core, a spiral coil surrounding the surface of the magnetic core is formed through etching and electroplating processes, and the lead-out structure is arranged on the surface of the spiral coil. The spiral coil comprises a circuit A, a circuit B and a circuit C, and the magnetic core and the spiral coil are encapsulated by the insulating medium layer. The inductor and the chip are stacked in an inverted or normal mode, the three-dimensional structure saves space, reduces parasitic inductance, resistance and the like, signal transmission is stable, electromagnetic interference is small, and the three-dimensional structure is suitable for the chip packaging field of miniaturization, high integration and the like.

The invention discloses a preparation method and structure of an interposer embedded with a silicon bridge and a high-density silicon capacitor, and belongs to the field of advanced packaging of integrated circuits. The method can be used for 2.5 D advanced packaging high-density interconnection; the interposer structure comprises an interposer back RDL rewiring layer, an intermediate layer which is formed by embedding a silicon bridge and a high-density silicon capacitor by using a high-molecular epoxy resin material EMC, and an RDL rewiring layer on the front side of the interposer. High-density vertical interconnection between the upper RDL layer and the lower RDL layer is achieved through an electroplating ultrahigh copper column penetrating through the resin material, micron-level and submicron-level ultrahigh-density interconnection can be achieved through a silicon bridge embedded in the EMC resin, and high-performance packaging-level power supply decoupling can be achieved through a high-density silicon capacitor embedded in the resin. The preparation method of the structure is easy to implement, the cost is greatly reduced compared with that of the TSV silicon adapter plate interposer, and the method can be used for large-scale mass production of 2.5 D interposers.

A module includes: a substrate having a first surface; a first component mounted on the first surface; a first sealing resin layer disposed to cover a side surface of the first component and the first surface; and a redistribution layer covering a surface of the first sealing resin layer on a side far from the substrate. The redistribution layer includes: a first metal film disposed to correspond to a projection area of the first component; a first insulating film covering a surface of the first metal film on a side far from the substrate; and a first group of conductor vias passing through the first insulating film and protruding from the first metal film in a direction away from the substrate.

A method of forming a semiconductor structure includes the following operations. First deep vias are formed in a first glass layer. A first redistribution layer structure is formed on a first side of the first glass layer, and the first redistribution layer structure is electrically connected to the first deep vias. A carrier is bonded to the first redistribution layer structure. The first glass layer is grinded until surfaces of the first deep vias are exposed. A second redistribution layer structure is formed on a second side of the first glass layer opposite to the first side, and the second redistribution layer structure is electrically connected to the first deep vias.

The present disclosure relates to a multilevel system-in-package (SIP) module having a double-sided module and a redistribution structure located underneath the double-sided module. The double-sided module includes a laminate body, a top component attached to a top surface of the laminate body, a bottom component and multiple copper posts attached to a bottom surface of the laminate body, and a bottom mold compound formed on the bottom surface of the laminate body and at least encapsulating side surfaces of the bottom component and side surfaces of each copper post. A bottom surface of the bottom mold compound is a portion of a bottom surface of the double-sided module. The redistribution structure includes a redistribution layer with multiple patterned conductive features, which are separate from each other. Each patterned conductive feature is coupled to at least one of the bottom component and the copper posts.

A package structure includes an interconnect structure, a first logic die, a molding material, a conductive via, and a redistribution layer. The interconnect structure is attached to a package substrate. The first logic die is disposed over the interconnect structure. The first logic die includes an upper through-silicon via (TSV) on the upper portion of the first logic die and a lower TSV on the lower portion of the first logic die. The upper portion of the first logic die includes a device layer and a power transmission layer, and the upper TSV penetrates through the device layer and physically connected to the power transmission layer. The molding material is over the interconnect structure and surrounds the first logic die. The conductive via penetrates through the molding material. The redistribution layer is over the first logic die and the molding material.

Integrated circuit packages having electrical and optical connectivity and methods of making the same are disclosed herein. According to one embodiment, an integrated circuit package includes a glass substrate, an optical channel, and redistribution layers. The integrated circuit package further includes an integrated circuit chip positioned on the glass substrate and in optical communication with the optical channel and in electrical continuity with the redistribution layers.

Provided is a package structure including a first redistribution layer (RDL) structure, a die, a circuit substrate, and a first thermoelectric cooler. The RDL) structure has a first side and a second side opposite to each other. The die is disposed on the first side of the first RDL structure. The circuit substrate is bonded to the second side of the first RDL structure through a plurality of first conductive connectors. The first thermoelectric cooler is between the first RDL structure and the circuit substrate, wherein the first thermoelectric cooler includes at least a N-type doped region and at least a P-type doped region.

The invention provides a high-density photoelectric common connection pinboard based on a low-loss silicon nitride grating coupler. The invention aims to overcome the difficulty that the existing photoelectric heterogeneous chip is difficult to integrate, stack and package, and realizes high-density interconnection between the chip and the interposer by using a grating coupling structure and a silicon through hole technology, thereby realizing high-integration low-loss packaging of the heterogeneous chip on the interposer. According to the invention, high-efficiency optical interconnection between the heterogeneous chip and the photoelectric co-connection intermediate layer is realized through the high-efficiency grating coupler, and high-density electrical interconnection between the chip and the photoelectric co-connection intermediate layer is realized through the TSV technology and the RDL technology. Meanwhile, the optical interconnection efficiency between the interposer and the chip is improved by utilizing the electrode patterning advantage of the RDL technology, and the self-alignment between the chip and the interposer is realized. The method has extremely high compatibility to the packaging scene of the existing photoelectric heterogeneous chip, so that the method has great significance in improving the integration density and reducing the interconnection loss of a photoelectric heterogeneous integrated system and promoting the practicability of the photoelectric heterogeneous integrated system.

The invention provides a chip packaging structure and electronic equipment, relates to the technical field of chips, and can meet the requirement of high bandwidth density between chips on the basis of supporting integration of heterogeneous chips (die). The chip packaging structure comprises a first chip, an electronic element and a hybrid adapter plate with a novel structure. The hybrid adapter plate comprises a silicon interposer and a rewiring layer, the front surface of the silicon interposer is provided with a metal wiring layer, and the silicon interposer is provided with a silicon through hole. The first chip is arranged on the front surface of the silicon interposer and is electrically connected with the metal wiring layer. Or the hybrid adapter plate comprises a first rewiring layer, a second rewiring layer, a bridge chip and a metal connecting structure, the bridge chip and the metal connecting structure are located between the two rewiring layers, and the bridge chip achieves interconnection between the first chips through the first rewiring layer. The second redistribution layer is connected with the first redistribution layer through a metal connection structure. The electronic component is located on the back face of the redistribution layer and connected with the redistribution layer or connected with the redistribution layer through the substrate.

A semiconductor package and associated methods, the package including a substrate; first and second semiconductor chips on the substrate; and external terminals below the substrate, wherein the substrate includes a core portion; first and second buildup portions on top and bottom surfaces of the core portion, the first and second buildup portions including a dielectric pattern and a line pattern; and an interposer chip in an embedding region in the core portion and electrically connected to the first and second buildup portions, the interposer chip includes a base layer; a redistribution layer on the base layer; and a via that penetrates the base layer, the via being connected to the redistribution layer and exposed at a surface of the base layer, the redistribution layer is connected to a line pattern of the first buildup portion, and the via is connected to a line pattern of the second buildup portion.

Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.

The embodiment of the invention provides a high-density redistribution interconnection packaging structure and a preparation method thereof, and relates to the technical field of chip packaging, and the packaging structure comprises a substrate rewiring layer, a first chip, a first plastic package body, a coating layer, an integrated rewiring layer, a first stacking rewiring layer, a second chip and a second plastic package body. Compared with the prior art, according to the high-density redistribution interconnection packaging structure provided by the embodiment of the invention, the first heat dissipation columns are additionally designed, so that the heat dissipation performance can be greatly improved, and an overheating phenomenon is slowed down. And meanwhile, the first heat dissipation column can be embedded in the first plastic package body and the coating layer at the same time, so that the binding force of each layer of the package structure is greatly improved, the structural stability is ensured, and the warping phenomenon of the package structure is relieved. Meanwhile, electrical conduction is achieved through the first conductive columns and the second conductive columns, parasitic inductance of the wiring layers is reduced, and the phenomena of short circuit, overheating and the like between the wiring layers caused by the electric leakage phenomenon are relieved.

An electronic device includes a routing structure, an electronic circuit, an antenna, and an RF reflector. The electronic circuit is coupled to a mounting surface of the routing structure above a circuit zone. The antenna is coupled to the routing structure in an antenna zone. The RF reflector is coupled to the mounting surface above a reflector zone. The RF reflector includes an inner boundary portion that is adjacent to the antenna zone, and a circuit-adjacent segment positioned between the inner boundary portion and the electronic circuit. At least part of an upper extent of the inner boundary portion is at a first height above the mounting surface. An upper extent of the circuit-adjacent segment is at a second height above the mounting surface that is greater than the first height. The routing structure may be a printed circuit board or a redistribution layer structure.

An example semiconductor package includes a package substrate, an electronic integrated circuit (EIC) package mounted on the package substrate, and a plurality of photonic integrated circuit (PIC) chips stacked on the EIC package. Each PIC chip of the plurality of PIC chips includes an upper groove recessed inwards from an upper surface of the PIC chip and being open toward a first side surface of the PIC chip. The EIC package includes a lower redistribution layer on the package substrate, an EIC chip mounted on the lower redistribution layer, a molding layer surrounding the EIC chip, a through via passing through the molding layer in a vertical direction and electrically connected with the lower redistribution layer, and an upper redistribution layer on the through via.

A chip package includes a semiconductor structure and a redistribution layer. The semiconductor structure has a substrate, a first isolation layer, and a lower ground pad. The substrate has a top surface, a bottom surface opposite to the top surface, a through hole through the top surface and the bottom surface, and a sidewall surrounding the through hole. The first isolation layer is located on the top surface of the substrate, and the lower ground pad is located in the through hole. The redistribution layer extends from the bottom surface of the substrate to the lower ground pad along the sidewall. The redistribution layer covers the entire bottom surface of the substrate and electrically connects the lower ground pad.

The invention discloses a semiconductor packaging alignment mark manufacturing method and a semiconductor packaging alignment mark product. The semiconductor packaging alignment mark manufacturing method comprises the following steps that a cofferdam is manufactured at the position, corresponding to a TSV area, on light glass; the cofferdam is coated with bonding glue; bonding the wafer on the optical glass and grinding and thinning the wafer; performing etching to form a first-order groove and an alignment Mark; completing the etching of the silicon through hole; preparing a dielectric layer on the wafer; preparing a passivation layer on the dielectric layer; preparing an RDL (redistribution layer); pre-cutting a groove, and half-cutting to a cofferdam; preparing a solder mask layer; and planting or printing a solder ball, and then cutting into a final finished product. According to the invention, the alignment function of the photoetching process after pre-cutting can be realized, the overall process capability can be improved, the process steps are reduced, the product manufacturing period is shortened, the packaging cost is reduced, and the product competitiveness is improved; a special laser marking station is not needed, wafer surface pollution caused by laser marking is reduced, operators of the original laser marking station are saved, manpower and material resources are saved, one manufacturing process is saved, and the packaging cost is reduced.

A semiconductor package includes an interposer substrate on a package substrate. The interposer substrate includes an upper pad on an upper surface of the insulating layer, a lower pad on a lower surface of the insulating layer, and a redistribution structure penetrating the insulating layer between the upper surface and the lower surface to connect the upper pad and the lower pad. A semiconductor chip is disposed above the interposer substrate and connected to the upper pad, and a connection bump directly contacts a lower surface of the lower pad. The redistribution structure includes redistribution layers and redistribution vias connected to the redistribution layers, wherein each of the redistribution layers and each of the redistribution vias includes a metal material layer and a plating seed layer, and the lower pad directly contacts the plating seed layer.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first redistribution layer (RDL), having a first surface with first conductive contacts having a first pitch between 170 microns and 400 microns, an opposing second surface, and first conductive pathways between the first and second surfaces; a first die and a conductive pillar in a first layer on the first RDL; a second RDL on the first layer, the second RDL having a first surface, an opposing second surface with second conductive contacts having a second pitch between 18 microns and 150 microns, and second conductive pathways between the first and second surfaces; and a second die, in a second layer on the second RDL, electrically coupled to the first conductive contacts via the first conductive pathways, the conductive pillar, the second conductive pathways, and the second conductive contacts.

A semiconductor package structure includes a substrate, a redistribution layer, a first semiconductor die, and a first capacitor. The substrate has a wiring structure. The redistribution layer is disposed over the substrate. The first semiconductor die is disposed over the redistribution layer. The first capacitor is disposed in the substrate and is electrically coupled to the first semiconductor die. The first capacitor includes a first capacitor substrate, a plurality of first capacitor cells, and a first through via. The first capacitor substrate has a first top surface and a first bottom surface. The first capacitor cells are disposed in the first capacitor substrate. The first through via is disposed in the first capacitor substrate and electrically couples the first capacitor cells to the wiring structure on the first top surface and the first bottom surface.

Provided are a package structure and a method of forming the same. The package structure includes an interposer at least including a first die sandwiched between a first redistribution layer (RDL) structure and a second RDL structure. The first die includes: a device layer disposed on a substrate; an inductor device disposed on the device layer; an internal RDL structure disposed on the inductor device; a plurality of conductive connectors disposed on the internal RDL structure; and an inductor contact disposed aside the inductor device and electrically connecting the internal RDL structure and inductor device. The internal RDL structure is configured to redistribute an electrical signal from the inductor contact to the plurality of conductive connectors, thereby preventing the electromigration (EM) failure.

A semiconductor package including a first semiconductor package that includes a redistribution layer, a substrate disposed on the redistribution layer and including a plurality of wiring layers, a first semiconductor chip disposed on the redistribution layer, and an encapsulant covering at least a portion of each of the substrate and the first semiconductor chip; and a second semiconductor package that is disposed on the first semiconductor package and includes a second semiconductor chip. The first semiconductor package includes a first side surface and a second side surface facing the first side surface. The plurality of wiring layers are disposed adjacent to the first side surface, the first semiconductor chip is disposed between the plurality of wiring layers and the second side surface, and a distance between the first semiconductor chip and the first side surface is greater than a distance between the first semiconductor chip and the second side surface.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface, in a first layer; a redistribution layer (RDL) on the first layer, wherein the RDL includes conductive vias having a greater width towards a first surface of the RDL and a smaller width towards an opposing second surface of the RDL; wherein the first surface of the RDL is electrically coupled to the second surface of the first die by first solder interconnects having a first solder; and a second die in a second layer on the RDL, wherein the second die is electrically coupled to the RDL by second solder interconnects having a second solder, wherein the second solder is different than the first solder.

A semiconductor package includes a base substrate, an interposer package disposed on the base substrate, and first and second semiconductor chips disposed on the interposer package, the interposer package includes a first redistribution layer, a bridge chip including a bridge circuit, and a vertical connection structure including a plurality of wiring layers, and wherein each of the first semiconductor chip and the second semiconductor chip is electrically connected to the bridge circuit and the plurality of wiring layers through the first redistribution layer.

A package structure including a semiconductor die, a redistribution layer, a plurality of antenna patterns, a die attach film, and an insulating encapsulant is provided. The semiconductor die have an active surface and a backside surface opposite to the active surface. The redistribution layer is located on the active surface of the semiconductor die and electrically connected to the semiconductor die. The antenna patterns are located over the backside surface of the semiconductor die. The die attach film is located in between the semiconductor die and the antenna patterns, wherein the die attach film includes a plurality of fillers, and an average height of the die attach film is substantially equal to an average diameter of the plurality of fillers. The insulating encapsulant is located in between the redistribution layer and the antenna patterns, wherein the insulating encapsulant encapsulates the semiconductor die and the die attach film.

The present application relates to the technical field of dies, and provides a die packaging structure and an electronic device, which can satisfy the high-bandwidth density requirement for dies while supporting heterogeneous die integration. The die packaging structure comprises a first die, an electronic element and a hybrid interposer of a novel structure. The hybrid interposer comprises a silicon interposer and a redistribution layer, a metal wiring layer is provided on the front surface of the silicon interposer, and a through silicon via is formed in the silicon interposer. The first die is disposed on the front surface of the silicon interposer and is electrically connected to the metal wiring layer. Alternatively, the hybrid interposer comprises a first redistribution layer, a second redistribution layer, a bridge die located between the two redistribution layers, and a metal connecting structure, and the bridge die achieves interconnection between first dies by means of the first redistribution layer. The second redistribution layer is connected to the first redistribution layer by means of the metal connecting structure. The electronic element is located on the back surface of the redistribution layer, is connected to the redistribution layer or is connected to the redistribution layer by means of a substrate.

The invention relates to a substrate and a preparation method thereof and a chip packaging structure, the substrate comprises a core layer and a rewiring layer arranged on at least one side surface of the core layer, the core layer comprises an inorganic non-metal material layer, and the material thermal expansion coefficient of the inorganic non-metal material layer is 3 ppm / DEG C to 8 ppm / DEG C. The core layer is made of the inorganic non-metal material with a lower thermal expansion coefficient, so that the high-frequency signal loss of the substrate can be reduced, the difference between the effective thermal expansion coefficient of the core layer and the thermal expansion coefficient of the silicon chip can be reduced, the effective thermal expansion performance of the core layer is further matched with the silicon chip, and the service life of the silicon chip is prolonged. When the silicon chip is arranged on the substrate, the silicon chip is connected with the core layer through the rewiring layer, and the core layer and the silicon chip have good thermal expansion coefficient matching performance, so that the thermal stress between the substrate and the silicon chip can be reduced, the reliability is improved, and the risk of warping and layering between the substrate and the silicon chip is reduced.

A chip package includes a semiconductor substrate, a first light-transmissive sheet, a second light-transmissive sheet, a first antenna layer, and a redistribution layer. The first light-transmissive sheet is disposed over the semiconductor substrate, and has a top surface facing away from semiconductor substrate and an inclined sidewall adjacent to the top surface. The second light-transmissive sheet is disposed over the first light-transmissive sheet. The first antenna layer is disposed between the first light-transmissive sheet and the second light-transmissive sheet. The redistribution layer is disposed on the inclined sidewall of the first light-transmissive sheet, and is in contact with an end of the first antenna layer.