2095 results about "Redistribution layer" patented technology

An optical-electrical substrate for providing electrical and optical connections to a photonic integrated circuit (PIC) includes a glass body with glass optical waveguides along an upper surface, and electrically conductive vias extending through a portion of the glass body from an intermediate surface to a lower surface. The intermediate surface is arranged at an elevation positioned between the upper and lower surfaces, and may optionally support redistribution layers and an electrical integrated circuit. An optical-electrical substrate may be fabricated by defining glass optical waveguides along an upper surface of a glass body, and forming electrically conductive vias through the glass body from the intermediate surface to the lower surface. A connection method includes registering a PIC with an optical-electrical substrate as described herein; heating bonding bumps arranged between the PIC and the intermediate surface; and providing optically transmissive paths between the PIC and glass optical waveguides of the substrate.

A semiconductor device with a through via between redistribution layers is disclosed. The semiconductor device includes a stack of semiconductor dies coupled with first contact pads on a first redistribution layer. The first redistribution layer further includes a second contact pad located outside the footprint of the die stack and circuitry coupling the second contact pad to the first contact pads. A gap fill is disposed around the stack of semiconductor dies. A second redistribution layer is disposed at the stack of semiconductor dies and the gap fill. The second redistribution layer includes third contact pads coupled with the stack of semiconductor dies, a fourth contact pad disposed beyond the footprint of the stack of semiconductor dies, fifth contact pads opposite the third and fourth contact pads, and circuitry coupling the contact pads. A through via is disposed through the gap fill coupling the second and fourth contact pads.

Interconnect structures for front-to-front stacked chips / dies and methods of fabrication thereof are disclosed herein. An exemplary system on integrated circuit (SoIC) includes a first die that is front-to-front bonded with a second die, for example, by bonding a first topmost metallization layer of a first frontside multilayer interconnect of the first die to a second topmost metallization layer of a second frontside multilayer interconnect of the second die. A through via extends partially through the first frontside multilayer interconnect of the first die, through a device layer of the first die, through a backside power rail of the first die, and through a carrier substrate. The backside power rail is between the carrier substrate and the device layer, and the backside power rail may be a portion of a backside multilayer interconnect of the first die. The through via may be connected to a redistribution layer (RDL) structure.

A package structure includes a frontside redistribution layer (RDL) structure with a recessed portion, a lower encapsulation layer on the frontside RDL structure and a plurality of through vias connected to the frontside RDL structure to an upper package, a first semiconductor die on the frontside RDL structure and in the lower encapsulation layer, and an integrated passive device (IPD) connected to the frontside RDL structure in the recessed portion that connects to the first semiconductor die. A method of forming a package structure includes forming a molded portion with a lower encapsulation layer, a plurality of through vias in the lower encapsulation layer and a first semiconductor die in the lower encapsulation layer, forming a RDL structure with a recessed portion on the molded portion, the plurality of through vias connect the frontside RDL structure to an upper package, and attaching an IPD in the recessed portion.

A semiconductor package may include a package redistribution layer including a plurality of package redistribution patterns and a package redistribution insulating layer surrounding the plurality of package redistribution patterns, a plurality of electronic components apart from each other in a horizontal direction on the package redistribution layer and including at least one sub package, a package molding layer covering a top surface of the package redistribution layer and surrounding the plurality of electronic components, and a plurality of package connection terminals attached to a bottom surface of the package redistribution layer in a fan-out manner. The at least one sub package may include a package substrate, a semiconductor chip attached to the package substrate, and a sub molding layer on the package substrate.

The present disclosure is directed to a method for forming metal insulator metal decoupling capacitors with scalable capacitance. The method can include forming a first redistribution layer with metal lines on a portion of a polymer layer, depositing a photoresist layer on the first redistribution layer, and etching the photoresist layer to form spaced apart first and second TIV openings in the photoresist layer, where the first TIV opening is wider than the second TIV opening. The method can further include depositing a metal in the first and second TIV openings to form respective first and second TIV structures in contact with the metal line, removing the photoresist layer, forming a high-k dielectric on a top surface of the first and second TIV structures, and depositing a metal layer on the high-k dielectric layer to form respective first and second capacitors.

A semiconductor package including at least one functional die; at least one dummy die free of active circuit, wherein the dummy die comprises at least one metal-insulator-metal (MIM) capacitor; and a redistribution layer (RDL) structure interconnecting the MIM capacitor to the at least one functional die.

The invention discloses a three-dimensional integrated packaging structure and a packaging process thereof. The three-dimensional integrated packaging structure comprises a flip or normal chip with a functional surface and an opposite back surface; the rewiring layer and the chip are vertically stacked and electrically connected with each other; electrically leading the rewiring layer out of the packaging structure; the stacking direction of the inductor and the chip is parallel to the thickness direction of the chip, the inductor and the chip, the rewiring layer and the lead-out structure are physically isolated through an insulating medium layer, the inductor is of a spiral, multi-ring layer overlapping or sectional winding structure, the inductor comprises a magnetic core, a spiral coil surrounding the surface of the magnetic core is formed through etching and electroplating processes, and the lead-out structure is arranged on the surface of the spiral coil. The spiral coil comprises a circuit A, a circuit B and a circuit C, and the magnetic core and the spiral coil are encapsulated by the insulating medium layer. The inductor and the chip are stacked in an inverted or normal mode, the three-dimensional structure saves space, reduces parasitic inductance, resistance and the like, signal transmission is stable, electromagnetic interference is small, and the three-dimensional structure is suitable for the chip packaging field of miniaturization, high integration and the like.

The invention discloses a preparation method and structure of an interposer embedded with a silicon bridge and a high-density silicon capacitor, and belongs to the field of advanced packaging of integrated circuits. The method can be used for 2.5 D advanced packaging high-density interconnection; the interposer structure comprises an interposer back RDL rewiring layer, an intermediate layer which is formed by embedding a silicon bridge and a high-density silicon capacitor by using a high-molecular epoxy resin material EMC, and an RDL rewiring layer on the front side of the interposer. High-density vertical interconnection between the upper RDL layer and the lower RDL layer is achieved through an electroplating ultrahigh copper column penetrating through the resin material, micron-level and submicron-level ultrahigh-density interconnection can be achieved through a silicon bridge embedded in the EMC resin, and high-performance packaging-level power supply decoupling can be achieved through a high-density silicon capacitor embedded in the resin. The preparation method of the structure is easy to implement, the cost is greatly reduced compared with that of the TSV silicon adapter plate interposer, and the method can be used for large-scale mass production of 2.5 D interposers.

A semiconductor device and a method of making the same are provided. A first die and a second die are placed over a carrier substrate. A first molding material is formed adjacent to the first die and the second die. A first redistribution layer is formed overlying the first molding material. A through via is formed over the first redistribution layer. A package component is on the first redistribution layer next to the copper pillar. The package component includes a second redistribution layer. The package component is positioned so that it overlies both the first die and the second die in part. A second molding material is formed adjacent to the package component and the first copper pillar. A third redistribution layer is formed overlying the second molding material. The second redistribution layer is placed on a substrate and bonded to the substrate.

A stacked integrated circuit (IC) device includes a first die having a first face, a first active region adjacent to the first face, and first die-interconnect contacts disposed on the first face and connected to first circuitry. The stacked IC device includes a second die having a second face, a second active region adjacent to the second face, and second die-interconnect contacts disposed on the second face and connected to second circuitry. The first face is oriented toward the second face, and the first die-interconnect contacts are connected to the second die-interconnect contacts. The stacked IC device includes a set of redistribution layers electrically connected to redistribution contacts on the first face, the second face, or both. The stacked IC device also includes interconnect conductors connected to the redistribution layers to provide signal paths from the first die, the second die, or both, to a set of external contacts.

An interposer structure is provided that can be used in semiconductor packaging to electrically connect a printed circuit board to a plurality of die. The interposer structure contains a high-density silicon-less link chiplet that is laterally surrounded by, and embedded in, a lower-density redistribution layer interposer.

A module includes: a substrate having a first surface; a first component mounted on the first surface; a first sealing resin layer disposed to cover a side surface of the first component and the first surface; and a redistribution layer covering a surface of the first sealing resin layer on a side far from the substrate. The redistribution layer includes: a first metal film disposed to correspond to a projection area of the first component; a first insulating film covering a surface of the first metal film on a side far from the substrate; and a first group of conductor vias passing through the first insulating film and protruding from the first metal film in a direction away from the substrate.

The embodiment of the invention provides an adapter plate and a preparation method thereof, a chip packaging structure and electronic equipment, relates to the technical field of semiconductors, and is used for improving the signal transmission efficiency in the adapter plate. The adapter plate comprises a substrate, a conductive structure arranged in the substrate, a first redistribution layer arranged on the substrate and a second redistribution layer arranged on the side, away from the first redistribution layer, of the substrate. The second redistribution layer is coupled to the first redistribution layer through the conductive structure. Wherein the material of the substrate comprises a semiconductor material, the first redistribution layer comprises a first metal wire, the second redistribution layer comprises a second metal wire, and the thickness of the first metal wire and / or the second metal wire is greater than 1 [mu] m.

The embodiment of the invention discloses a packaging piece, an integrated circuit and a packaging method, relates to the technical field of semiconductors, and is convenient for optimizing the heat dissipation performance by improving the internal structure of the packaging piece. A package includes: a redistribution layer; the cache crystal grain is positioned on the rewiring layer and is interconnected with the rewiring layer; and the core crystal grain is arranged above the cache crystal grain, is positioned on the top layer of the internal structure of the packaging piece, and is interconnected with the cache crystal grain. The core crystal grain is arranged on the top layer in the stacked structure form in the packaging piece, so that a large amount of heat generated by the central processing unit can be directly dissipated upwards from the top of the packaging piece, and the heat dissipation performance can be improved. The method is suitable for chip structure design and packaging.

A semiconductor device has a substrate. An electrical component is disposed over the substrate. An encapsulant is deposited over the electrical component. A conductive layer is formed over the substrate opposite the electrical component after depositing the encapsulant. The conductive layer is deposited as a plurality of graphene-coated metal balls in a matrix. The conductive layer is sintered by intensive pulsed light (IPL) irradiation.

A method of forming a semiconductor structure includes the following operations. First deep vias are formed in a first glass layer. A first redistribution layer structure is formed on a first side of the first glass layer, and the first redistribution layer structure is electrically connected to the first deep vias. A carrier is bonded to the first redistribution layer structure. The first glass layer is grinded until surfaces of the first deep vias are exposed. A second redistribution layer structure is formed on a second side of the first glass layer opposite to the first side, and the second redistribution layer structure is electrically connected to the first deep vias.

The present disclosure relates to a multilevel system-in-package (SIP) module having a double-sided module and a redistribution structure located underneath the double-sided module. The double-sided module includes a laminate body, a top component attached to a top surface of the laminate body, a bottom component and multiple copper posts attached to a bottom surface of the laminate body, and a bottom mold compound formed on the bottom surface of the laminate body and at least encapsulating side surfaces of the bottom component and side surfaces of each copper post. A bottom surface of the bottom mold compound is a portion of a bottom surface of the double-sided module. The redistribution structure includes a redistribution layer with multiple patterned conductive features, which are separate from each other. Each patterned conductive feature is coupled to at least one of the bottom component and the copper posts.

A package structure includes an interconnect structure, a first logic die, a molding material, a conductive via, and a redistribution layer. The interconnect structure is attached to a package substrate. The first logic die is disposed over the interconnect structure. The first logic die includes an upper through-silicon via (TSV) on the upper portion of the first logic die and a lower TSV on the lower portion of the first logic die. The upper portion of the first logic die includes a device layer and a power transmission layer, and the upper TSV penetrates through the device layer and physically connected to the power transmission layer. The molding material is over the interconnect structure and surrounds the first logic die. The conductive via penetrates through the molding material. The redistribution layer is over the first logic die and the molding material.

A non-volatile memory chip comprises a cell region that includes a first surface, a second surface opposite to the first surface, a first cell structure, and a second cell structure spaced apart from the first cell structure; a peripheral circuit region on the first surface of the cell region, and that includes a first peripheral circuit connected to the first cell structure, a second peripheral circuit connected to the second cell structure, and a connection circuit between the first and second peripheral circuits; a through via between the first and second cell structures and that extends from the second surface of the cell region to the connection circuit of the peripheral circuit region; a redistribution layer that covers the through via on the second surface of the cell region, is connected to the through via, and extends along the second surface; and a chip pad connected to the redistribution layer.

Integrated circuit packages having electrical and optical connectivity and methods of making the same are disclosed herein. According to one embodiment, an integrated circuit package includes a glass substrate, an optical channel, and redistribution layers. The integrated circuit package further includes an integrated circuit chip positioned on the glass substrate and in optical communication with the optical channel and in electrical continuity with the redistribution layers.

An all-glass stacked packaging structure and a preparation method therefor. The preparation method for the all-glass stacked packaging structure comprises the following steps: S1, providing an embedded chip fan-out packaging structure and a glass metallized circuit structure that are each provided with a glass substrate, and aligning and bonding metal bumps of the embedded chip fan-out packaging structure to a second redistribution layer of the glass metallized circuit structure, and fixing the two together by welding; and S2, filling a gap between the embedded chip fan-out packaging structure and the glass metallized circuit structure with an inorganic silicate or an alkali-metal-free silicon compound, and sintering to obtain the all-glass stacked packaging structure.

Provided is a package structure including a first redistribution layer (RDL) structure, a die, a circuit substrate, and a first thermoelectric cooler. The RDL) structure has a first side and a second side opposite to each other. The die is disposed on the first side of the first RDL structure. The circuit substrate is bonded to the second side of the first RDL structure through a plurality of first conductive connectors. The first thermoelectric cooler is between the first RDL structure and the circuit substrate, wherein the first thermoelectric cooler includes at least a N-type doped region and at least a P-type doped region.

The invention provides a high-density photoelectric common connection pinboard based on a low-loss silicon nitride grating coupler. The invention aims to overcome the difficulty that the existing photoelectric heterogeneous chip is difficult to integrate, stack and package, and realizes high-density interconnection between the chip and the interposer by using a grating coupling structure and a silicon through hole technology, thereby realizing high-integration low-loss packaging of the heterogeneous chip on the interposer. According to the invention, high-efficiency optical interconnection between the heterogeneous chip and the photoelectric co-connection intermediate layer is realized through the high-efficiency grating coupler, and high-density electrical interconnection between the chip and the photoelectric co-connection intermediate layer is realized through the TSV technology and the RDL technology. Meanwhile, the optical interconnection efficiency between the interposer and the chip is improved by utilizing the electrode patterning advantage of the RDL technology, and the self-alignment between the chip and the interposer is realized. The method has extremely high compatibility to the packaging scene of the existing photoelectric heterogeneous chip, so that the method has great significance in improving the integration density and reducing the interconnection loss of a photoelectric heterogeneous integrated system and promoting the practicability of the photoelectric heterogeneous integrated system.

A semiconductor device includes a bottom die including a first semiconductor layer, and a first redistribution layer (RDL) disposed on a bottom surface of the first semiconductor layer; a top die disposed on a top surface of the first semiconductor layer and including a second semiconductor layer, and a second RDL disposed on the top surface of the first semiconductor layer; a stress control (SC) layer disposed on the top surface of the first semiconductor layer and side surfaces of the first die; and a dielectric layer disposed on the SC layer, wherein the SC layer is configured to apply a compressive stress of at least −100 MPa to the top surface of the first semiconductor layer, or the SC layer is configured to apply a tensile stress of at least 100 MPa to the top surface of the first semiconductor layer.

The invention provides a chip packaging structure and electronic equipment, relates to the technical field of chips, and can meet the requirement of high bandwidth density between chips on the basis of supporting integration of heterogeneous chips (die). The chip packaging structure comprises a first chip, an electronic element and a hybrid adapter plate with a novel structure. The hybrid adapter plate comprises a silicon interposer and a rewiring layer, the front surface of the silicon interposer is provided with a metal wiring layer, and the silicon interposer is provided with a silicon through hole. The first chip is arranged on the front surface of the silicon interposer and is electrically connected with the metal wiring layer. Or the hybrid adapter plate comprises a first rewiring layer, a second rewiring layer, a bridge chip and a metal connecting structure, the bridge chip and the metal connecting structure are located between the two rewiring layers, and the bridge chip achieves interconnection between the first chips through the first rewiring layer. The second redistribution layer is connected with the first redistribution layer through a metal connection structure. The electronic component is located on the back face of the redistribution layer and connected with the redistribution layer or connected with the redistribution layer through the substrate.

A semiconductor package and associated methods, the package including a substrate; first and second semiconductor chips on the substrate; and external terminals below the substrate, wherein the substrate includes a core portion; first and second buildup portions on top and bottom surfaces of the core portion, the first and second buildup portions including a dielectric pattern and a line pattern; and an interposer chip in an embedding region in the core portion and electrically connected to the first and second buildup portions, the interposer chip includes a base layer; a redistribution layer on the base layer; and a via that penetrates the base layer, the via being connected to the redistribution layer and exposed at a surface of the base layer, the redistribution layer is connected to a line pattern of the first buildup portion, and the via is connected to a line pattern of the second buildup portion.

Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.

The embodiment of the invention provides a high-density redistribution interconnection packaging structure and a preparation method thereof, and relates to the technical field of chip packaging, and the packaging structure comprises a substrate rewiring layer, a first chip, a first plastic package body, a coating layer, an integrated rewiring layer, a first stacking rewiring layer, a second chip and a second plastic package body. Compared with the prior art, according to the high-density redistribution interconnection packaging structure provided by the embodiment of the invention, the first heat dissipation columns are additionally designed, so that the heat dissipation performance can be greatly improved, and an overheating phenomenon is slowed down. And meanwhile, the first heat dissipation column can be embedded in the first plastic package body and the coating layer at the same time, so that the binding force of each layer of the package structure is greatly improved, the structural stability is ensured, and the warping phenomenon of the package structure is relieved. Meanwhile, electrical conduction is achieved through the first conductive columns and the second conductive columns, parasitic inductance of the wiring layers is reduced, and the phenomena of short circuit, overheating and the like between the wiring layers caused by the electric leakage phenomenon are relieved.

An electronic device includes a routing structure, an electronic circuit, an antenna, and an RF reflector. The electronic circuit is coupled to a mounting surface of the routing structure above a circuit zone. The antenna is coupled to the routing structure in an antenna zone. The RF reflector is coupled to the mounting surface above a reflector zone. The RF reflector includes an inner boundary portion that is adjacent to the antenna zone, and a circuit-adjacent segment positioned between the inner boundary portion and the electronic circuit. At least part of an upper extent of the inner boundary portion is at a first height above the mounting surface. An upper extent of the circuit-adjacent segment is at a second height above the mounting surface that is greater than the first height. The routing structure may be a printed circuit board or a redistribution layer structure.