19 results about "Semiconductor device modeling" patented technology

The invention discloses an intelligent generation method and system for a field-effect transistor device model, and relates to the technical field of semiconductor device modeling, and the method comprises the steps: collecting FET related data in a working process of a field-effect transistor device in real time, carrying out the preprocessing, and rapidly recognizing the potential deviation and coupling change according to the preprocessed FET related data, thereby achieving the intelligent generation of the field-effect transistor device model. The method comprises the following steps: accurately modeling the frequency domain response characteristics of the field effect transistor device, constructing an FET frequency domain equivalent current model, and automatically sending a calibration instruction and controlling the field effect transistor device to calibrate when detecting that the working state of the field effect transistor device is abnormal, so as to realize the timely identification and processing of the abnormality of the field effect transistor device. The stability and the output consistency of the field effect transistor device in the signal amplification process are ensured, a feedback mechanism with intelligent evaluation and adaptive calibration capabilities is constructed, and the long-term operation reliability and the signal processing precision of the field effect transistor device in a complex application scene are effectively improved.

This invention provides an automatic parameter extraction method and system for GaN HEMT device models based on differential evolution algorithms, belonging to the field of semiconductor device modeling technology. By deeply integrating the global optimization capability of differential evolution algorithms with semiconductor device physical models, and utilizing pulse test data and self-heating effect iterative models, this invention achieves physical-level decoupling of electrical and thermal parameters. It overcomes the problems of traditional methods, such as being prone to getting trapped in local optima, the tendency for small physical quantities to collapse to zero values, and the extraction distortion caused by multi-physics coupling, significantly improving parameter extraction accuracy and model generalization ability.

The invention discloses a construction method and device of a device performance determination model, equipment, a medium and a product, and relates to the technical field of semiconductor device modeling. The method comprises the following steps: respectively responding to configuration operation on an input layer and an output layer of an initial model in an interactive interface, and displaying the input layer and the output layer in a model display area of the interactive interface; in response to a configuration operation on a hidden layer of the initial model in the interactive interface, displaying the hidden layer in a model display area of the interactive interface; in response to a selection operation on an activation function of the hidden layer in the interactive interface, displaying the activation function in a model display area of the interactive interface; and in response to a model loading operation, constructing and displaying an initial device performance determination model according to the number of neurons of the input layer and the output layer, the number of hidden layers of the initial model, the number of neurons of each hidden layer and the target activation function of the hidden layers. Through the technical scheme, the modeling efficiency can be improved.

This invention discloses a quality inspection method for compact transistor models based on machine learning, belonging to the field of semiconductor device modeling and EDA. The method includes: receiving a Verilog-A model file and a JSON configuration file defining geometric dimensions and simulation parameters; performing syntax checks and generating OSDI shared objects using the OpenVAF compiler; performing physical consistency verification, including the Gummel symmetry test (GST) and energy conservation checks; extracting device-level DC and AC characteristic indicators; and conducting circuit-level benchmark tests, determining model stability through simulation time and convergence of different unit circuits. This invention constructs a full-link automated evaluation framework from syntax to physical characteristics, effectively solving the problems of physical rationality and simulation convergence of machine learning models in integrated circuit design, and significantly improving model development efficiency and reliability.

This invention provides a method and system for fitting device model parameters, relating to the field of semiconductor device modeling and parameter optimization technology. The method includes: acquiring initial information of a target device model, the initial information including parameters to be fitted; inputting the initial information into the target model to obtain fitting guidance parameters for the parameters to be fitted, the fitting guidance parameters being relevant parameters corresponding to each fitting stage, and the target model being a pre-trained large language model; after the fitting guidance parameters pass verification, fitting the parameters to be fitted at each fitting stage according to the fitting guidance parameters, obtaining the initial fitting result for each fitting stage; dynamically correcting the fitting guidance parameters according to the initial fitting result for each fitting stage to obtain corrected fitting guidance parameters; and fitting the parameters to be fitted at each fitting stage according to the corrected fitting guidance parameters to obtain the target fitting parameters for the parameters to be fitted.

The application belongs to the technical field of semiconductor device modeling and EDA, and discloses a method for extracting parameters of a compact model of an anti-radiation SiGe HBT based on a physical mechanism. The method prepares a test structure array containing different geometric sizes and doping, obtains direct current / alternating current characteristics through multi-dose point irradiation of a 60Co gamma ray, establishes a logarithmic-linear or saturation exponential degradation equation based on an irradiation damage mechanism, embeds a standard MEXTRAM / HICUM model in the form of a Verilog-A subcircuit, adds a dose input pin, extracts degradation coefficients to construct a total dose-key parameter degradation mapping library, and integrates the library with an EDA tool to realize irradiation environment simulation. The application shortens the anti-radiation circuit design cycle from 6 months to 2 weeks, and the model-measured error is less than 5% after 1 Mrad irradiation, so the application is suitable for the design of anti-radiation integrated circuits such as spaceborne phased arrays and space communication.

The invention relates to a GaN HEMT device model parameter automatic extraction method based on a genetic algorithm, and belongs to the technical field of semiconductor device modeling. The method solves the problems that a traditional parameter extraction method is sensitive to an initial value and is prone to falling into local optimum and multi-physics coupling. According to the technical scheme, the method comprises the steps that a dual-mode physical model is constructed, the model is provided with a self-heating switch to simulate pulse and direct current test conditions respectively, pulse and direct current test data are obtained, and electrical parameters and thermal parameters are extracted in two stages through a genetic algorithm. According to the method, the efficiency, precision and physical reliability of parameter extraction are improved, the generalization ability of the model is enhanced, and the electric heating parameters are effectively decoupled.

The invention discloses a GaN HEMT nonlinear current model parameter extraction method, and belongs to the technical field of semiconductor device modeling. The method comprises the following steps: firstly, carrying out parasitic parameter de-embedding on actually measured current data of a GaN HEMT device to obtain intrinsic current data; then based on the intrinsic current data under the first bias condition, extracting parameters irrelevant to self-heating and trap effects in the nonlinear current model by adopting an initial value enhanced cold and hot start composite fitting strategy; and further extracting parameters related to self-heating and trap effects in the model by adopting multi-round fitting and an Revaluation strategy on the basis of intrinsic current data under a second bias condition in combination with the extracted irrelevant parameters. According to the method, the dependency on the initial values of the parameters is remarkably reduced through the hybrid fitting strategy, the robustness, the automation degree and the overall precision of parameter extraction are improved, and the method is suitable for high-precision GaN HEMT device modeling and circuit design.

The invention relates to the technical field of semiconductor device modeling, in particular to a neural network data DC preprocessing method and modeling system.The method comprises the steps that transfer characteristic curve test data, output characteristic curve test data and diode forward characteristic curve test data of a semiconductor device are obtained to serve as original data; performing cleaning processes on the three types of data respectively and then merging and de-duplicating the three types of data; performing data deformation, normalization and standardization on the merged data in sequence; taking Vgs, Vds, Fingernorm, Widthnorm and Tempnorm as input features, taking Idsy as an output target, adopting a full-connection feedforward neural network for training, and obtaining a model weight file; the weight file is injected into the Verilog-A language, the flow of anti-standardization, anti-normalization and anti-data deformation is carried out in the Verilog-A language to restore Ids, the mapping relation of the formula Ids = f (Vgs, Vds, size and temperature) is obtained, SPICE simulation is achieved, multi-size and temperature adaptation can be considered, the precision of Vds = 0 during simulation can be guaranteed, process corner support can be provided, and SPICE simulation is guaranteed to be on the ground.

The invention relates to a power SiC-MOSFET semiconductor device modeling method, and belongs to the field of power electronic device modeling, the method is based on a BSIM3HV parallel reverse PNJDiode device model, is used for analogue simulation of a power semiconductor device, and comprises the following steps: (1) extracting quiescent current characteristics of the power device through actual measurement or a specification manual; (2) determining the geometric structure and key process characteristic parameters of the power SiC-MOSFET device; (3) determining an equivalent circuit topology of the SiC D-MOSFET device; (4) utilizing TCAD to extract and process static electrical characteristics, and performing parameter optimization fitting verification on the known SPICE model; and (5) in combination with other default value process parameters, establishing a complete set of SiC D-MOSFET model. According to the modeling method, the characteristic error of ID-VG and ID-VD compared with an actual measurement result or a specification manual for N-type SiC-MOSFET device simulation is strictly smaller than 5%, the performance of a power semiconductor device can be accurately reflected, and time delay between semiconductor device simulation and a semiconductor process is overcome; and a reliable research basis is provided for early circuit design and technical development based on the power semiconductor device.

The application discloses a modeling method and system based on improved dispersion type Angelov, relates to the technical field of semiconductor device modeling, and constructs an improved dispersion type Angelov model current equation, including a drain current equation and a dispersion current equation; a transistor without dispersion and a transistor with dispersion parameter are extracted by using a pulse voltage current test method and a pulse test method with a pre-pulse respectively; the transistor without dispersion and the transistor with dispersion parameter are substituted into the drain current equation and the dispersion current equation respectively, the total drain source current of the transistor is calculated, and the simulation and the actual measurement difference of S parameters of the transistor under multi-bias are described by adding topological circuit parameters; optimization iteration is carried out on fitting parameters in the current equation, an optimal current equation is obtained, and finally, the improved dispersion type Angelov model of the transistor is obtained. The dispersion current equation is added, so that the S parameters of the transistor under different biases can be better simulated, and the modeling precision is improved.

The invention belongs to the technical field of semiconductor device modeling, and particularly relates to a method and system for extracting parameters of a small-signal equivalent circuit model of a semiconductor device, and the method comprises the steps: training different model parameter sets and corresponding S parameter sets in a small-signal equivalent circuit model structure; a mapping relation structural body between the model parameters and simulation output S parameters is constructed, and all mapping relations are combined into a unified framework; calculating an error between the actual measurement S parameter and the simulation S parameter to obtain an RMS value of each structure; performing preliminary screening, Pareto frontier analysis and multi-dimensional evaluation on the small-signal equivalent circuit model in sequence; according to the RMS value and the screening result, selecting an optimal equivalent circuit model parameter and automatically building an equivalent circuit diagram; the invention provides a semiconductor device small-signal equivalent circuit model parameter extraction method and system. An optimization algorithm is not needed, human intervention is low, modeling difficulty is low, time cost is saved, and the automation degree is high.

The invention provides a semiconductor parametric modeling method based on a polynomial regression algorithm, belongs to the technical field of semiconductor modeling, and aims at solving the problems that traditional TCAD fitting calculation amount is large and the requirement for machine learning data is high, the method utilizes a small amount of TCAD simulation data to construct an agent model, and global rapid optimization is achieved in combination with PDK exact parameters and empirical values. Taking a FinFET device as an example, the scheme not only realizes high-precision fitting consistent with actual measurement data in a wide temperature range from-40 DEG C to 120 DEG C, but also has excellent extremely low temperature characteristic prediction capability. According to the method, through cooperation of agent model optimization and parameter sensitivity analysis, the efficiency and precision of semiconductor device modeling are effectively improved while the computing power cost and the sample collection workload are remarkably reduced.

The application belongs to the technical field of semiconductor device modeling and parameter extraction, and discloses a MOS device BSIM4 model parameter extraction method based on reinforcement learning. The method comprises the following steps: acquiring measured I-V and C-V curve data of a MOS device; constructing a reinforcement learning environment based on the data, defining a state space, an action space adopting a grouping cooperative mechanism, and a composite reward function based on fitting error; constructing a reinforcement learning intelligent agent adopting Dueling DQN and a priority experience replay mechanism; iteratively training the intelligent agent in the environment, and the intelligent agent optimizes the strategy by observing the state, outputting the action of adjusting the parameter group, and obtaining the reward; an improved ε-greedy and optimal step exploration mechanism is adopted during training; when the convergence condition is met, the optimized BSIM4 model parameter set is output, the automation of the parameter extraction process is realized, and the extraction efficiency and precision are greatly improved.

The application discloses an improved BSIM parameter extraction method based on a dueling DQN, aims to improve the efficiency and accuracy of parameter extraction in semiconductor device modeling, uses TCAD simulation data and WAT measurement data in the parameter extraction process, extracts parameters related to channel length, width, current and capacitance, models the BSIM parameter extraction problem as a Markov decision process, calculates target Q values and losses by creating a dueling DQN network model and performing model training, and updates the network parameters of the dueling DQN; in the training process, the root mean square error value is calculated, invalid actions are removed, even and odd action pairs are processed, the root mean square error value difference is sorted, the model converges, and the converged BSIM parameter value is obtained. The method can converge within a preset error range, and significantly improves the efficiency and accuracy of BSIM parameter extraction.

This invention discloses a method for extracting parameters from a GaN HEMT nonlinear current model, belonging to the field of semiconductor device modeling technology. First, parasitic parameters are removed from the measured current data of the GaN HEMT device to obtain intrinsic current data. Then, based on the intrinsic current data under a first bias condition, a composite fitting strategy of initial value enhancement and cold / hot start is used to extract parameters in the nonlinear current model that are unrelated to self-heating and trapping effects. Further, based on the intrinsic current data under a second bias condition, and combined with the extracted irrelevant parameters, a multi-round fitting and R² evaluation strategy is used to extract parameters related to self-heating and trapping effects from the model. This invention significantly reduces the dependence on initial parameter values ​​through a hybrid fitting strategy, improving the robustness, automation, and overall accuracy of parameter extraction, making it suitable for high-precision GaN HEMT device modeling and circuit design.

The invention discloses a modeling method and system based on improved dispersion type Angellov, relates to the technical field of semiconductor device modeling, and constructs improved dispersion type Angellov model current equations including a leakage current equation and a dispersion current equation; a pulse voltage and current test method and a pulse test method with pre-pulse are respectively used for extracting transistor direct current parameters without dispersion and with dispersion parameters of the transistor; and respectively substituting the direct current parameters of the transistors without dispersion and with dispersion parameters into a leakage current equation and a dispersion current equation, calculating the total drain-source current of the transistors, describing simulation and actual measurement differences of S parameters of the transistors under multi-bias by adding topological circuit parameters, and carrying out optimization iteration on fitting parameters in the current equations. An optimal current equation is obtained, and finally the improved dispersion type Angellov model of the transistor is obtained. And a dispersion current equation is added, so that the S parameter of the transistor under different biases can be better simulated, and the modeling precision is improved.

The invention relates to the technical field of semiconductor device modeling, and provides a modular editing and execution method and system for semiconductor device modeling, and the method comprises the steps: initializing a script analysis engine embedded in an application program; creating a device modeling unit Step and distributing a unique identifier StepID; calling a configuration interface editor, automatically generating a structured configuration description Schema according to a parameter field set in a configuration interface, and carrying out association binding on the Schema and the StepID; based on the parameter field definition, finishing the modeling task when the running script calls the numerical value or the object of the parameter field; and configuring a trigger message for the Step in the message responder, and when the interface operation triggers the corresponding message, calling the running script to execute the modeling task and outputting a result. By introducing the concept of a modular modeling unit Step and combining configuration interface editing, operation logic editing, a script analysis engine and a message response mechanism, the limitation that an existing tool interface is fixed and logic cannot be programmed is broken through, the modeling period is shortened, and repeated operation is reduced.

The application discloses a kind of GaN HEMT physical base large signal model parameter extraction methods for switch, belong to semiconductor device modeling and design field, including transistor current model parameter extraction;Transistor intrinsic gate-source and gate-drain capacitance calculation;Edge capacitance model parameter extraction.The application is accurately extracted by the mode of considering the equivalent gate voltage model parameter of source-drain interaction effect under reverse bias condition, accurately characterizes the current characteristics under the condition of drain reverse bias;Using the parameter extraction method of edge capacitance bias-dependent model, the accurate characterization of deep pinch-off region nonlinear capacitance is realized, and then the precise modeling of small signal and large signal characteristics under the off state of switch device is successfully realized.