72results about How to "Reduce metal pollution" patented technology

A method for forming a precoat film on a metal surface in a chamber before forming a silicon-containing film having an identical composition system with that of the precoat film on a substrate in the chamber using a PECVD method, wherein the precoat film is formed using a PEALD method in which a first gas and a second gas are supplied into the chamber by shifting timing of supply, the PEALD method comprises an adsorption step comprising supplying the first gas into the chamber so that the source gas component adsorbs on the metal surface, a first purge step comprising discharging an excessive source gas component not adsorbed on the metal surface, and a precoat film forming step comprising supplying the second gas into the chamber and applying high-frequency power to generate plasma in the reactant gas component in the second gas.

This invention relates to substrate supports, e.g., coated electrostatic chucks, having a dielectric multilayer formed thereon; dielectric multilayers that provide erosive and corrosive barrier protection in harsh environments such as plasma treating vessels used in semiconductor device manufacture; process chambers, e.g., deposition chambers, for processing substrates; methods for protecting substrate supports; and methods for producing substrate supports and electronic devices. The dielectric multilayer comprises (a) an undercoat dielectric layer comprising a metal oxide or metal nitride formed on a surface; and (b) a topcoat dielectric layer comprising a metal oxide formed on the undercoat dielectric layer. The topcoat dielectric layer has an aluminum oxide content of less than about 1 weight percent. The topcoat dielectric layer has a corrosion resistance and/or plasma erosion resistance greater than the corrosion resistance and/or plasma erosion resistance of the undercoat dielectric layer. The undercoat dielectric layer can have a resistivity greater than the resistivity of the topcoat dielectric layer. The topcoat dielectric layer can have a dielectric constant greater than the dielectric constant of the undercoat dielectric layer. The undercoat dielectric layer can have a porosity greater than the porosity of the topcoat dielectric layer. The invention is useful, for example, in the manufacture and protection of electrostatic chucks used in semiconductor device manufacture.

The invention discloses a silicon wafer polishing composition in the field of chemical mechanical polishing (CMP). The polishing composition comprises silica, a polishing interface control agent, a surfactant, a chelating agent, an alkaline compound and water, wherein the particle diameter of the silica in the polishing composition is between 1 and 200 nm; the content of the silica is between 0.05 and 50 weight percent; the polishing interface control agent is polyhydroxy cellulose ether; the content of the polishing interface control agent is between 0.001 and 10 weight percent; the content of the surfactant is between 0.001 and 1 weight percent; the content of the chelating agent is between 0.001 and 1 weight percent; the content of the alkaline compound is between 0.001 and 10 weight percent; the balance being water; and the PH value is between 8.5 and 12. The polishing interface control agent can control a polishing interface between abrasive particles and a polishing object in the chemical mechanical polishing process in order that the surface of the polished silicon wafer is more perfect. The polishing composition is in particular suitable for polishing the silicon wafer and has the advantages of rapid polishing speed, little surface defect and high planeness; and the polished silicon wafer has few metal ion contaminants and is easy to clean.

Crystallization-inducing metal elements are introduced onto an amorphous silicon thin film. A first, low-temperature, heat-treatment induces nucleation of metal-induced crystallization (MIC), resulting in the formation of small polycrystalline silicon “islands”. A metal-gettering layer is formed on the resulting partially crystallized thin film. A second, low-temperature, heat-treatment completes the MIC process, whilst gettering metal elements from the partially crystallized thin film. The process results in the desired polycrystalline silicon thin film.

Pre heat-treatment processing of a silicon wafer to grow a hydrophilic oxide layer includes an initial step of contacting the wafer with a pre-clean SC-1 bath, thereby producing a silicon wafer surface that is highly particle free. After a deionized water rinse, the wafer is scoured with an aqueous solution containing hydrofluoric acid and hydrochloric acid to remove metallic-containing oxide from the wafer surface. In order to grow a hydrophilic oxide layer, an SC-2 bath (containing hydrogen peroxide and a dilute concentration of metal-scouring HCl) is used. The resulting hydrophilic silicon oxide layer grown on the surface of the silicon wafer using the combined SC-1->AF/HCL->SC-2 wafer cleaning process has a metal concentration no greater than 1x109. The diffusion length of minority carriers is increased from a range on the order of 500-600 microns to a range on the order of 800-900 microns.

A substrate manufacturing method includes steps of preparing a bonded substrate stack formed by bonding a second substrate to a first substrate having an insulator at least on a surface, forming a gettering layer to capture a metal contamination on the surface of the bonded substrate stack to form a composite substrate stack, annealing the composite substrate stack, and removing the gettering layer from the composite substrate stack.

An ion implantation apparatus comprises an ion source section (18) for generating ions; an ion implantation section (14) for implanting the ions generated in the ion source section (18), in a substrate (92); a charged particle generator (62) for generating charged particles having a charge opposite to that of the ions; a beam guide section (24) having an inlet aperture (24a) for accepting the ions from the ion source section (18), an outlet aperture (24b) for delivering the ions into the ion implantation section (18), a guide tube (24c) extending from the inlet aperture (24a) to the outlet aperture (24b), and an introducing section (80) having an opening (82) thereof in an internal surface (24d) of the guide tube (24c), for introducing the charged particles from the charged particle generator (62) into the guide tube (24c); and a shield section (84) located between the opening (82) of the introducing section (80) and the outlet aperture (24b) inside the guide tube (24c). A shield surface (84a) of the shield section (84) blocks the charged particles' reaching the wafer.

The silicon wires formed around metal particles by crystal growth have the problem of metal pollution. For its solution, in the present invention, a silicon bridge is formed through standard silicon processes such as the lithography and the wet etching using hydrofluoric acid performed to an SOI substrate. Thereafter, a thermal oxide film is desirably formed at a high temperature to form a high-quality gate insulating film. It is also desirable to form a coaxial gate electrode. Then, after burying the bridge sections of the silicon bridge in a resist film, the silicon on the bridge girders is removed, and thereafter, the silicon wires buried in the resist film are collected. In this manner, the silicon wires can be collected without dispersing into the hydrofluoric acid solution. Then, a transistor using the silicon wires as a channel is formed.

An etchant and an etching method that contribute to prevention of metal contamination of a semiconductor silicon wafer, and a semiconductor silicon wafer in which metal contamination is extremely reduced, are provided. The etchant according to the present invention is prepared by immersing stainless steel in an alkali aqueous solution for not less than 10 hours. In the etching method according to the present invention, a semiconductor silicon wafer is etched by using the etchant. Thereby, the semiconductor silicon wafer according to the present invention, in which metal contamination is extremely reduced, is obtained.

A silicon substrate is manufactured from a single crystal silicon that is doped with phosphorus (P) and is grown by a CZ method to have a predetermined carbon concentration and a predetermined initial oxygen concentration. An n+ epitaxial layer or an n+ implantation layer that is doped with phosphorus (P) at a predetermined concentration or more is formed on the silicon substrate. An n epitaxial layer that is doped with phosphorus (P) at a predetermined concentration is formed on the n+ layer.

Provided are the methods of evaluating thermal treatment. In the methods, a wafer comprising a silicon substrate having an oxygen concentration of approximately equal to or less than 1.0×10¹⁸ atoms/cm³ and a silicon epitaxial layer on at least one surface of the substrate is employed.

A system for measuring gas density in a vacuum includes a gauge, a housing for containing the gauge, and a magnet secured to an exterior surface of the housing. The magnet is a flexible magnetic strips, and positioned around the exterior surface of the housing. The gauge includes grid insulator posts extending longitudinally along a tubular section of the housing, and the magnet is secured to the exterior surface of the housing adjacent to the grid insulator posts, and oriented transversely to the grid insulator posts. The magnet is a flexible magnetic strip, and a clamp secures the magnet to the exterior surface of the housing.

A method of manufacturing a semiconductor device using a metal oxide includes forming a metal oxide layer on a substrate, forming an amorphous semiconductor layer on the metal oxide layer, and forming a polycrystalline semiconductor layer by crystallizing the amorphous semiconductor layer using the metal oxide layer.

The method of manufacturing a semiconductor substrate including mirror polishing a silicon wafer surface, wherein the mirror polishing is conducted using a slurry having a Cu content of approximately equal to or less than 10 ppb, a Ni content of approximately equal to or less than 10 ppb, and an Fe content of approximately equal to or less than 1,000 ppb. The method of evaluating a quality of a semiconductor substrate including etching the surface of the semiconductor substrate by SC-1 cleaning and/or a HF cleaning, detecting bright points on the surface of the etched substrate with a foreign matter inspection device, and evaluating the quality of the semiconductor substrate based on the bright points detected on the surface of the substrate.

In the method for manufacturing a SIMOX wafer, oxygen ions are implanted into a silicon wafer, then the silicon wafer is subjected to a prescribed heat treatment so as to form a buried oxide layer in the silicon wafer. The prescribed heat treatment includes: a step of ramping up a temperature of the silicon wafer in a low oxygen partial pressure gas atmosphere having an oxygen partial pressure ratio of less than 5%; either or both of a step of oxidizing the silicon wafer in a high oxygen partial pressure gas atmosphere having an oxygen partial pressure ratio of 5% or more and a step of annealing the silicon wafer in a low oxygen partial pressure gas atmosphere having an oxygen partial pressure ratio of less than 5%; and a step of ramping down the temperature of the silicon wafer in a low oxygen partial pressure gas atmosphere having an oxygen partial pressure ratio of less than 5%. A hydrogen chloride gas is mixed with the low oxygen partial pressure gas having an oxygen partial pressure ratio of less than 5% in at least one step from among the ramp-up step, the anneal step and the ramp-down step.

Disclosed herein are a chemical mechanical polishing slurry composition for chemical mechanical planarization of metal layers, which comprises a non-ionized, heat-activated nano-catalyst, and a polishing method using the same. The polishing slurry composition comprises: a non-ionized, heat-activated nano-catalyst which releases electrons and holes by energy generated in a chemical mechanical polishing process; an abrasive; and an oxidizing agent. The non-ionized heat-activated nano-catalyst and the abrasive are different from each other, and the non-ionized, heat-activated nano-catalyst is preferably a semiconductor material which releases electrons and holes at a temperature of 10 to 100° C. in an aqueous solution state, more preferably a transition metal silicide selected from the group consisting of CrSi, MnSi, CoSi, ferrosilicon (FeSi), mixtures thereof, and most preferably, a semiconductor material such as nano ferrosilicon. The content of the content of the non-ionized, heat-activated nano-catalyst is 0.00001 to 0.1 wt % based on the total weight of the slurry composition.

The invention discloses a pipeline device for a high-density plasma stock. An NF3 gas for cleaning a cavity and an NF3 gas for participating in an etching process respectively adopt an independent first branch pipe and a second branch pipe to enter the cavity, the NF3 gas for participating in the etching process can directly enter the stock cavity without through a remote plasma system, and thus, the fact that during an STI etching process, due to corrosion of the NF3 gas for participating in the etching process, metal elements are left in the inner cavity of the remote plasma system can be avoided, and metal pollution problems caused by metal element over specification during the STI etching process can be reduced.

A method of manufacturing a semiconductor substrate, in which a silicon layer is provided on a buried oxide film, includes preparing a base substrate having a seed layer of the silicon layer on the buried oxide film with a film thickness equal to or more than 1 nm and equal to or less than 100 nm, and epitaxially growing the seed layer at a temperature equal to or more than 1000° C. and equal to or less than 1300° C. so as to form the silicon layer with a film thickness equal to or more than 1 μm and equal to or less than 20 μm.