91results about How to "Improve component performance" patented technology

An information handling system's thermal management is selectively altered by coupling a thermal barrier to the bottom surface of the information handling system chassis so that an air channel insulates against the passage of thermal energy from the bottom surface. A vent opening in a side of the thermal barrier allows airflow through the air channel to a vent opening of the information handling system. The airflow through the air channel cools the base of the thermal barrier so that an end user will experience reduced thermal energy if the information handling system rests on the end user, such as in the end user's lap.

A caliper assembly comprising: a brake pad comprising a carrier plate having two opposing faces and a top edge a bottom edge and two opposing side edges, wherein on one face is friction material and on the opposing face is a projection adapted to seat in a matched hole or recess in a caliper body, the two opposing side edges each having an ear which is adapted to seat in pad locator indentations in a support structure; a support structure comprising a recess for housing at least one brake pad and at least two pad locator indentations adapted for receiving the ears located on the two opposing sides of the brake pad and at least two caliper body locator indentations for seating two ears defined by the caliper body; and a caliper body having a hole or recess adapted for seating the projection on the opposing face of the brake pad and having two ears on each opposing side which are adapted to seat in the caliper body locator indentations of the support structure; wherein the ears of the brake pad are seated in the pad locator indentations of the support structure, the projection on the opposing face of the brake pad is seated in the hole or recess located in the caliper body, and a clip which engages the opposing face of the brake pad and the caliper body and holds the brake pad in position with respect to the caliper body and the ears of the caliper body are seated in the caliper body locator indentations in the support structure.

A system and method of managing computing systems and, more particularly, to a system and method for modeling applications in a network. The method includes determining dependency of components in a shared distributed computing environment and measuring consumption of the dependent components. The method further includes building a model to compare component behavior with a current load of the dependent components to optimize component performance or to find a deviation and hence a “troubled spot”. The system includes a local agent configured to perform the method and to provide data to a centralized storage.

The invention discloses a polycrystalline silicon film and a preparation method thereof, an array substrate and a display device, belonging to the technical field of semiconductors. The preparation method of the polycrystalline silicon film comprises the following steps of: (1) forming a graphene layer and a noncrystalline silicon layer which are adjacent; and (2) enabling noncrystalline silicon to crystallize and form polycrystalline silicon and obtaining the polycrystalline silicon film. The polycrystalline silicon in the polycrystalline silicon film has the advantages of no pollution and low defect density, the crystal grain size of the polycrystalline silicon is uniform in size, the arrangement is ordered, the crystal grain is larger, and further the surface flatness is better. The speed rate of current carriers in the polycrystalline silicon film prepared by the method is increased, and the element performance of a polycrystalline silicon film transistor is improved.

An automatic packaging method of optical elements includes a focusing platform set, a Z-axis feeder set and an automatic feeding set. The Z-axis feeder set is provided above the focusing platform set. An automatic feeding set is arranged on a horizontal plane between the Z-axis feeder set and the focusing platform set by an appropriate distance. An upper part and a lower part of an optical element are supported by the lower end of the Z-axis feeder set and the upper end of the focusing platform set, respectively. The lower end of the Z-axis feeder set is adjusted vertically and horizontally with respect to the focusing platform set such that the upper part and the lower part are arranged in a line and coincide with each other. Afterward, by using the automatic feeding set, the upper part and the lower part of the optical element are bound together via the solders.

A waterproof enclosure for a cochlear implant system or other hearing assistance device includes an outer housing, an inner support in the interior of the outer housing, an acoustic element supported by the inner support, and water-impermeable polymeric protective membrane sealing the interior of the outer housing against water ingress. A hearing device such as a cochlear implant sound processor, a headpiece, an earhook, or a hearing aid comprises an outer housing, an inner support in the interior of the outer housing, a microphone supported by the inner support, and a water- impermeable polymeric protective membrane sealing the interior of the outer housing against water ingress. A method for waterproofing an acoustic element comprises molding an outer support having a water-impermeable polymeric protective membrane; inserting an acoustic element into an inner support; anchoring the acoustic element to the inner support; inserting the inner support into the outer support; and anchoring the inner support to the outer support.

A graphene-containing electrochemical device includes cathode/anode current collectors, cathode/anode active layers and a separator. The cathode/anode active layers are formed on the cathode/anode current collectors, and include a metal foil substrate and a graphene conductive layer. The graphene conductive layer includes several first graphene sheets and the polymer binder used to bind the first graphene sheets. The cathode/anode active layers include several second graphene sheets and cathode/anode active particles. The second graphene sheets and the cathode/anode active particles are bound by the polymer binder and further adhered to the graphene conductive layer. The second graphene sheets are blended among the cathode/anode active particles. The graphene conductive layer is employed to increase the compatibility between the cathode/anode active material and the metal foil substrate, and to reduce the junction resistance, thereby forming an integrated conductive network and improving the performance of the elements in the device.

The present invention relates to a method for manufacturing transformer of metal-insulant-metal. It is applicable to simultaneously form-metal-insulant-metal capacitor and transformer. Said manufacture method includes the following steps: firstly providing a base plate on which a dielectric layer is formed, then forming a patterned first metal layer of metal-insulant-metal capacitor on said base plate, simultaneously forming first metal coil of transformer, then forming an insulating layer for covering base plate, first metal layer and first metal coil, then forming patterned second metal layer or metal-insulant-metal capacitor on the insulating layer, at same time forming second metal coil of transformer.

A thermal isolation device for a gas turbine combustor assembly includes a plurality of substantially flat plates secured in spaced relationship by a plurality of columns, at least one column incorporating a bolt hole for use in securing the device between a pair of combustor components.

Using Eu²⁺ as the luminescence center for a green-emitting phosphor, a plasma display panel and a PDP device using it are configured by using an Eu²⁺-activated silicate green-emitting phosphate (Ca_1-xM1_x)_2-e.M2.Si₂O₇:Eu_e with improved decay characteristics. In the formula, M1 is at least one element selected from the group containing Sr and Ba; M2 is at least one element selected from the group containing Mg and Zn; and x indicates the mole fraction of the component M1 and e indicates the mole fraction of Eu respectively satisfy the following conditions: 0<x<1 and 0.001≦e≦0.2.

The invention relates to a low temperature polycrystalline silicon thin film transistor and a manufacturing method therefor. A conductive buffer cushion is arranged in a source electrode region and a drain electrode region for preventing the polycrystalline silicon in a contact hole from being etched; and the electrical conductivity among the polycrystalline silicon layer, the source electrode and the drain electrode is improved so as to reduce contact resistance and improve the assembly performance of the polycrystalline silicon thin film transistor.

The invention discloses a manufacturing method of metal oxide semiconductor transistors. This method includes following steps. It first provides a basement. Then, the material layer with the gate structure is formed on the basement. Later, the carbon-containing precursor gas and the reaction gas are pumped to form the carbon-containing mask material layer on the material layer with gate structure. Then, both carbon-containing mask material layer and the gate structure material layer are graphically modeled to form carbon-containing hard mask layer and gate structure. After that, the clearance wall is formed on the side wall of the gate structure and carbon-containing hard mask layer. Subsequently, the protective layer is formed on the basement. Then, some protective layer is removed to expose part of the surface of the substrate. Then, doping epitaxial layer is formed on the exposed surface of the basement formed.

The invention discloses a middle-bolted slit steel plate shear wall and a processing and manufacturing method thereof. The slit steel plate shear wall comprises two vertical slit steel plates and two T-shaped splints, wherein the longitudinal edge of each vertical slit steel plate is provided with a profile steel stiffener; the two vertical slit steel plates are arranged one above the other; a gap for adjusting a vertical installation error is formed between the two vertical slit steel plates; and two T-shaped splints are connected with the two vertical slit steel plates which are arranged one above the other through bolts. A high-intensity bolt connection position of a slit steel plate wall is moved to a middle region in which overturning moment is reduced greatly and the slit steel plate wall is connected with upper and lower frame steel girders by welding, so that the problem of bolt slippage of the slit steel plate wall is solved to a great extent and the increase of a large number of construction expenses for preventing the bolt slippage is avoided. Due to the overcoming or delaying of the bolt slippage, great noise caused by slippage is avoided and the problem of corner instability of the slit steel plate shear wall caused by the slippage is avoided or relieved. Simultaneously, the T-shaped splints form stronger traverse stiffeners in the middle of the slit steel plate wall, so that anti-seismic performance is enhanced remarkably.

The invention provides a grounding strategy for electronic components. In particular, the present provides ground connections in thin-film electronic components by connecting one group of one or more resonators to one ground connection and connecting a second group of one or more resonators to another ground connection.

A semiconductor device, comprising: a substrate which includes an active circuit region, and a boundary region surrounding the active circuit region, the boundary region including an edge portion of the substrate; a first lower conductive pattern disposed on the substrate of the boundary region; and a first upper conductive pattern connected to the first lower conductive pattern over the first lower conductive pattern, wherein the first upper conductive pattern includes a first portion having a first thickness, a second portion having a second thickness greater than the first thickness, and a third portion having a third thickness greater than the second thickness, and the third portion of the first upper conductive pattern is connected to the first lower conductive pattern, is provided.

A helical stacked integrated inductor formed by a first inducing unit and a second inducing unit includes a first helical coil and a second helical coil. The first helical coil is substantially located at a first plane and includes a first outer turn and a first inner turn. The first inner turn is surrounded by the first outer turn. The first helical coil forms a part of the first inducing unit and a part of the second inducing unit. The second helical coil is substantially located at a second plane different from the first plane and overlaps the first helical coil. The second helical coil forms a part of the first inducing unit and a part of the second inducing unit. The first helical coil and the second helical coil are stacked in a staggered arrangement.