40 results about "Low-temperature polycrystalline silicon" patented technology

The application provides a pixel circuit, a pixel driving method and a display device. The pixel circuit comprises a first initialization circuit and a compensation circuit. The first initialization circuit controls a first initial voltage to be provided to a driving control node under the control of a first initial control signal. The compensation circuit controls a compensation node to be in communication with a first node under the control of a compensation control signal. At least one of the first initialization circuit and the compensation circuit comprises an oxide thin film transistor and a low-temperature polysilicon thin film transistor connected in series with each other.

A display substrate is provided to include a base substrate and: a first transistor layer including a first active layer and a second transistor layer including a second active layer sequentially along a direction away from the base substrate; the first and second active layers are provided with at least one insulating layer therebetween, and are made of low-temperature polysilicon materials; the first active layer includes first channel region(s) and first source-drain doped region(s); the second active layer includes second channel region(s) and second source-drain doped region(s); orthographic projections of a second source-drain doped region and a first source-drain doped region on the base substrate overlap with each other; and a second source-drain doped region is connected to a first source-drain doped region through a connecting part filled in a corresponding first via in the insulating layer. A method for manufacturing a display substrate and a display apparatus are provided.

A display substrate and a display device are provided. The display substrate includes: a base substrate, and a low temperature poly-silicon thin film transistor and a metal oxide thin film transistor on the base substrate; the low temperature poly-silicon thin film transistor includes: a low temperature poly-silicon semiconductor layer, a first gate insulating layer, a first gate electrode, a first interlayer insulating layer, a first source electrode, and a first drain electrode; the metal oxide thin film transistor includes: a metal oxide semiconductor layer, a second gate insulating layer, a second gate electrode, a second interlayer insulating layer, a passivation layer, a second source electrode, and a second drain electrode; and the second drain electrode is on a side of the metal oxide semiconductor layer away from the base substrate.

A display panel includes a pixel driving circuit, where the pixel driving circuit includes a driving transistor (T3) and a first transistor (T1), a first electrode of the first transistor (T1) is connected to a gate of the driving transistor (T3), a second electrode thereof is connected to a first initial signal line (Vinit1), the driving transistor (T3) is a P-type low temperature polysilicon transistor, and the first transistor (T1) is an N-type oxide transistor. The display panel further includes: a base substrate, a second conductive layer, a second active layer, a third conductive layer, and a fourth conductive layer.

Embodiments of the present disclosure provide a display substrate and a display device. The display substrate includes a base substrate, a driving circuit layer on the base substrate, a light-emitting structure layer on a side of the driving circuit layer away from the base substrate, and a shield electrode layer on a side of the driving circuit layer proximal to the base substrate. The light-emitting structure layer includes a plurality of light-emitting devices. The driving circuit layer includes a plurality of pixel driving circuits. At least part of transistors in each of the pixel driving circuits are oxide thin film transistors, and at least part of transistors are low-temperature polycrystalline silicon thin film transistors.

The invention discloses an LTPO display panel and a display device. The LTPO display panel comprises a substrate, a buffer layer, a first low-temperature polycrystalline silicon thin film transistor, a second low-temperature polycrystalline silicon thin film transistor and an oxide thin film transistor, each of the first low-temperature polycrystalline silicon thin film transistor and the second low-temperature polycrystalline silicon thin film transistor comprises a low-temperature polycrystalline silicon layer, a first gate insulating layer and a first gate layer which are stacked; the first low-temperature polycrystalline silicon thin film transistor and the second low-temperature polycrystalline silicon thin film transistor are covered with a second gate insulating layer, and at least part of the second gate insulating layer is covered with a second gate layer; the oxide thin film transistor is located above the first low-temperature polycrystalline silicon thin film transistor and / or above the second grid electrode layer. The first low-temperature polycrystalline silicon thin film transistor is of a top gate structure and can serve as a barrier layer, hydrogen ions on the low-temperature polycrystalline silicon thin film transistor are prevented from diffusing to a channel region of the oxide thin film transistor, and the stability of the oxide thin film transistor is improved.

The invention relates to the technical field of super-large-scale integrated circuit manufacturing in the semiconductor industry, and particularly provides a low-temperature polycrystalline silicon thin film transistor, a display panel and a preparation method. The method aims at solving the problems that in the prior art, an optimization method for interface defects is still high in process complexity, cost is increased or the effect is limited. Therefore, the invention provides a preparation method of a low-temperature polycrystalline silicon thin film transistor, which comprises the following steps of: forming an amorphous silicon layer on a substrate; forming a silicon oxide layer on the amorphous silicon layer; laser annealing is carried out, so that the amorphous silicon layer is converted into a polycrystalline silicon layer, the polycrystalline silicon layer is used for forming a channel region and an electrode contact region of the low-temperature polycrystalline silicon thin film transistor, and the thickness of the silicon oxide layer is configured to be capable of inhibiting the height of protrusions formed when the amorphous silicon layer is converted into the polycrystalline silicon layer. According to the method, the protruding height of the polycrystalline silicon layer is reduced, the interface defects of polycrystalline silicon and GI are optimized, and the problems of residual images and the like caused by accumulation of the interface defects are solved.

A display panel and a display device are provided. The display panel includes a display area and a signal detection module. The display area includes a plurality of pixel areas. One pixel area includes at least one pixel and a monitoring unit. The monitoring unit includes a conductive unit. The conductive unit includes a low-temperature polysilicon material; and / or the monitoring unit includes a first driving circuit. The first driving circuit includes at least one low-temperature polysilicon transistor. The signal detection module is used to detect a signal on at least one terminal of the monitoring unit.

A display apparatus includes a substrate having a first substrate, a second substrate, and an inorganic insulating layer between the first substrate and the second substrate. A first buffer layer is on the substrate, wherein the first buffer layer includes n+1 layers, and ‘n’ is 0 or an even number. A first thin film transistor, a second thin film transistor, and a storage capacitor are each on the first buffer layer. The first thin film transistor includes a first active layer formed of a low temperature poly silicon material. The second thin film transistor includes a second active layer formed of an oxide semiconductor material. The storage capacitor includes a first capacitor electrode and a second capacitor electrode.

A display panel and a display apparatus are provided. In the display panel, a first electrode of the threshold compensation transistor is connected to a first electrode of the driving transistor, a second electrode of the threshold compensation transistor is connected to a gate electrode of the driving transistor, and the data writing transistor is connected to a second electrode of the driving transistor, a material of an active layer of the threshold compensation transistor includes low-temperature poly-silicon, the gate line and the scan line are arranged along a second direction, the second direction intersects with the first direction, the gate line is different from the scan line, an active layer of the data writing transistor is located on a side of an active layer of the driving transistor away from the active layer of the threshold compensation transistor in the second direction.

A pixel includes a pixel circuit and an organic light emitting diode. The pixel circuit has first, second, third, and fourth transistors. The first transistor controls an amount of current flowing from a first driving power supply coupled to a first node to a second driving power supply through the organic light emitting diode. The turns on when a scan signal is supplied to a first scan line. The third transistor turns on when a scan signal is supplied to a second scan line. The fourth transistor turns on when a scan signal is supplied to a third scan line. The first transistor is a p-type Low Temperature Poly-Silicon thin film transistor and the third transistor and the fourth transistor are n-type oxide semiconductor thin film transistors.

A display panel, which includes a display area (AA) and a non-display area (NA), wherein a first active layer (123) of the display area (AA) includes low-temperature polysilicon transistors, and a second active layer (127) thereof includes metal oxide transistors; and each of gate driving units (200a) of the non-display area (NA) includes a plurality of gate transistors and a storage capacitor (Cst1) connected to the gate transistors, active parts of the gate transistors and one electrode plate of the storage capacitor (Cst1) being located in mutually different ones of the first active layer (123) and the second active layer (127).

A display panel and a display apparatus are provided. In the display panel, a first electrode of the threshold compensation transistor is connected to a first electrode of the driving transistor, a second electrode of the threshold compensation transistor is connected to a gate electrode of the driving transistor, and the data writing transistor is connected to a second electrode of the driving transistor, a material of an active layer of the threshold compensation transistor includes low-temperature poly-silicon, the gate line and the scan line are arranged along a second direction, the second direction intersects with the first direction, the gate line is different from the scan line, an active layer of the data writing transistor is located on a side of an active layer of the driving transistor away from the active layer of the threshold compensation transistor in the second direction.

This utility model proposes a curved luminous screen for vehicle instrument panels, including an instrument body, which comprises an instrument shell, a mounting plate, and an OLED self-emissive screen. The mounting plate has a mounting cavity, and a control component is disposed between the mounting plate and the instrument shell. A glass cover is disposed on the mounting plate. The OLED self-emissive screen includes a liquid crystal display module, which comprises a polarizing film, a glass encapsulation layer, a low-temperature polycrystalline silicon layer, and a graphite sheet layer arranged sequentially. The use of an OLED self-emissive screen in the vehicle instrument panel only requires power to the illuminated pixels, resulting in 40%-50% lower power consumption than LCD. This is particularly suitable for extending the range of new energy vehicles. Furthermore, the self-emissive nature of OLED pixels allows for a contrast ratio of up to one million to one, with near-pure black, reducing light pollution, especially during nighttime driving, and improving the readability of instrument information. OLED covers the DCI-P3 wide color gamut, with superior color saturation and reproduction compared to LCD, making warning icons, navigation maps, and other details on the instrument panel clearer.

The application discloses a display panel and a display device. The display panel comprises a first transistor and a second transistor which are electrically connected, the first transistor comprises a first active part formed by low-temperature polysilicon material, and the second transistor comprises a second gate and a second active part formed by metal oxide material; the display panel further comprises a substrate, the first active part is arranged on the substrate; the second active part is located on a side of the first active part away from the substrate; the second gate is located on a side of the second active part away from the first active part; and a normal projection of the second active part on the substrate and a normal projection of the first active part on the substrate at least partially overlap. The application can improve the space utilization and resolution of the display panel.

A display panel can include a circuit layer disposed on a flexible substrate, the circuit layer including a plurality of oxide thin film transistors (oxide TFTs) and / or a plurality of low temperature polysilicon thin film transistors (LTPS TFTs), a light-emitting element layer disposed on the circuit layer, the light-emitting element layer including a plurality of light-emitting elements, an encapsulation layer configured to cover the light-emitting element layer, a touch sensor layer disposed on the encapsulation layer, and a color filter layer disposed on the touch sensor layer. Also, the flexible substrate includes a display area and a non-display area, the circuit layer includes a gate driver disposed on at least one of sides of the non-display area, and each of the light-emitting elements includes an anode electrode, an organic compound layer, and a cathode electrode.

The invention discloses a high-transmittance OLED display panel for under-screen fingerprint identification and a preparation method thereof. The high-transmittance OLED display panel comprises a substrate; sequentially forming a buffer layer, a low-temperature polycrystalline silicon layer, a gate insulation layer, a gate layer, an interlayer insulation layer, a source and drain electrode layer, a flat layer, an anode layer, a pixel definition layer, a spacer layer, a light-emitting layer, a cathode layer, a packaging layer, a touch layer and a reflection reduction layer on the substrate; an oxide semiconductor layer is arranged between the gate insulating layer and the gate layer, and the source-drain electrode layer is connected with the oxide semiconductor layer and the low-temperature polycrystalline silicon layer; the anode layer is connected with the source-drain electrode layer; the pixel definition layer and the spacer layer are respectively connected with the anode layer; the light-emitting layer at least partially covers the anode layer; the cathode layer at least partially covers the light-emitting layer, the pixel definition layer and the spacer layer. According to the OLED display panel, except for the driving TFT, the other TFTs are oxide semiconductors, and the transmittance of the oxide semiconductors is far higher than that of low-temperature polycrystalline silicon, so that the transmittance of the OLED display panel is improved.

The invention provides a display device of a hybrid thin film transistor, which belongs to the technical field of display, and comprises a plurality of thin film transistors formed on the same semiconductor substrate, the thin film transistors comprise a first thin film transistor and a second thin film transistor, the first thin film transistor is a low-temperature polycrystalline silicon thin film transistor, and the second thin film transistor is a low-temperature polycrystalline silicon thin film transistor. The second thin film transistor is an oxide semiconductor thin film transistor; the shielding layer is located below the active layer of the first thin film transistor and on the projection perpendicular to the semiconductor substrate, and the shielding layer at least partially covers the active layer of the first thin film transistor and completely covers the channel region of the first thin film transistor; and the shading layer is located below the active layer of the second thin film transistor and on the projection perpendicular to the semiconductor substrate, and the shading layer at least completely covers the active layer of the second thin film transistor. The invention has the beneficial effects that the advantages of the low-temperature polycrystalline silicon thin film transistor and the oxide semiconductor thin film transistor are fully combined, the display effect is ensured while low power consumption is realized, and the device reliability is improved.

The present disclosure provides a display substrate, a preparation method thereof, and a display apparatus. The display substrate includes a base substrate and a drive structure layer disposed on the base substrate, wherein the drive structure layer includes a first transistor and a second transistor arranged side by side, the first transistor includes a low temperature poly silicon transistor, and the second transistor includes an oxide transistor; the first transistor includes a first bottom gate electrode simultaneously served as a shielding layer, the second transistor includes a second bottom gate electrode simultaneously served as a shielding layer, and the first bottom gate electrode and the second bottom gate electrode are arranged in a same layer.

Glasses that are substantially free of alkalis that possess high annealing points and, thus, good dimensional stability (i.e., low compaction) for use as TFT backplane substrates in amorphous silicon, oxide and low-temperature polysilicon TFT processes.

This application belongs to the field of semiconductor devices and discloses an active layer of a semiconductor device, its fabrication method, and its application. The active layer of the semiconductor device includes nanowires and a low-temperature polycrystalline silicon film layer; wherein the nanowires are distributed within the low-temperature polycrystalline silicon film layer. This active layer of the semiconductor device is formed by combining nanowires and a low-temperature polycrystalline silicon film layer, which can improve mobility, carrier lifetime, and reduce on-state resistance.

The invention discloses a preparation method of a low-temperature polycrystalline silicon thin film. The preparation method is used for solving the problems that a low-temperature polycrystalline silicon thin film prepared through an existing preparation method of the low-temperature polycrystalline silicon thin film is unstable in passivation effect, and hydrogen-induced defects are likely to be formed. The method comprises the following steps: forming a buffer layer on a substrate; an amorphous silicon layer is formed on the surface, away from the substrate, of the buffer layer, laser irradiation is conducted on the amorphous silicon layer, the amorphous silicon layer is converted into a first polycrystalline silicon layer, and the first polycrystalline silicon layer comprises a plurality of crystal grains and crystal boundaries located between the crystal grains; carrying out oxidation treatment on the first polycrystalline silicon layer so as to widen crystal boundaries among crystal grains in the first polycrystalline silicon layer and obtain a second polycrystalline silicon film layer; and adding a silicon nanoparticle solution on the surface of the second polycrystalline silicon film layer, and filling the widened grain boundary with silicon nanoparticles, so that the silicon nanoparticles and dangling bonds at the grain boundary form silicon-silicon covalent bonds.

The utility model discloses an array substrate and a low-temperature polycrystalline silicon liquid crystal display panel. The array substrate comprises an active layer, a grid insulating layer, a grid layer and an interlayer insulating layer, the gate insulation layer is manufactured on the active layer, the interlayer insulation layer is manufactured on the gate insulation layer, and the gate layer is manufactured on the gate insulation layer and located in the interlayer insulation layer; the active layer is of a multi-bending structure, and the gate layer forms at least three gates in a channel region corresponding to the active layer. According to the low-temperature polycrystalline silicon liquid crystal display panel, the active layer is designed into the multi-bending structure, so that the grid layer forms a plurality of grids in the corresponding channel region, the total length of the channel is increased, the current in the channel region can be adjusted more efficiently by using the multi-grid structure, the leakage current can be reduced, and the product image quality and the reliability of the low-temperature polycrystalline silicon liquid crystal display panel are improved.

Embodiments disclosed herein generally relate to thin-film transistor (TFT) and capacitor structures. The structures include one or more layers having a dielectric constant greater than five. The layer(s) having the dielectric constant greater than five may be implemented in a second buffer layer, a first bottom gate insulator (Gl) layer, a first top Gl layer, a second top Gl layer, a first low temperature polycrystalline silicon (LTRS) interlayer dielectric (ILD) layer, and / or a first ILD layer. The first top Gl layer may also have a dielectric constant less than five. Implementing the layer(s) with different dielectric constants results in various functional improvements of TFT and capacitor structures.

The application provides a display substrate, a manufacturing method thereof and a display device. The display substrate comprises a substrate and a driving circuit layer arranged on the substrate, the driving circuit layer comprises a plurality of thin film transistors, the plurality of thin film transistors comprises a target transistor, the target transistor comprises a first gate layer, an active layer and a source-drain metal layer, the active layer comprises a low-temperature polysilicon layer and an amorphous silicon layer arranged in a stack, the amorphous silicon layer is located between the low-temperature polysilicon layer and the source-drain metal layer, and the source-drain metal layer is in contact with the amorphous silicon layer. The embodiment of the application can reduce the process steps of the display substrate, help to reduce the manufacturing cost of the display substrate and improve the yield of the display substrate.

A display panel includes a pixel driving circuit, where the pixel driving circuit includes a driving transistor (T3) and a first transistor (T1), a first electrode of the first transistor (T1) is connected to a gate of the driving transistor (T3), a second electrode thereof is connected to a first initial signal line (Vinit1), the driving transistor (T3) is a P-type low temperature polysilicon transistor, and the first transistor (T1) is an N-type oxide transistor. The display panel further includes: a base substrate, a second conductive layer, a second active layer, a third conductive layer, and a fifth conductive layer.

The present disclosure provides a display substrate, a manufacturing method thereof, and a display device. The display substrate includes a substrate and a driving structure layer disposed on the substrate, the driving structure layer includes a first transistor and a second transistor disposed side by side, the first transistor includes a low-temperature polysilicon transistor, and the second transistor includes an oxide transistor; the first transistor includes a first bottom gate electrode serving as a shielding layer, the second transistor includes a second bottom gate electrode serving as a shielding layer, and the first bottom gate electrode and the second bottom gate electrode are disposed in the same layer.

To provide a glass capable of manufacturing a smaller and faster transistor, thereby finally providing a glass for a brighter and faster display.SOLUTION: A glass that is substantially free of alkali and has a high annealing point and therefore good dimensional stability (e.g., low compaction) for use as a TFT backplane substrate in amorphous silicon, oxide, and low temperature polysilicon TFT processes.SELECTED DRAWING: Figure 3

Embodiments disclosed herein generally relate to thin-film transistor (TFT) and capacitor structures. The structures include one or more layers having a dielectric constant greater than five. The layer(s) having the dielectric constant greater than five may be implemented in a second buffer layer, a first bottom gate insulator (GI) layer, a first top GI layer, a second top GI layer, a first low temperature polycrystalline silicon (LTPS) interlayer dielectric (ILD) layer, and / or a first ILD layer. The first top GI layer may also have a dielectric constant less than five. Implementing the layer(s) with different dielectric constants results in various functional improvements of TFT and capacitor structures.

An array substrate includes at least one low temperature polysilicon thin film transistor and at least one oxide thin film transistor. The low temperature polysilicon thin film transistor includes an active layer and a first gate electrode. The oxide thin film transistor includes an oxide semiconductor layer, a second source electrode, and a second drain electrode. The first gate electrode, the second source electrode, and the second drain electrode are disposed in a same layer, and the active layer and the oxide semiconductor layer are disposed in different layers. A method is used for fabricating the array substrate. A display panel includes the array substrate.