765 results about "Oxide thin-film transistor" patented technology

Provided are display apparatuses and methods of operating the same. In a display apparatus, a display image may be continuously held for longer than about 10 msec after the power of the display panel is turned off. The display apparatus may indicate a liquid crystal display (LCD) apparatus including an oxide thin film transistor (TFT). Off leakage current of the oxide TFT may be less than about 10⁻¹⁴ A.

The invention provides a shift register unit and a driving method thereof, a shift register, and a display device. A turn-off module is arranged for breaking the electrical connection among a pulling-up node PU, a pre-charge module and a pulling-down module at a pulling-up stage so that the over-large electric leakage problem of a GOA circuit can be solved, and the reliability and power consumption problem of the adopted GOA circuit applying an oxide film transistor can be effectively solved.

Embodiments of the invention disclose an array substrate and a manufacturing method therefor. The array substrate comprises a plurality of first thin film transistors and a plurality of second thin film transistors; the first thin film transistors and the second thin film transistors are formed above a substrate; the active layer of each first thin film transistor is low-temperature polysilicon; the active layer of each second thin film transistor is an oxide semiconductor; the first thin film transistors are positioned in a peripheral circuit region of the array substrate; the second thin film transistors are positioned in a display region of the array substrate; the grid electrodes of the first thin film transistors and the second thin film transistors are positioned on different layers; and the source and drain electrodes of the first thin film transistors and the source and drain electrodes of the second thin film transistors are positioned on the same layer. By adoption of the array substrate and the manufacturing method therefor, the problem of incompatibility of two film layers of two types of thin film transistors when the metal oxide thin film transistors and the low-temperature polysilicon thin film transistors are formed in a display panel at the same time is solved, so that the electrical performance and the stability of the display panel are improved.

A CMOS thin film transistor arrangement including a PMOS poly-silicon thin film transistor having a top gate configuration and a NMOS oxide thin film transistor having an inverted staggered bottom gate configuration where both transistors share the same gate electrode. The shared gate electrode is used as a doping or implantation mask in the formation of the source and drain regions of the poly-silicon transistor.

An electronic device may include a display having an array of display pixels on a substrate. The display pixels may be organic light-emitting diode display pixels or display pixels in a liquid crystal display. In an organic light-emitting diode display, hybrid thin-film transistor structures may be formed that include semiconducting oxide thin-film transistors, silicon thin-film transistors, and capacitor structures. The capacitor structures may overlap the semiconducting oxide thin-film transistors. Organic light-emitting diode display pixels may have combinations of oxide and silicon transistors. In a liquid crystal display, display driver circuitry may include silicon thin-film transistor circuitry and display pixels may be based on oxide thin-film transistors. A single layer or two different layers of gate metal may be used in forming silicon transistor gates and oxide transistor gates. A silicon transistor may have a gate that overlaps a floating gate structure.

A gate electrode, a gate insulating layer, a semiconductor layer, a drain electrode, a source electrode and a passivation insulating layer are fabricated in turn on an insulating substrate, thereby forming a thin film transistor. The thin film transistor is designed in such a way that a silicon oxide film is employed as a second gate insulating layer adjacent to the semiconductor layer; a thickness of the silicon oxide film is set to the range of 0.5 to 3.0 nm; and it shows the characteristics in which when a stress voltage which is negative with respect to the drain electrode and the source electrode is applied to the gate electrode, the operating threshold voltage is reduced.

The invention belongs to the technical field of liquid crystal display, and particularly relates to an array substrate and a method for manufacturing the same. The oxide film transistor array substrate is provided with a source electrode and/or a drain electrode made of transparent conductive materials, a thin film transistor structure is simplified, and the aperture opening of a liquid crystal display device using the array substrate is increased. A common electrode wire and a data line are arranged on the same layer, the distance between the common electrode wire and a pixel electrode is shortened, storage capacitance is increased, and the performance of the array substrate is improved. When the array substrate is manufactured, by the aid of a half gray-level mask multi-step etching method, an etching protective film and the data line are obtained by means of mask exposure once, only five times of mask exposure are needed during manufacture of the array substrate, the process is simplified, and the manufacturing cost is reduced.

Transistors and methods of manufacturing the same. A transistor may be an oxide thin film transistor (TFT) with a self-aligned top gate structure. The transistor may include a gate insulating layer between a channel region and a gate electrode that extends from two sides of the gate electrode. The gate insulating layer may cover at least a portion of source and drain regions.

Certain example embodiments relate to methods of making oxide thin film transistor arrays (e.g., IGZO, amorphous or polycrystalline ZnO, ZnSnO, InZnO, and/or the like), and devices incorporating the same. Blanket layers of an optional barrier layer, semiconductor, gate insulator, and/or gate metal are disposed on a substrate. These and/or other layers may be deposited on a soda lime or borosilicate substrate via low or room temperature sputtering. These layers may be later patterned and/or further processed in making a TFT array according to certain example embodiments. In certain example embodiments, all or substantially all TFT processing may take place at a low temperature, e.g., at or below 150 degrees C., until a post-annealing activation step, and the post-anneal step may take place at a relatively low temperature (e.g., 200-250 degrees C.).

The invention provides a method for manufacturing a self-aligned metal-oxide film transistor. First, a metal source drain region, a metal-oxide semiconductor channel region and a transparent gate medium layer are sequentially arranged on a glass substrate, then positive photoresist is coated on the gate medium layer, after pre-baking is carried out, exposure, developing and hardbaking are carried out from the back of the glass substrate, afterwards, a layer of conductive film develops with glue, then a gate electrode is obtained after stripping the photoresist and the conductive film, photoetching and etching. The method of the invention can ensure self alignment between the gate electrode and the source drain region of a component, namely, the gate electrode is symmetrically arranged right above between the source and the drain, while, length of the gate electrode is determined by the distance between the source and the drain instead of size of a mask, thus effectively avoiding ghost effect.

A thin film transistor (TFT), a method for fabricating a TFT, an array substrate for a display device having a TFT, and a method for fabricating the same are provided. An oxide thin film transistor (TFT) includes: a gate electrode formed on a substrate; a gate insulating layer formed on the gate electrode; an active layer formed on the gate insulating layer above the gate electrode; an etch stop layer pattern formed on the active layer; a source alignment element and a drain alignment element formed on the etch stop layer pattern and spaced apart from one another; and a source electrode in contact with the source alignment element and the active layer and a drain electrode in contact with the drain alignment element and the active layer.

The invention discloses an electronic equipment display device having pixel circuit arrays. Each pixel circuit can comprise organic light emitting diodes and driving transistors, each driving transistor can be adjusted to control the magnitude of a current flowing through the organic light emitting diodes, each pixel circuit can comprise a storage capacitor and one or more additional transistors such as switch transistors. Semiconductor oxide transistors and silicon transistors are used for forming pixel circuits. Storage capacitor and transistors can be formed through use of metal layers, semiconductor structures and dielectric layers. Some of the layers can be removed along the edge of a display device and therefore the display device can bend conveniently. The dielectric layers can have a multistep shape where data wires in the arrays are allowed to gradually lower toward the surface of a substrate when the data wires extend to an invalid edge area.

There are provided an oxide TFT, a method for fabricating a TFT, an array substrate for a display device having a TFT, and a method for fabricating the display device. The oxide thin film transistor includes: a gate electrode formed on a substrate; a gate insulating layer formed on the entire surface of the substrate including the gate electrode; an active layer pattern formed on the gate insulating layer above the gate electrode and completely overlapping the gate electrode; an etch stop layer pattern formed on the active layer pattern and the gate insulating layer; and a source electrode and a drain electrode formed on the gate insulating layer including the etch stop layer pattern and the active layer pattern and spaced apart from one another, and overlapping both sides of the etch stop layer pattern and the underlying active layer pattern.

A thin film transistor allowed to suppress a failure caused by an interlayer insulating film and improve reliability of a self-alignment structure, and a display device including this thin film transistor are provided. The thin film transistor includes: a gate electrode; an oxide semiconductor film having a channel region facing the gate electrode, and having a source region on one side of the channel region, and a drain region on the other side of the channel region; an interlayer insulating film provided in contact with the oxide semiconductor film as well as having a connection hole, and including an organic resin film; and a source electrode and a drain electrode connected to the source region and the drain region, respectively, via the connection hole.

The embodiment of the invention discloses an amorphous-oxide thin-film transistor, a manufacturing method thereof, and a display panel, relates to the field of design and manufacture of the thin-film transistor and the display panel, which are used for reducing parasitic resistance of a source and a drain. The amorphous-oxide thin-film transistor is characterized in that the substrate comprises a grid electrode, a grid insulating layer, a semiconductor active layer, a source electrode, a drain electrode and a passivation protecting layer, wherein the semiconductor active layer is of a two-layer structure with a channel layer and an ohmic contact layer, and the oxygen content of the channel layer is higher than that of the ohmic contact layer; and in addition, the channel layer and the ohmic contact layer are attached, and the ohmic contact layer is divided into two independent ohmic contact areas which are respectively attached with the source electrode and the drain electrode.

The invention provides an array substrate and a display panel. A driving circuit layer in the array substrate is formed on one side of a substrate, and the driving circuit layer comprises a low-temperature polycrystalline silicon thin film transistor and a low-temperature polycrystalline oxide thin film transistor which are electrically connected. The low-temperature polycrystalline silicon thin film transistor sequentially comprises a polycrystalline silicon active layer, a first grid electrode, a first source electrode and a first drain electrode in the direction away from the low-temperature polycrystalline silicon thin film transistor, and the low-temperature polycrystalline oxide thin film transistor sequentially comprises an oxide active layer, a second grid electrode, a second source electrode and a second drain electrode; a hydrogen barrier layer is formed on at least one side of the upper side or the lower side of the oxide active layer; a pixel electrode layer is formed on the side, away from the substrate, of the drive circuit layer, a pixel electrode is formed through patterning, and the pixel electrode is connected with the first source electrode or the first drain electrode. The hydrogen barrier layer can prevent hydrogen ions in other film layers from invading the oxide active layer to cause device characteristic drift, so that the performance of the transistorsis improved.

The invention provides a thin film transistor and a manufacturing method thereof, an array substrate and a display device. The thin film transistor comprises a substrate, a gate electrode, an active layer, a source drain electrode, a pixel electrode and one or more insulation layers, wherein at least one insulation layer comprises a bottom insulation layer and an upper insulation layer, and the content of the hydrogen in the upper insulation layer is higher than the content of the hydrogen in the bottom insulation layer. The thin film transistor is produced by the double-layer etching barrier layer process, the content of the hydrogen in a silicon oxide thin film in an etching barrier layer is effectively reduced, the hydrogen ion generated by silicane decomposition is prevented from reacting with the metal oxide in the active layer, thus the oxide thin film transistor keeps better characteristics, and the thin film deposition rate of the etching barrier layer is increased.

Provided is a multi-layered memory apparatus including an oxide thin film transistor. The multi-layered memory apparatus includes an active circuit unit and a memory unit formed on the active circuit unit. A row line and a column line are formed on memory layers. A selection transistor is formed at a side end of the row line and the column line.

The invention discloses an array substrate and a manufacturing method thereof, and a display device. The array substrate comprises a substrate, wherein a first region and a second region of the substrate are respectively provided with a first transistor and a second transistor, the first transistor has a first active layer, the first active layer is low temperature polysilicon, the second transistor has a second active layer, the second active layer is metal-oxide semiconductor, the first active layer, an interlayer dielectric layer and the second active layer are sequentially arranged on the substrate, and a blocking layer is arranged between the interlayer dielectric layer and the second active layer. The array substrate is advantaged in that through arranging the blocking layer, the insulation and hydrogen blocking effect between the interlayer dielectric layer of the low temperature polysilicon film transistor and the active layer of the oxide film transistor is realized, hydrogen penetration in the subsequent heat treatment technology between the low temperature polysilicon film transistor and the oxide film transistor can be prevented, and bad influence of transistor characteristics of the low temperature polycrystalline silicon film transistor and the oxide film transistor can be prevented.

The invention discloses an array substrate, a manufacturing method of the array substrate and a display device. The array substrate comprises a first thin film transistor and a second thin film transistor. The first thin film transistor and the second thin film transistor are formed above an underlayer substrate. The first thin film transistor is a polycrystalline silicon thin film transistor. The second thin film transistor is a metallic oxide thin film transistor or an amorphous silicon thin film transistor. The first thin film transistor is located on the peripheral region of the array substrate, and the second thin film transistor is located on the display region of the array substrate. By means of the technical scheme, the problem that the polycrystalline silicon thin film transistor cannot be applied to production of large display panels with the ram being over 6 G is solved, the limit of the excimer laser crystallization process bottleneck is broken through thoroughly, and the array substrate, the manufacturing method and the display device have very high application value.

The present invention provides a manufacturing method of a thin film transistor, an array substrate and a display device, relating to the technical field of display. The invention is used for solving the problems of large current, high power consumption of a low-temperature polysilicon thin film transistor. The thin film transistor comprises semiconductor layers comprising a first semiconductor layer and a second semiconductor layer, and the first semiconductor layer and the second semiconductor layer are laminated. The material of the first semiconductor layer is low-temperature polysilicon, and the carrier mobility of the second semiconductor layer is smaller than the carrier mobility of the first semiconductor layer. The above thin film transistor is used in the array substrate, and pixels are driven.

The invention relates to a sull transistor with an etching barrier layer, which comprises a substrate, a grid, an insulating barrier, an electric conduction channel, a source electrode and a drain electrode; the electric conduction channel is arranged on the surface of the insulating barrier far from the grid and is corresponding to the grid; the etching barrier layer wholly covers the electric conduction channel and the surface of the insulating layer and is provided with a through hole on a position corresponding to the surface of the electric conduction channel; the source electrode and the drain electrode are connected with the electric conduction channel by the through hole in the etching barrier layer. The invention also provides a method for preparing the transistor. The invention has the advantages that the etching barrier layer is adopted for wholly covering the insulating layer and the surface of the electric conduction channel, the through hole is only manufactured on a position needing the connection forming, thus avoiding the influence of a plasma etching technique on the insulating layer and the electric conduction channel and ensuring the stability of the electrical property of the sull transistor.