5677 results about "Polycrystalline silicon" patented technology

The invention provides a remote monitoring and fault diagnosis method for a distributed photovoltaic power generation system, and the method comprises the steps: obtaining the real-time power generation data of a polycrystalline silicon photovoltaic module and a monocrystalline silicon photovoltaic module in the distributed photovoltaic power generation system, and extracting key parameters reflecting the power generation characteristics of different types of photovoltaic modules from the real-time power generation data, establishing a plurality of power generation characteristic models comprising a photovoltaic module layout mode and an array connection topology, wherein the power generation characteristic models are used for describing current and voltage characteristics of the photovoltaic modules under different working conditions; the method comprises the following steps: continuously tracking subsequent power generation current, voltage and power of an abnormal photovoltaic module, optimizing an abnormality diagnosis model, applying the optimized model to other distributed photovoltaic power stations adopting the same photovoltaic module model and array connection topology, and determining model parameters in combination with influences of different geographic positions and environmental conditions.

The embodiment of the invention relates to the field of photovoltaic technology, and provides a solar cell and a preparation method thereof, and a photovoltaic module, so as to avoid the electric leakage condition of doped regions with different doping types, thereby improving the photoelectric conversion efficiency. The solar cell comprises a substrate which comprises a front surface and a back surface which are oppositely arranged; the back surface of the substrate comprises a first doped region and a second doped region which are sequentially arranged at an interval, and an insulating region arranged between the first doped region and the second doped region; the doped polycrystalline silicon passivation contact structure is arranged in the first doped region, the doped amorphous silicon structure is arranged in the second doped region, and the passivation layer is arranged in the insulating region; the doped polycrystalline silicon passivation contact structure comprises a tunneling oxide layer and a doped polycrystalline silicon layer which are sequentially laminated on the back surface of the substrate; the doped amorphous silicon structure comprises a doped amorphous silicon layer, and the doped polycrystalline silicon layer and the doped amorphous silicon layer are different in doping type; wherein the passivation layer is not overlapped with the doped polycrystalline silicon passivation contact structure and the doped amorphous silicon structure respectively along the thickness direction of the substrate.

The present disclosure relates to the technical field of back contact solar cells, and in particular relates to a combined passivation back contact solar cell having front wide band gap doping, and a preparation method therefor. The solar cell comprises a silicon wafer, and a first semiconductor layer, a second semiconductor layer and a third semiconductor layer arranged on the front face of the silicon wafer. The third semiconductor layer comprises a second tunneling oxide layer and a third doped polycrystalline silicon layer, provided in sequence from inside to outside. The third doped polycrystalline silicon layer is a doped polycrystalline silicon layer containing a first doping element and a second doping element, the first doping element being phosphorus, and the second doping element comprising any one of carbon and oxygen. Furthermore, the band gap width of the third doped polycrystalline silicon layer is ≥1.6eV. The present disclosure, while ensuring a passivation effect, can greatly decrease device investment costs, greatly reduce parasitic absorption of a third semiconductor layer on the front surface of a cell, and increase short-circuit current of the cell, thereby increasing cell conversion efficiency.

A method for creating polycrystalline silicon nitride fibers is discussed. The method includes dispersing silicon nitride powder to create dispersed silicon nitride powder. The dispersed silicon nitride powder is classified to create classified fine silicon nitride powder. Likewise, a sintering aid is dispersed to create a dispersed sintering aid and then classified to create a classified sintering aid. A plasticizer, a binder, and the classified sintering aid are added to the classified fine silicon nitride powder to define a compound. The compound is mixed to create a mixed slurry, which is then dried to create a material. The material is extruded through a nozzle that is less than 40 micrometers in diameter to create a preform, which is then sintered to create the polycrystalline silicon nitride fibers.

The invention discloses a solar cell and a preparation method and application thereof, and relates to the technical field of solar cells. P-type doped regions and N-type doped regions are alternately arranged on the back surface of the crystalline silicon substrate, a boron diffusion doped layer, a first passivation layer and a first antireflection layer are sequentially arranged in the P-type doped regions, and a phosphorus-doped silicon oxide layer, a phosphorus-doped polycrystalline silicon layer, a second passivation layer and a second antireflection layer are sequentially arranged in the N-type doped regions from the surface of the crystalline silicon substrate. A traditional TBC battery P region mostly adopts a two-step process of intrinsic amorphous silicon deposition and boron diffusion to form a polycrystalline silicon layer, but the P region does not contain the polycrystalline silicon layer and can be prepared through a one-step boron diffusion process, so that the process steps can be reduced, and the process time can be shortened; and the action of laser and P-region polycrystalline silicon is avoided, the patterning difficulty of the battery is reduced, and the production yield of the battery can be greatly improved.

The invention relates to a back contact battery, a manufacturing method thereof and a photovoltaic module. The back contact cell includes: a substrate; the first passivation contact structure and the second passivation contact structure are arranged in the first region and the second region respectively, the first passivation contact structure comprises a P-type first polycrystalline silicon doped conductive layer, and the second passivation contact structure comprises an N-type second polycrystalline silicon doped conductive layer; the first electrode and the second electrode are electrically connected to the first polycrystalline silicon doped conductive layer and the second polycrystalline silicon doped conductive layer respectively; the first area is provided with a suede structure, and at least part of the orthographic projection of the first electrode on the first surface is located in the setting area of the suede structure; or the second area is provided with a suede structure, and at least part of the orthographic projection of the second electrode on the first surface is located in the setting area of the suede structure. According to the back contact battery and the manufacturing method thereof, the contact loss of the photovoltaic module is relatively small, and the efficiency is relatively high.

The invention discloses an MEMS device architecture, which comprises a cap layer, a device layer and a substrate layer, the cap layer is bonded with the device layer, the bonded whole is bonded with the substrate layer, the cap layer is manufactured based on a first silicon substrate, the bottom of the cap layer is provided with a cavity structure, and the cap layer is internally provided with a high-deep groove structure. A silicon dioxide film is arranged on the groove wall of the high-deep groove structure, polycrystalline silicon is deposited and filled in the high-deep groove structure, and a silicon dioxide layer is arranged on the upper surface of the first silicon substrate; the device layer is manufactured based on an SOI wafer and comprises a first silicon structure layer composed of top layer silicon, a buried oxide layer and a second silicon structure layer composed of back substrate silicon. The substrate layer comprises a second silicon substrate, a bottom layer cavity is formed in the top face of the second silicon substrate, and exhaust holes are formed in the bottom face of the second silicon substrate. According to the method, deep groove etching, polycrystalline silicon groove filling and bonding technologies are combined, advanced materials such as the SOI wafer and the polyimide layer are utilized, and excellent signal isolation and flexibility of various MEMS IMU applications are achieved.

The invention relates to the technical field of MOS semiconductors, and discloses a silicon carbide plane MOS device polysilicon gate self-alignment process and a low resistance structure, the silicon carbide plane MOS device polysilicon gate self-alignment process comprises a plurality of parallel MOS cells, each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode, the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, an N well layer, a P + layer and a P well layer, and the N drift layer comprises a drain electrode, a source electrode and a grid electrode. The height of the P well layer in the single MOS cell is aligned with that of the grid electrode, and the P well layer is located on the left side and the right side of the grid electrode; the N well layer and the P + layer are both located above the grid electrode and the P well layer, and the P + layer is located on the outer side of the N well layer. According to the invention, the height of the P well layer is accurately aligned with the grid electrode, the P well layer is arranged at the two sides of the grid electrode, the design of the T-shaped source electrode is combined, the conduction path is optimized, and when the voltage is applied to the grid electrode, vertical channels are formed at the two sides of the P well layer, so that the path of current flowing from the drain electrode to the source electrode through the N drift layer is shorter and the distribution is uniform.

The disclosure relates to a π type trench gate silicon carbide MOSFET device and a fabrication method thereof. To protect a trench gate oxide layer without increasing a channel resistance and process complexity, a second conductivity type of heavily doped deep well inserted with double gate trenches along the sidewalls of deep well is designed. The deep well is connected to the source metal directly. The electric potential is clamped to the source during the voltage blocking and turn-off state, which reduces the electric field in the gate oxide and reduces the miller capacitance. An interlayer dielectric layer is deposited above the conductive dielectric polysilicon layers and extends outward separately to cover a part of the source region. A smaller cell pitch can be achieved by controlling the spacing between the first and the second trench gate, thereby increasing the channel density and reducing the channel resistance.

The invention relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses a double-gate structure for a high-performance MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and an optimization method, the double-gate structure comprises a plurality of MOS cells, and each MOS cell comprises a drain electrode, a source electrode, a gate electrode, a gate oxide layer and a semiconductor epitaxial layer; the semiconductor epitaxial layer comprises an N substrate layer, an N diffusion layer, a P-layer, a P well layer and an N well layer, two grid electrodes are arranged in a single MOS cell and are respectively positioned on the left side and the right side in a grid oxide layer, and the section outline of the grid oxide layer is semicircular; polycrystalline silicon is arranged in the gate oxide layer and located between the two grid electrodes, and the polycrystalline silicon is in ohmic contact with the source electrode. Through the double-gate structure, geometric shape optimization, doping layer design and process innovation, the switching speed, the voltage endurance capability, the thermal stability and the integration degree of the MOSFET are remarkably improved, meanwhile, the leakage current and the on-resistance are reduced, and the MOSFET is suitable for high-performance power devices and high-frequency application scenes.

The present application relates to a solar cell, a method for manufacturing the same, a photovoltaic module and a photovoltaic system. The solar cell includes: a substrate (110), including a first surface (S1) and a second surface (S2) being opposite to each other, wherein the first surface (S1) has a first region (A) and a second region (B) adjacent to each other in a first direction; a passivating contact layer (120), located in the first region (A) of the first surface (S1); a polysilicon layer (130) located on at least a part of a surface of the passivating contact layer (120) away from the substrate (110); the passivating contact layer (120) including a first tunneling layer (121) and a first doped layer (122), the first tunneling layer (121) and the first doped layer (122) being sequentially stacked on the first region (A) of the first surface (S1) of the substrate (110) in a direction away from the second surface (S2); and a first passivation layer (140), located on a surface of the polysilicon layer (130) away from the passivating contact layer (120) and on the second region (B) of the first surface (S1).

The present disclosure belongs to the technical field of back contact cells, and specifically relates to a back contact cell capable of reducing back parasitic absorption and a manufacturing method therefor. The back contact cell comprises a silicon wafer having a front surface and a back surface, and a first semiconductor layer provided on the back surface of the silicon wafer, the back surface of the silicon wafer being an inverted pyramid textured structure; the first semiconductor layer comprises a tunneling oxide layer and a first doped polycrystalline silicon layer; the inverted pyramid textured structure has alternate flat surfaces and pits sunken in the silicon wafer; the first doped polycrystalline silicon layer comprises a polycrystalline inner layer, a polycrystalline silicon middle layer and a polycrystalline silicon outer layer, the polycrystalline silicon inner layer, the polycrystalline silicon middle layer and the polycrystalline silicon outer layer all being doped with phosphorus, and carbon and / or oxygen; in the polycrystalline silicon inner layer, the polycrystalline silicon middle layer and the polycrystalline silicon outer layer, the amount of doped oxygen gradually decreasing, and the amount of doped carbon and the amount of doped phosphorus gradually increasing. The present disclosure can reduce the parasitic absorption of the back surface while ensuring passivation performance and conductivity, thereby helping to increase short-circuit current density and cell conversion efficiency.

The embodiment of the invention relates to the photovoltaic field, and provides a back contact cell and a manufacturing method thereof, a back contact laminated cell and a photovoltaic module, and the manufacturing method comprises the steps: providing a substrate with a first surface and a second surface which are opposite to each other, and the second surface comprises a first region and a second region which are alternately arranged along a second direction; forming a laminated structure comprising a tunneling layer, a doped polycrystalline silicon layer and a first protection layer which are stacked on the first region; forming an initial second passivation lamination layer which covers the second surface and comprises an intrinsic amorphous silicon film and a doped amorphous silicon film which are stacked; forming a second protection layer on one side, far away from the substrate, of the doped amorphous silicon film; etching the first region by adopting a first laser etching process; and taking the second protection layer on the second region as an etching barrier layer, taking the first protection layer as an etching stop layer, and removing the initial second passivation lamination layer or the second protection layer and the initial second passivation lamination layer remaining on the first region by adopting a first etching solution, thereby at least facilitating the improvement of the photoelectric conversion efficiency of the back contact battery.

The invention provides a solar cell and a preparation method thereof. The solar cell comprises a silicon substrate, the front surface of the silicon substrate is provided with a textured structure, the front surface of the silicon substrate is divided into a working area and an edge isolation area, the working area comprises a p-type emitter, a first passivation layer and a first electrode which are sequentially arranged on the front surface from inside to outside, and the edge isolation area comprises the first passivation layer arranged on the front surface. A tunneling oxide layer, an n-type doped polycrystalline silicon layer, a second passivation layer and a second electrode are sequentially arranged on the back face of the silicon substrate from inside to outside, the reflectivity of the suede structure in the working area is R1, the reflectivity of the suede structure in the edge isolation area is R2, R1 / R2 is within the range of 0.3-3, and R2 is within the range of 0.3-3. And the distance between the suede structure substrate of the working area and the suede structure substrate of the edge isolation area is within the range of 3-10 [mu] m.

The invention discloses a preparation method of a back contact solar cell, which comprises the following steps of: depositing a first tunneling oxide layer, a non-activated amorphous silicon layer containing a first doping element and a silicon oxide layer on a second surface of a silicon substrate, removing the non-activated amorphous silicon layer containing the first doping element and the silicon oxide layer in an E2 region and an E3 region, and annealing to obtain the back contact solar cell. And forming a first doped polycrystalline silicon layer and a silica glass layer containing a first doping element on the surface of the E1 region. According to the preparation method provided by the invention, the process steps of the back contact solar cell, especially the TBC cell, can be effectively optimized, the process time is shortened, the production cost is reduced, and commercialized popularization of the TBC cell is facilitated.

The invention provides a back contact solar cell and a preparation method thereof, and relates to the technical field of back contact solar cells. The preparation method of the back contact solar cell comprises the steps that an isolation area, a P area and an N area are arranged on the back face of a silicon wafer, and the isolation area is located between the P area and the N area; forming a silicon dioxide mask layer only on the isolation region; after a silicon dioxide mask layer is formed on the isolation region, a P-type polycrystalline silicon layer is formed in the P region; after a silicon dioxide mask layer is formed on the isolation region, an N-type polycrystalline silicon layer is formed in the N region; and removing the silicon dioxide mask layer after the P-type polycrystalline silicon layer and the N-type polycrystalline silicon layer are formed. According to the scheme, high-temperature diffusion of impurity atoms can be blocked, and the problem that the photoelectric conversion efficiency of the battery is reduced due to the fact that boron and phosphorus impurity atoms exist at the junction of the P region and the N region at the same time is effectively solved.

The invention relates to the technical field of semiconductors, in particular to a shield gate groove type power device and a preparation method thereof. The method comprises the following steps: preparing a semiconductor wafer to be processed; performing grid polycrystalline silicon deposition on the upper surface of the epitaxial layer of the semiconductor wafer and the groove structure, so that a groove is formed above the groove structure; etching the grid polycrystalline silicon in the groove until the grid polycrystalline silicon reaches the oxide layer above the source polycrystalline silicon to form two sub-grids, and forming an inter-grid groove between the two sub-grids; performing planarization processing on the grid polycrystalline silicon until the oxide layer on the surface of the epitaxial layer is exposed; forming an oxide film dielectric layer which covers the oxide layer covering the upper surface of the epitaxial layer and the grid polycrystalline silicon; and performing planarization processing on the oxide film dielectric layer to obtain a flat surface of the oxide film dielectric layer. According to the shield gate trench type power device and the preparation method thereof provided by the invention, the gate-source overlapping area can be adjusted, the gate-source capacitance is reduced, and the freedom degree of device preparation is increased.

The embodiment of the invention relates to the photovoltaic field, and provides a photovoltaic cell and a manufacturing method thereof, and the manufacturing method comprises the steps: providing a substrate with a first surface and a second surface which are opposite to each other; at least performing doping treatment on the first surface to form a doped layer with a first doped element; performing first laser processing on a part of the doping layer to form an activation part, wherein the residual doping layer is a doping part; performing first etching treatment on the first surface by taking the residual doped layer as a dead layer so as to remove the activated part and form a first suede surface; forming a doped polycrystalline silicon layer with a second doping element and a silica glass layer at least on one side, far away from the doping part, of the substrate; performing second laser treatment on at least part of the silica glass layer to form a loose part; taking the residual silica glass layer as a protective layer, at least carrying out second etching treatment on the second surface to remove the loose part and the doped polycrystalline silicon layer opposite to the loose part, and forming a second textured surface; the laser types adopted by the first laser treatment and the second laser treatment are different, so that the manufacturing process is at least simplified.

According to the SGT MOSFET of the Low-k material and the preparation method of the SGT MOSFET, a gate insulating layer of the SGT MOSFET is deposited by adopting the Low-k material based on carbon-doped silicon oxide, and an oxide layer on the side wall of a shielding gate adopts an ONO structure, so that on one hand, the capacitance effect of a device can be reduced through the Low-k material under the condition that the physical thickness of the insulating layer is kept unchanged and electric leakage is not influenced, and the performance of the device is improved; the performance of the device is improved; and on the other hand, the compactness of the silicon nitride layer is high, and the side wall and the bottom of the shield gate polycrystalline silicon are protected by the silicon nitride layer, so that the on resistance of the device is further reduced and the conduction loss of the device is reduced by improving the doping concentration of the epitaxial layer on the basis of not reducing the breakdown voltage. Meanwhile, by controlling the depth of the oxide layer and the silicon nitride layer which are etched on the side wall of the groove, the silicon nitride layer is far away from the grid polycrystalline silicon, and the reliability of the device is improved.

The invention provides a solar cell and a photovoltaic module, and belongs to the technical field of solar cells. The solar cell includes: a semiconductor substrate; a tunneling oxide layer located on at least one surface of the semiconductor substrate; the doped polycrystalline silicon layer is positioned on one surface, far away from the semiconductor substrate, of the tunneling oxide layer; wherein at least one part of the surface, far away from the tunneling oxide layer, of the doped polycrystalline silicon layer is provided with silicon-containing convex particles. The photovoltaic module provided by the invention comprises the solar cell. According to the invention, the silicon-containing protruding particles are formed on at least one part of the surface, far away from the tunneling oxide layer, of the doped polycrystalline silicon layer, so that the light trapping effect of at least one surface of the solar cell is improved, and the double-sided rate of the solar cell is further improved.

This disclosure relates to an intermediate substrate (10) for the fabrication of a semiconductor substrate, comprising successively: a first semiconductor layer (2), a first thermal barrier layer (5), a support (13) comprising an absorption layer (3) configured to absorb laser radiation in a predetermined wavelength range, the temperature of the absorption layer (3) increasing during absorption, and a separation zone (8) adjacent to the absorption layer (3) and configured to thermally degrade under the effect of the temperature increase of the absorption layer, so as to separate at least a portion of the support (13) from the remainder of the intermediate substrate (10). (Shortcut figure: Fig. 1)

The invention discloses a back contact battery and a photovoltaic module, relates to the technical field of photovoltaic, and aims to improve the manufacturing efficiency of the back contact battery, increase the manufacturing capacity of the back contact battery and reduce the electric leakage risk of the battery. The back contact battery comprises a semiconductor substrate, a first doped silicon layer and a second doped silicon layer. The semiconductor substrate comprises a first surface and a second surface which are opposite. The first surface is provided with a first area and a second area which are distributed at an interval, and an interval area positioned between the first area and the second area; the area ratio of the first region in the first surface is greater than or equal to 50% and less than or equal to 60%. A first doped silicon layer is disposed on the first region. The material of the first doped silicon layer comprises polycrystalline silicon and / or monocrystalline silicon. A second doped silicon layer is disposed on the second region. The conductive type of the second doped silicon layer is opposite to that of the first doped silicon layer. The extinction coefficient corresponding to the first doped silicon layer is larger than the extinction coefficient corresponding to the second doped silicon layer.

A solar cell comprises a substrate, a first passivated contact layer and a second passivated contact layer, a first passivation film layer and a first dielectric layer, and a first electrode. The first passivation film layer is stacked on the first passivated contact layer, in an insulating isolation groove and on the second passivated contact layer; a first through groove is formed in an area, which corresponds to each first polycrystalline silicon doped conductive layer, of the first passivation film layer; one end of the first electrode passes through the first through groove to be in ohmic contact with the first passivated contact layer; and the first dielectric layer covers the first passivation film layer and covers first areas on the first passivated contact layer, wherein the first areas are areas that are located in a surface, which is exposed from the first through groove, of the first passivated contact layer, and are located between side walls of the first through groove and the first electrode.

The invention discloses a passivation contact cell with a selective polysilicon layer and a method of making the same. According to the invention, each laser scanning line on the back surface of the TOPCon solar cell adopts a separation form and is separated by the phosphorus heavily-doped polycrystalline silicon layer, so that overlapping of laser scanning paths does not exist, and a part of the phosphorus-doped polycrystalline silicon layer structure in the surrounding area of the main grid is reserved; according to the structure mode, the transmission distance of carriers in a laser ablation area can be reduced, the carriers can be collected by the fine grid more quickly, and the filling factor FF of the cell is improved especially under the special conditions of grid breakage and the like. According to the invention, the laser grooving area is 40%-80% of the total area of the back of the cell, which is beneficial for balancing the passivation performance of the cell while reducing the parasitic absorption of the polycrystalline silicon to light. The passivation contact cell has high short-circuit current, open-circuit voltage and fill factor.

The invention relates to a preparation method of a solar cell piece and the solar cell piece, and the preparation method of the solar cell piece comprises the following steps: preparing a tunneling oxide layer on the surface of an n-type crystalline silicon substrate, depositing polycrystalline silicon on the surface of the tunneling oxide layer under a first condition, and forming a first polycrystalline silicon layer, polycrystalline silicon is deposited on the surface of the first polycrystalline silicon layer under a second condition to form a second polycrystalline silicon layer, the temperature T1 of the first condition is larger than the temperature T2 of the second condition, the crystallization rate in the first polycrystalline silicon layer is smaller than the crystallization rate in the second polycrystalline silicon layer, annealing treatment and boron diffusion are carried out on the first polycrystalline silicon layer and the second polycrystalline silicon layer under the same condition, and the polycrystalline silicon layer is formed. The first polycrystalline silicon layer is converted into a first doped polycrystalline silicon layer, the second polycrystalline silicon layer is converted into a second doped polycrystalline silicon layer, the ratio F of the concentration of the first doped polycrystalline silicon layer to the concentration of the second doped polycrystalline silicon layer is larger than or equal to 0.01 and smaller than or equal to 0.1, the boron doping concentration in the first doped polycrystalline silicon layer in direct contact with the tunneling oxide layer is reduced, and the passivation level is improved.

The invention relates to the technical field of crystalline silicon solar cells, and particularly discloses a low parasitic absorption TOPCon solar cell which comprises an N-type silicon substrate, a boron emitter is arranged on the front surface of the N-type silicon substrate, a front passivation layer and an antireflection layer are arranged on the side face of the boron emitter, and a tunneling oxide layer is arranged on the back surface of the N-type silicon substrate. Hydrogenated lightly-doped polycrystalline silicon and hydrogenated heavily-doped polycrystalline silicon are arranged on the side surface of the tunneling oxide layer, and conductive oxide is arranged between the hydrogenated lightly-doped polycrystalline silicon and the hydrogenated heavily-doped polycrystalline silicon. According to the low parasitic absorption TOPCon solar cell provided by the invention, on the basis of a TOPCon cell, the thickened fluorine-doped tin oxide is used as the second conductive oxide layer by utilizing the transparent and conductive characteristics of the fluorine-doped tin oxide. Inward diffusion of phosphorus atoms can be effectively prevented during annealing, and inward diffusion of metal Ag can be limited during sintering. Thus, the thinned outer layer hydrogenated heavily doped Poly-Si is configured through the thickened fluorine-doped tin oxide, so that parasitic absorption is reduced.

The invention discloses a back surface structure of a TBC battery, a preparation method of the back surface structure, the TBC battery and a preparation method of the TBC battery, and belongs to the technical field of solar batteries. According to the back surface structure of the TBC battery, the first doped polycrystalline silicon layer is provided with the high-concentration doped region and the low-concentration doped region, so that on one hand, good contact between a metal electrode and polycrystalline silicon is ensured, and meanwhile, the battery has relatively low contact resistance and high conversion efficiency. According to the back surface structure of the TBC battery or the preparation method of the TBC battery provided by the invention, on the basis of ensuring that the thickness of the first doped polycrystalline silicon layer is not reduced, by arranging the low-concentration doped region, the adverse effect of laser patterning processing on subsequent wet etching of polycrystalline silicon is reduced, the wet etching effect of the polycrystalline silicon is ensured, and the production efficiency of the TBC battery is improved. Therefore, on the basis of ensuring the battery performance, the difficulty of the preparation process is reduced, and the battery manufacturing yield is improved.

The invention relates to the technical field of solar cell preparation, and discloses a laser patterned polycrystalline silicon passivation cell, a preparation method and a photovoltaic module. The preparation method comprises the following steps: preparing a passivation contact structure and an oxidation film on the surface of a silicon substrate; laser patterning processing is carried out on the surface of the silicon substrate, the passivation contact structure and the non-metallization area of the oxidation film, so that the processed non-metallization area is not subjected to alkali etching resistance, and doping atoms are pushed into the silicon substrate through laser diffusion to form a doping area; performing alkali wash etching to form an alkali wash etching region etched into the silicon substrate, and leaving a doped region on the silicon substrate exposed in the alkali wash etching region; respectively depositing a passivation antireflection film and an antireflection film on the front surface and the back surface of the silicon substrate; and preparing the metal electrode. According to the preparation method, parasitic absorption loss can be avoided, the transverse transmission capability of internal carriers can be enhanced, the light utilization rate and the photoelectric conversion efficiency of the cell are further improved, the process window is larger, and the process steps are simple.

A MEMS sensor and a preparation method therefor. The method comprises: forming a first oxide layer on a substrate wafer, performing patterned etching on the first oxide layer, and performing deposition and doping on the first oxide layer that has undergone the patterned etching, so as to form a first polycrystalline silicon layer; performing patterned etching on the first polycrystalline silicon layer to form a wiring, and depositing a second oxide layer on the first polycrystalline silicon layer; upon performing patterned etching on the second oxide layer, performing deposition and doping to form a second polycrystalline silicon layer; performing patterned etching on the second polycrystalline silicon layer to form bonding anchor points and a capacitive plate having a lower height than the bonding anchor points; bonding a device wafer with the bonding anchor points, and performing patterned etching on the device wafer to generate a movable structure, so as to obtain a device layer; and bonding the side of the device wafer distant from the substrate wafer with a cover layer.

The invention discloses a combined passivation back contact battery which comprises an N-type silicon wafer, a second intrinsic amorphous silicon layer, a microcrystalline silicon layer, an anti-reflection layer, a second semiconductor opening region, a first semiconductor opening region and a transition region, the anti-reflection layer is a single-layer amorphous silicon carbonitride layer or a laminated structure composed of an amorphous silicon carbide layer and an amorphous silicon carbonitride layer, and the second semiconductor opening area is composed of a first intrinsic amorphous silicon layer, a P-type amorphous silicon layer, a transparent conductive film and a metal electrode which are sequentially arranged on the back face of the silicon wafer. The first semiconductor opening area is composed of a tunneling oxide layer, an N-type polycrystalline silicon layer, a transparent conductive film and a metal electrode which are sequentially arranged on the back face of the silicon wafer, and an opening is etched in the transparent conductive film on the surface of the transition area to form an insulation groove. Amorphous silicon carbonitride or amorphous silicon carbide / amorphous silicon carbonitride laminated layers are adopted as the anti-reflection layers, so that reflection loss is reduced, the reliability and durability of the cell are improved, and the conversion efficiency of the cell is improved.