2078 results about "Polycrystalline silicon" patented technology

A method of manufacturing a semiconductor device includes: preparing semiconductor substrate having a front surface and a back surface opposite to each other, the semiconductor substrate being of a first conductivity type; forming a device structure in the semiconductor substrate, at the front surface; performing thermal oxidation to form a gate insulating film and depositing a polysilicon to form a plurality of gate electrodes; removing the polysilicon at the back surface of the semiconductor substrate while leaving an oxide film formed at the back surface and a side surface of the semiconductor substrate by the thermal oxidation; forming a surface electrode on the device structure; and forming a plating film on the surface electrode while continuing to leave the oxide film at the back surface and the side surface of the semiconductor substrate.

The utility model discloses a water residue and water quenching prevention system for polycrystalline silicon broken material packaging, and particularly relates to the technical field of polycrystalline silicon processing, the system comprises an integrated control unit, a water quenching module, a water residue and water treatment module, a packaging module, a crushing module, a screening module, a drying module, a quality detection module and an environmental adaptability module. According to the water quenching system for preventing moisture residue in the polycrystalline silicon broken material packaging, the utilization rate of materials is improved through efficient crushing and accurate screening, the waterproof performance of products is enhanced through vacuum degassing and automatic humidity control, the consistency of product quality is ensured through automatic quality detection, and the production efficiency is improved. And the safety of the system is improved through integrated control and an emergency discharge device. The characteristics jointly improve the production efficiency, and ensure the stability and reliability of the product in a changeable environment.

A method of forming a device comprises forming sacrificial pillar structures over conductive structures overlying a barrier structure substantially impermeable to hydrogen. The sacrificial pillar structures are separated from one another by trenches linearly extending in a first lateral direction orthogonal to a second lateral direction in which the conductive structures linearly extend. Gate electrodes are formed within the trenches and laterally adjacent sidewalls of the sacrificial pillar structures. The sacrificial pillar structures are removed to form openings between the gate electrodes. Dielectric liner structures are formed within the openings and laterally adjacent sidewalls of the gate electrodes. Channel structures are formed within the openings after forming the dielectric liner structures. The channel structures comprise a semiconductive material having a band gap larger than that of polycrystalline silicon. Conductive contacts are formed on the channel structures. A device, a memory device, and an electronic system are also described.

The invention discloses a perovskite / crystalline silicon laminated cell based on polycrystalline silicon tunnel junction and interface modification, and belongs to the field of photovoltaic technology. The laminated cell is sequentially provided with a crystal silicon bottom cell, a polycrystalline silicon tunnel junction, an interface modification layer and a perovskite top cell from bottom to top. The polycrystalline silicon tunnel junction comprises an n-type polycrystalline silicon layer, an intrinsic layer and a p-type polycrystalline silicon layer from bottom to top; the doping concentration of the n-type polycrystalline silicon layer is gradually reduced towards the intrinsic layer, and the doping concentration of the p-type polycrystalline silicon layer is increased towards the direction far away from the intrinsic layer; the interface modification layer is arranged between the p-type polycrystalline silicon layer and the perovskite top cell; and the interface modification layer is adjacent to an electron transport layer of the perovskite top cell. Through the change design of the doping concentration of the polycrystalline silicon tunneling junction and the design of the interface modification layer and the hole transport layer, the problem of interface compatibility between the polycrystalline silicon tunneling layer and the perovskite top cell and the problem of poor stability of the laminated cell are solved, and the performance of the laminated cell is comprehensively improved.

The invention belongs to the technical field of visible light detection, and aims to realize accurate detection of multicolor visible light and monolithic integration of a multi-wavelength receiver. The invention provides a fully-integrated multicolor visible light detector based on a sub-wavelength polycrystalline silicon grating, which comprises three detectors capable of selectively detecting blue, green and red signals respectively. The principle is as follows: a one-dimensional sub-wavelength polycrystalline silicon grating in the multicolor detector is embedded in an upper SiO2 layer and a lower shallow trench isolation region to form a dielectric waveguide structure of which the middle is a high-refractive-index medium and the periphery is a low-refractive-index oxide layer. The period and the grating width of the sub-wavelength grating are changed, so that the incident polarized light and the sub-wavelength periodic structure are strongly coupled to cause a guided-mode resonance effect, and the sub-wavelength grating can be applied to a transmission optical filter. The size and the cost of the multicolor visible light communication system can be effectively reduced, and the data transmission rate of the system is greatly improved.

The utility model provides a power semiconductor device, comprising a substrate which comprises a body region and a drift region which are arranged at an interval; the first well region is formed in the body region; the substrate leading-out region is formed in the body region, the first well region and the substrate leading-out region are arranged at intervals, the substrate leading-out region comprises a polycrystalline silicon body, the polycrystalline silicon body extends into the body region from the surface of the body region, and the vertical size of the polycrystalline silicon body is larger than the junction depth of the first well region; the first dielectric layer is arranged on the outer side of the polycrystalline silicon body, and the first well region and the polycrystalline silicon body are separated by the first dielectric layer; the second well region is formed in the drift region; the gate dielectric layer is arranged on the surface of the drift region, the gate dielectric layer is located between the body region and the second well region, and the gate dielectric layer is separated from the second well region; and the polysilicon gate layer is arranged on the surfaces of the gate dielectric layer, the drift region, the substrate and the body region. Without increasing the lateral dimension of the semiconductor device, the withstand voltage between the source electrode and the substrate can be improved.

The invention relates to the technical field of silicon carbide semiconductor devices, in particular to an integrally-formed equal-depth double-groove SiC MOSFET structure and a preparation method thereof. According to the structure, an N + buffer layer and an N-drift layer are sequentially formed on an N-type SiC substrate, and a main groove and an auxiliary groove which are consistent in depth are formed in the surface of the N-type SiC substrate; a gate oxide layer and a polycrystalline silicon gate are sequentially formed in the main groove, and the auxiliary groove is filled with a SiC epitaxial material which is doped with the drift layer in the same type, so that a charge compensation and electric field regulation and control unit is formed; the P-type body region surrounds the trench structure and forms an N + source region, and the drain electrode is formed through a back metallization process. Through the collaborative design of the equal-depth double grooves, the uniformization of electric field distribution is realized, the on-resistance and the switching loss are effectively reduced, the thermal stability and the reliability of the device are improved, the integrated process is adopted for integration, the process is simplified, the production efficiency and the yield are improved, and the semiconductor device is suitable for high-frequency and high-voltage application scenes and has a wide industrialization prospect.

The invention provides a back contact solar cell and a photovoltaic module, the back contact solar cell comprises a substrate, the substrate is provided with a backlight surface, and the backlight surface comprises a first polarity area, a second polarity area and an isolation area arranged between the first polarity area and the second polarity area; a first doped layer and a second doped layer, the first doped layer is arranged in the first polarity region, the second doped layer is arranged in the second polarity region, and the doping types of the first doped layer and the second doped layer are opposite; the isolation layer is arranged in the isolation region, the isolation layer comprises an intrinsic polycrystalline silicon layer, a first passivation layer and a third doping layer which are sequentially stacked in the direction away from the substrate, and the doping type of the third doping layer is the same as that of the first doping layer or the second doping layer. The main isolation effect is achieved through the intrinsic polycrystalline silicon layer, the composite passivation effect can be achieved through combination of the first passivation layer and the third doping layer, composite passivation with chemical passivation and field passivation is achieved in the isolation area, and the surface recombination rate is greatly reduced.

The invention relates to the technical field of polycrystalline silicon preparation, and discloses a polycrystalline silicon reduction furnace intelligent regulation and control system based on multi-parameter prediction, which is based on full-dimensional data such as current, raw material purity, silicon rod temperature and the like acquired by a multi-parameter sensing module, and realizes the intelligent regulation and control of a polycrystalline silicon reduction furnace through a burst interference quantification sub-module in a bidirectional linkage fusion prediction module. The deviation entropy quantification interference intensity of the multi-parameter change rate is calculated, migration learning emergency correction terms are synchronously called to dynamically compensate prediction errors, meanwhile, the one-way dependence defect is broken through, and a dynamic physical boundary is provided for a data driving prediction constraint module through physics, electrode contact resistance and in-furnace heat balance parameters; the NMPC module takes a bidirectional fusion high-precision predicted value as a target, solves a multi-target optimization control sequence and issues and executes the multi-target optimization control sequence, and the closed-loop iterative optimization module synchronously updates physical and data model parameters through incremental learning on the basis of an actual regulation and control effect, so that the problems of current regulation lag and formula parameter stiffness are solved, and long-term stable operation of the reduction furnace is supported.

The invention provides a TBC cell P region structure, a TBC cell and a preparation method thereof, and a photovoltaic module, and relates to the technical field of solar cells, the TBC cell P region structure comprises a first tunneling oxide layer, a first boron-doped polycrystalline silicon layer, a second tunneling oxide layer and a second boron-doped polycrystalline silicon layer which are sequentially laminated on the back surface of a silicon substrate; wherein the doping concentration of the second boron-doped polycrystalline silicon layer is higher than that of the first boron-doped polycrystalline silicon layer. In the invention, the bottom layer is doped with i-poly at a relatively low concentration, so that boron accumulation on the interface is inhibited, the BRL (boron-rich layer) concentration is reduced, and a low Auger composite interface is obtained; and then a thin tunneling layer is deposited again, and a second polycrystalline silicon layer is doped with a high concentration, so that auger recombination is reduced, passivation and contact performance is improved, opening voltage is improved, filling factors are improved, and the conversion efficiency of the cell is improved finally.

The invention discloses a TBC battery structure, a preparation method thereof and a TBC battery, in the structure, a P region and an N region are respectively provided with a P-type / N-type doped polycrystalline silicon passivation layer, and an oxygen-doped polycrystalline silicon layer is arranged between the P region and the N region. The preparation method comprises the step of preparing the P-type / N-type doped polycrystalline silicon passivation layer and the oxygen-doped polycrystalline silicon layer on the P region and the N region. In the structure, the oxygen-doped polycrystalline silicon layer is arranged between the P region and the N region, so that the P region and the N region can be effectively separated, an excellent shadow shielding resisting function of a corresponding assembly can be realized, and the generating capacity of the assembly in a shadow shielding environment can be further improved. According to the preparation method, the design of depositing multiple tunneling oxide layers and polycrystalline silicon layers at a time, the design of a laminated mask, a new isolation mode, an efficient cleaning process and the like are adopted, the problems that an existing TBC battery preparation process is tedious, boron-doped polycrystalline silicon laser ablation residues exist, the investment and generation cost is high and the like are effectively solved, and the preparation method is a brand-new TBC battery route.

The invention relates to the technical field of screening devices, in particular to an energy-saving polycrystalline silicon raw material ultrasonic resonance pre-crushing screening tower with a hard impurity removing function and application thereof, the energy-saving polycrystalline silicon raw material ultrasonic resonance pre-crushing screening tower comprises a swinging mechanism, a plurality of screening frames are arranged above the swinging mechanism, and a filtering mechanism is arranged at the tops of the screening frames. According to the energy-saving type polycrystalline silicon raw material ultrasonic resonance pre-crushing screening tower with the hard impurity removing function and the application of the energy-saving type polycrystalline silicon raw material ultrasonic resonance pre-crushing screening tower, the two functions of polycrystalline silicon conveying and hard impurity cleaning can be achieved on the same rotating shaft through switching of forward rotation and reverse rotation of a second motor without an additional power source, and the energy-saving type polycrystalline silicon raw material ultrasonic resonance pre-crushing screening tower is further conveniently cleaned through a knocking part. The knocking block periodically knocks the filter disc, so that the effect of gathering impurities towards the center is enhanced, and the automation degree of impurity removal is improved.

The present disclosure is applicable to the technical field of solar cells. Provided are a solar cell, a cell assembly, and a photovoltaic system. The solar cell comprises: a silicon substrate, which comprises an N region and a P region, wherein the N region and the P region are located on the same surface or two opposite surfaces of the silicon substrate; an N-type doped polysilicon layer, which is arranged on the N region; a P-type doped polysilicon layer, which is arranged on the P region; a first passivation layer, which is provided with several first through holes; a second passivation layer, which is provided with several second through holes; a first electrode, which passes through the several first through holes to come into contact with the N-type doped polysilicon layer; and a second electrode, which passes through the several second through holes to come into contact with the P-type doped polysilicon layer, wherein the contact area of the second electrode and the P-type doped polysilicon layer is greater than that of the first electrode and the N-type doped polysilicon layer. The solar cell of the present disclosure can increase a bonding pull force between a P-type doped polysilicon layer and a second electrode, thereby improving the reliability of a cell structure; and the solar cell can also improve the conductive effect of a P region, thereby improving the conversion efficiency of the cell.

The invention is suitable for the field of photovoltaic technology, and provides a solar cell, a cell assembly and a photovoltaic system, and the solar cell comprises a silicon substrate which is provided with a front surface and a back surface opposite to the front surface; first doped regions and second doped regions are alternately arranged on the back surface of the silicon substrate at intervals; shallow doping without a polycrystalline silicon layer is directly carried out on the surface of the silicon substrate in the first doping region, the first doping layer is formed on the outer surface of the back surface of the silicon substrate, light parasitic absorption is greatly reduced, the cell efficiency and the double-sided rate are improved, meanwhile, the third doping layer is arranged in the second doping region, and the light emitting efficiency is improved. And low recombination and high conductivity of the second doped region are realized. In addition, the dielectric layer of the second doped region effectively adsorbs impurities and inhibits recombination, and the cell efficiency is improved. Finally, the photoelectric conversion efficiency and the double-sided rate of the cell with the structure are greatly improved.

The invention discloses a manufacturing method of a trench gate semiconductor power device. The manufacturing method comprises the following steps: forming a first hard mask layer on a first epitaxial layer; and performing graphical etching on the first hard mask layer to open the forming region of the gate trench. And etching the first epitaxial layer to form a gate trench. And after the first hard mask layer is removed, performing a first thermal oxidation process to form a first field oxide layer on the inner side surface of the gate trench and the outer surface of the gate trench. And performing a first CVD growth process to form a second field oxide layer, and overlapping the first field oxide layer and the second field oxide layer to form a third field oxide layer. And performing a first CMP process to remove the third field oxide layer outside the gate trench. And forming a first polycrystalline silicon layer to completely fill the gate trench and extend out of the gate trench. And performing a second CMP process to flatten the first polycrystalline silicon layer. The structure consistency of the gate trench region and the platform region can be improved at the same time, and the performance and the yield of the device can be comprehensively improved.

The present disclosure relates to the technical field of solar cells. Disclosed are a solar cell, a preparation method therefor and a use thereof. A P-type doped region and an N-type doped region are alternately arranged on the back surface of a crystalline silicon substrate; a boron diffusion doped layer, a first passivation layer and a first anti-reflection layer are sequentially formed in the P-type doped region; and a phosphorus-doped silicon oxide layer, a phosphorus-doped polycrystalline silicon layer, a second passivation layer and a second anti-reflection layer are sequentially formed on the surface of the crystalline silicon substrate in the N-type doped region. The P regions of traditional TBC cells mostly adopt a two-step process of depositing intrinsic amorphous silicon and performing boron diffusion to form a polycrystalline silicon layer. However, the P region of the present disclosure does not contain a polycrystalline silicon layer, and can be prepared by a one-step boron diffusion process, which can reduce the process steps and shorten the process time. The interaction between laser and the polycrystalline silicon in the P region is also avoided, the difficulty of cell patterning is reduced, and the production yield of cells can be greatly improved.

The invention relates to the technical field of chemical engineering, and discloses a trichlorosilane hydrogen reduction polycrystalline silicon growth monitoring system fusing multi-source data. Comprising a multi-sensor monitoring module, a multi-sensor data acquisition module, a multi-source data preprocessing module, a growth process data analysis module, a growth state online evaluation module, a process parameter online regulation and control module, a regulation and control result feedback module and a system collaborative management module, the multi-sensor monitoring module monitors the growth process of trichlorosilane hydrogen reduction polycrystalline silicon through multiple sensors, the multi-sensor data acquisition module acquires original data, the multi-source data preprocessing module preprocesses the data, the growth process data analysis module carries out data calculation, and the growth state online evaluation module carries out online comprehensive evaluation. The process parameter online regulation and control module regulates and controls process parameters online, the regulation and control result feedback module generates an adjustment strategy, and the system collaborative management module performs system parameter recording and storage, system optimization and exception handling.

The invention provides a semiconductor device and a manufacturing method, and relates to the technical field of semiconductors. According to the invention, after a groove structure is formed on a long polycrystalline silicon channel, a high-aspect-ratio region with an extremely high aspect ratio is formed in a shoulder region of the groove structure according to an etching-back process of side wall oxide layers on two sides of the groove structure, and the aspect ratio of the high-aspect-ratio region is far away from the working range of an ultra-high-density plasma oxide deposition process; an oxide filling structure formed in a groove structure based on a high-density plasma oxide deposition process may have bubble defects, and the performance of a device is affected. For the situation, before the high-density plasma oxide deposition process is executed, the oxide interface and the polycrystalline silicon interface in the groove structure are adjusted to be flush to eliminate the high aspect ratio region, so that the aspect ratio of the groove structure meets the working range of the high-density plasma oxide deposition process; therefore, a compact oxide filling structure is formed, and the electrical isolation performance is ensured.

The invention discloses an MEMS device and a preparation method thereof, and relates to the technical field of semiconductor devices. The MEMS device comprises a substrate layer, a stress matching layer and a doped polycrystalline silicon structure layer which are sequentially stacked from bottom to top, and the preparation method comprises the following steps: forming a sacrificial layer on the substrate layer, patterning the sacrificial layer, and defining anchor regions of the stress matching layer and the doped polycrystalline silicon structure layer; depositing a stress matching layer on the patterned sacrificial layer, wherein the stress matching layer is a silicon nitride-based composite film with stress increased from bottom to top in a gradient manner; depositing a doped polycrystalline silicon structure layer on the stress matching layer; and sequentially carrying out patterning treatment and anchor region annealing treatment on the doped polycrystalline silicon structure layer, and carrying out removal treatment and drying treatment on the sacrificial layer to prepare the MEMS device. The MEMS device prepared by the invention has the characteristics of high stress matching, uniform doping concentration and relatively good process compatibility.

The embodiment of the invention provides a back contact crystalline silicon solar cell and a back contact photovoltaic module, the back contact crystalline silicon solar cell comprises a crystalline silicon substrate, the back surface of the crystalline silicon substrate is alternately provided with a first region and a second region, and the first region comprises a current collection region and a lamination region; in the collector region, the back surface of the crystalline silicon substrate is sequentially provided with a doped internal expansion layer, a first interface passivation layer, an N-type doped polycrystalline silicon layer, a transparent conductive oxide layer and a first back electrode, and a plurality of protruding structures are distributed on the surface of the N-type doped polycrystalline silicon layer. The contact area between the protruding structure and the first back electrode through the transparent conductive oxide layer is increased, so that the transmission resistance loss of carriers transported from the crystalline silicon substrate to the first back electrode is reduced, and the photoelectric conversion efficiency of the back contact crystalline silicon solar cell is improved.

The utility model discloses a vacuumizing device and a polycrystalline silicon coral material water-quenching crushing system, relates to the technical field of polycrystalline silicon production, and mainly aims to remove water residues in a water-quenched polycrystalline silicon coral material and ensure the quality of a polycrystalline silicon packaged finished product. According to the main technical scheme, the vacuumizing device comprises a supporting frame and a lifting mechanism; a closed cavity is installed on the upper portion of the supporting frame, the upper end of the closed cavity is connected to a vacuum pump, an opening is formed in the lower end of the closed cavity, and the supporting frame below the closed cavity is fixedly connected to a bearing platform. The lifting mechanism comprises a driving gear, a rack and a sealing plate, the driving gear is rotationally connected to the bearing platform, the rack is slidably connected to the bearing platform through a guide rail, the driving gear is meshed with the rack, the upper end of the rack is fixedly connected to the sealing plate, the upper surface of the sealing plate is fixedly connected to the limiting groove and used for containing coral charge bars, and the sealing plate is matched with the opening.

The invention relates to the technical field of semiconductors, and discloses an ion implantation process optimization method and device, a semiconductor structure and a preparation method thereof.The ion implantation process optimization method comprises the steps that the current position of a current wafer in furnace tube equipment is obtained, the multiple wafers are arranged in the furnace tube equipment, polycrystalline silicon layers are formed on the wafers, and the polycrystalline silicon layers are arranged in the furnace tube equipment; the current wafer is a wafer to be subjected to ion implantation processing at the current moment in the plurality of wafers; according to the current position and a resistance deviation model, the resistance deviation of the polycrystalline silicon layer of the current wafer is determined, and the resistance deviation model is the corresponding relation between the position of the wafer and the resistance under the target temperature and the target gas flow field; according to the resistance deviation, optimization process parameters of the current wafer during ion implantation processing are determined, and the optimization process parameters are used for compensating the resistance deviation. According to the method, the resistance trend caused by the position of the furnace tube can be specifically compensated, the resistance uniformity between sheets is improved, the furnace tube equipment of the LPCVD does not need to be modified, and the production cost is reduced.

The invention discloses a silane and chlorosilane mixed gas treatment process and a control system and method, and relates to the technical field of waste gas treatment in polycrystalline silicon production, and the process comprises the following steps: S1, mixed gas pretreatment; s2, deep removal of chlorosilane; s3, silane is removed, after three-stage treatment, the content of silane in tail gas is smaller than or equal to 1.0 mg / m < 3 >, the content of chlorosilane is smaller than or equal to 1.0 mg / m < 3 >, and then the tail gas is emptied, meanwhile, the control system and the control method suitable for the process are disclosed, optimization treatment of mixed process gas containing chlorosilane, silane, nitrogen and hydrogen generated in polycrystalline silicon production is achieved, use of alkali liquor is reduced, and the production cost is reduced. The emission is reduced, and the production cost is reduced.

The invention relates to a silicon nitride crystal based on high static nitrogen pressure and active nitrogen regulation and a growth method thereof. The silicon nitride crystal is prepared by the growth method, and the method adopts a physical gas phase transmission process and specifically comprises the following steps: introducing high static pressure nitrogen (1-3 bar) and trace NH3 / N2 mixed gas into source powder formed by mixing high-purity beta-Si3N4 and polycrystalline silicon, and dynamically maintaining the gas phase N / Si molar ratio to be (1.33 + / -0.1): 1, thereby inhibiting the decomposition of the source powder and stabilizing the crystal growth; carrying out spray granulation on the source powder, carrying out compression molding, placing the obtained product in a graphite crucible with the inner wall coated with TaC, and carrying out ordered epitaxial growth by controlling the temperature difference of a temperature zone at 1800-2000 DEG C and the axial temperature gradient; according to the method, the dislocation density and the carbon impurity content of the silicon nitride crystal can be remarkably reduced, then the high-purity silicon nitride crystal with a complete structure and a smooth surface is obtained, and the method is suitable for the fields of high-temperature electronic devices and deep ultraviolet light electronics.

The invention relates to a novel semiconductor power device with a built-in gate resistor structure and a preparation method of the novel semiconductor power device. The active region of the semiconductor substrate is provided with a grid electrode electrolyte layer, the grid electrode electrolyte layer is provided with a polycrystalline silicon layer, the polycrystalline silicon layer is provided with first through holes, each first through hole is provided with a temperature coefficient thermistor, the temperature coefficient thermistors extend out of the first through holes, the polycrystalline silicon layer and the temperature coefficient thermistors are provided with interlayer dielectric layers, and the interlayer dielectric layers are arranged between the polycrystalline silicon layer and the temperature coefficient thermistors. The interlayer dielectric layer is provided with a second through hole and a third through hole, the second through hole is filled with a first metal layer, the third through hole is filled with a second metal layer, the interlayer dielectric layer is provided with a grid electrode bonding pad and a grid electrode flow channel, and the grid electrode bonding pad, the grid electrode flow channel and the interlayer dielectric layer are provided with passivation layers. The novel semiconductor power device with the built-in gate resistor structure is designed to solve the technical problem that an existing semiconductor power device with the built-in gate resistor structure is high in loss at a high temperature.

The invention provides a deep trench capacitor and a preparation method thereof. The preparation method comprises the following steps: forming a deep trench in a substrate; forming a first dielectric layer on the inner wall of the deep trench; forming a second dielectric layer on the surface of a part of the first dielectric layer on the deep trench to reduce the opening of the deep trench, the second dielectric layer further extending to the surface of the first dielectric layer above the substrate; the deep trench is filled with polycrystalline silicon, the polycrystalline silicon seals an opening of the deep trench, the polycrystalline silicon forms an air gap in the lower part of the deep trench, and the polycrystalline silicon further extends to the surface of a second dielectric layer above the substrate; forming grooves in the second dielectric layer, the first dielectric layer and the polycrystalline silicon on the surface of the substrate; forming a side wall on the side wall of the groove, wherein the side wall covers part of the surface of the substrate in the groove; a first metal silicide layer is formed on the surface of the polycrystalline silicon, a second metal silicide layer is formed on the surface of the substrate in the groove, and the first metal silicide layer and the second metal silicide layer form an upper pole plate and a lower pole plate of the capacitor respectively.

To provide a semiconductor device capable of improving the dielectric strength between a polysilicon wiring and a semiconductor substrate.SOLUTION: The semiconductor element (DEV1, DEV2) includes a semiconductor element substrate (SUB), a first insulating film (IF1, IF4), a second insulating film (IF2, IF5), a third insulating film (IF3, IF6), and a polysilicon wire (PW1,). PW2. The substrate has a first F1 and a first lower F2 opposite to the first upper surface. The first upper surface has a trench (side TR1, TR2) extending toward the first lower surface. The first insulating film is formed in the trench. The third insulating film is formed above the first insulating film so as to cover an upper surface of the second insulating film. The polysilicon wiring is formed on the third insulating film and electrically insulated from the semiconductor substrate by at least the second insulating film and the third insulating film.SELECTED DRAWING: Figure 1

A semiconductor device includes a peripheral circuit region on a substrate, a polysilicon layer on the peripheral circuit region, a memory cell array region on the polysilicon layer and overlapping the peripheral circuit region, the peripheral circuit region being under the memory cell array region, an upper interconnection layer on the memory cell array region, and a vertical contact through the memory cell array region and the polysilicon layer, the vertical contact connecting the upper interconnection layer to the peripheral circuit region.

The invention relates to the technical field of semiconductors, and discloses a chemical vapor deposition method and device, electronic equipment and a deposition device.The chemical vapor deposition method comprises the steps that identification information of a to-be-deposited product is obtained, the polycrystalline silicon density parameter of the product is extracted, and the theoretical thickness of a thin film is determined according to the polycrystalline silicon density parameter; and dynamically adjusting the first process duration of chemical vapor deposition in combination with the target thickness of the thin film required by device design. According to the method, the original fixed deposition time is converted into process parameters which are adaptively adjusted according to the density of local graphs, so that the deposition time is properly shortened in a graph sparse region to avoid over-thickness, and the deposition time is properly prolonged in a graph dense region to compensate for insufficient film thickness; and the thickness non-uniformity caused by a pattern load effect is effectively counteracted.

The invention provides a semiconductor device threshold voltage control method, system and equipment and a medium, and the control method comprises the steps: manufacturing a gate dielectric layer, and measuring and obtaining the first thickness of the gate dielectric layer; forming a gate polycrystalline silicon layer on the basis of the gate dielectric layer, oxidizing the surface of the gate polycrystalline silicon layer to obtain an ion barrier layer, and measuring and obtaining a second thickness of the polycrystalline silicon layer and a third thickness of the ion barrier layer; and determining the ion implantation amount of grid pre-doping according to the first thickness, the second thickness and the third thickness so as to perform ion implantation on the grid polycrystalline silicon layer, so that the threshold voltage of the device after grid pre-doping is kept within a preset target voltage range. According to the method, the pre-doped threshold voltage can be dynamically adjusted under the condition of not increasing any device manufacturing process steps, and the threshold voltage control precision and the product stability are guaranteed.