4169 results about "Polycrystalline silicon" patented technology

A method for creating polycrystalline silicon nitride fibers is discussed. The method includes dispersing silicon nitride powder to create dispersed silicon nitride powder. The dispersed silicon nitride powder is classified to create classified fine silicon nitride powder. Likewise, a sintering aid is dispersed to create a dispersed sintering aid and then classified to create a classified sintering aid. A plasticizer, a binder, and the classified sintering aid are added to the classified fine silicon nitride powder to define a compound. The compound is mixed to create a mixed slurry, which is then dried to create a material. The material is extruded through a nozzle that is less than 40 micrometers in diameter to create a preform, which is then sintered to create the polycrystalline silicon nitride fibers.

The invention relates to the technical field of MOS semiconductors, and discloses a silicon carbide plane MOS device polysilicon gate self-alignment process and a low resistance structure, the silicon carbide plane MOS device polysilicon gate self-alignment process comprises a plurality of parallel MOS cells, each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode, the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, an N well layer, a P + layer and a P well layer, and the N drift layer comprises a drain electrode, a source electrode and a grid electrode. The height of the P well layer in the single MOS cell is aligned with that of the grid electrode, and the P well layer is located on the left side and the right side of the grid electrode; the N well layer and the P + layer are both located above the grid electrode and the P well layer, and the P + layer is located on the outer side of the N well layer. According to the invention, the height of the P well layer is accurately aligned with the grid electrode, the P well layer is arranged at the two sides of the grid electrode, the design of the T-shaped source electrode is combined, the conduction path is optimized, and when the voltage is applied to the grid electrode, vertical channels are formed at the two sides of the P well layer, so that the path of current flowing from the drain electrode to the source electrode through the N drift layer is shorter and the distribution is uniform.

The disclosure relates to a π type trench gate silicon carbide MOSFET device and a fabrication method thereof. To protect a trench gate oxide layer without increasing a channel resistance and process complexity, a second conductivity type of heavily doped deep well inserted with double gate trenches along the sidewalls of deep well is designed. The deep well is connected to the source metal directly. The electric potential is clamped to the source during the voltage blocking and turn-off state, which reduces the electric field in the gate oxide and reduces the miller capacitance. An interlayer dielectric layer is deposited above the conductive dielectric polysilicon layers and extends outward separately to cover a part of the source region. A smaller cell pitch can be achieved by controlling the spacing between the first and the second trench gate, thereby increasing the channel density and reducing the channel resistance.

The invention relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses a double-gate structure for a high-performance MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and an optimization method, the double-gate structure comprises a plurality of MOS cells, and each MOS cell comprises a drain electrode, a source electrode, a gate electrode, a gate oxide layer and a semiconductor epitaxial layer; the semiconductor epitaxial layer comprises an N substrate layer, an N diffusion layer, a P-layer, a P well layer and an N well layer, two grid electrodes are arranged in a single MOS cell and are respectively positioned on the left side and the right side in a grid oxide layer, and the section outline of the grid oxide layer is semicircular; polycrystalline silicon is arranged in the gate oxide layer and located between the two grid electrodes, and the polycrystalline silicon is in ohmic contact with the source electrode. Through the double-gate structure, geometric shape optimization, doping layer design and process innovation, the switching speed, the voltage endurance capability, the thermal stability and the integration degree of the MOSFET are remarkably improved, meanwhile, the leakage current and the on-resistance are reduced, and the MOSFET is suitable for high-performance power devices and high-frequency application scenes.

The present application relates to a solar cell, a method for manufacturing the same, a photovoltaic module and a photovoltaic system. The solar cell includes: a substrate (110), including a first surface (S1) and a second surface (S2) being opposite to each other, wherein the first surface (S1) has a first region (A) and a second region (B) adjacent to each other in a first direction; a passivating contact layer (120), located in the first region (A) of the first surface (S1); a polysilicon layer (130) located on at least a part of a surface of the passivating contact layer (120) away from the substrate (110); the passivating contact layer (120) including a first tunneling layer (121) and a first doped layer (122), the first tunneling layer (121) and the first doped layer (122) being sequentially stacked on the first region (A) of the first surface (S1) of the substrate (110) in a direction away from the second surface (S2); and a first passivation layer (140), located on a surface of the polysilicon layer (130) away from the passivating contact layer (120) and on the second region (B) of the first surface (S1).

The embodiment of the invention relates to the photovoltaic field, and provides a back contact cell and a manufacturing method thereof, a back contact laminated cell and a photovoltaic module, and the manufacturing method comprises the steps: providing a substrate with a first surface and a second surface which are opposite to each other, and the second surface comprises a first region and a second region which are alternately arranged along a second direction; forming a laminated structure comprising a tunneling layer, a doped polycrystalline silicon layer and a first protection layer which are stacked on the first region; forming an initial second passivation lamination layer which covers the second surface and comprises an intrinsic amorphous silicon film and a doped amorphous silicon film which are stacked; forming a second protection layer on one side, far away from the substrate, of the doped amorphous silicon film; etching the first region by adopting a first laser etching process; and taking the second protection layer on the second region as an etching barrier layer, taking the first protection layer as an etching stop layer, and removing the initial second passivation lamination layer or the second protection layer and the initial second passivation lamination layer remaining on the first region by adopting a first etching solution, thereby at least facilitating the improvement of the photoelectric conversion efficiency of the back contact battery.

The invention provides a solar cell and a preparation method thereof. The solar cell comprises a silicon substrate, the front surface of the silicon substrate is provided with a textured structure, the front surface of the silicon substrate is divided into a working area and an edge isolation area, the working area comprises a p-type emitter, a first passivation layer and a first electrode which are sequentially arranged on the front surface from inside to outside, and the edge isolation area comprises the first passivation layer arranged on the front surface. A tunneling oxide layer, an n-type doped polycrystalline silicon layer, a second passivation layer and a second electrode are sequentially arranged on the back face of the silicon substrate from inside to outside, the reflectivity of the suede structure in the working area is R1, the reflectivity of the suede structure in the edge isolation area is R2, R1 / R2 is within the range of 0.3-3, and R2 is within the range of 0.3-3. And the distance between the suede structure substrate of the working area and the suede structure substrate of the edge isolation area is within the range of 3-10 [mu] m.

The invention relates to a preparation method of a solar cell piece and the solar cell piece, and the preparation method of the solar cell piece comprises the following steps: preparing a tunneling oxide layer on the surface of an n-type crystalline silicon substrate, depositing polycrystalline silicon on the surface of the tunneling oxide layer under a first condition, and forming a first polycrystalline silicon layer, polycrystalline silicon is deposited on the surface of the first polycrystalline silicon layer under a second condition to form a second polycrystalline silicon layer, the temperature T1 of the first condition is larger than the temperature T2 of the second condition, the crystallization rate in the first polycrystalline silicon layer is smaller than the crystallization rate in the second polycrystalline silicon layer, annealing treatment and boron diffusion are carried out on the first polycrystalline silicon layer and the second polycrystalline silicon layer under the same condition, and the polycrystalline silicon layer is formed. The first polycrystalline silicon layer is converted into a first doped polycrystalline silicon layer, the second polycrystalline silicon layer is converted into a second doped polycrystalline silicon layer, the ratio F of the concentration of the first doped polycrystalline silicon layer to the concentration of the second doped polycrystalline silicon layer is larger than or equal to 0.01 and smaller than or equal to 0.1, the boron doping concentration in the first doped polycrystalline silicon layer in direct contact with the tunneling oxide layer is reduced, and the passivation level is improved.

A MEMS sensor and a preparation method therefor. The method comprises: forming a first oxide layer on a substrate wafer, performing patterned etching on the first oxide layer, and performing deposition and doping on the first oxide layer that has undergone the patterned etching, so as to form a first polycrystalline silicon layer; performing patterned etching on the first polycrystalline silicon layer to form a wiring, and depositing a second oxide layer on the first polycrystalline silicon layer; upon performing patterned etching on the second oxide layer, performing deposition and doping to form a second polycrystalline silicon layer; performing patterned etching on the second polycrystalline silicon layer to form bonding anchor points and a capacitive plate having a lower height than the bonding anchor points; bonding a device wafer with the bonding anchor points, and performing patterned etching on the device wafer to generate a movable structure, so as to obtain a device layer; and bonding the side of the device wafer distant from the substrate wafer with a cover layer.

The invention discloses a combined passivation back contact battery which comprises an N-type silicon wafer, a second intrinsic amorphous silicon layer, a microcrystalline silicon layer, an anti-reflection layer, a second semiconductor opening region, a first semiconductor opening region and a transition region, the anti-reflection layer is a single-layer amorphous silicon carbonitride layer or a laminated structure composed of an amorphous silicon carbide layer and an amorphous silicon carbonitride layer, and the second semiconductor opening area is composed of a first intrinsic amorphous silicon layer, a P-type amorphous silicon layer, a transparent conductive film and a metal electrode which are sequentially arranged on the back face of the silicon wafer. The first semiconductor opening area is composed of a tunneling oxide layer, an N-type polycrystalline silicon layer, a transparent conductive film and a metal electrode which are sequentially arranged on the back face of the silicon wafer, and an opening is etched in the transparent conductive film on the surface of the transition area to form an insulation groove. Amorphous silicon carbonitride or amorphous silicon carbide / amorphous silicon carbonitride laminated layers are adopted as the anti-reflection layers, so that reflection loss is reduced, the reliability and durability of the cell are improved, and the conversion efficiency of the cell is improved.

The invention discloses a back contact cell and a preparation method thereof, a laminated cell and a photovoltaic module, and belongs to the technical field of photovoltaics, the back contact cell comprises a substrate, the substrate comprises a first region, a second region and a spacer region located between the first region and the second region, and a tunneling oxide layer and a doped polycrystalline silicon layer are arranged in the first region and the spacer region. The doped polycrystalline silicon layer is arranged on the surface, deviating from the substrate in the thickness direction, of the tunneling oxide layer, the amorphous silicon passivation layer and the doped amorphous silicon layer are arranged in the second region and the spacer region, and the doped amorphous silicon layer is arranged on the surface, deviating from the substrate in the thickness direction, of the amorphous silicon passivation layer. And the amorphous silicon passivation layer in the spacer region is positioned on one side, deviating from the substrate along the thickness direction, of the doped polycrystalline silicon layer. The insulating layer is arranged between the amorphous silicon passivation layer and the doped polycrystalline silicon layer, the insulating layer comprises a first insulating part which extends in the thickness direction and is arranged at the junction position of the second region and the spacer region, the first insulating part can prevent the back contact cell from leaking electricity in the horizontal direction, and the overall electrical performance of the back contact cell is improved.

The invention relates to the technical field of MOS semiconductors, and discloses a vertical D-MOSFET with trench isolation and an improved channel structure and a preparation method, the vertical D-MOSFET comprises a plurality of MOS cells which are parallel to one another, each MOS cell comprises a drain electrode, a source electrode, a grid electrode, a grid oxide layer and a semiconductor epitaxial layer, the semiconductor epitaxial layer comprises an N substrate layer, an N diffusion layer, a P + layer, a P well layer and an N well layer, the profile of the cross section of the grid electrode is triangular, and a polycrystalline silicon covering layer is deposited at the junction of the grid electrode and the gate oxide layer; the profile of the cross section of the gate oxide layer is in a semi-elliptical shape, and the profile of the cross section of the polycrystalline silicon covering layer is in a triangular shape. The section profile of the grid electrode is designed to be triangular, the grid oxide layer is controlled to be in a semi-oval shape, electric field distribution and a carrier migration path are optimized, the triangular grid electrode can reduce electric field concentration at the edge of the grid electrode, and the breakdown risk is reduced.

The invention relates to the technical field of back contact solar cells, in particular to a back contact solar cell with a double-passivation structure and a preparation method thereof, and the front surface of the cell sequentially comprises an antireflection film, a suede structure and an N-type monocrystalline silicon wafer from outside to inside; a back field region on the back surface of the back contact solar cell sequentially comprises a metal electrode, an antireflection film, a second phosphorus-doped polycrystalline silicon layer, a second tunneling oxide layer, a first phosphorus-doped polycrystalline silicon layer, a first tunneling oxide layer and an N-type monocrystalline silicon wafer from outside to inside; the emitter region sequentially comprises a metal electrode, an antireflection film, a transparent conductive film, a boron-doped amorphous silicon layer, an intrinsic amorphous silicon layer and an N-type monocrystalline silicon wafer from outside to inside; the isolation area sequentially comprises an antireflection film, a suede structure and an N-type monocrystalline silicon wafer from outside to inside. A P-type TOPCon structure of an emitter region of the TBC battery is optimized into an intrinsic amorphous silicon + P-type amorphous silicon passivation structure with better passivation performance and contact performance, and the conversion efficiency is improved.

The invention discloses a preparation method of a passivation contact cell with double tunneling polycrystalline silicon layers. A first tunneling oxide layer, a first intrinsic amorphous silicon layer, a low-doping p-type amorphous silicon layer, a second tunneling oxide layer, a high-doping p-type amorphous silicon layer and a first silicon dioxide mask layer are sequentially deposited in a p region on the back surface of a silicon wafer; sequentially depositing a third tunneling oxide layer, a second intrinsic amorphous silicon layer, a low-doping n-type amorphous silicon layer, a fourth tunneling oxide layer, a high-doping n-type amorphous silicon layer and a second silicon dioxide mask layer in an n region on the back surface of the silicon wafer; and the p-type amorphous silicon and the n-type amorphous silicon are simultaneously converted into p-type polycrystalline silicon and n-type polycrystalline silicon through high-temperature annealing crystallization treatment, so that the preparation of the p-region and n-region dual-tunneling passivation contact structure of the TBC battery is realized. The doping level and passivation performance of the p-region p-type polycrystalline silicon and the n-region n-type polycrystalline silicon are improved, the conversion efficiency of the TBC battery is improved, the production steps are reduced, and the preparation cost is reduced.

The invention relates to a TBC battery and a preparation method thereof. The preparation method comprises the following steps: S1, depositing a tunneling oxide layer and a polycrystalline silicon layer; S2, depositing a dopant source layer of first conductive type impurities and a mask layer; S3, opening a film and cleaning; according to the invention, the process flow is simplified, the series resistance is obviously reduced, the current density is improved, the passivation performance and the UV attenuation resistance of the TBC battery are improved, and the conversion efficiency of the battery is improved.

A preparation method of a p-region double-tunneling passivation contact TBC battery comprises the steps that a first tunneling oxide layer, a first intrinsic amorphous silicon layer, a low-doping p-type amorphous silicon layer, a second tunneling oxide layer, a high-doping p-type amorphous silicon layer and a silicon dioxide mask layer are sequentially deposited in a P region on the back face of a silicon wafer, and then the p-type amorphous silicon layer is converted into p-type polycrystalline silicon through high-temperature annealing crystallization treatment. According to the invention, the preparation of the p-region double-tunneling passivation contact structure of the TBC battery is realized, the doping level and passivation performance of p-type polycrystalline silicon in the p region are improved, the conversion efficiency of the TBC battery is improved, and the preparation cost is reduced.

A full-automatic quantitative packaging device for polycrystalline silicon relates to the technical field of polycrystalline silicon packaging equipment, and adopts the technical scheme that the full-automatic quantitative packaging device comprises a rack, a weighing unit, a bag opening unit and a conveying unit, a collecting hopper is arranged at the top of the rack, and a discharging pipe is arranged at the bottom of the collecting hopper; a plurality of weighing units are arranged at the top of the collection hopper, and each weighing unit comprises a weighing bin and a weighing sensor; the bag opening unit comprises a supporting frame and a vertical moving device, the supporting frame is provided with a pair of first telescopic devices, the pair of first telescopic devices are both provided with first connecting plates, and the first connecting plates are provided with suction cups; the conveying unit comprises a conveyor. The steps of automatic quantitative weighing, bag opening packaging, conveying and the like are completed through cooperation of all the assemblies, flexible switching operation among materials with different particle sizes can be achieved, the problem that the labor intensity of manual operation is large is solved, the occupied area is small, the packaging technology is achieved, the structure is simple, and cost is low.

The embodiment of the invention relates to the photovoltaic field, and provides a solar cell piece and a manufacturing method thereof, a laminated cell and a photovoltaic module, and the solar cell piece comprises a substrate which comprises a front surface and a back surface which are opposite to each other, and is also provided with a first region and a second region; the tunneling layer covers the back surface of the substrate; the doped conductive layer covers the surface of the tunneling layer, the doped conductive layer with the orthographic projection located in the first region comprises a first doped sub-layer and a second doped sub-layer which are stacked, the first doped sub-layer covers the surface of the tunneling layer, the second doped sub-layer covers the surface of the first doped sub-layer, and the second doped sub-layer covers the surface of the second doped sub-layer; the doping concentration of the first doping sub-layer is smaller than that of the second doping sub-layer, the second doping sub-layer is made of nanocrystalline silicon, or part of the second doping sub-layer is made of amorphous silicon, and the first doping sub-layer is made of polycrystalline silicon; a passivation layer; and the back electrode is electrically connected with the second doped sub-layer. The reliability of the solar cell can be improved.

The invention relates to the technical field of MOS (Metal Oxide Semiconductor), and discloses an MOSFET (Metal Oxide Semiconductor Field Effect Transistor) semiconductor structure for optimizing source and drain contact, which comprises a drain, a semiconductor epitaxial layer, a source and a grid, the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P well layer, an N well layer and a P-layer, the P-layer is internally provided with source polycrystalline silicon, and the N drift layer is internally provided with drain polycrystalline silicon. The top end of the source polycrystalline silicon is in ohmic contact with the source electrode; three metal oxide layers are arranged in the N well layer, and the top ends of the three metal oxide layers are connected with a source electrode; a plurality of semicircular metal layers are also arranged in the drain electrode; and the semicircular metal layers are in ohmic contact with the N substrate layer. According to the invention, a low-resistance channel is formed through the high-concentration phosphorus-doped heavily-doped gate, the charge and discharge time of gate charges is reduced, and the doped gate provides an additional conductive path, so that the switching time is reduced, the power conversion efficiency is improved, and the heat loss is reduced.

The present invention relates to a solar cell and a preparation method therefor, and a photovoltaic module. The solar cell comprises: an N-type substrate; a patterned first passivation contact structure, which is arranged on a light-receiving surface of the substrate, and comprises a first dielectric layer having a thickness less than or equal to 2 nm and an N-type first doped polysilicon layer; a second passivation contact structure, which is arranged on the entire backlight surface of the substrate, and comprises a second dielectric layer having a thickness greater than 2 nm and having a through hole and a P-type second doped polysilicon layer having a doping concentration of 5×1018 to 3×1020 atom / cm3; a first functional layer on the substrate and the first passivation contact structure; a second functional layer on the second doped polysilicon layer; a first electrode, which penetrates the first functional layer to make ohmic contact with the first doped polysilicon layer; and a second electrode, which penetrates the second functional layer to make ohmic contact with the second doped polysilicon layer.

The invention relates to a silicon carbide super-junction transverse MOS device and a manufacturing method thereof, and belongs to the technical field of semiconductor devices. The device sequentially comprises a substrate and an epitaxial layer from bottom to top, a p column region is arranged on the outer side of the epitaxial layer, a drain region is arranged on the outer side of the p column region, a p well region is arranged on the inner side of the epitaxial layer, a source region is arranged on the inner side of the p well region, a p + region is arranged on the outer side of the p well region, a groove is formed in the middle of the epitaxial layer, and a gate oxide layer is arranged in the groove. A gate polycrystalline silicon is arranged in the gate oxide layer, source electrode metal is arranged on the upper sides of the source electrode region and the p + region, drain electrode metal is arranged on the upper side of the drain electrode region, a dielectric layer is arranged between the source electrode metal and the drain electrode metal, and top layer metal is arranged at the tops of the source electrode metal and the drain electrode metal. According to the invention, the doping concentration of the drift region can be improved while the withstand voltage of the device is ensured, and higher withstand voltage and lower on resistance of the device are realized.

The invention is applicable to the field of photovoltaic technology, and provides a solar cell, a cell module and a photovoltaic system, the solar cell comprises a silicon substrate, the silicon substrate comprises a first area and a second area, a P-type polycrystalline silicon layer is arranged in the first area, and an N-type polycrystalline silicon layer is arranged in the second area; the P-type polycrystalline silicon layer comprises a plurality of P-type crystal grains, a first crystal boundary is arranged between adjacent P-type crystal grains, the N-type polycrystalline silicon layer comprises a plurality of N-type crystal grains, a second crystal boundary is arranged between adjacent N-type crystal grains, and the width of the first crystal boundary is smaller than that of the second crystal boundary. According to the invention, recombination of holes at the grain boundary is reduced, the transmission efficiency of electrons is enhanced, the photoelectric conversion efficiency of the solar cell is improved, the overall stress of the silicon wafer is more balanced, the bending possibility of the silicon wafer is reduced, and the manufacturing yield of the solar cell is finally improved.

The embodiment of the invention relates to the photovoltaic field, and provides a back contact cell and a processing method thereof, a back contact laminated cell and a photovoltaic module, and the processing method comprises the step of texturing a substrate. And carrying out boron diffusion on the substrate to form a boron-doped layer and a borosilicate glass layer on the surface of the substrate. And performing laser etching on the first region and the second region of the substrate, and removing the boron-doped layer, the borosilicate glass layer and part of the substrate in the first region and the second region. And carrying out phosphorus expansion on the substrate, and forming a polycrystalline silicon layer and a phosphorosilicate glass layer on the surface of the substrate. And performing laser etching on the substrate to remove the phosphorosilicate glass layers in the second area and the third area. And texturing the substrate and removing the phosphorosilicate glass layer in the first region and the polycrystalline silicon layers in the second region and the third region to form a textured surface in the second region. And forming a passivation layer on the substrate. Electrode paste is printed in the first area and the third area and sintered. And sintering the back surface of the substrate. The design can improve the double-sided rate and the efficiency of the back contact battery.

The invention discloses a passivation contact cell structure and a preparation method thereof, the structure comprises a silicon substrate, and the back surface of the silicon substrate comprises a metal contact area and a non-metal contact area; a metal contact area on the back face of the silicon substrate is of a suede structure, and the suede structure is sequentially provided with a back face first tunneling oxide layer, a back face first doped polycrystalline silicon layer, a back face second tunneling oxide layer, a back face second doped polycrystalline silicon layer, a back face aluminum oxide layer, a back face silicon nitride layer and a back face electrode in a stacked mode from inside to outside. A non-metal contact area on the back face of the silicon substrate is of a polished face structure, and a first back face tunneling oxide layer, a first back face doped polycrystalline silicon layer, a back face aluminum oxide layer and a back face silicon nitride layer are sequentially arranged on the polished face structure in a stacked mode from inside to outside. According to the battery structure, parasitic absorption can be reduced, current gain is brought, diffusion of silver ions in electrode slurry can be inhibited, and metal recombination is improved; the interface contact resistance can be obviously improved, and the cell efficiency can be improved.

The invention relates to a SiC groove type JFET device structure and a preparation method thereof. The SiC groove type JFET device structure comprises a drain metallization layer, a SiC N + substrate layer, a first N type drift region, a source groove structure, a second N type drift region, a P-well region, an N + source region, a P + gate region, an isolation dielectric layer, a gate metallization layer and a source metallization layer. The source trench structure is arranged in the first N-type drift region, the upper surface of the source trench structure is in contact with the P-well region and the source metallization layer, and an oxide layer and a polycrystalline silicon layer are sequentially filled in a trench, so that the upper surface of the trench structure is flush with the upper surface of the first N-type drift region. By introducing the trench structure connected with the source electrode in the drift region, the transverse electric field distribution condition in the device can be optimized, the peak electric field is reduced, the conduction capability of the device is further improved under the condition of ensuring that the original breakdown voltage is not changed, the performance of the SiC JFET is greatly improved, and the conduction loss during working is reduced.

A shield trench power device such as a trench MOSFET or IGBT includes a substrate or an epitaxial layer of silicon, silicon carbide, gallium nitride, or gallium arsenide and employs an in-trench structure including a gate structure and an underlying polysilicon or oxide shield region that contacts a shield region in an epitaxial or crystalline layer of the device. The poly silicon region may be laterally confined by spacers in a gate trench and may contact or be isolated from the underlying shield region. Alternatively, the polysilicon region may be replaced with an insulating region.

The invention provides a solar cell and a preparation method thereof, the solar cell comprises a silicon substrate and a laminated structure, and the laminated structure is arranged on the back surface of the silicon substrate along the thickness direction of the solar cell. The silicon substrate and the laminated structure contain the antimony element, and the antimony element in the laminated structure can be bonded with the silicon element, so that the passivation effect is effectively improved, the problem of low carrier conductivity is solved, and the working efficiency of the solar cell is improved. The laminated structure at least comprises a first tunneling oxide layer, a first doped polycrystalline silicon layer, a second tunneling oxide layer and a second doped polycrystalline silicon layer which are sequentially stacked in the thickness direction of the solar cell. The doping concentrations of antimony elements in the first tunneling oxide layer, the first doped polycrystalline silicon layer, the second tunneling oxide layer and the second doped polycrystalline silicon layer are different, so that the antimony elements among the structural layers of the laminated structure have concentration gradient characteristics, and the conductivity of carriers in the laminated structure is further improved.

The utility model relates to the technical field of solar cells, and discloses a solar cell which is provided with a grid line area and a non-grid line area. The solar cell includes: a silicon substrate; the backlight surface is provided with a first backlight area and a second backlight area, the first backlight area corresponds to the grid line area in position, and the second backlight area corresponds to the non-grid line area in position; the patterned passivation contact structure comprises a dielectric layer and a doped polycrystalline silicon layer, the doped polycrystalline silicon layer is provided with a first surface deviating from one side of the dielectric layer, and a patterned area of the passivation contact structure corresponds to the grid line area in position; the first functional layer is arranged on the surface of the silicon substrate and the doped polycrystalline silicon layer corresponding to the second backlight area; the first electrode penetrates through the first functional layer and is in ohmic contact with the doped polycrystalline silicon layer; the flatness of the first surface is higher than that of the second backlight area. The solar cell can reduce the problem of film explosion of the first passivation layer and reduce the contact resistance between the doped polycrystalline silicon layer and the first electrode.

The invention relates to the technical field of solar cells, and particularly discloses a high-boron-doped single-mask TBC solar cell structure and a manufacturing method thereof.In the process of forming a patterned region, a P region does not need a mask structure, and through the combination of boron diffusion doping, annealing and two-time laser doping treatment, the high-boron-doped single-mask TBC solar cell structure is obtained. The boron atom doping concentration of the polycrystalline silicon layer is greatly improved, so that the boron-doped polycrystalline silicon layer in the P region is high in doping concentration and uniform in doping. According to the TBC solar cell prepared by the method, the processes of preparing and removing the mask structure are simplified, the technological process is short, the manufacturing cost is low, the contact resistance is reduced, the passivation effect is improved, the filling factor of the cell is increased, and the efficiency of the cell is improved. And the open-circuit voltage and the photoelectric conversion efficiency of the battery are improved.

The present application discloses a cell contact structure, a semiconductor device, and a method for fabricating the semiconductor device. The cell contact structure includes a contact layer positioned on a substrate and enclosed by a plurality of bit line structures and a plurality of partition layers; and a liner layer positioned between the contact layer and the substrate, between the contact layer and the plurality of bit line structures, and between the contact layer and the plurality of partition layers. A top surface of the contact layer and a top surface of the liner layer are substantially coplanar. The liner layer includes doped polycrystalline silicon, doped polycrystalline germanium, or doped polycrystalline silicon germanium. The contact layer includes tungsten, titanium, or titanium nitride.