2846 results about "Polycrystalline silicon" patented technology

The invention discloses a back contact cell and a preparation method thereof, a laminated cell and a photovoltaic module, and belongs to the technical field of photovoltaics, the back contact cell comprises a substrate, the substrate comprises a first region, a second region and a spacer region located between the first region and the second region, and a tunneling oxide layer and a doped polycrystalline silicon layer are arranged in the first region and the spacer region. The doped polycrystalline silicon layer is arranged on the surface, deviating from the substrate in the thickness direction, of the tunneling oxide layer, the amorphous silicon passivation layer and the doped amorphous silicon layer are arranged in the second region and the spacer region, and the doped amorphous silicon layer is arranged on the surface, deviating from the substrate in the thickness direction, of the amorphous silicon passivation layer. And the amorphous silicon passivation layer in the spacer region is positioned on one side, deviating from the substrate along the thickness direction, of the doped polycrystalline silicon layer. The insulating layer is arranged between the amorphous silicon passivation layer and the doped polycrystalline silicon layer, the insulating layer comprises a first insulating part which extends in the thickness direction and is arranged at the junction position of the second region and the spacer region, the first insulating part can prevent the back contact cell from leaking electricity in the horizontal direction, and the overall electrical performance of the back contact cell is improved.

A shield trench power device such as a trench MOSFET or IGBT includes a substrate or an epitaxial layer of silicon, silicon carbide, gallium nitride, or gallium arsenide and employs an in-trench structure including a gate structure and an underlying polysilicon or oxide shield region that contacts a shield region in an epitaxial or crystalline layer of the device. The poly silicon region may be laterally confined by spacers in a gate trench and may contact or be isolated from the underlying shield region. Alternatively, the polysilicon region may be replaced with an insulating region.

A method of manufacturing a semiconductor device includes: preparing semiconductor substrate having a front surface and a back surface opposite to each other, the semiconductor substrate being of a first conductivity type; forming a device structure in the semiconductor substrate, at the front surface; performing thermal oxidation to form a gate insulating film and depositing a polysilicon to form a plurality of gate electrodes; removing the polysilicon at the back surface of the semiconductor substrate while leaving an oxide film formed at the back surface and a side surface of the semiconductor substrate by the thermal oxidation; forming a surface electrode on the device structure; and forming a plating film on the surface electrode while continuing to leave the oxide film at the back surface and the side surface of the semiconductor substrate.

The invention provides a silicon carbide trench MOSFET device with a three-side trench structure and a preparation method thereof, and the method comprises the steps: growing a silicon carbide epitaxy on a silicon carbide substrate, and carrying out the injection to form a P-well region; forming a first barrier layer on the P-well region, and performing injection to form a P + region; removing the first barrier layer to form a second barrier layer, and performing injection to form an N + region; removing the second barrier layer, and simultaneously performing rapid thermal annealing on the P-well region, the P + region and the N + region; forming a third barrier layer, and etching to form a gate trench region; removing the third barrier layer, and performing dry-oxygen thermal oxidation to form a gate oxide layer; forming polycrystalline silicon by using chemical vapor deposition; after the polycrystalline silicon is doped, etching is carried out to form a grid electrode; and depositing metal to form a drain electrode and a source electrode, and performing rapid thermal annealing on the drain electrode and the source electrode to form ohmic contact. By arranging the three-side groove structure, the area of the channel is increased, and conduction resistance is reduced.

The invention relates to the technical field of semiconductors, in particular to a source heterojunction contact semiconductor structure and device and a manufacturing method, the semiconductor structure comprises a gate structure, a body region structure, a source structure and a drain structure, and the source structure comprises a polycrystalline silicon source contact layer; the semiconductor structure comprises a body region structure and a polycrystalline silicon source contact layer, the body region structure is surrounded by the gate structure, a source contact region is arranged in the body region structure, the polycrystalline silicon source contact layer is in contact with the source structure through the source contact region so as to form a heterojunction diode with the source structure, and the heterojunction diode is a freewheeling diode of the semiconductor structure. The drain electrode structure is located on one side, back to the gate electrode structure, of the body region structure; the semiconductor structure can be a SiC MOSFET structure, reverse conduction voltage drop during follow current of the SiC MOSFET can be greatly reduced, and conduction loss and loss caused during switching are reduced.

The invention provides a shield gate trench MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure and a manufacturing method thereof, according to the manufacturing method, a field oxide layer is formed twice (a first oxide layer and a second oxide layer), a polycrystalline silicon interlayer is introduced between the first oxide layer and the second oxide layer, and the polycrystalline silicon interlayer is only reserved on a side wall opposite to a non-floating shield gate layer after being etched twice, so that the field oxide layer is formed in the first oxide layer and the second oxide layer; and a floating shield grid layer is formed. As the floating shield grid layer is introduced to the side wall opposite to the non-floating shield grid layer, the field intensity of the middle area in the depth direction of the groove can be increased, and the overall voltage endurance capability is improved. The floating shield gate layer is introduced into the shield gate trench MOSFET structure, so that the voltage withstanding level of a device can be improved, and the voltage withstanding level of the device can be improved by utilizing a capacitive coupling effect between a part of the floating shield gate layer and a part of the floating shield gate layer and a capacitive coupling effect between a source electrode and the drain electrode. Therefore, gate-drain capacitance and source-drain capacitance of the device can be reduced, and switching speed of the device is improved.

The invention relates to a preparation method of a local ITO interconnected perovskite-TOPCon laminated cell, which comprises the following steps: taking an n-type monocrystalline silicon wafer as a substrate, cleaning and texturing, diffusing boron on the back to form a P + emitter, oxidizing at high temperature, and treating the surface through acid etching and alkali polishing; sequentially preparing a tunneling oxide layer and a phosphorus-doped polycrystalline silicon layer on the front surface, annealing and crystallizing, depositing an aluminum oxide film and a multi-layer silicon nitride film on the back surface after cleaning, and depositing a single-layer silicon nitride film on the front surface; preparing a back metal electrode, etching according to a designed pattern to remove a local silicon nitride film on the front surface, sequentially preparing an ITO interconnection layer, a hole transport layer, a perovskite layer, a passivation layer, an electron transport layer and an ITO transparent conductive layer on the front surface, and finally preparing a front metal electrode and solidifying to form a contact electrode. According to the invention, the problems of back corrosion risk, effective area loss and tedious process in the existing method are solved, full-size manufacturing is realized, the cell performance is improved, and industrialization is easier.

The invention provides a solar cell, a manufacturing method thereof, a cell module and a photovoltaic system. The solar cell comprises a silicon substrate and a passivation structure. The passivation structure comprises a dielectric layer, a first polycrystalline silicon layer arranged on one side, back to the silicon substrate, of the dielectric layer, and at least one second polycrystalline silicon layer; wherein the first polycrystalline silicon layers are nitrogen-doped polycrystalline silicon layers, the nitrogen concentration of at least one first polycrystalline silicon layer is larger than that of any second polycrystalline silicon layer, and the nitrogen concentration of at least one first polycrystalline silicon layer ranges from 0.3 at.% to 35 at.%. According to the solar cell, the nitrogen-doped first polycrystalline silicon layer is introduced into the passivation structure of the solar cell, so that the polycrystalline silicon layer has a stress buffering function, the interface stress of the dielectric layer in the high-temperature passivation process can be effectively reduced, the risk that the dielectric layer in the solar cell has a notch is reduced, and the performance of the solar cell is improved. Therefore, the passivation effect of the solar cell can be improved.

The invention relates to the technical field of photovoltaic power generation, and discloses a solar cell and a preparation method thereof, and a photovoltaic module. The invention provides a solar cell. The doping concentration of a boron element in a first doped polycrystalline silicon layer is 8 * 10 < 19 > atoms / cm < 3 > to 8 * 10 < 20 > atoms / cm < 3 >; a second tunneling oxide layer, wherein the second tunneling oxide layer is arranged in the second region of the silicon substrate; and the second doped polycrystalline silicon layer is arranged on one side, far away from the silicon substrate, of the second tunneling oxide layer. Therefore, the high-doping-amount contact structure of the backlight surface of the solar cell has relatively high passivation quality and good contact characteristics, and carrier recombination and resistance loss can be reduced, so that the photoelectric conversion efficiency of the solar cell is improved.

An embodiment of the present disclosure relates to the field of photovoltaics, and provides a solar cell and a manufacturing method thereof. The manufacturing method includes the steps of: providing a substrate having a first surface and a second surface facing each other; performing a doping process on at least the first surface to form a doped layer having a first doping element; performing a first laser process on a portion of the doped layer to form an activated portion and leaving the remaining doped layer as a doped portion; performing a first etching process on the first surface, using the remaining doped layer as a dead layer, to remove the activated portion and form a first textured surface; forming a doped polysilicon layer and a silicate glass layer having a second doping element at least on a side of the substrate away from the doped portion; performing a second laser process on at least a portion of the silicate glass layer to form a sparse portion; and performing a second etching process on at least the second surface, using the remaining silicate glass layer as a protective layer, to remove the sparse portion and the doped polysilicon layer facing the sparse portion and form a second textured surface. The first laser process and the second laser process use different laser types, thereby simplifying at least the manufacturing process.

The invention discloses a polycrystalline silicon solar panel intelligent fault detection early warning system and method, and relates to the technical field of intelligent fault detection. The polycrystalline silicon solar panel intelligent fault detection early warning system comprises a power attenuation fault detection module; a hot spot effect fault detection module; and a short circuit fault detection module. According to the invention, power attenuation early warning timeliness analysis is carried out, whether sine wave signal extraction optimization determination and early warning are carried out is determined, then hot spot effect early warning timeliness analysis is carried out, whether hot spot effect optimization determination and early warning are carried out is determined, and finally short circuit early warning timeliness analysis is carried out. According to the method, whether temperature-waveform extraction optimization judgment and early warning are carried out or not is judged, accurate and timely early warning of faults such as power attenuation, hot spot effect and short circuit is achieved, and the problem that in the prior art, fault detection and early warning of the polycrystalline silicon solar panel are not timely due to interference in the fault feature extraction process is effectively solved.

The invention relates to a quartz crucible coating and a preparation method thereof.The coating is of a double-layer composite structure and comprises a substrate layer and a functional layer, the substrate layer is composed of 40-65 vol% of polycrystalline silicon powder (the particle size D50 ranges from 1 micrometer to 5 micrometers) and 35-60 vol% of nanometer silica sol, and the functional layer covers the surface of the substrate layer and is composed of 50-70 vol% of polycrystalline silicon powder, 20-35 vol% of nanometer silica sol and 5-15 vol% of calcium fluoride powder (the particle size D90 is smaller than 0.5 micrometer). The preparation method comprises the following steps: preparing a substrate layer slurry and a functional layer slurry, sequentially coating the inner wall of a crucible with the slurry, drying, and sintering in an inert atmosphere according to a three-step temperature control program to finally form a coating with the thickness of 180-300 microns and the porosity of 8-15 vol%; the coating structure can avoid pollution of silicon nitride or silicon carbide particles, has excellent demolding performance, thermal stability and adhesive force, further improves the service life of a crucible and the purity of a silicon ingot, and meets the requirements of an advanced semiconductor process for cleanliness and reliability.

The invention relates to the technical field of semiconductors, and discloses an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a preparation method thereof, and the LDMOS device comprises a substrate layer comprising a drift region, a field oxide layer and a gate oxide layer which are located on the surface of the substrate layer, a gate structure, a polycrystalline silicon structure at the side part, a first dielectric layer and a first conductive column, the metal field plate, the second conductive through hole and the field plate connecting structure are arranged at the side part of the gate metal layer; wherein the field oxide layer is located on the surface of the drift region, and the gate structure, the drift region and the field oxide layer between the gate structure and the drift region form a first field plate structure; the metal field plate, the polycrystalline silicon structure and the first dielectric layer therebetween form a first capacitor, the polycrystalline silicon structure, the drift region and the field oxide layer therebetween form a second capacitor, and the first capacitor and the second capacitor are coupled in series to form a second field plate structure; the first field plate structure and the second field plate structure are connected through the field plate connecting structure and the second conductive through hole to form a double-field-plate structure. According to the invention, the breakdown voltage of the device can be improved under the condition of low on-resistance.

The utility model discloses a water residue and water quenching prevention system for polycrystalline silicon broken material packaging, and particularly relates to the technical field of polycrystalline silicon processing, the system comprises an integrated control unit, a water quenching module, a water residue and water treatment module, a packaging module, a crushing module, a screening module, a drying module, a quality detection module and an environmental adaptability module. According to the water quenching system for preventing moisture residue in the polycrystalline silicon broken material packaging, the utilization rate of materials is improved through efficient crushing and accurate screening, the waterproof performance of products is enhanced through vacuum degassing and automatic humidity control, the consistency of product quality is ensured through automatic quality detection, and the production efficiency is improved. And the safety of the system is improved through integrated control and an emergency discharge device. The characteristics jointly improve the production efficiency, and ensure the stability and reliability of the product in a changeable environment.

The invention discloses a 4kV low-resistance super-junction planar gate SiC VDMOS device structure and a preparation method thereof, and relates to the technical field of silicon carbide power devices, the 4kV low-resistance super-junction planar gate SiC VDMOS device structure comprises drain electrode metal, an n + SiC substrate and an n-type drift layer are arranged above the drain electrode metal, an n-type region is arranged in the middle of the n-type drift layer, a p-type shielding layer is arranged below the n-type region, p-type regions are arranged on two sides of the n-type drift layer, and the n + SiC substrate is arranged above the n-type region. A p-type well region is arranged above the p-type region; strip-shaped Schottky metal and strip-shaped polycrystalline silicon are arranged in the p-type well region, and an n + source region, source electrode metal, an insulating medium and grid electrode metal are arranged above the p-type well region; and the device is prepared. By constructing the transverse and longitudinal double-space charge region structure, the doping concentration of the n-type drift layer of the device is higher, the on-resistance of the device is reduced, the ohmic contact resistance and the body diode on-resistance of the device can be effectively reduced by the Schottky metal and polycrystalline silicon structure, and the follow current loss of the device is further reduced.

A method of forming a device comprises forming sacrificial pillar structures over conductive structures overlying a barrier structure substantially impermeable to hydrogen. The sacrificial pillar structures are separated from one another by trenches linearly extending in a first lateral direction orthogonal to a second lateral direction in which the conductive structures linearly extend. Gate electrodes are formed within the trenches and laterally adjacent sidewalls of the sacrificial pillar structures. The sacrificial pillar structures are removed to form openings between the gate electrodes. Dielectric liner structures are formed within the openings and laterally adjacent sidewalls of the gate electrodes. Channel structures are formed within the openings after forming the dielectric liner structures. The channel structures comprise a semiconductive material having a band gap larger than that of polycrystalline silicon. Conductive contacts are formed on the channel structures. A device, a memory device, and an electronic system are also described.

The invention discloses a back contact solar cell and a preparation method thereof, and relates to the technical field of solar cells. The back contact solar cell comprises a silicon substrate, first doped regions, second doped regions and isolation regions, the first doped regions, the second doped regions and the isolation regions are arranged on a first main surface of the silicon substrate, the first doped regions and the second doped regions are arranged alternately, and the isolation regions are located between the adjacent first doped regions and second doped regions; the tunneling passivation layer is arranged in the first doped region and the isolation region; the intrinsic polycrystalline silicon layer is arranged on the outer side of the tunneling passivation layer of the isolation region; the first doped polycrystalline silicon layer is arranged on the outer side of the tunneling passivation layer of the first doped region and comprises first doped atoms; the emitting electrode is arranged in the second doped region and comprises second doped atoms; the conduction types of the first doping atoms and the second doping atoms are opposite; the intrinsic polycrystalline silicon layer and the first doped polycrystalline silicon layer are located on the same layer. According to the embodiment, the influence of laser etching on the cell can be reduced, the preparation process is shortened, and the photoelectric conversion efficiency of the cell is improved.

The invention discloses a perovskite / crystalline silicon laminated cell based on polycrystalline silicon tunnel junction and interface modification, and belongs to the field of photovoltaic technology. The laminated cell is sequentially provided with a crystal silicon bottom cell, a polycrystalline silicon tunnel junction, an interface modification layer and a perovskite top cell from bottom to top. The polycrystalline silicon tunnel junction comprises an n-type polycrystalline silicon layer, an intrinsic layer and a p-type polycrystalline silicon layer from bottom to top; the doping concentration of the n-type polycrystalline silicon layer is gradually reduced towards the intrinsic layer, and the doping concentration of the p-type polycrystalline silicon layer is increased towards the direction far away from the intrinsic layer; the interface modification layer is arranged between the p-type polycrystalline silicon layer and the perovskite top cell; and the interface modification layer is adjacent to an electron transport layer of the perovskite top cell. Through the change design of the doping concentration of the polycrystalline silicon tunneling junction and the design of the interface modification layer and the hole transport layer, the problem of interface compatibility between the polycrystalline silicon tunneling layer and the perovskite top cell and the problem of poor stability of the laminated cell are solved, and the performance of the laminated cell is comprehensively improved.

The invention belongs to the technical field of visible light detection, and aims to realize accurate detection of multicolor visible light and monolithic integration of a multi-wavelength receiver. The invention provides a fully-integrated multicolor visible light detector based on a sub-wavelength polycrystalline silicon grating, which comprises three detectors capable of selectively detecting blue, green and red signals respectively. The principle is as follows: a one-dimensional sub-wavelength polycrystalline silicon grating in the multicolor detector is embedded in an upper SiO2 layer and a lower shallow trench isolation region to form a dielectric waveguide structure of which the middle is a high-refractive-index medium and the periphery is a low-refractive-index oxide layer. The period and the grating width of the sub-wavelength grating are changed, so that the incident polarized light and the sub-wavelength periodic structure are strongly coupled to cause a guided-mode resonance effect, and the sub-wavelength grating can be applied to a transmission optical filter. The size and the cost of the multicolor visible light communication system can be effectively reduced, and the data transmission rate of the system is greatly improved.

The invention provides a power device and a preparation method thereof. The preparation method comprises the following steps: forming a P-type layer and an N-type layer on an N-type substrate; forming a groove; performing ion implantation to form an N-type source region; forming a gate oxide layer in the groove; forming a first polycrystalline silicon layer, a thick oxide layer and a second polycrystalline silicon layer in the groove; depositing a dielectric layer; forming a source contact region, wherein the source contact region exposes a part of the N-type source region and a part of the P-type layer; forming an insulating layer; forming a gate contact region, wherein the gate contact region extends into the first polycrystalline silicon layer; forming a drain contact region, wherein the N-type layer is exposed out of the drain contact region; and forming a source electrode, a grid electrode and a drain electrode, wherein the source electrode is simultaneously contacted with the N-type source region and the P-type epitaxial layer. According to the invention, the source electrode, the grid electrode and the drain electrode can be attached to the heat dissipation substrate at the same time, so that the heat dissipation path is greatly optimized, and the access inductance of the source electrode is reduced; the connection of the P-type layer and the N-type source region is formed in the device through the groove, so that the process can be effectively simplified, an additional lead-out process is avoided, and the manufacturing cost is effectively saved.

The utility model provides a power semiconductor device, comprising a substrate which comprises a body region and a drift region which are arranged at an interval; the first well region is formed in the body region; the substrate leading-out region is formed in the body region, the first well region and the substrate leading-out region are arranged at intervals, the substrate leading-out region comprises a polycrystalline silicon body, the polycrystalline silicon body extends into the body region from the surface of the body region, and the vertical size of the polycrystalline silicon body is larger than the junction depth of the first well region; the first dielectric layer is arranged on the outer side of the polycrystalline silicon body, and the first well region and the polycrystalline silicon body are separated by the first dielectric layer; the second well region is formed in the drift region; the gate dielectric layer is arranged on the surface of the drift region, the gate dielectric layer is located between the body region and the second well region, and the gate dielectric layer is separated from the second well region; and the polysilicon gate layer is arranged on the surfaces of the gate dielectric layer, the drift region, the substrate and the body region. Without increasing the lateral dimension of the semiconductor device, the withstand voltage between the source electrode and the substrate can be improved.

The invention provides a TBC battery and a preparation method thereof, and relates to the technical field of solar batteries. The TBC battery comprises a silicon substrate, and the back surface of the silicon substrate comprises at least one N region and at least one P region; an N-type doped polycrystalline silicon layer is arranged on the N region, and a P-type doped polycrystalline silicon layer is arranged on the P region; an isolation region is arranged between the N region and the P region, and the isolation region comprises an intrinsic polycrystalline silicon layer. According to the preparation method of the TBC battery, the space between the N region and the P region is filled with intrinsic polycrystalline silicon, the isolation purpose is achieved, the N-type doped polycrystalline silicon layer and the P-type doped polycrystalline silicon layer are prepared in the N region and the P region through the silk-screen printing technology respectively, laser is not needed for physical isolation, the space between the N region and the P region is filled with the intrinsic polycrystalline silicon, and the production cost is reduced. And the loss of the laser to the battery piece is reduced, so that the conversion efficiency is remarkably improved.

A solar cell and a preparation method thereof belong to the field of photovoltaic technology, the solar cell at least comprises a substrate, a tunneling oxide layer, a tin oxide layer and a doped polycrystalline silicon layer, along the thickness direction of the substrate, the tunneling oxide layer is arranged on the surface of the substrate, the tin oxide layer is arranged on the surface of the tunneling oxide layer, and the doped polycrystalline silicon layer is arranged on the surface of the substrate. The doped polycrystalline silicon layer is arranged on the surface of the tin oxide layer, so that the tin oxide layer is located between the tunneling oxide layer and the doped polycrystalline silicon layer. The phosphorus doping concentration alpha of the tunneling oxide layer satisfies 1 * 10 < 13 > cm <-3 > < = alpha < = 1 * 10 < 16 > cm <-3 >, the phosphorus doping concentration beta of the tin oxide layer satisfies 1 * 10 < 15 > cm <-3 > < = beta < = 1 * 10 < 20 > cm <-3 >, and the phosphorus doping concentration gamma of the doped polycrystalline silicon layer satisfies 1 * 10 < 19 > cm <-3 > < = gamma < = 1 * 10 < 21 > cm <-3 >. The tin oxide layer is arranged between the tunneling oxide layer and the doped polycrystalline silicon layer, the tin oxide layer has excellent conductivity and light transmission, parasitic absorption is reduced, more light is absorbed by the substrate, and the photoelectric conversion efficiency of the solar cell is improved.

The invention discloses a cutting and polishing combined machining treatment method suitable for polycrystalline silicon. The method comprises the following steps: step 1, silicon ingot pretreatment: loading historical process data of a silicon ingot in combination with a block chain technology, generating a machining parameter packet, and issuing the machining parameter packet to cutting and polishing equipment to form a machining quantization instruction set; a plasma channel is formed through combination of femtosecond laser focusing and high-frequency electromagnetic field constraint for cutting, annular laser is synchronously used for deep micro-area fusion polishing, and the surface roughness of the cut silicon wafer is reduced by means of argon protection and the surface tension self-leveling effect; 3, polishing: immersing the anode of the silicon wafer into TEMPO / [EMIM] [BF] electrolyte, and regulating and controlling by using pulse voltage; 4, cleaning and drying, wherein megasonic assisted nanobubble ultrapure water is adopted for flushing, and Malangori drying is carried out; and 5, quality control: verifying the surface appearance and the subsurface defect density, and carrying out secondary processing flow on the abnormal silicon wafer.

The invention relates to the technical field of silicon carbide semiconductor devices, in particular to an integrally-formed equal-depth double-groove SiC MOSFET structure and a preparation method thereof. According to the structure, an N + buffer layer and an N-drift layer are sequentially formed on an N-type SiC substrate, and a main groove and an auxiliary groove which are consistent in depth are formed in the surface of the N-type SiC substrate; a gate oxide layer and a polycrystalline silicon gate are sequentially formed in the main groove, and the auxiliary groove is filled with a SiC epitaxial material which is doped with the drift layer in the same type, so that a charge compensation and electric field regulation and control unit is formed; the P-type body region surrounds the trench structure and forms an N + source region, and the drain electrode is formed through a back metallization process. Through the collaborative design of the equal-depth double grooves, the uniformization of electric field distribution is realized, the on-resistance and the switching loss are effectively reduced, the thermal stability and the reliability of the device are improved, the integrated process is adopted for integration, the process is simplified, the production efficiency and the yield are improved, and the semiconductor device is suitable for high-frequency and high-voltage application scenes and has a wide industrialization prospect.

A trench in a semiconductor substrate is lined with a first insulation layer. A hard mask layer deposited on the first insulation layer is used to control performance of an etch that selectively removes a first portion of the first insulating layer from an upper trench portion while leaving a second portion of first insulating layer in a lower trench portion. After removing the hard mask layer, an upper portion of the trench is lined with a second insulation layer. An opening in the trench that includes a lower open portion delimited by the second portion of first insulating layer in the lower trench portion and an upper open portion delimited by the second insulation layer at the upper trench portion, is then filled by a single deposition of polysilicon material forming a unitary gate / field plate conductor of a field effect rectifier diode.

The invention provides a solar cell and a preparation method thereof, a photovoltaic module and a laminated cell, and relates to the field of photovoltaic technology. The solar cell includes a silicon substrate; along the thickness direction of the silicon substrate, the silicon substrate comprises a light facing surface and a backlight surface which are opposite to each other; the light-facing face and the backlight face are each provided with a suede structure, and the average size of the suede structures of the light-facing face is smaller than that of the suede structures of the backlight face. The whole tunneling oxide layer and the doped polycrystalline silicon layer are sequentially stacked on the light-facing surface; the whole intrinsic amorphous silicon passivation layer and the whole doped amorphous silicon layer are sequentially arranged on the backlight face in a stacked mode. Good passivation effects and anti-reflection effects are obtained on the two sides of the silicon substrate.

The invention relates to the technical field of solar cells, and provides a photovoltaic module, a laminated cell, a back contact cell and a manufacturing method thereof. The manufacturing method comprises the following steps: providing a substrate, wherein a second surface of the substrate comprises a first region and a second region; forming a tunneling layer on the second surface; forming a first polycrystalline silicon layer on the surface of the tunneling layer by adopting a first deposition process; forming a second polycrystalline silicon layer on the surface of the first polycrystalline silicon layer by adopting a second deposition process; the temperature and pressure of the first deposition process are higher than those of the second deposition process; carrying out doping treatment, and converting the first polycrystalline silicon layer and the second polycrystalline silicon layer into a first semiconductor doped layer; forming a second semiconductor doping layer on the second region; a first electrode and a second electrode are formed, the first electrode being in electrical contact with the first semiconductor doped layer and the second electrode being in electrical contact with the second semiconductor doped layer. According to the invention, low-resistance ohmic contact between the first semiconductor doping layer and the first electrode is realized at least while a good surface passivation effect is ensured.

The invention provides a back contact solar cell and a photovoltaic module, the back contact solar cell comprises a substrate, the substrate is provided with a backlight surface, and the backlight surface comprises a first polarity area, a second polarity area and an isolation area arranged between the first polarity area and the second polarity area; a first doped layer and a second doped layer, the first doped layer is arranged in the first polarity region, the second doped layer is arranged in the second polarity region, and the doping types of the first doped layer and the second doped layer are opposite; the isolation layer is arranged in the isolation region, the isolation layer comprises an intrinsic polycrystalline silicon layer, a first passivation layer and a third doping layer which are sequentially stacked in the direction away from the substrate, and the doping type of the third doping layer is the same as that of the first doping layer or the second doping layer. The main isolation effect is achieved through the intrinsic polycrystalline silicon layer, the composite passivation effect can be achieved through combination of the first passivation layer and the third doping layer, composite passivation with chemical passivation and field passivation is achieved in the isolation area, and the surface recombination rate is greatly reduced.

The invention discloses a double-heating-system electronic-grade polycrystalline silicon reduction furnace and a process method thereof, and relates to the technical field of polycrystalline silicon production equipment, and the reduction furnace comprises a cooling liquid inlet and a cooling liquid outlet which are respectively formed in the upper part and the lower part of a microwave window; a microwave emission branch pipe is fixedly arranged on the outer side of each microwave window, and each microwave emission branch pipe is connected with the microwave emitter through a microwave transmission header pipe; the method comprises the following steps: S1, starting the furnace; s2, early growth stage of the silicon rod; s3, middle growth stage of the silicon rod; s4, later growth stage of the silicon rod; and S5, blowing out the furnace and cooling. The double-heating-system electronic-grade polycrystalline silicon reduction furnace has the beneficial effects that silicon rods with larger diameters can be produced, and the yield of a single furnace is remarkably increased; the quality of the silicon rod is improved, and the high quality requirement of electronic-grade polycrystalline silicon is met; according to the process method disclosed by the invention, the utilization rate of raw materials is increased to 89% or above, the generation amount of amorphous silicon powder is reduced to 7.2 kg / furnace or below, and the energy consumption of a unit silicon rod is reduced.