741 results about "Carbon doped" patented technology

This invention discloses the method of forming silicon nitride, silicon oxynitride, silicon oxide, carbon-doped silicon nitride, carbon-doped silicon oxide and carbon-doped oxynitride films at low deposition temperatures. The silicon containing precursors used for the deposition are monochlorosilane (MCS) and monochloroalkylsilanes. The method is preferably carried out by using plasma enhanced atomic layer deposition, plasma enhanced chemical vapor deposition, and plasma enhanced cyclic chemical vapor deposition.

A method for forming and the structure of a vertical channel of a field effect transistor, a field effect transistor and CMOS circuitry are described incorporating a drain, body and source region on a sidewall of a vertical single crystal semiconductor structure wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect the body region and wherein the drain region contains a carbon doped region to prevent the diffusion of dopants (i.e., B and P) into the body. The invention reduces the problem of short channel effects such as drain induced barrier lowering and the leakage current from the source to drain regions via the hetero-junction and while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials. The problem of scalability of the gate length below 100 nm is overcome by the heterojunction between the source and body regions.

A method is provided for forming an amorphous carbon layer, deposited on a dielectric material such as oxide, nitride, silicon carbide, carbon doped oxide, etc., or a metal layer such as tungsten, aluminum or poly-silicon. The method includes the use of chamber seasoning, variable thickness of seasoning film, wider spacing, variable process gas flows, post-deposition purge with inert gas, and post-deposition plasma purge, among others, to make the deposition of an amorphous carbon film at low deposition temperatures possible without any defects or particle contamination.

A method of forming an interconnect for a semiconductor device using triple hard layers, comprises: forming a first hard layer serving as an etch stop layer on a metal interconnect-formed dielectric layer; forming a second hard layer on the first hard layer; forming a dielectric layer on the second hard layer; forming a third hard layer on the dielectric layer; forming a hole through the third and second hard layers, the dielectric layer, and the first hard layer; and filling the hole with metal to establish an interconnect. The second and third hard layers are each made of carbon-doped silicon oxide formed from a source gas and a redox gas, while controlling the carbon content in the second hard layer as a function of a flow rate of the redox gas.

The present invention includes a process for selectively etching a low-k dielectric material formed on a substrate using a plasma of a gas mixture in a plasma etch chamber. The gas mixture comprises a fluorine-rich fluorocarbon or hydrofluorocarbon gas, a nitrogen-containing gas, and one or more additive gases, such as a hydrogen-rich hydrofluorocarbon gas, an inert gas and/or a carbon-oxygen gas. The process provides a low-k dielectric to a photoresist mask etching selectivity ratio greater than about 5:1, a low-k dielectric to a barrier/liner layer etching selectivity ratio greater about 10:1, and a low-k dielectric etch rate higher than about 4000 Å/min.

Embodiments of the invention relate to deposition of a conformal carbon-based material. In one embodiment, the method comprises depositing a sacrificial dielectric layer with a predetermined thickness over a substrate, forming patterned features on the substrate by removing portions of the sacrificial dielectric layer to expose an upper surface of the substrate, introducing a hydrocarbon source, a plasma-initiating gas, and a dilution gas into the processing chamber, wherein a volumetric flow rate of hydrocarbon source: plasma-initiating gas: dilution gas is in a ratio of 1:0.5:20, generating a plasma at a deposition temperature of about 300 C to about 500 C to deposit a conformal amorphous carbon layer on the patterned features and the exposed upper surface of the substrate, selectively removing the amorphous carbon layer from an upper surface of the patterned features and the upper surface of the substrate, and removing the patterned features.

A method that includes forming a pattern of strained material and relaxed material on a substrate; forming a strained device in the strained material; and forming a non-strained device in the relaxed material is disclosed. In one embodiment, the strained material is silicon (Si) in either a tensile or compressive state, and the relaxed material is Si in a normal state. A buffer layer of silicon germanium (SiGe), silicon carbon (SiC), or similar material is formed on the substrate and has a lattice constant/structure mis-match with the substrate. A relaxed layer of SiGe, SiC, or similar material is formed on the buffer layer and places the strained material in the tensile or compressive state. In another embodiment, carbon-doped silicon or germanium-doped silicon is used to form the strained material. The structure includes a multi-layered substrate having strained and non-strained materials patterned thereon.

A method for forming and the structure of a vertical channel of a field effect transistor, a field effect transistor and CMOS circuitry are described incorporating a drain, body and source region on a sidewall of a vertical single crystal semiconductor structure wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect the body region and wherein the drain region contains a carbon doped region to prevent the diffusion of dopants (i.e., B and P) into the body. The invention reduces the problem of short channel effects such as drain induced barrier lowering and the leakage current from the source to drain regions via the hetero-junction and while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials. The problem of scalability of the gate length below 100 nm is overcome by the heterojunction between the source and body regions.

A method for forming and the structure of a strained vertical channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a sidewall of a vertical single crystal semiconductor structure wherein a heterojunction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect to the body region and wherein the drain region contains a carbon doped region to prevent the diffusion of dopants (boron) into the body. The invention reduces the problem of leakage current from the source region via the heterojunction and lattice strain while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials.

The invention provides high-strength and high-toughness reactive powder concrete of a carbon doped nano-tube. The high-strength and high-toughness reactive powder concrete is prepared by taking cement, a carbon nano-tube, silica fume, a water reducing agent, silica sand, coal ash, quartz powder, steel fiber and water as raw materials, wherein all the components in the mixture are calculated in parts by mass: 1000-1200 parts of cement, 250-350 parts of silica fume, 250-350 parts of slag powder, 40-50 parts of water reducing agent, 1200-1400 parts of silica sand, 180-230 parts of water, 190-230 parts of steel fiber, 180-250 parts of coal ash, 80-120 parts of quartz powder, 0.1-5 parts of carbon-nano-tube dispersing agent and 1-10 parts of carbon nano-tube powder. The invention also provides a preparation method of the high-strength and high-toughness reactive powder concrete. The reactive powder concrete obtained by the invention has the high compression strength of 250-300MPa and breaking strength of 45-60MPa, which are higher than the 200-level related performances of the traditional RPC (Reactive Powder Concrete). Meanwhile, the initial cracking strength of the reactive powder concrete material prepared by using the carbon nano-tube is greatly improved and is up to 10MPa in a direct stretching state, and the tensile strain corresponding to peak stress is up to more than 0.5%, so that the toughness and strength of the traditional RPC material are greatly improved.

A CMOS transistor and a method for manufacturing the same are disclosed. A semiconductor substrate having at least a PMOS transistor and an NMOS transistor is provided. The source/drain of the PMOS transistor comprises SiGe epitaxial layer. A carbon implantation process is performed to form a carbon-doped layer in the top portion of the source/drain of the PMOS transistor. A silicide layer is formed on the source/drain. A CESL is formed on the PMOS transistor and the NMOS transistor. The formation of the carbon-doped layer is capable of preventing Ge out-diffusion.

The invention relates to a vanadium sodium phosphate composite material as well as a preparation method and an application thereof. The general formula of the composite material provided by the invention is C1-xNx-LaNabMcVd(PO4)3, wherein C1-xNx is carbon or carbon doped with nitrogen, L is one or two selected from Li and K; M is one or more than one selected from Mg, B, Al, Ca, Ti, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ce, Y, Zr, Nb, Mo, Sn, La, Ta and W; and x, a, b, c and d are mol percents, wherein x is more than or equal to 0 and less than 1, a is more than or equal to 0 and less than 2, b is more than 1 and less than or equal to 3, c is more than or equal to 0 and less than or equal to 1, and d is more than or equal to 1 and less than or equal to 2. The invention also provides a preparation method and an application of the composite material. The vanadium sodium phosphate composite material can be taken as cathode or anode material of a secondary sodium-ion battery, especially vanadium sodium phosphate composite material coated with carbon and nitrogen has higher coulombic efficiency and ion and electron conductivity and better cycling performance, is high in safety, low in price, simple in process and wide in application range and can be applied to energy storage equipment, a backup power supply, a spare power supply and the like.

A process of selectively etching a sacrificial light absorbing material (SLAM) over a dielectric material, such as carbon doped oxide, on a substrate using a plasma of a gas mixture in a plasma etch chamber. The gas mixture comprises a hydrofluorocarbon gas, an optional hydrogen-containing gas, an optional fluorine-rich fluorocargon gas, a nitrogen gas, an oxygen gas, and an inert gas. The process could provide a SLAM to a dielectric material etching selectivity ratio greater than 10:1.

Copper diffusion barrier films having a boron-doped silicon carbide layer with at least 25% boron by atomic weight of the layer composition have advantages for semiconductor device integration schemes. The films have an integration worthy etch selectivity to carbon doped oxide of at least 10 to 1, can adhere to copper with an adhesion energy of at least 20 J/m², and can maintain an effective dielectric constant of less than 4.5 in the presence of atmospheric moisture. The films are suitable for use in a wide range of VLSI and ULSI structures and devices.

Methods for forming an interconnection line and interconnection line structures are disclosed. The method includes forming an interlayer insulating layer on a semiconductor substrate, wherein the interlayer insulating layer is formed of a carbon-doped low-k dielectric layer. An oxidation barrier layer is formed on the interlayer insulating layer. An oxide capping layer is formed on the oxidation barrier layer. A via hole is in the oxide capping layer, the oxidation barrier, and the interlayer insulating layer. A conductive layer pattern is formed within the via hole.