21 results about "Patterned substrate" patented technology

The present invention relates to the field of patterning substrates with periodic dot structures in the micro- or sub-micrometer range, in particular to an apparatus and a method for structuring surfaces and the interior of a transparent substrate by means of laser interference structuring. The pattern produced in this way with periodic dot structures in the micro- or sub-micrometer range is characterized by a pronounced anti-reflective property. In addition, the present invention relates to a patterned substrate with anti-reflective properties comprising a periodic dot structure.

An electronic device manufacturing system configured to obtain sensor data associated with a deposition process performed in a process chamber to deposit a film stack on a surface of a substrate. The film stack can include a known film pattern and an unknown film pattern. The manufacturing system is further configured to input the sensor data into a first trained machine-learning model to obtain a first output value of the first trained machine-learning model. The first output value can be associated with the known film pattern. The manufacturing system is further configured to input the first output value into a second trained machine-learning model to obtain a second output value of the second trained machine-learning model. The second output value can be indicative of metrology data of the known film pattern.

Described herein are machine learning based systems, methods, and non-transitory computer readable media for determining three-dimensional (3D) information of structures of a patterned substrate. The 3D information can be determined using a neural network to convert a two-dimensional image to a 3D image. In a method, the neural network is trained by supplying varying parameters to simulated images of a sample to model a real manufactured IC structure. The trained network generates a depth map from a newly supplied image of the sample to predict defect locations. The depth map can be converted to a binary map to predict defect size and location, which can be used to guide inspection of the sample using an inspection tool.

Disclosed is a method of deforming a first patterned substrate or one or more first substrate portions thereof, configured to be bonded to a second patterned substrate, the method comprising providing at least said first patterned substrate or one or more first substrate portions thereof with a layer comprising a material that changes its phase when exposed to a radiation; and irradiating the layer with the radiation, wherein the radiation imposes a stress within the first patterned substrate or one or more first substrate portions thereof, the stress causing deformation of the first patterned substrate or one or more first substrate portions thereof that at least partially corrects a position error of a pattern of the first patterned substrate or one or more first substrate portions thereof.

The application provides a composite patterned substrate and a preparation method and application thereof, and the substrate comprises a sapphire substrate layer and a pattern structure layer arranged on the sapphire substrate layer, wherein the pattern structure layer comprises a plurality of periodic convex structures, and each convex structure comprises, from bottom to top, a sapphire root, a Pt metal film interlayer and a hetero-material pattern. The application effectively improves the light-emitting efficiency of a GaN-LED by sandwiching the Pt metal film between the sapphire substrate layer and the hetero-material pattern. Meanwhile, the design ingeniously solves the problem of the influence of the metal reflection layer on the growth of a GaN single crystal, and realizes the epitaxial preparation of a high-efficiency LED device. In addition, the preparation method is simple and low in cost, and has a good industrialization prospect.

The invention relates to an optoelectronic component comprising a substrate, in particular a cover layer, an optoelectronically active layer and a contact layer, the outer and / or inner surface of which has a patterned region with a point structure composed of pyramids or inverted pyramids. With such a point structure, it is possible to advantageously adjust the optical and wetting properties of the optoelectronic component in a targeted manner. In this regard, in particular, it is possible to improve the coupling-in or coupling-out of light to the optoelectronic component and thus the efficiency. The invention also relates to an optoelectronic module, a method for producing an optoelectronic component and the use of a patterned substrate for an optoelectronic component.

This invention discloses a patterned substrate and its fabrication method, as well as an epitaxial wafer for a light-emitting diode (LED), relating to the field of semiconductor optoelectronic devices. The patterned substrate includes a substrate body, a metal reflective layer, and multiple pyramidal protrusions. The substrate body has a first surface and a second surface disposed opposite to each other; the metal reflective layer covers the first surface; the multiple pyramidal protrusions are uniformly distributed on the metal reflective layer; each pyramidal protrusion includes a first AlN layer and a SiO2 layer sequentially stacked on the metal reflective layer. Implementing this invention can improve the luminous efficiency of the LED.

The application discloses a large-exposure-field photolithography technology implementation method, a chip-level chip interconnection method and a photolithography device. The large-exposure-field photolithography technology implementation method is applied to the photolithography device, the photolithography device comprises a projection system with a reduction ratio of 0.1-2.5, and the method comprises the following steps: loading a patterned substrate to be exposed to a stage, performing alignment through alignment marks on the substrate, and offsetting by a set offset distance; performing first exposure, transferring a preset pattern of a mask to a first exposure area of the substrate through the projection system; laterally stepping the substrate or the mask by M times of the lateral size of an original pattern unit or vertically stepping the substrate or the mask by N times of the vertical size of the original pattern unit, performing second exposure, and transferring the preset pattern to a second exposure area of the substrate through the projection system; and continuously performing lateral stepping or vertical stepping and second exposure until exposure of a target area on the substrate is completed. The scheme can form a large-size exposure field and realize high-density interconnection of integrated circuits.

A specialized machine learning model configured to minimize and / or eliminate the need for motorized hardware to block higher order diffracted radiation from corrupting alignment measurements in semiconductor manufacturing metrology processes. For example, a radiation source illuminates a metrology target in a layer of a patterned substrate with radiation, the metrology target diffracts the radiation. A radiation sensor outputs phase data and intensity data of the diffracted radiation. The phase data includes different energies associated with different diffraction orders of the diffracted radiation. The model is configured to determine a subset of the intensity data associated with positive first order diffracted radiation and negative first order diffracted radiation incident on the radiation sensor based on the phase data, and determine an intensity difference or intensity imbalance between the positive first order diffracted radiation and the negative first order diffracted radiation based on the subset of the intensity data. An alignment is determined based on the intensity imbalance.

A surface-enhanced Raman spectroscopy (SERS) having a plurality of ordered nanostructures arranged on a substrate and a process of making the same are provided. The process of fabricating silver nanoparticles from surface nanodroplet reaction includes placing a chemically micro-patterned substrate inside a narrow fluid chamber; filling the chamber with a ternary mixture; replacing the ternary mixture by water saturated with Vitamin E to form droplets of Vitamin E (VE) on the substrate with hydrophobic micro-patterns; providing a precursor solution to the substrate by passing the precursor solution through the microchamber; providing VE droplet liquid on the micro-patterned substrate; and reacting the precursor solution with the VE droplet liquid at a biphasic interface of the droplets on the substrate leading to the nucleation of AgNPs and subsequent growth towards nanostructures.

Gallium nitride (GaN) epitaxy on patterned substrates for integrated circuit technology is described. In an example, an integrated circuit structure includes a material layer including gallium and nitrogen, the material layer having a first side and a second side opposite the first side. A plurality of fins is on the first side of the material layer, the plurality of fins including silicon. A device layer is on the second side of the material layer, the device layer including one or more GaN-based devices.

Described is a patterned liquid crystal monolayer structure (100) on a patterned substrate (900), wherein said patterned substrate is comprising surface areas which grafted onto (500) by a liquid crystal compounds (300) as a self-assembled monolayer (SAM) (200) and surface areas which are not grafted onto (400) by this SAM on this patterned substrate. Also described, are compositions of select liquid crystal (200) with different types of polar anchor groups, in an organic spin casting solvent and the method of using this composition to selectively deposit a SAM on a substrate containing both metallic surface areas and non-metallic inorganic silicon compound surface areas on either one of these areas, depending on the nature of a polar anchor group on the liquid crystal compound, and using this selective SAM deposition as a barrier to selectively deposit a metal oxide dielectric by ALD on the area not grafted by a SAM.

This application provides a patterned substrate and its fabrication method, an epitaxial wafer, and an LED chip. The patterned substrate includes patterned areas and unpatterned areas. The patterned areas include multiple microstructures, and unpatterned areas are spaced apart from adjacent patterned areas, with each unpatterned area having a certain width. The unpatterned areas act as a separator between the patterned areas, allowing for a relatively clear distinction between them. The patterned substrate does not have any abnormal splicing patterns caused by closely adjacent exposed areas. In applications where a semiconductor epitaxial layer is fabricated on the patterned substrate, and then the epitaxial layer is etched to fabricate LED pixels, the unpatterned areas can be avoided. This ensures that all LED pixels in the LED chip are fabricated within the patterned areas, resulting in essentially uniform luminous performance among the LED pixels. This improves the uneven luminous performance of the LED chip and enhances wavelength uniformity.

The application relates to the technical field of semiconductors, and discloses a multi-structure patterned substrate and a preparation method thereof. The preparation method comprises the following steps: depositing a silicon oxide layer on an Al2O3 substrate; coating a stamping adhesive layer on the silicon oxide layer; placing the substrate into a stamping machine to transfer a pattern on a soft film plate to obtain a first preset pattern; performing ICP etching on the first preset pattern to obtain a second preset pattern; performing photoresist coating on the second preset pattern, and performing exposure and development to obtain an adhesive column covering the second preset pattern; baking the substrate with the adhesive column to deform the top of the adhesive column, so that a substrate with a third preset pattern is obtained; depositing an amorphous Al2O3 layer on the substrate with the third preset pattern; and finally, annealing the substrate with the deposited amorphous Al2O3 layer. The pattern structure provided by the application can reduce more total reflection of light, increase the scattering path of light, make more photons find an escape path, and thus improve the light extraction efficiency.

A light-emitting device includes a patterned substrate, a buffer layer, an epitaxial layered unit, and at least one hole structure. The patterned substrate includes a supporting substrate having an upper surface, and a plurality of protrusions formed on the upper surface. Each of the protrusions includes a base and a cone sequentially stacked in such order on the upper surface. The cone is made of a material different from that of the supporting substrate. The buffer layer formed on a side wall surface of each of the protrusions and the upper surface of the supporting substrate exposed from the protrusions. The epitaxial layered unit is formed on the buffer layer opposite to the patterned substrate. The hole structure is disposed above a top end of at least one of the protrusions. A method for manufacturing the light-emitting device is also disclosed.

This application belongs to the field of display technology, specifically relating to a method for fabricating a substrate and a display panel. The method includes providing a substrate, forming an electrode layer on the substrate, the electrode layer including at least one driving electrode; fabricating a hydrophobic layer on the surface of the substrate with the electrode layer; configuring the driving electrode to connect to a driving circuit; applying a voltage to a selected driving electrode according to a target pattern, causing a corresponding area on the hydrophobic layer to become a hydrophilic area, thereby forming a hydrophilic pattern; and delivering a functional material solution to the substrate surface via a microfluidic chip, causing the functional material solution to adsorb onto the hydrophilic pattern, thus obtaining a patterned target substrate. This application, by applying voltage to the substrate and allowing solution adsorption, produces a patterned substrate, reducing the process cost of display panel manufacturing and improving the material utilization rate in the display panel patterning process.

This invention discloses an interface treatment method for reducing the defect density of selective epitaxial growth in the germanium-silicon base region of an HBT (Hardware-to-Bit) device. The method includes: providing a patterned substrate; performing wet cleaning on the patterned substrate to remove intrinsic oxides, and drying the wet-cleaned patterned substrate; performing in-situ plasma cleaning on the patterned substrate; performing in-situ H2 baking on the patterned substrate; and forming a germanium-silicon base region in the base region growth window through selective germanium-silicon epitaxy. In this invention, due to the strict thermal budget constraints of the SiGe BiCMOS process, three surface pretreatment methods—wet cleaning, in-situ plasma cleaning, and in-situ H2 baking—are specifically combined to treat the growth interface before SiGe epitaxy, thereby obtaining a high-quality SiGe epitaxial layer and improving the electrical performance of the SiGe HBT device.

Described herein is a method, and system for training a deblurring model and deblurring an image (e.g., SEM image) of a patterned substrate using the deblurring model and depth data associated with multiple layers of the patterned substrate. The method includes obtaining, via a simulator using a target pattern as input, a simulated image of the substrate, the target pattern comprising a first target feature to be formed on a first layer, and a second target feature to be formed on a second layer located below the first layer; determining, based on depth data associated with multiple layers of the substrate, edge range data for features of the substrate; and adjusting, using the simulated image and the edge range data associated with the target pattern as training data, parameters of a base model to generate the deblurring model to a deblur image of a captured image.

A device comprising: a trench (107) with a rim and a bottom, in an insulating layer (301, 302) located on a substrate (103) having a first lattice constant; wherein (a) the trench (107) extends downwards towards the substrate (103); (b) the trench (107) has a lower width (110) near the trench bottom and an upper width above the lower width (110); and (c) the upper width is narrower than the lower width (110); a lower epitaxial, EPI, layer (104) having in the trench (107) near the trench bottom and below the upper trench width a second lattice constant mismatched to the first lattice constant; and at least two alternating upper EPI layers (105, 106) in the trench (107) above the lower EPI layer (104);wherein the lower EPI layer (104) contains more defects than the upper EPI layers (105, 106), and wherein each of the upper EPI layers (105, 106) has a different lattice constant than the first and / or second lattice constant.;

This invention discloses a method for selective epitaxy of the SiGe:C base region in high-speed silicon-germanium (HBT), comprising: providing a patterned substrate having a base region growth window; performing RCA cleaning on the patterned substrate; forming a low-pressure environment in the epitaxial chamber; and forming the SiGe:C base region in the base region growth window of the patterned substrate through selective epitaxy. In this invention, optimized pretreatment of the patterned substrate surface effectively suppresses the etching damage caused by highly reactive carbon atoms and their uncontrollable migration on the dielectric surface; thereby significantly widening the process window for selective SiGe:C epitaxy and improving process stability and repeatability; conducting the reaction under low pressure increases the mean free path of gas molecules and facilitates surface reaction control, strengthening the dependence of growth / etching on surface chemical properties and enhancing selectivity.