21069 results about "Dielectric layer" patented technology

Disclosed are methods of microelectronic processing to reveal conductive vias that are at least partially embedded in a bulk semiconductor, and resulting structures. A method of forming a microelectronic structure includes revealing the plurality of conductive vias from a back surface of the bulk semiconductor and forming a protective cap on each of the conductive vias on the back surface of the bulk semiconductor. The protective caps can be patterned or disposed selectively onto the conductive vias. The protective caps can cover the conductive vias or also cover a portion of the bulk semiconductor surrounding the conductive vias. The back surface of the bulk semiconductor is etched to form protruding conductive vias, which can be surrounded by sleeves of the bulk semiconductor. A dielectric layer is deposited over the back surface and planarized to reveal the plurality of conductive vias from the back surface.

The invention is applicable to the field of photovoltaic technology, and provides a back contact solar cell, which comprises a silicon substrate, non-recessed areas and recessed areas are alternately arranged on the backlight surface of the silicon substrate, and the silicon substrate is provided with extending parts extending and protruding to the upper parts of the recessed areas at the edges of the non-recessed areas and the recessed areas; the first dielectric layer and the first polarity doping layer are sequentially stacked on the non-sunken region and the extension part; the second dielectric layer comprises a first part stacked on the first polarity doping layer and a second part stacked in the sunken region; the second polarity doped layer is stacked on the first portion and the second portion. Under the shielding effect of the extension part, the first polarity doping layer in the non-recessed area is effectively isolated from the second polarity doping layer in the recessed area, and electric leakage is avoided.

The invention provides a 2.5 D substrate manufacturing method and a packaging structure. The 2.5 D substrate manufacturing method comprises the following steps: providing a first carrier on which a metal part and an intermediate layer are mounted; a metal column is arranged in the intermediate layer; forming a protective layer covering the metal component and the interposer on the first carrier; a first recess is formed on the metal feature. The interposer and the protective layer are ground such that the interposer and protective layer surfaces are lower than the surface of the metal feature. Forming a first dielectric layer with a first opening on the surfaces of the intermediate layer and the protective layer; the first opening exposes the metal column. Forming a seed layer in the first opening; the seed layer extends to the surface of the metal part and fills the first groove. A wiring layer is formed on the seed layer. The bonding force of the seed layer and the first dielectric layer can be improved, the corrosion to the side wall of the interposer in the etching process is prevented, and the packaging quality and precision are improved.

The invention relates to a manufacturing method of a high dielectric layer metal gate device, and relates to the field of integrated circuits. The manufacturing method comprises the steps that a substrate is provided, the substrate comprises active regions and isolation structures, and the isolation structures and the active regions are arranged at intervals; the substrate is provided with a first region and a second region, the active region protrudes out of the isolation structure to form a first fin part in the first region, and a second fin part is formed in the second region; forming a first work function layer to cover the first fin part and the second fin part; free radicals generated by exciting the first gas through the metastable state particles are in contact with the surface of the first work function layer, and free dangling bonds on the surface of the first work function layer are removed; forming a second work function layer on the first work function layer; etching to remove the second work function layer on the first fin part; and the surface of the first work function layer is treated by free radicals generated by exciting the second gas through the metastable state particles. The problem of material loss of the first work function layer when devices with different threshold voltages are formed on the same substrate is solved.

The invention relates to the field of pressure sensors, in particular to a pressure sensor and a processing method, and a chip comprises a silicon substrate, a silicon dioxide dielectric layer, a device layer, a metal electrode and packaging glass. The device layer comprises a silicon carbide single crystal device layer and a silicon device layer; the silicon carbide single crystal device layer is arranged on the silicon device layer; the silicon device layer, the silicon dioxide dielectric layer and the silicon substrate are connected in sequence; the device layer is etched to form a sensitive resistor device layer, an annular sealing region and a micro-channel; the sensitive resistance device layer is isolated from the annular sealing area through the micro-channel; the device layer, the silicon dioxide dielectric layer and the silicon substrate are etched to form a cross beam etching area; the silicon substrate is etched to form a silicon pressure cavity and a beam film; the metal electrode is arranged on the top of the device layer; and the packaging glass anode is bonded at the top of the device layer or the bottom of the silicon substrate so as to solve the problems of low high temperature resistance and low sensitivity of the MEMS pressure sensor.

The invention relates to a modeling and optimizing method for inter-layer signal crosstalk of a PCB (Printed Circuit Board). Frequency response data of all dielectric layers of the PCB under different temperature and humidity conditions are collected, and a mapping model with the temperature gradient and the humidity diffusion gradient as input and the dielectric constant as output is established. And calculating the dynamic distribution of mutual capacitance and mutual inductance under the environment change by combining the spatial layout parameters of the differential signal pair, and constructing a crosstalk sensitivity evaluation model with coupled frequency, environment and layout. And high-risk areas with crosstalk sensitivity caused by environment change are identified, and the crosstalk change rate of each area is quantified. For a sensitive area, a temperature and humidity compensation medium structure is introduced to stabilize local dielectric characteristics and reduce the influence of the environment on crosstalk. And according to the compensated medium distribution, adjusting a differential signal wiring path and impedance matching by adopting an optimization method with the aim of minimizing the crosstalk change rate, and generating a wiring layout with environmental robustness. According to the invention, the signal integrity and the transmission reliability of the multi-layer PCB in a temperature and humidity changing environment can be effectively improved.

The invention discloses a semiconductor device and a preparation method thereof. The preparation method of the semiconductor device comprises the steps that a substrate is provided, a stacking layer formed by alternately arranging a plurality of first sacrificial layers and a plurality of second sacrificial layers is formed on the substrate, and the second sacrificial layers and the substrate are made of the same material; forming a vertical opening penetrating through the stack layer, extending into the substrate, and forming a cavity in the substrate; forming a protective layer in the concave cavity of the substrate; taking the protection layer as an etching stop layer, and transversely etching a part of the second sacrificial layer in the stack layer along the vertical opening to form a plurality of side cavities which are arranged at intervals in the vertical direction; forming a plurality of lower electrodes on the surface of the second sacrificial layer exposed by the plurality of side cavities; forming a capacitor dielectric layer on the surfaces of the plurality of lower electrodes, wherein the capacitor dielectric layer is also located in the vertical opening and is in contact with the protection layer; an upper electrode is formed on the surface of the capacitor dielectric layer, and the multiple lower electrodes, the capacitor dielectric layer and the upper electrode form a capacitor structure. The embodiment of the invention can improve the performance of the device.

The embodiment of the invention discloses an embedded substrate, a power supply device and electronic equipment. The embedded substrate comprises a front surface first adding layer jointed with the first surface of the core part maintaining body, a conduction structure electrically connected with a circuit layer of the dielectric layer is arranged in the dielectric layer of the front surface first adding layer, and the conduction structure comprises a first conduction structure electrically connected with a bonding pad on the chip; the dielectric layer of the first additional layer on the front side is made of an exposable and developable material, an open pore for constructing the conduction structure is formed through exposure and development, the open window of the outer protection layer has a first projection on the first surface, the first open pore for constructing the first conduction structure has a second projection on the first surface, and the second projection covers the first projection. Through the arrangement, the first conduction structure with a larger through-flow cross section is constructed and formed by utilizing the windowing size of the chip side, so that the through-flow capability is effectively improved, and the heat conduction capability is high. In addition, the bonding stress between the circuit layer and the front surface of the chip can be reduced, the layering risk is reduced, and the reliability is better.

The invention provides a forming method of a double-shallow-trench isolation structure with different depths and a semiconductor device, and the method comprises the steps: S1, providing a substrate which comprises a first region and a second region; s2, sequentially forming a first dielectric layer, a first hard mask layer and a second hard mask layer on the substrate, wherein the first hard mask layer and the second hard mask layer are made of different materials; s3, forming a first initial opening in the second hard mask layer of the first region, performing etching by taking the second hard mask layer as a mask, and stopping forming a first opening on the surface of the first dielectric layer; s4, forming a second initial opening in the second hard mask layer of the second region, etching by taking the second hard mask layer as a mask, and stopping on the surface of the substrate to form a second opening; s5, removing the second hard mask layer; and S6, etching the first opening and the second opening at the same time by taking the first hard mask layer as a mask, forming a first shallow trench below the first opening, and forming a second shallow trench below the second opening. The depth difference between the first shallow trench and the second shallow trench is determined by the thickness of the first dielectric layer.

The invention relates to the technical field of electromagnetic materials, and discloses a lossy multimode resonant metasurface unit and a multifunctional active coding wave absorber. The lossy multimode resonant metasurface unit comprises a lossy metal pattern layer, a supporting dielectric layer, an impedance matching dielectric layer and a metal ground layer which are sequentially arranged from top to bottom; the lossy metal pattern layer comprises a multi-mode resonator and a radio frequency PIN diode, the multi-mode resonator is used for realizing a plurality of resonance modes and playing a role in electromagnetic wave frequency selection, and the radio frequency PIN diode is used for playing a role of an adjustable resistor and adjusting the electromagnetic wave loss so as to realize intensity adjustment of reflected electromagnetic waves; every two adjacent multi-mode resonators are connected in a cascading mode through a radio frequency PIN diode and are combined to form a closed-loop pattern. The multifunctional electromagnetic wave absorber is simple in structure, has the constant phase scattering cancellation characteristic, and can independently regulate and control the reflection amplitude so as to solve the technical problem of an existing multifunctional electromagnetic wave absorber.

Provided are a solar cell, a method for preparing a solar cell, and a photovoltaic module, relating to the field of photovoltaics. The solar cell includes a substrate, a dielectric layer and a doped semiconductor layer which are stacked, a passivation layer, and electrodes. The substrate has a first surface. The first surface includes an edge region and a center region. The edge region surrounds the center region. The edge region is substantially flush with or closer to the second surface than the center region. The dielectric layer is formed over the center region. The passivation layer covers the edge region and a surface of the doped semiconductor layer facing away the dielectric layer. The electrodes are located in the center region, and penetrate the passivation layer in a thickness direction to be in electrical contact with the doped semiconductor layer.

The invention discloses a solar cell and a preparation method thereof. The solar cell comprises a semiconductor substrate, the semiconductor substrate is provided with a light receiving surface and a backlight surface which are oppositely arranged, and the backlight surface of the semiconductor substrate is provided with a first area and a second area; a tunneling dielectric layer and a first doping layer, wherein the tunneling dielectric layer and the first doping layer are sequentially stacked on the first region; the intrinsic passivation layer and the second doping layer are sequentially arranged on the second area in a stacked mode, the intrinsic passivation layer is made of intrinsic silicon, and the doping type of the second doping layer is opposite to that of the first doping layer; and the oxidation isolation layer is arranged between the first doping layer and the second doping layer and is used for isolating the first doping layer from the second doping layer in an insulating manner. The problem of electric leakage can be improved.

The disclosure relates to a π type trench gate silicon carbide MOSFET device and a fabrication method thereof. To protect a trench gate oxide layer without increasing a channel resistance and process complexity, a second conductivity type of heavily doped deep well inserted with double gate trenches along the sidewalls of deep well is designed. The deep well is connected to the source metal directly. The electric potential is clamped to the source during the voltage blocking and turn-off state, which reduces the electric field in the gate oxide and reduces the miller capacitance. An interlayer dielectric layer is deposited above the conductive dielectric polysilicon layers and extends outward separately to cover a part of the source region. A smaller cell pitch can be achieved by controlling the spacing between the first and the second trench gate, thereby increasing the channel density and reducing the channel resistance.

The invention relates to the technical field of printed embedded PCBs, and discloses an embedded PCB and a manufacturing method thereof.The embedded PCB comprises a daughter board, a first dielectric layer and a first circuit layer which are sequentially arranged in a stacked mode in the first direction, a device is embedded in the daughter board, the device is located on the side, close to the first dielectric layer, of the daughter board, and the first dielectric layer is located on the first circuit layer. One side, close to the first dielectric layer, of the device is provided with a first part, and the first part is provided with a first protection part; a first connection hole is formed in the first dielectric layer, a first conductive part is filled in the first connection hole, the first protection part is connected and electrically conducted with the first conductive part, and the first conductive part is connected and electrically conducted with the first circuit layer. The embedded PCB and the manufacturing method thereof provided by the invention are used for improving the problem of poor hole filling in the electroplating hole filling process in the related technology.

To provide a multilayer electronic component having excellent reliability by preventing penetration of external moisture or plating solution.SOLUTION: According to one embodiment of the present invention, there is provided a multilayer electronic component which includes: a body including a dielectric layer and an internal electrode alternately disposed with the dielectric layer; an external electrode including a base electrode layer connected to the internal electrode; and an interface layer disposed between an end of the dielectric layer and the base electrode layer. The interface layer includes a first glass containing Ba, Zn, and Si, and the base electrode layer includes a second glass containing Ba and Si. When an average molar ratio (Ba / Si) of Ba to Si contained in the first glass is M1 and an average molar ratio (Ba / Si) of Ba to Si contained in the second glass is M2, M1 and M2 satisfy M1 / M2≥1.5.SELECTED DRAWING: Figure 5

The invention discloses a medium-wave infrared pixel-level spectral polarization optical system, which belongs to the field of lenses and comprises a refraction lens group, a cold diaphragm, a super-structure micro-lens array and a medium-wave infrared quantum dot detector which are sequentially arranged along an incident light path, the super-structure micro-lens array comprises an object side micro-structure and an image side micro-structure; the image side microstructure is used for realizing focusing; the object side microstructure comprises a plurality of object side units which are periodically distributed; each object side unit comprises a polarization metal wire grating structure and a plurality of metasurface-microcavity structures; the polarization metal wire grating structure is formed by arranging metal wire gratings according to different directions so as to realize detection of different orthogonal polarization states; the metasurface-microcavity structure comprises a middle dielectric layer, distributed Bragg gratings located on the two sides of the middle dielectric layer and a metasurface columnar structure unit array embedded into the middle dielectric layer, and the metasurface columnar structure unit array is used for achieving filtering of light of different wave bands. The system has the advantages of good imaging quality, small size, real-time imaging and the like.

The invention relates to the technical field of textiles. The invention discloses a textile dyeing uniformity detection system, a detection method and a dyeing method. The device comprises a light source supply device which is arranged above a textile and is used for providing light sources with two wavelengths and generating monochromatic coherent light, a dielectric layer supply device for forming a uniform dielectric layer, a reflective light path device for splitting beams and guiding the beams to form an interference area, and an image acquisition device for acquiring interference fringe images, the angle adjusting device is used for adjusting irradiation and acquisition angles; and the image processing device is used for analyzing signals and identifying non-uniform dyeing areas and flaws. A high-precision detection system is constructed, the light source and the dielectric layer cooperate to realize micron-sized defect recognition, the visibility of interference fringes is improved to 0.8 or above, and the dynamic tension frame guarantees the precision. The reflective light path and angle adjusting device adapts to a complex environment, a detection method and a dyeing method are cooperated, and through pretreatment, quantitative analysis and multi-dimensional verification, the misjudgment rate is greatly reduced, and the detection speed adapts to production.

The invention relates to the technical field of vehicle-mounted antennas, and aims to solve the technical problem of low antenna gain. In order to solve the technical problem, the invention provides the double-frequency automobile glass antenna applied to vehicle-mounted satellite navigation. According to the invention, an intermediate dielectric layer is stacked below an outer glass dielectric layer; the inner glass dielectric layer is stacked below the middle dielectric layer; the first patch is attached between the outer glass dielectric layer and the middle dielectric layer; the first patch is provided with four fan-shaped grooves penetrating through the thickness of the first patch; the second patch is attached between the middle dielectric layer and the inner glass dielectric layer; the second patch is provided with four linear grooves penetrating through the thickness of the second patch, and the four linear grooves are distributed in a cross shape; the fan-shaped grooves and the straight-line-shaped grooves are arranged in a one-to-one correspondence mode, and orthographic projections of the straight-line-shaped grooves are covered by orthographic projections of the fan-shaped grooves The feed patch is attached to the lower surface of the inner glass dielectric layer and is used for feeding; and the PCB layer is attached to the lower surface of the feed patch. The antenna covers two resonance points, and the antenna gain is high.

The invention provides a silicon bridge chip packaging method and a silicon bridge chip packaging structure, which can reduce the manufacturing cost and improve the heat dissipation effect of a packaging body. A silicon through hole and a first dielectric substance layer are manufactured on the first surface of a silicon wafer, a groove is manufactured by avoiding the silicon through hole, a silicon bridge chip is mounted in the groove, a rewiring layer is arranged on the first surface of the silicon wafer, and the silicon bridge chip is packaged by the rewiring layer. Welding salient points are arranged on the rewiring layer, and the welding salient points are connected to the silicon bridge chip through lines on the rewiring layer; at least two chips are connected with the welding bumps, so that the chips are connected through the silicon bridge chip, the first surface of the silicon wafer is subjected to plastic packaging, the second surface, away from the silicon bridge chip, of the silicon wafer is thinned until the bottom of the silicon through hole is exposed, then a second dielectric substance layer is manufactured, and metal bumps are arranged; and thinning the plastic packaging layer on the first surface of the silicon wafer to expose the back surface of the chip, cutting the silicon wafer into single packaging bodies, inversely welding the single packaging bodies on the first surface of the substrate through the metal bumps, and arranging solder balls on the second surface of the substrate.

The invention discloses a method for improving the heat dissipation performance of an AlGaInP red light Micro LED chip. The method comprises the following steps: S1, preparing an epitaxial structure: processing a substrate and a buffer layer, growing an etching barrier layer and an ohmic contact layer, and carrying out stacking epitaxy on a functional layer; s2, patterning the silicon-based substrate: preparing a dielectric layer and a metal structure; s3, diamond ohmic contact layer integration: processing a p-type conductive diamond film layer, and carrying out metal reflection and bonding; s4, removing the substrate and forming an n-type structure: stripping the substrate to be in n-type contact; s5, back-end process integration: preparing an electrode and an optical structure; according to the invention, the heat dissipation performance of the chip is significantly improved; the series resistance is reduced by 30%-50%; the resistivity of the p / n type diamond ohmic contact layer is reduced by 1-2 orders of magnitude compared with ITO; gaAs material light absorption and metal shading are avoided, and the red light transmittance is improved from 75% to more than 90% by combining with the micro lens array; the method is compatible with existing MOCVD, CVD and photoetching processes, large-scale production of wafers of 2-12 inches can be achieved, and the manufacturing cost is reduced.

The invention relates to the field of molecular photoelectric devices, and provides a single photon source based on an up-conversion photoelectric device and a preparation method thereof, and the preparation method comprises the steps: preparing a dielectric layer; preparing a graphene array electrode on the dielectric layer; constructing a graphene nano gap point electrode pair; placing the graphene nano gap point electrode pair in a two-neck flask, adding 1-(3-dimethylaminopropyl)-3-2-ethylcarbodiimide hydrochloride and an up-conversion luminescent molecule A part into the two-neck flask, adding anhydrous pyridine into the two-neck flask in a nitrogen environment, and stirring to obtain a graphene nano gap point electrode pair; and putting the device connected with an up-conversion luminescent molecule part A at two ends and an up-conversion luminescent molecule part B containing lanthanide metal into a tetrahydrofuran solution for molecular system chelation to obtain the single-molecule up-conversion photoelectric device containing the chiral group. A liquid metal Ga2O3 protective layer is plated on a single-molecule up-conversion photoelectric device, so that a single photon source is obtained, and the stability and the anti-interference capability of the single photon source are enhanced.

A multi-chip package comprising an interconnection substrate; a first semiconductor IC chip over the interconnection substrate, wherein the first semiconductor IC chip comprises a first silicon substrate, a plurality of first metal vias passing through the first silicon substrate, a plurality of first transistors on a top surface of the first silicon substrate and a first interconnection scheme over the first silicon substrate, wherein the first interconnection scheme comprises a first interconnection metal layer over the first silicon substrate, a second interconnection metal layer over the first interconnection layer and the first silicon substrate and a first insulating dielectric layer over the first silicon substrate and between the first and second interconnection metal layers; a second semiconductor IC chip over and bonded to the first semiconductor IC chip; and a plurality of second metal vias over and coupling to the interconnection substrate, wherein the plurality of second metal vias are in a space extending from a sidewall of the first semiconductor IC chip.

The invention relates to a preparation method of a solar cell and the solar cell, the solar cell comprises a substrate, a first surface of the substrate is provided with a plurality of first areas and a plurality of second areas which are distributed in a staggered manner, and each second area comprises a first sub-area and a second sub-area which are distributed along a first direction; the first region is provided with a tunneling oxide layer and a first doped conductive layer. The preparation method comprises the following steps: providing a substrate, and sequentially preparing a tunneling oxide layer, a first doped conductive layer and a dielectric layer on a first surface; performing graphical processing on the second region by adopting first laser, and sequentially modifying the dielectric layers in the plurality of first sub-regions into loose structures along the first direction; performing graphical processing on the second region by adopting second laser, and modifying the dielectric layers in the plurality of second sub-regions into loose structures in sequence along the first direction; and removing the modified dielectric layer, the first doped conductive layer and the tunneling oxide layer in the second region. The preparation method can reduce the surface defects of the battery and can improve the conversion efficiency of the battery.

The embodiment of the invention relates to the photovoltaic field, and provides a back contact battery and a manufacturing method thereof, and a photovoltaic module, the back contact battery comprises a substrate, the substrate is provided with a first surface and a second surface which are opposite to each other along a first direction, and the second surface is provided with first regions and second regions which are alternately arranged along a second direction; the first dielectric layer and the first doping layer are stacked on the first region, and P-type doping elements are arranged in the first doping layer; the second dielectric layer and the second doping layer are stacked on the second region, and the second doping layer is provided with N-type doping elements; wherein the first doped layer comprises N layers of stacked first doped films, the crystallization rate of the (N-1) th layer of first doped film is higher than the crystallization rate of the Nth layer of first doped film in the direction away from the substrate, and N is a positive integer greater than or equal to 2. The embodiment of the invention is at least beneficial to improving the photoelectric conversion efficiency of the back contact battery.

The invention relates to an optical fiber hydrogen sensor based on a silver film-nanowire hole array structure and a preparation method thereof in the field of photochemical sensors. The optical fiber hydrogen sensor comprises a multimode optical fiber, and a sensing area is formed on the multimode optical fiber; the sensing area is formed by stripping a coating layer with a preset length from the multimode optical fiber, thinning the optical fiber in the area, plating a silver film on the surface of the thinned optical fiber, and adsorbing a nanowire hole array structure which is sequentially and vertically arranged on the surface of the silver film in a liquid level self-assembly manner; the nanowire hole array is of a metal-medium-metal (MIM) structure, a gold-palladium nanowire array is arranged at the bottom, an intermediate medium layer is made of aluminum oxide, and a silver film with a hole array in any shape is arranged at the top. When light is transmitted to a sensing area from a fiber core of the multimode optical fiber, the light and a metal silver film can excite a surface plasmon resonance (SPR) effect, meanwhile, an MIM structure formed by a gold-palladium nanowire, an aluminum oxide dielectric layer and a porous silver film serves as an optical coupling antenna through a local surface plasmon resonance (LSPR) effect at the edge of a top hole, and the optical coupling antenna is used for transmitting the light to the sensing area. Light energy is efficiently converged and excited in an extremely bound gap plasmon (Gap Plasmon) in an aluminum oxide dielectric layer, so that far-unconventional electromagnetic field enhancement is generated in a sensing core area, and the sensitivity of the sensor is greatly improved.

The invention relates to the field of surface-mounted metasurface structure design, in particular to a design method and device for a multi-frequency transparent transmission type surface-mounted metasurface structure, and the method comprises the steps: representing a multi-layer structure of a glass surface-mounted metasurface through a cascade transmission matrix; wherein the metasurface comprises a metal layer and a dielectric layer; a corresponding transmission coefficient is calculated by using the represented cascade transmission matrix, and a theoretical optimal transmission coefficient of a target frequency band under the structure is obtained by adjusting the dielectric constant and the thickness of a metasurface dielectric layer and the equivalent impedance of a metasurface metal layer to determine an initial structure and a parameter change interval of a to-be-optimized metasurface unit; simulating to obtain a transmission coefficient under the initial structure of the metasurface; and based on the transmission coefficient under the initial structure of the metasurface, taking a theoretical optimal transmission coefficient as an optimization target, and adopting a quasi-Newton algorithm to optimize metasurface design to obtain a metasurface structure corresponding to the optimal transmission coefficient. Compared with the prior art, the invention has the advantages of greatly and stably improving the transmission performance of multiple frequency bands and the like.

The invention provides a method for adjusting the height of a grid electrode and a semiconductor structure, and belongs to the field of semiconductors. The method of adjusting gate height includes providing a semiconductor substrate. And etching back the hard mask layer in the NMOS region to reduce the thickness of the hard mask layer in the NMOS region. And after back etching, gate structures are respectively formed in the PMOS region and the NMOS region. And filling a dielectric layer, wherein the dielectric layer covers the gate structure of the NMOS region. And patterning a groove, etching the groove in the PMOS region, and when the groove is etched in the PMOS region, the thickness lost by the hard mask layer in the PMOS region is basically equal to the thickness lost by etching the hard mask layer in the NMOS region. By depositing the hard mask layer and etching the hard mask layer, the thickness of the hard mask layer in the PMOS region is basically equal to that of the hard mask layer in the NMOS region, so that the height of the formed grid electrode in the PMOS region is basically equal to that of the grid electrode in the NMOS region, and the performance of the device can be improved.

The invention discloses a laser film structure and a preparation method thereof. Wherein the thin film structure comprises a first dielectric layer, a metal layer, a second dielectric layer and a base material layer, and the second dielectric layer is formed by alternately depositing a dielectric material with a low refractive index and a dielectric material with a high refractive index; the structural expression of the second dielectric layer is H (LH) s, H represents a high-refractive-index dielectric material with the optical thickness of lambda / 4, L represents a low-refractive-index dielectric material with the optical thickness of lambda / 4, and s represents the number of cycles of the film system. According to the invention, the camouflage capability is improved, and the excellent laser protection performance is ensured.

The present application discloses a semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate; a word line structure including a word line dielectric layer in the substrate and including a U-shaped profile, a word line conductive layer on the word line dielectric layer and within the substrate, and a word line capping layer on the word line conductive layer; a top thickening layer including a U-shaped profile, between the word line conductive layer and the word line capping layer, and between the word line dielectric layer and the word line capping layer; a bottom capping layer on the substrate and adjacent to the word line dielectric layer; and a top capping layer covering the bottom capping layer and the word line structure. Top surfaces of the top thickening layer and the word line dielectric layer are coplanar and higher than the substrate.

The invention discloses a rigid-flex circuit board slotting process based on a laser depth control technology. The rigid-flex circuit board slotting process comprises the steps that the surface of a rigid layer of a rigid-flex circuit board is pretreated, and a laser sensitive layer is sprayed; cNC depth-controlled milling is adopted to form a grooved rough blank structure on the surface of the pretreated rigid layer; positioning laser is used for scanning, a three-dimensional model is established through collected reflected signals, then layered depth-controlled ablation is conducted, second-power laser is sequentially adopted for fine cutting, third-power laser is sequentially adopted for depth calibration, and a groove body structure is formed; cleaning an interface, scanning a groove bottom area and synchronously introducing low-temperature gas; performing morphology repairing treatment, and generating a periodic micro-nano structure on the groove wall by adopting short pulse laser to form a stress concentration resistant surface; depositing an insulating medium layer, and forming a continuous packaging protection layer on the groove wall and the bottom through a vacuum coating process; the high-precision depth-controlled slotting of the rigid-flex circuit board is realized, and meanwhile, the ultra-low thermal damage and anti-fatigue structure and long-acting environmental stability are realized.