16881 results about "Dielectric layer" patented technology

Disclosed are methods of microelectronic processing to reveal conductive vias that are at least partially embedded in a bulk semiconductor, and resulting structures. A method of forming a microelectronic structure includes revealing the plurality of conductive vias from a back surface of the bulk semiconductor and forming a protective cap on each of the conductive vias on the back surface of the bulk semiconductor. The protective caps can be patterned or disposed selectively onto the conductive vias. The protective caps can cover the conductive vias or also cover a portion of the bulk semiconductor surrounding the conductive vias. The back surface of the bulk semiconductor is etched to form protruding conductive vias, which can be surrounded by sleeves of the bulk semiconductor. A dielectric layer is deposited over the back surface and planarized to reveal the plurality of conductive vias from the back surface.

The invention provides a 2.5 D substrate manufacturing method and a packaging structure. The 2.5 D substrate manufacturing method comprises the following steps: providing a first carrier on which a metal part and an intermediate layer are mounted; a metal column is arranged in the intermediate layer; forming a protective layer covering the metal component and the interposer on the first carrier; a first recess is formed on the metal feature. The interposer and the protective layer are ground such that the interposer and protective layer surfaces are lower than the surface of the metal feature. Forming a first dielectric layer with a first opening on the surfaces of the intermediate layer and the protective layer; the first opening exposes the metal column. Forming a seed layer in the first opening; the seed layer extends to the surface of the metal part and fills the first groove. A wiring layer is formed on the seed layer. The bonding force of the seed layer and the first dielectric layer can be improved, the corrosion to the side wall of the interposer in the etching process is prevented, and the packaging quality and precision are improved.

The invention relates to a modeling and optimizing method for inter-layer signal crosstalk of a PCB (Printed Circuit Board). Frequency response data of all dielectric layers of the PCB under different temperature and humidity conditions are collected, and a mapping model with the temperature gradient and the humidity diffusion gradient as input and the dielectric constant as output is established. And calculating the dynamic distribution of mutual capacitance and mutual inductance under the environment change by combining the spatial layout parameters of the differential signal pair, and constructing a crosstalk sensitivity evaluation model with coupled frequency, environment and layout. And high-risk areas with crosstalk sensitivity caused by environment change are identified, and the crosstalk change rate of each area is quantified. For a sensitive area, a temperature and humidity compensation medium structure is introduced to stabilize local dielectric characteristics and reduce the influence of the environment on crosstalk. And according to the compensated medium distribution, adjusting a differential signal wiring path and impedance matching by adopting an optimization method with the aim of minimizing the crosstalk change rate, and generating a wiring layout with environmental robustness. According to the invention, the signal integrity and the transmission reliability of the multi-layer PCB in a temperature and humidity changing environment can be effectively improved.

The invention relates to the technical field of electromagnetic materials, and discloses a lossy multimode resonant metasurface unit and a multifunctional active coding wave absorber. The lossy multimode resonant metasurface unit comprises a lossy metal pattern layer, a supporting dielectric layer, an impedance matching dielectric layer and a metal ground layer which are sequentially arranged from top to bottom; the lossy metal pattern layer comprises a multi-mode resonator and a radio frequency PIN diode, the multi-mode resonator is used for realizing a plurality of resonance modes and playing a role in electromagnetic wave frequency selection, and the radio frequency PIN diode is used for playing a role of an adjustable resistor and adjusting the electromagnetic wave loss so as to realize intensity adjustment of reflected electromagnetic waves; every two adjacent multi-mode resonators are connected in a cascading mode through a radio frequency PIN diode and are combined to form a closed-loop pattern. The multifunctional electromagnetic wave absorber is simple in structure, has the constant phase scattering cancellation characteristic, and can independently regulate and control the reflection amplitude so as to solve the technical problem of an existing multifunctional electromagnetic wave absorber.

Provided are a solar cell, a method for preparing a solar cell, and a photovoltaic module, relating to the field of photovoltaics. The solar cell includes a substrate, a dielectric layer and a doped semiconductor layer which are stacked, a passivation layer, and electrodes. The substrate has a first surface. The first surface includes an edge region and a center region. The edge region surrounds the center region. The edge region is substantially flush with or closer to the second surface than the center region. The dielectric layer is formed over the center region. The passivation layer covers the edge region and a surface of the doped semiconductor layer facing away the dielectric layer. The electrodes are located in the center region, and penetrate the passivation layer in a thickness direction to be in electrical contact with the doped semiconductor layer.

The invention discloses a solar cell and a preparation method thereof. The solar cell comprises a semiconductor substrate, the semiconductor substrate is provided with a light receiving surface and a backlight surface which are oppositely arranged, and the backlight surface of the semiconductor substrate is provided with a first area and a second area; a tunneling dielectric layer and a first doping layer, wherein the tunneling dielectric layer and the first doping layer are sequentially stacked on the first region; the intrinsic passivation layer and the second doping layer are sequentially arranged on the second area in a stacked mode, the intrinsic passivation layer is made of intrinsic silicon, and the doping type of the second doping layer is opposite to that of the first doping layer; and the oxidation isolation layer is arranged between the first doping layer and the second doping layer and is used for isolating the first doping layer from the second doping layer in an insulating manner. The problem of electric leakage can be improved.

The invention relates to the technical field of printed embedded PCBs, and discloses an embedded PCB and a manufacturing method thereof.The embedded PCB comprises a daughter board, a first dielectric layer and a first circuit layer which are sequentially arranged in a stacked mode in the first direction, a device is embedded in the daughter board, the device is located on the side, close to the first dielectric layer, of the daughter board, and the first dielectric layer is located on the first circuit layer. One side, close to the first dielectric layer, of the device is provided with a first part, and the first part is provided with a first protection part; a first connection hole is formed in the first dielectric layer, a first conductive part is filled in the first connection hole, the first protection part is connected and electrically conducted with the first conductive part, and the first conductive part is connected and electrically conducted with the first circuit layer. The embedded PCB and the manufacturing method thereof provided by the invention are used for improving the problem of poor hole filling in the electroplating hole filling process in the related technology.

The invention relates to the technical field of textiles. The invention discloses a textile dyeing uniformity detection system, a detection method and a dyeing method. The device comprises a light source supply device which is arranged above a textile and is used for providing light sources with two wavelengths and generating monochromatic coherent light, a dielectric layer supply device for forming a uniform dielectric layer, a reflective light path device for splitting beams and guiding the beams to form an interference area, and an image acquisition device for acquiring interference fringe images, the angle adjusting device is used for adjusting irradiation and acquisition angles; and the image processing device is used for analyzing signals and identifying non-uniform dyeing areas and flaws. A high-precision detection system is constructed, the light source and the dielectric layer cooperate to realize micron-sized defect recognition, the visibility of interference fringes is improved to 0.8 or above, and the dynamic tension frame guarantees the precision. The reflective light path and angle adjusting device adapts to a complex environment, a detection method and a dyeing method are cooperated, and through pretreatment, quantitative analysis and multi-dimensional verification, the misjudgment rate is greatly reduced, and the detection speed adapts to production.

The invention discloses a method for improving the heat dissipation performance of an AlGaInP red light Micro LED chip. The method comprises the following steps: S1, preparing an epitaxial structure: processing a substrate and a buffer layer, growing an etching barrier layer and an ohmic contact layer, and carrying out stacking epitaxy on a functional layer; s2, patterning the silicon-based substrate: preparing a dielectric layer and a metal structure; s3, diamond ohmic contact layer integration: processing a p-type conductive diamond film layer, and carrying out metal reflection and bonding; s4, removing the substrate and forming an n-type structure: stripping the substrate to be in n-type contact; s5, back-end process integration: preparing an electrode and an optical structure; according to the invention, the heat dissipation performance of the chip is significantly improved; the series resistance is reduced by 30%-50%; the resistivity of the p / n type diamond ohmic contact layer is reduced by 1-2 orders of magnitude compared with ITO; gaAs material light absorption and metal shading are avoided, and the red light transmittance is improved from 75% to more than 90% by combining with the micro lens array; the method is compatible with existing MOCVD, CVD and photoetching processes, large-scale production of wafers of 2-12 inches can be achieved, and the manufacturing cost is reduced.

The embodiment of the invention relates to the photovoltaic field, and provides a back contact battery and a manufacturing method thereof, and a photovoltaic module, the back contact battery comprises a substrate, the substrate is provided with a first surface and a second surface which are opposite to each other along a first direction, and the second surface is provided with first regions and second regions which are alternately arranged along a second direction; the first dielectric layer and the first doping layer are stacked on the first region, and P-type doping elements are arranged in the first doping layer; the second dielectric layer and the second doping layer are stacked on the second region, and the second doping layer is provided with N-type doping elements; wherein the first doped layer comprises N layers of stacked first doped films, the crystallization rate of the (N-1) th layer of first doped film is higher than the crystallization rate of the Nth layer of first doped film in the direction away from the substrate, and N is a positive integer greater than or equal to 2. The embodiment of the invention is at least beneficial to improving the photoelectric conversion efficiency of the back contact battery.

The invention relates to an optical fiber hydrogen sensor based on a silver film-nanowire hole array structure and a preparation method thereof in the field of photochemical sensors. The optical fiber hydrogen sensor comprises a multimode optical fiber, and a sensing area is formed on the multimode optical fiber; the sensing area is formed by stripping a coating layer with a preset length from the multimode optical fiber, thinning the optical fiber in the area, plating a silver film on the surface of the thinned optical fiber, and adsorbing a nanowire hole array structure which is sequentially and vertically arranged on the surface of the silver film in a liquid level self-assembly manner; the nanowire hole array is of a metal-medium-metal (MIM) structure, a gold-palladium nanowire array is arranged at the bottom, an intermediate medium layer is made of aluminum oxide, and a silver film with a hole array in any shape is arranged at the top. When light is transmitted to a sensing area from a fiber core of the multimode optical fiber, the light and a metal silver film can excite a surface plasmon resonance (SPR) effect, meanwhile, an MIM structure formed by a gold-palladium nanowire, an aluminum oxide dielectric layer and a porous silver film serves as an optical coupling antenna through a local surface plasmon resonance (LSPR) effect at the edge of a top hole, and the optical coupling antenna is used for transmitting the light to the sensing area. Light energy is efficiently converged and excited in an extremely bound gap plasmon (Gap Plasmon) in an aluminum oxide dielectric layer, so that far-unconventional electromagnetic field enhancement is generated in a sensing core area, and the sensitivity of the sensor is greatly improved.

The invention discloses a rigid-flex circuit board slotting process based on a laser depth control technology. The rigid-flex circuit board slotting process comprises the steps that the surface of a rigid layer of a rigid-flex circuit board is pretreated, and a laser sensitive layer is sprayed; cNC depth-controlled milling is adopted to form a grooved rough blank structure on the surface of the pretreated rigid layer; positioning laser is used for scanning, a three-dimensional model is established through collected reflected signals, then layered depth-controlled ablation is conducted, second-power laser is sequentially adopted for fine cutting, third-power laser is sequentially adopted for depth calibration, and a groove body structure is formed; cleaning an interface, scanning a groove bottom area and synchronously introducing low-temperature gas; performing morphology repairing treatment, and generating a periodic micro-nano structure on the groove wall by adopting short pulse laser to form a stress concentration resistant surface; depositing an insulating medium layer, and forming a continuous packaging protection layer on the groove wall and the bottom through a vacuum coating process; the high-precision depth-controlled slotting of the rigid-flex circuit board is realized, and meanwhile, the ultra-low thermal damage and anti-fatigue structure and long-acting environmental stability are realized.

A semiconductor device includes a plurality of gate separated by an interlayer dielectric (ILD), a backside contact. The backside contact is extended below the plurality of gates and a dielectric layer, and from a first gate to a second gate of the plurality of gates, and a placeholder. The placeholder is extended below the plurality of gates and between the second gate and a third gate of the plurality of gates. The backside contact and the placeholder are not directly electrically connected.

The invention relates to a laser drilling method for a thin copper HDI circuit board. The laser drilling method comprises the following steps that a circuit board to be machined is positioned and installed on a machining station of laser machining equipment; a first section of laser drilling is carried out, a first laser parameter is adopted, uncovering drilling is carried out on a preset machining area of the outer copper foil layer, and an initial hole structure is formed; performing second-section laser drilling, namely performing compensation drilling on the dielectric layer exposed at the bottom of the initial hole structure by adopting a second laser parameter of which the energy is lower than that of the first laser parameter to form a transition hole structure; and in the third section of laser drilling, a third laser parameter with energy lower than that of the second laser parameter is adopted, the bottom of the transition hole structure is trimmed, and a final hole channel is formed. According to the method, drilling is conducted in three sections, namely the first section of uncovering drilling, the second section of compensation drilling and the third section of finishing treatment. Therefore, the bottom cushion copper cannot absorb a large amount of heat in a short time, the base material layer below the bottom cushion copper can be protected from being burnt, and the product quality is improved.

The embodiment of the invention provides a glass-based structural member as well as a preparation method and application thereof, and the preparation method comprises the following steps: carrying out at least one pre-plating cleaning selected from alkali cleaning, acid pickling and plasma treatment on a glass substrate, so that the surface water drop angle of the glass substrate is in a range of 10-30 degrees; forming a dielectric layer comprising a silicon dioxide layer on the surface of one side of the glass substrate cleaned before plating; forming an anti-fingerprint layer on the silicon dioxide layer; si-CH2 bonds are formed between the silicon dioxide layer and the anti-fingerprint layer. After the glass base material is cleaned before plating, the binding force between the SiO2 layer formed on the glass base material and the glass base material and the binding force between the anti-fingerprint layer and the SiO2 layer are both high, so that the thickness of the SiO2 layer and the anti-fingerprint layer can be large, the structure of the whole coating is stable, and the glass-based structural part can have good abrasion resistance, good scratch resistance and a lasting anti-fingerprint effect; and the application requirements in the fields of electronic equipment and the like can be well met.

The invention relates to the technical field of radio frequency integrated circuits and advanced semiconductor packaging, in particular to a multilayer spiral inductor structure based on an RDL process and a preparation method. The preparation method comprises the steps of seed layer deposition, gradient line width coil formation through photoetching and electroplating, alternate dielectric layer deposition, through hole etching to form vertical interconnection copper columns, air bridge forming through a photoresist sacrificial layer process and silicon nitride passivation packaging. Through fan-shaped topological layout, dielectric material collaborative optimization and three-dimensional interconnection structure design, the self-resonant frequency bandwidth is effectively improved, conductor and dielectric loss is reduced, and miniaturization integration and high reliability of high-frequency inductance elements are achieved.

A high-density ferroelectric memory, and a preparation method therefor and an application thereof, belonging to the field of semiconductor memories. In the memory, multiple memory cells are arranged in an array, and the two sides of the array of the memory cells are connected to substantially orthogonal word lines and bit lines, the memory cell of the present invention adopts a stacked structure of a top electrode, a resistive switching dielectric layer, an intermediate metal layer, a ferroelectric dielectric layer, and a bottom electrode, which is electrically equivalent to a ferroelectric capacitor and a resistive switching selector connected in series; the voltage division of the distributed ferroelectric capacitor in the unselected cells is reduced by regulating the RC delay of the memory cell, so that its disturbance is reduced; and the capacitance value of the ferroelectric capacitor is stable, and the influence of the disturbance voltage can be effectively reduced by RC regulation. The storage window of the memory is improved and the bit error rate is reduced, without increasing additional area overhead.

The invention relates to the technical field of flexible pressure sensors, in particular to a preparation method and application of a capacitance flexible pressure sensor with an adjustable gradient random micro-cone structure, and the sensor comprises an upper electrode and a lower electrode which are transparent indium tin oxide conductive films (PET / ITO); the packaging layer is a polyimide (PI) adhesive tape and covers the outer side of the electrode; the flexible isolation layer is polydimethylsiloxane (PDMS) with a hollow structure, and is positioned between the upper electrode and the lower electrode; the dielectric layer of a gradient random micro-cone structure is located in the flexible isolation layer and is formed by compounding polyvinyl alcohol (PVA) and phosphoric acid (H3PO4) according to the mass ratio of 1: 1; the gradient micro-cone structure and the ionization effect are combined, the electric double layer effect grading phenomenon occurs, and the gradient micro-cone sensor has the advantages of being high in sensitivity, wide in detection range, capable of keeping linearity under large pressure, short in response time and good in cycling stability.

The invention provides a multifunctional floating gate transistor based on a two-dimensional material heterojunction and a preparation method thereof, and relates to the technical field of semiconductors, and the multifunctional floating gate transistor comprises a substrate which comprises a back gate and a gate dielectric layer which are stacked from bottom to top; the floating gate layer is located on the surface, away from the back gate, of the gate dielectric layer; the tunneling dielectric layers are located on the surfaces, away from the back gate, of the floating gate layer and the gate dielectric layer respectively, and the floating gate layer is covered with the tunneling dielectric layers; the channel layer is located on the surface, away from the substrate, of the tunneling dielectric layer, and the first orthographic projection of the channel layer on the substrate and the second orthographic projection of the floating gate layer on the substrate are at least partially overlapped; the channel layer is also provided with a source electrode and a drain electrode, and a channel region is formed between the source electrode and the drain electrode. The multifunctional floating gate transistor based on the two-dimensional material heterojunction can be used as a nonvolatile memory and has excellent storage capability.

The present application discloses a memory device and a method for fabricating the memory device. The memory device includes a substrate; a landing area positioned on the substrate; a bottom electrode positioned on the landing area, wherein the bottom electrode has a container-shaped profile; a support layer positioned over the substrate and laterally surrounded the bottom electrode; a dielectric structure including a dielectric layer conformally positioned on the bottom electrode and on a top surface of the support layer, and covering top corners of the support layer, and a plurality of dielectric portions conformally positioned on the dielectric layer and covering the top corners of the support layer; and a top electrode structure positioned on the dielectric structure. The dielectric portions are sandwiched by the top electrode structure and the dielectric layer. The top surface of the third support layer is higher than a top surface of the bottom electrode.

Disclosed in the present application are a silicon carbide MOSFET device and a manufacturing method therefor. The silicon carbide MOSFET is provided with a first withstand voltage masking structure and a second withstand voltage masking structure. The withstand voltage performance of the device is improved, the breakdown problem of a gate insulating dielectric layer can be avoided, the electrostatic effect of the device on a severe environment and the high-voltage peak tolerance capability in the circuit are improved, and the surge voltage resistance of the device and the over-voltage protection capability are improved. Ion implantation can be carried out on a first trench to form the first withstand voltage masking structure, and ion implantation can be carried out on a second trench to form the second withstand voltage masking structure.

A method includes forming a dielectric layer over a source / drain region. An opening is formed in the dielectric layer. The opening exposes a portion of the source / drain region. A conductive liner is formed on sidewalls and a bottom of the opening. A surface modification process is performed on an exposed surface of the conductive liner. The surface modification process forms a surface coating layer over the conductive liner. The surface coating layer is removed to expose the conductive liner. The conductive liner is removed from the sidewalls of the opening. The opening is filled with a conductive material in a bottom-up manner. The conductive material is in physical contact with a remaining portion of the conductive liner and the dielectric layer.

A structure includes a transistor, e.g., HEMT, with a field plate positioned laterally to a side of an active gate and including a first portion extending over the active gate. A dielectric layer isolates a lower surface of the first portion from an upper surface of the active gate. A field plate contact includes interconnect layers located directly over the active gate and electrically coupled to the first portion directly over the active gate. The field plate contact allows electrical operation of the field plate, but also acts as a thermally conductive path from the active gate through the interconnect layers to cool likely hot spots within the transistor.

The invention discloses a three-dimensional integrated packaging structure and a packaging process thereof. The three-dimensional integrated packaging structure comprises a flip or normal chip with a functional surface and an opposite back surface; the rewiring layer and the chip are vertically stacked and electrically connected with each other; electrically leading the rewiring layer out of the packaging structure; the stacking direction of the inductor and the chip is parallel to the thickness direction of the chip, the inductor and the chip, the rewiring layer and the lead-out structure are physically isolated through an insulating medium layer, the inductor is of a spiral, multi-ring layer overlapping or sectional winding structure, the inductor comprises a magnetic core, a spiral coil surrounding the surface of the magnetic core is formed through etching and electroplating processes, and the lead-out structure is arranged on the surface of the spiral coil. The spiral coil comprises a circuit A, a circuit B and a circuit C, and the magnetic core and the spiral coil are encapsulated by the insulating medium layer. The inductor and the chip are stacked in an inverted or normal mode, the three-dimensional structure saves space, reduces parasitic inductance, resistance and the like, signal transmission is stable, electromagnetic interference is small, and the three-dimensional structure is suitable for the chip packaging field of miniaturization, high integration and the like.

The invention provides a 2.5 D substrate manufacturing method and a packaging structure, and relates to the technical field of semiconductor packaging. The 2.5 D substrate manufacturing method comprises the steps that an interposer is provided, and conductive columns are arranged in the interposer; a portion of the interposer is removed such that the conductive pillar portion protrudes from a surface of the interposer. An insulating layer is formed on a side of the interposer where the conductive pillars are exposed. A first groove is formed in the side, away from the interposer, of the insulating layer. Forming a film coating layer on the insulating layer; the film covering layer covers the opening of the first groove to form a first cavity. Forming a first dielectric layer provided with a first wiring layer on the film coating layer; the first wiring layer is electrically connected with the conductive column. In the manufacturing process of the substrate, the insulating layer and the film coating layer are arranged to play a better role in protecting the conductive columns, so that the subfissure and damage of the conductive columns in the packaging process are prevented. And the first cavity is formed, so that warping can be relieved, heat dissipation is improved, and a buffering effect is achieved.

Dipole engineering techniques for devices of stacked device structures are disclosed herein. An exemplary method for forming a gate stack of a transistor (e.g., a top transistor) of a transistor stack includes forming a high-k dielectric layer, forming a p-dipole dopant source layer over the high-k dielectric layer, performing a thermal drive-in process that drives a p-dipole dopant from the p-dipole dopant source layer into the high-k dielectric layer, and forming at least one electrically conductive gate layer over the high-k dielectric layer after removing the p-dipole dopant source layer. A drive-in temperature of the thermal drive-in process is less than 600° C. (e.g., about 300° C. to about 500° C.). The p-dipole dopant can be titanium. The method can further include tuning thermal drive-in process parameters to provide the gate dielectric with a p-dipole dopant profile having a peak located at a high-k / interfacial interface ±0.5 nm.

The invention discloses a method for manufacturing a high-precision circuit board based on material transfer, which comprises the following steps of: taking a thick copper layer, attaching a micro-mucous membrane layer, manufacturing a dry film pattern layer on the other surface, etching off a part of thickness of the thick copper layer, stripping a film, screen-printing solder resist ink, baking and curing, polishing, forming a solder resist ink pattern, laminating an insulating medium layer, and stripping the micro-mucous membrane layer. Etching for the second time to form a circuit pattern layer, and performing surface treatment to form the high-precision circuit board; a reverse processing flow is formed through a material transfer mode, a semi-circuit layer is firstly manufactured, then solder resist ink is directly screen-printed to form a solder resist pattern, then the pattern is transferred to an insulating medium layer, the manufactured circuit pattern and the solder resist pattern are etched and exposed, alignment and exposure are carried out only once, the circuit processing precision is greatly improved, and the production cost is reduced. The solder resist pattern is not subjected to exposure and development processing, the phenomena of irregular pattern edge and lateral erosion are avoided, the whole processing flow is efficient and convenient, and a high-precision circuit board product is formed.

The embodiment of the invention provides a microresonator and a preparation method of the microresonator, the microresonator can be obtained by connecting an MIM plate capacitor and an inductor of a planar coil structure, and an upper electrode, a lower electrode and the inductor of the MIM plate capacitor and a microstrip line connecting the capacitor and the inductor are all prepared from superconducting materials. A dielectric layer of the MIM plate capacitor can be prepared by adopting an ALD technology, a dielectric film grown by adopting the ALD technology is very compact and has very good thickness uniformity, a relatively high dielectric constant can be realized, and the quality factor of the microresonator can be remarkably improved by combining the zero resistance characteristic of a superconducting material; and the miniaturization of the microresonator can be realized. Moreover, in the preparation process, the three layers of thin films for forming the capacitor and the inductor are formed through deposition firstly, and then the three layers of thin films are patterned layer by layer, so that introduction of excessive impurities can be avoided, interlayer contact can be optimized, and the risk of electric leakage can be reduced.

The invention provides a wide-angle scanning dual-circularly-polarized phased-array antenna unit, which belongs to the field of dual-circularly-polarized antennas and comprises a first dielectric layer, a second dielectric layer and a third dielectric layer which are sequentially stacked, the antenna radiator is arranged on the side, away from the second dielectric layer, of the first dielectric layer, the antenna radiator comprises four radiation patches, each radiation patch comprises a metal patch and a loading branch knot, and each metal patch is provided with a slotted structure; the first metal ground layer is clamped between the first dielectric layer and the second dielectric layer, and a cross coupling gap and a first coupling gap and a second coupling gap which are perpendicular to each other are formed in the first metal ground layer; the U-shaped feeder line is clamped between the second dielectric layer and the third dielectric layer, and two ends of the U-shaped feeder line are respectively connected with a coaxial feed column penetrating through the third dielectric layer; the second metal ground layer is arranged on the side, away from the second dielectric layer, of the third dielectric layer; an array is also provided; the problem that a traditional circularly polarized antenna is narrow in impedance bandwidth and limited in polarization is solved.

A multilayer electronic component according to an example embodiment of the present disclosure may include: a body including a plurality of capacitance formation portions including first dielectric layers and internal electrodes alternately arranged in a first direction. An intermediate layer disposed is between the adjacent capacitance formation portions and includes a second dielectric layer. An external electrode is disposed on the body and connected to the internal electrode. The first and second dielectric layers may include a plurality of grains and pores. An average grain size of the first dielectric layer may be smaller than an average grain size of the second dielectric layer. A porosity of the first dielectric layer may be lower than a porosity of the second dielectric layer.