420 results about "Dielectric membrane" patented technology

Active and passive electronic components are placed on a substrate and encapsulated with mold material to produce a molded core substrate for fabricating a hybrid integrated circuit (IC) device. A carrier has a release film laminated to a face thereof. A seed layer of copper is added over the release film and fiducials are plated onto the copper seed layer for component placement using alignment marks on the fiducials. Mold material is applied to the encapsulation layer and around and over the components. Mold material is ground planar with component tops. The carrier and release film are removed, leaving the copper seed layer exposed, which is etched to a pattern. Holes are formed in the mold material and then surfaces thereof are copper plated. A multilayer dielectric film is laminated over copper plating. Vias are formed in the multilayer dielectric film for connections to components.

In an electrode unit of an active gas generation apparatus according to the present disclosure, a dielectric film support member includes a support surface supporting a high voltage side dielectric film from a lower side. A lower surface of the dielectric film suppression member provided on an upper side of a ground side dielectric film includes a dielectric contact region overlapped with a peripheral region of the high voltage side dielectric film and the support surface of the dielectric film support member in a plan view and a dielectric non-contact region overlapped with an intermediate region of the high voltage side dielectric film in a plan view. The high voltage side dielectric film is suppressed from the dielectric contact region on an upper side by the dielectric film suppression member receiving suppress strength of a plurality of suppression auxiliary members.

The present disclosure provides a semiconductor device and a method of forming the same. A method according one embodiment of the present disclosure include forming a stack over a substrate, forming a fin-shape structure from patterning the stack and the substrate, recessing the fin-shape structure to form a source / drain trench, depositing a dielectric film in the source / drain trench with a top surface below a top surface of the substrate in the fin-shape structure, and forming an epitaxial feature over the dielectric film. A bottom surface of the epitaxial feature is below the top surface of the substrate in the fin-shape structure.

The invention relates to a preparation method of a porous polyimide low-dielectric material. The method comprises the following specific steps: preparing a polyamide acid solution with a certain solid content under an ice-water bath condition; after the solution is recovered to normal temperature, adding a certain amount of sodium alginate, and after the solution is homogenized, adding a catalyst and a dehydrating agent for chemical imidization; the method comprises the following steps: coating a substrate medium with a solution after a certain time of reaction, standing in air for a certain time, sequentially and respectively placing the substrate medium in ethanol and a hot water bath for replacement for a certain time, airing at normal temperature, and transferring to a high-temperature oven for gradient cyclization to realize complete imidization. According to the method, conditions are mild and easy to control, and the low-dielectric film material which is flat in appearance and ordered in structure is prepared only through a normal-pressure drying method.

To provide a thin film capacitor having a pair of terminal electrodes capable of being disposed on the same plane. A thin film capacitor 1 includes a metal foil having a non-roughened center portion and a roughened upper surface, a dielectric film covering the roughened upper surface of the metal foil, an electrode layer contacting the non-roughened center portion of the metal foil through an opening formed in the dielectric film, and an electrode layer contacting the dielectric film without contacting the metal foil. A thickness of the center portion of the metal foil at a position overlapping the electrode layer is larger than a thickness thereof at a position overlapping the electrode layer.

To provide a thin film capacitor having a large capacitance. A thin film capacitor includes a metal foil having roughened main surfaces, a dielectric film covering the main surfaces, an electrode layer contacting the metal foil through an opening formed in the dielectric film and having a surface formed as a metal terminal, an electrode layer contacting the dielectric film without contacting the metal foil and having a surface formed as a metal terminal, and an electrode layer contacting the dielectric film without contacting the metal foil. The electrode layers include a conductive polymer layer contacting the dielectric film.

A thermal conductivity sensor for measuring a concentration of a gas, the sensor comprising: a substrate portion; a dielectric layer comprising a dielectric membrane, wherein the dielectric membrane is provided with a heater; a first gap between the substrate portion and the dielectric membrane wherein the primary dielectric membrane is located above the first primary gap; and a micro-machined cap layer; a second gap located between the cap layer and the dielectric membrane. A method of manufacturing a thermal conductivity sensor is also described.

The present disclosure relates to an apparatus for collecting reaction by-products for semiconductor processes through pyrolysis in a high-temperature region and an oxidation reaction in a low-temperature region, and an object of the present disclosure is to provide an apparatus for collecting reaction by-products, which is capable of collecting powdered oxides grown from High K materials by inducing an oxidation reaction in a box-shaped collection part having a low-temperature region formed by a cooling pad part after thermally decomposing the High K material at a high temperature of a heater in an inlet port of the collection apparatus when High K deposition precursors, which are supplied to a process chamber for an oxidation process for depositing a semiconductor dielectric film with the High K material having high permittivity in order to miniaturize a semiconductor circuit, are discharged together with exhaust gas.

An acoustic wave device includes a piezoelectric layer including lithium tantalate or lithium niobate, a dielectric film on the piezoelectric layer, the dielectric film including a dielectric material having a higher dielectric constant than that of the lithium tantalate or lithium niobate, and an IDT electrode on the dielectric film.

A thermal conductivity sensor for measuring a concentration of a gas, the sensor comprising: a substrate portion; a dielectric layer comprising a dielectric membrane, wherein the dielectric membrane is provided with a heater; a first gap between the substrate portion and the dielectric membrane wherein the primary dielectric membrane is located above the first primary gap; and a micro-machined cap layer; a second gap located between the cap layer and the dielectric membrane. A method of manufacturing a thermal conductivity sensor is also described.

A trench capacitor manufacturing method is provided. The method includes forming a deep trench in a wafer, forming a trench capacitor structure including a plurality of dielectric films and a plurality of conductive layers in the deep trench; determining if the wafer has a tensile stress based on the forming of the trench capacitor structure; performing a high temperature heat treatment to the trench capacitor structure to change a form of the wafer to a direction that offsets the tensile stress; forming an inter-layer insulating film on the trench capacitor structure; and forming a metal interconnect on the inter-layer insulating film.

To provide a thin film capacitor in which warpage is less likely to occur. A thin film capacitor includes: a metal foil having roughened upper and lower surfaces; a dielectric film covering the upper surface of the metal foil and having an opening through which the metal foil is partly exposed; a dielectric film covering the lower surface of the metal foil and made of a dielectric material having a thermal expansion coefficient smaller than that of the metal foil; a first electrode layer contacting the metal foil through the opening; and a second electrode layer contacting the first dielectric film without contacting the metal foil. The lower surface of the metal foil is thus covered with the dielectric film having a small thermal expansion coefficient, thereby making it possible to prevent the occurrence of warpage.

A film capacitor includes a stack including at least one dielectric film and a plurality of metal films, the at least one dielectric film including a polyarylate film, wherein each of the at least one of dielectric film and each of the plurality of metal films are alternately stacked in a stacking direction, each of the plurality of metal films deposited on each of the at least one dielectric film by vapor deposition, cover films on two first side surfaces, the two first side surfaces facing each other in a first direction, the first direction orthogonal to the stacking direction, the cover films containing a polyester hot-melt resin, and metal-sprayed electrodes on two second side surfaces, the two second side surfaces facing each other in a second direction, the second direction perpendicular to the first direction and orthogonal to the stacking direction.

A thermal conductivity sensor for measuring a concentration of a gas comprises: a substrate portion; an intermediate layer disposed on the substrate portion; a semiconductor layer disposed on the intermediate layer; and a dielectric layer comprising a dielectric membrane, the dielectric membrane provided with a heater; wherein the dielectric membrane is located over a gap, the gap being located in the semiconductor layer. Methods for manufacturing a thermal conductivity sensor are also described.

An acoustic wave device includes a support substrate, a piezoelectric layer on the support substrate, a functional electrode on the piezoelectric layer, first and second electrode films on the piezoelectric layer, facing each other, and having different electric potentials from each other, and a dielectric film between at least one of at least a portion of the first electrode film and the piezoelectric layer and at least a portion of the second electrode film and the piezoelectric layer.

A structure for semiconductor devices having a high-dielectric constant dielectric film on the top surface can be used to form devices that are composed of hybrid bonded structures with reduced dielectric surface area and reduced pitch for metal studs. The dielectric constant of the dielectric film can be about or greater than 8. A device can be formed by hybrid bonding the dielectric film of the structure to a dielectric film of a similar structure. A technique for forming the structure can include selectively depositing the dielectric film via atomic layer deposition after features filled with metal in a top layer of oxide in an oxide-metal-substrate stack. In order to selectively deposit the dielectric film, the metal may be covered with a polymer which can be burned off. A chemical-mechanical polishing technique can be used to precisely form the surface of the structure in preparation for hybrid bonding.

A semiconductor structure including a dielectric film wherein stress has been inducted into one or more stressed portions of the dielectric film to create one or more stress zones. The stress zones correspond to locations of warpage in the semiconductor structure and reduce warpage. In some examples, the stress zones can be created by exposing portions of the dielectric film to different amounts of heat. In some examples, the stress zones can be created by one or more recesses in the dielectric film.

Methods of manufacturing memory devices are provided. The methods improve the quality of a selectively deposited silicon-containing dielectric layer. The method comprises selectively depositing a silicon-containing dielectric layer in a recessed region of a film stack. The selectively deposited silicon-containing dielectric layer is then exposed to a high-density plasma and annealed at a temperature greater than 800° C. to provide a silicon-containing dielectric film having a wet etch rate of less than 4 Å / min.

The present disclosure provides a semiconductor device and a method of forming the same. A method according one embodiment of the present disclosure include bonding a first semiconductor substrate having (110) orientation on a second semiconductor substate having (100) orientation, forming a stack over the first semiconductor substrate, the stack comprising a plurality of channel layers interleaved by a plurality of sacrificial layers, patterning the stack to form a fin-shape structure, the fin-shape structure comprising a channel region and a source / drain region, recessing the source / drain region to form a source / drain trench, forming a dielectric film in the source / drain trench, and epitaxially growing an epitaxial feature over the dielectric film, the epitaxial feature being in contact with the plurality of channel layers. The epitaxial feature has (110) orientation.

A semiconductor device includes an upper conductive line extending in a first horizontal direction over a substrate, a channel layer facing the upper conductive line in a second horizontal direction that is perpendicular to the first horizontal direction, a gate dielectric film between the channel layer and the upper conductive line, a conductive contact pattern including a lower surface, which is in contact with an upper surface of the channel layer, and sidewalls including a first sidewall, which faces the upper conductive line in the second horizontal direction, and an insulating spacer including a first portion between the upper conductive line and the conductive contact pattern in the second horizontal direction.

A capacitor that includes a substrate having a surface; a lower electrode opposing the surface of the substrate; a dielectric film on the lower electrode; an upper electrode on the dielectric film; a protective layer on the lower electrode, the dielectric film, and the upper electrode, the protective layer defining a through-hole exposing at least one of the lower electrode and the upper electrode; at least one protrusion in the through-hole; and an outer electrode covering the through-hole and the at least one protrusion.

Disclosed are a three-dimensional memory array and a method for manufacturing the same. More specifically, a three-dimensional memory array including isolated insulating layers and memory cell layers alternately stacked in a vertical direction and individually constructing a transistor and a capacitor includes the transistor in which a channel, and a source and a drain are respectively made of semiconductor materials with different doping concentrations, and / or the capacitor including a capacitor dielectric film with an increased opposing area size.

A structure for semiconductor devices having a high-dielectric constant dielectric film on the top surface of the structure can be used to form semiconductor devices that are composed of hybrid bonded structures with reduced dielectric surface area and reduced pitch for metal studs. For example, the dielectric constant of the dielectric film can be about or greater than 7 or 8. A semiconductor device can be formed by hybrid bonding the dielectric film of the structure to a dielectric film of a similar structure. A dielectric film-oxide-metal-substrate structure can be formed with the dielectric film on the top surface of the stack. A multi-material etch can be used etch features in the dielectric film and the oxide in a dielectric film-oxide-metal-substrate stack. A chemical-mechanical polishing technique can be used to precisely form the surface of the structure in preparation for hybrid bonding.

A plasma processing apparatus including a processing chamber and a cylindrical sample stage disposed within the processing chamber and having an upper surface on which the wafer is placed, the sample stage including a disc-like substrate; a dielectric film covering an upper surface of the substrate; and a heater layer disposed inside the dielectric film. The heater layer includes a plurality of film heaters disposed in a plurality of rectangular regions each disposed with one side of the rectangular shapes facing to adjacent regions. A cylindrical power supply connector detachable from a bottom of the substrate is configured to be electrically connected to each of the plurality of film heaters, and a wiring component includes a plurality of lines and is made of a resin-made plate-like component connected to a bottom of the power supply connector, and has an arm part extending along a bottom surface of the substrate.

The invention provides a post-processing method for the efficiency of a battery piece, and the method comprises the steps: selecting to apply a corresponding bias voltage to a substrate of the battery piece according to the electrical property of charges needing to be injected into a dielectric film of the battery piece; irradiating the dielectric film with laser, and injecting required charges into the dielectric film; and carrying out charge fixation. According to the method, effective passivation of the surface of the battery piece can be achieved, the method is simple and rapid, the charge polarity and the charge concentration can be flexibly adjusted, and the conversion efficiency of the battery piece can be remarkably improved.

The invention discloses a coplanar parallel capacitance-piezoelectric multi-mode tactile sensor and a preparation method thereof. The coplanar parallel capacitance-piezoelectric multi-mode tactile sensor comprises a substrate, a lower electrode, a middle functional layer, an upper electrode and a packaging protection layer which are sequentially arranged from bottom to top, the middle functional layer is a high-molecular polyvinylidene fluoride (PVDF) polymer film layer; the middle functional layer is divided into a capacitance functional area and a piezoelectric functional area which are coplanar and parallel, the piezoelectric functional area is located in the middle area of the polymer film layer, and the capacitance functional area surrounds the periphery of the piezoelectric functional area; the packaging protection layer is arranged at the top of the upper electrode; different functional areas of a capacitance functional area and a piezoelectric functional area are arranged on the same film layer surface, so that a capacitance dielectric film layer and a piezoelectric functional film layer are designed to be the same film layer, in combination with an in-situ plasma polarization process, directional high-voltage polarization processing is carried out on film surfaces of different areas of the same film layer, the overall thickness of the sensor after packaging can be effectively reduced, and the packaging cost is reduced. The sensor precision is improved.

Provided is a synaptic device including a substrate, a channel layer on the substrate, a gate dielectric layer on the channel layer; and a gate electrode on the gate dielectric layer, wherein the gate dielectric layer includes a charge supply dielectric film and a piezoelectric film, wherein the charge supply dielectric film includes a metal oxide or metal sulfide, wherein the piezoelectric film includes a piezoelectric material that converts a pressure stimulation into an electrical signal, wherein accordance to a change in a signal applied to the gate electrode, a magnitude and aspect of a current flowing through the channel layer are changed.

The present application provides a mutually matched dual-chamber system for preparing a high-k dielectric film, comprising: a first chamber, a second chamber, an inner chamber total air inlet pipe, an inner chamber total air outlet pipe, an outer chamber total air inlet pipe and an outer chamber total air outlet pipe, wherein the first chamber and the second chamber are used to process different substrates at the same time. The dual-chamber system of the present application comprises a first chamber and a second chamber with a consistent structure, and the reaction chamber of the first chamber and the reaction chamber of the second chamber share an air inlet and outlet pipe, and the transmission chamber of the first chamber and the transmission chamber of the second chamber also share an air inlet and outlet pipe, so that the two chambers match in structure and air inlet and outlet, so that the process performance of the two chambers matches, and can be used to simultaneously process and obtain two substrates with consistent performance, thereby improving production and yield.

Disclosed are a method of forming an oxide film including at least two non-oxygen elements, a method of manufacturing a semiconductor device, a method of forming a dielectric film, and a semiconductor device. The method of forming an oxide film including at least two non-oxygen elements includes providing a first source material on a substrate, the first source material including a first central element; providing an electron donor compound to combine with the first source material; providing a second source material on the substrate after providing the electron donor compound, the second source material including a second central element; and providing an oxidizing agent on the substrate.

A semiconductor device includes a first dielectric film, a resistor element disposed on the first dielectric film, and a second dielectric film disposed on the resistor element. The resistor element contains silicon, chromium, and carbon. The silicon concentration in the resistor element increases from a center part of the resistor element towards an upper surface of the resistor element, and also increases from the center part of the resistor element towards a lower surface of the resistor element.