4667 results about "Silicon chip" patented technology

The invention relates to a polishing process for improving local flatness of a silicon wafer, which belongs to the technical field of semiconductor manufacturing, and comprises the following operation steps of: 1, pretreating the silicon wafer, cleaning the silicon wafer, activating the surface of the silicon wafer, removing surface impurities and an oxide layer, and preparing for subsequent polishing; secondly, partition parameter setting is conducted, the wafer is scanned, the surface of the wafer is divided into a plurality of different areas, and independent polishing parameters are set for each area according to the material characteristics, the thickness and the preset flatness target of each area; and thirdly, dynamic polishing is conducted, specifically, multi-axis linkage polishing equipment is adopted, and the movement tracks and working parameters of the polishing head in different areas are dynamically adjusted in real time according to preset partition parameters. Through silicon wafer pretreatment, partition parameter setting and dynamic polishing process monitoring and feedback adjustment mechanisms, polishing process parameters can be accurately controlled, deviation in the polishing process can be corrected in time, and stability and consistency of polishing quality are ensured.

The invention provides a method for detecting silicon single crystal COP free area distribution, and relates to the technical field of silicon single crystal quality detection.The method comprises the steps that a silicon wafer to be detected is cleaned to obtain a first silicon wafer; uniformly smearing a transition metal ion solution on the surface of the first silicon wafer to obtain a second silicon wafer; placing the second silicon wafer in a high-temperature environment, and performing heat treatment under three temperature gradients to obtain a third silicon wafer; wherein in the first stage, transition metal ions are diffused to the surface layer of the silicon wafer to activate oxygen precipitates in a Pv region, in the second stage, the transition metal ions are promoted to be diffused into the silicon wafer to develop a Pi low-oxygen region, and in the third stage, nuclei coalescence in a B-band region is activated at high temperature to form a differential arrangement ring; cleaning the third silicon wafer through a mixed acid solution to obtain a fourth silicon wafer; and placing the fourth silicon wafer in a preferential corrosion liquid for preferential corrosion, and carrying out COP free area distribution detection on the obtained detection sample wafer. According to the scheme, the definition of each region boundary can be improved, so that the detection accuracy of COP free region distribution is improved.

The invention discloses a combined passivation back contact battery which comprises an N-type silicon wafer, a second intrinsic amorphous silicon layer, a microcrystalline silicon layer, an anti-reflection layer, a second semiconductor opening region, a first semiconductor opening region and a transition region, the anti-reflection layer is a single-layer amorphous silicon carbonitride layer or a laminated structure composed of an amorphous silicon carbide layer and an amorphous silicon carbonitride layer, and the second semiconductor opening area is composed of a first intrinsic amorphous silicon layer, a P-type amorphous silicon layer, a transparent conductive film and a metal electrode which are sequentially arranged on the back face of the silicon wafer. The first semiconductor opening area is composed of a tunneling oxide layer, an N-type polycrystalline silicon layer, a transparent conductive film and a metal electrode which are sequentially arranged on the back face of the silicon wafer, and an opening is etched in the transparent conductive film on the surface of the transition area to form an insulation groove. Amorphous silicon carbonitride or amorphous silicon carbide / amorphous silicon carbonitride laminated layers are adopted as the anti-reflection layers, so that reflection loss is reduced, the reliability and durability of the cell are improved, and the conversion efficiency of the cell is improved.

The invention provides a preparation method of an inertial sensor and the sensor. The preparation method comprises the following steps: sequentially forming a first cavity and a first oxide layer on a first silicon wafer; bonding the first silicon wafer and a second silicon wafer, wherein the second silicon wafer is a low-resistance silicon wafer; forming an inertia sensitive structure in the second silicon wafer; correspondingly forming a second cavity on a third silicon wafer, wherein the third silicon wafer is a low-resistance silicon wafer; bonding the third silicon wafer and the second silicon wafer; an isolation groove penetrating through the third silicon wafer is formed through etching, a conductive silicon column and an electric signal isolation ring are formed, and the conductive silicon column is connected with the inertia sensitive structure; and forming a sealing insulating layer on the surface of the third silicon wafer, and forming a signal lead-out pin in the sealing insulating layer. According to the scheme, thermal stress caused by thermal expansion coefficient mismatch among the three layers of wafers is reduced through an all-silicon wafer level packaging process, and the full-temperature characteristic of the device is greatly enhanced; and the preparation process flow is optimized, the process control difficulty is reduced, and the preparation cost is reduced.

The invention belongs to the technical field of rare and precious metal recovery, and particularly relates to a method for recovering metallic silver from waste crystalline silicon battery pieces, which comprises the following steps: (1) putting the waste crystalline silicon battery pieces into an inorganic alkali aqueous solution for soaking reaction to obtain an aluminum-containing solution and dealuminized crystalline silicon pieces; (2) adding the dealuminized crystal silicon wafer into a mixed solution of organic acid and hydrogen peroxide for soaking reaction, filtering and washing to respectively obtain silver-containing filtrate and a silver-removed silicon wafer; (3) carrying out chlorination precipitation reaction on the silver-containing filtrate and a chlorine source, filtering and drying to obtain silver chloride powder; (4) adding silver chloride powder into an ammonia water solution, heating and stirring to completely dissolve silver chloride to obtain a silver-ammonia solution; (5) adding PVP (Polyvinyl Pyrrolidone) into the silver-ammonia solution, heating and stirring until the PVP is completely dissolved, adding ascorbic acid, and carrying out reduction reaction at room temperature to obtain metal silver powder precipitate; and filtering, washing and drying the precipitate to obtain the spherical silver powder. According to the method, the silver recovery efficiency is high, the spherical nanoscale silver powder can be prepared, and the purity is high.

The CPO system packaging method provided by the embodiment of the invention comprises the following steps: by taking a high-resistance silicon wafer as a base material, completing processing of a silicon intermediate layer through spiral micro-channel etching, silicon through hole preparation, electroplating hole filling and back thinning; integrating the silicon optical chip and the electronic chip to the silicon interposer through the diamond micro bump array containing the copper core; installing a piezoelectric micropump at a corresponding fluid interface in the silicon intermediate layer, and filling adaptive liquid into the communicated flow channels in a vacuum environment; and after the reliability verification test is passed, carrying out system packaging by adopting an anti-static shielding bag. The CPO system adopting the packaging process has the advantages of high heat dissipation efficiency, ultrahigh integration precision and strong environmental adaptability.

The invention discloses a photoresist micro-lens array preparation method and system, and relates to the field of micro-nano optical device manufacturing. The preparation method of the photoresist micro-lens array comprises the following steps: carrying out chemical mechanical polishing treatment on a silicon wafer, spin-coating photoresist on a substrate to form a cylindrical array, and eliminating solvent gradient through pre-drying; forming a fluorocarbon nano film on the surface of the photoresist through plasma deposition so as to reduce the surface energy of the photoresist; realizing hot reflux of the photoresist based on gradient annealing, wherein the gradient annealing comprises a preheating section, a main reflux section and a stable section; on the basis of the preheating section, glass transition stress is avoided, fluorine-containing gas and inert gas are synchronously introduced into the main backflow section to act on a plasma sheath layer, so that the flowing direction of photoresist is regulated and controlled, and the edge coffee ring effect is inhibited; the stable section synchronously performs plasma assistance to lock the shape; and the precision and the consistency of the micro-lens array are improved through segmented temperature regulation and control and a plasma auxiliary technology.

The invention discloses a low-warpage damp-heat-resistant liquid epoxy molding compound as well as a preparation method and application thereof. The liquid epoxy molding compound is prepared from the following raw material components in parts by mass: 85 to 90 parts of modified silicon dioxide, 5 to 8 parts of naphthalene type epoxy resin monomer, 5 to 8 parts of anhydride curing agent, 0.1 to 0.3 part of coupling agent, 0.1 to 0.3 part of adhesion promoter and 0.2 to 0.5 part of temperature response type amine catalyst. The modified silicon dioxide is obtained by carrying out surface modification on micron-sized silicon dioxide by adopting a silane coupling agent containing an epoxy group, and the mass of the silane coupling agent containing the epoxy group is 0.3-0.8% of the mass of silicon dioxide. The liquid epoxy molding compound provided by the invention has excellent flowability, adhesive force and heat and humidity resistance, can significantly relieve and reduce the warping of a silicon wafer, and is suitable for integrated circuit packaging.

The invention relates to a photovoltaic monocrystalline silicon material resistivity uniformity evaluation method, and belongs to the technical field of photovoltaic material detection. The method comprises the following steps: evaluating all-form resistivity and doping uniformity of a photovoltaic single crystal silicon rod, a single crystal silicon wafer and a single crystal silicon square wafer; carrying out standardized point distribution on the monocrystalline silicon wafer by using a concentric circular ring and a small circle, and calculating in-plane uniformity by using a triple integral derivation equation; the monocrystalline silicon square pieces are distributed in the form of grid small squares, and in-plane uniformity is calculated by means of a triple integral derivation equation; and for the axial direction of the silicon rod, the uniformity is quantified by utilizing range and variance models through the resistivity of the head, middle and tail wafers. Meanwhile, a continuous grid is generated through interpolation, and a 3D color mapping curved surface diagram with plane projection is drawn to visually present distribution. According to axial and in-plane uniformity results, silicon wafers are classified and graded, the doping uniformity of monocrystalline silicon is accurately reflected, and a support is provided for quality control, process optimization and silicon wafer sorting of photovoltaic monocrystalline silicon.

A back-contact solar cell, a battery assembly and a photovoltaic system. In the back-contact solar cell, several grooves arranged at intervals are formed in a back surface of a silicon wafer, so as to divide the back surface of the silicon wafer into several first regions and second regions that are alternately arranged in sequence, in an arrangement direction of the first regions and the second regions, the silicon wafer is provided on the first regions and the edges of the grooves with extension portions that extrude to the upper side of the grooves, and second polarity doping layers are disposed on second tunneling layers in a stacked manner and have a preset distance with the edges of the grooves.

The invention discloses a full-opening solar cell printing plate, and belongs to the technical field of solar cell printing. The full-opening solar cell printing plate comprises a frame, an annular auxiliary material piece and a graphical steel plate, the graphical steel plate is arranged on the annular auxiliary material piece, an avoiding area is larger than a graphical area of the graphical steel plate, the graphical steel plate comprises a buffer metal layer and a first metal layer, the graphical area of the buffer metal layer is provided with a plurality of first grid line holes, and the first grid line holes are communicated with the annular auxiliary material piece. A plurality of second grid line holes are formed in the pattern area of the first metal layer, at least one buffer metal layer is arranged on the pasting and printing face of the first metal layer, the first grid line holes are communicated with the corresponding second grid line holes, and the hardness of the buffer metal layer is smaller than that of the silicon wafer. According to the method, the surface of the steel plate can be matched with the uneven surface of the silicon wafer in the printing process, consumption of printing silver paste is saved, stable batch production is facilitated, and the electrical performance of a battery piece is improved.

The invention discloses a photovoltaic TOPCon battery piece etching device, relates to the technical field of silicon piece etching, and aims to solve the technical problems that corrosives generated in the etching process easily pollute a chemical solution, so that the service life of the chemical solution is shortened, and the etching uniformity is reduced. The photovoltaic TOPCon battery piece etching device comprises a workbench, and an etching groove, a cleaning groove and a supporting frame are arranged at the top of the workbench; a movable frame is arranged on the supporting frame in a sliding mode, a movable unit is arranged in the movable frame, the movable end of the movable unit is connected with a lifting frame, an etching cover assembly and a silicon wafer frame assembly are arranged below the lifting frame, the silicon wafer frame assembly is movably arranged in the etching cover assembly, the etching cover assembly comprises a cover body frame, and a micropore filter screen is arranged at the bottom of the cover body frame. A plurality of baffles are movably arranged on the side wall of the cover body frame. The chemical solution in the etching tank can be kept pure, and the service life of the chemical solution is prolonged.

The invention provides a cutting height adjusting method and device of a cutting knife, wafer processing equipment and a medium, and relates to the technical field of wafer processing equipment.The method comprises the steps that the surface height difference between a sample silicon wafer on an auxiliary workbench and a to-be-processed wafer on a main working disc is measured; after the cutting knife cuts the sample silicon wafer to form a cutting mark, calculating a cutting depth value corresponding to the cutting mark; calculating the surface height information of the sample silicon wafer according to the cutting depth value of the cutting mark and the height information corresponding to the lowest point of the cutting knife when the cutting knife cuts the sample silicon wafer on the auxiliary workbench; and according to a preset cutting depth value, the surface height information of the sample silicon wafer and the surface height difference between the sample silicon wafer on the auxiliary workbench and the to-be-processed wafer, target cutting height information of the cutting knife when the cutting knife cuts the to-be-processed wafer is determined. After the height of the cutting knife is adjusted according to the target cutting height information, the cutting mark cut by the cutting knife has high-precision cutting depth.

The invention provides a waste photovoltaic module high-value recovery process based on pyrolysis and wet purification, which comprises the following steps: carrying out pyrolysis decarburization on a waste photovoltaic module to obtain a glass plate, a crystalline silicon battery piece and a copper-tin soldering strip; the method comprises the following steps of: performing alkaline leaching on a crystal silicon cell to obtain a dealuminized crystal silicon wafer, performing acid pickling on the dealuminized crystal silicon wafer to obtain a silver-removed crystal silicon wafer and a silver leaching solution, and extracting a silver elementary substance from the silver leaching solution; removing impurities from the silver-removed crystal silicon wafer through a hydrofluoric acid solution to obtain a high-purity crystal silicon wafer; recovering a copper strip from the copper-tin soldering strip through a high-temperature smelting reduction method; after fluorine-containing pyrolysis gas generated in the pyrolysis process is subjected to combustion and heat exchange, hydrogen fluoride is removed in a two-stage alkali liquor absorption mode, then washing is conducted, and finally obtained flue gas is discharged. According to the wet purification process, the waste crystalline silicon battery piece can be subjected to high-purity recovery, and the crystalline silicon piece, silver and copper with high purity can be obtained. The hydrogen fluoride is removed by adopting a two-stage alkali liquor absorption method, so that the treatment efficiency of the hydrogen fluoride in the pyrolysis gas is improved.

The invention discloses a silicon / graphite / carbon-aluminum oxide composite negative electrode material and a green preparation method thereof, and belongs to the technical field of lithium ion batteries. Aiming at the problems of high volume expansion rate and poor cycling stability of a silicon-based negative electrode and high cost of a traditional process, the invention innovatively provides the following scheme: 1) waste photovoltaic silicon wafer ball-milling liquid and waste graphite are taken as core raw materials, and resource recycling is realized; (2) phenolic resin and chitosan are adopted as double carbon sources, a nitrogen-doped carbon layer (the nitrogen content is 3-5 wt.%) is formed through pH-induced self-assembly, and the conductivity and the Li < + > diffusion rate are synchronously improved; and 3) aluminum nitrate is introduced for pyrolysis to generate 2-5nm aluminum oxide for doping, so that the side reaction of the electrolyte is inhibited, and the volume expansion of silicon is relieved (the expansion rate is less than or equal to 120%). The preparation process comprises the steps of silicon / graphite dispersion, double-carbon-source compounding, ammonia water regulation and control precipitation and gradient calcination. Experiments show that the specific capacity of the optimized material under the current of 0.5 A / g reaches more than 800mAh / g, the 100-time cycle capacity retention ratio is more than 98%, the 1000-time cycle capacity retention ratio is more than 80%, the reversible specific capacity under the multiplying power of 3A / g is more than 550mAh / g, and the raw material cost is reduced by 40%. The invention has the advantages of high capacity, long service life, environmental protection and economy, and provides an innovative solution for the fields of power batteries and energy storage.

The invention relates to a preparation method of a silicon single crystal rod and a silicon wafer. Comprising a melting stage, a temperature adjusting stage, a welding stage, a seeding stage, a shouldering stage, an equal-diameter stage, an ending stage and a breaking stage which are carried out in sequence, in the equal-diameter stage, the pulling speed is controlled to be within a first pulling speed range, and the solid-liquid interface temperature gradient is controlled to be within a first gradient range; wherein the range of the first pulling speed ranges from 0.5 mm / min to 1.1 mm / min; the first gradient range is 3 DEG C / cm to 5 DEG C / cm. By reducing the temperature gradient of a solid-liquid interface and lowering the crystal pulling rate, the stability of a thermal field is enhanced, and sufficient conditions are provided for the composite reaction of Sii and V, so that the impurity capturing efficiency is improved, the internal purity of the crystal is improved, and the impurities are effectively removed.

The invention belongs to the technical field of back contact cell preparation, and particularly relates to a back contact cell of an opening semiconductor without etching and a preparation method thereof, and the method comprises the steps: S103, carrying out the polishing or texturing of the back surface of a silicon wafer obtained in S102; s104, depositing an intrinsic crystalline silicon layer on the back surface of the silicon wafer; s105, the non-target deposition area is masked through a hard mask plate, and N-type crystalline silicon layers which are alternately arranged are deposited on the back face; replacing the mask of the hard mask plate to form a P-type crystalline silicon layer and an overlapping region; s106, depositing a conductive film layer on the back surface of the silicon wafer; s107, an opening is formed in the conductive film layer to form an isolation groove, and the width W4 of the isolation groove is controlled to range from 0.03 mm to 0.15 mm; and S108, forming a metal electrode on the back surface. According to the invention, the back semiconductor does not need to be opened by etching, the technological process is greatly simplified, etching damage is avoided, and the cell conversion efficiency, the cell stability and the production yield are improved.

The invention belongs to the technical field of back contact cells, and particularly relates to a back contact cell manufacturing method for improving passivation performance and a back contact cell thereof, and the method comprises the steps: S2, depositing a first semiconductor layer and a phosphorosilicate glass layer on the back surface of a silicon wafer, and reserving the first semiconductor layer and the phosphorosilicate glass layer as a first mask layer; s3, performing texturing cleaning on the front surface of the silicon wafer; the first mask layer is removed in the final cleaning process after texturing; s4, forming a passivation layer and an anti-reflection layer on the front surface of the silicon wafer; s5, coating the back surface to form a second mask layer; s6, forming a second semiconductor opening region; and S7, texturing or polishing the second semiconductor opening area on the back surface, and cleaning by using an HF solution with the mass concentration of 0.5%-5% to remove the second mask layer and the winding plating layer generated in the front surface coating process in the S4. The back surface winding plating layer does not need to be removed, damage to the first semiconductor layer and the front surface film layer can be avoided, the overall passivation level can be improved, and therefore the battery efficiency is improved.

The invention discloses a rotary carrying working platform for a hold-down tool of a battery piece, relates to the technical field of carrying working platforms, and solves the problem of low efficiency of rotary carrying operation of the battery piece. And meanwhile, the problems that the precision is low and wrong welding is easy to occur when the battery piece hold-down clamp and the silicon wafer are subjected to series welding are solved. The invention discloses a rotary carrying working platform for a hold-down clamp of a battery piece. The rotary carrying working platform comprises an equipment substrate, the lifting conveying assemblies are mounted on the two sides of the top of the equipment base plate; the rotary carrying platform structure is mounted in the center of the top of the equipment base plate and located between the two lifting conveying assemblies; and the suction pressure clamp is magnetically fixed at the top of the lifting conveying assembly. According to the invention, the efficiency can be doubled, meanwhile, the position correction operation can be automatically carried out on the battery piece hold-down tool and the silicon wafer structure, the accuracy of series welding of the battery piece hold-down tool and the silicon wafer is ensured, and the problem that the quality of the battery piece is influenced by wrong welding and the like is avoided.

The invention provides a model training method, a silicon wafer processing method, a silicon wafer processing device, a storage medium and equipment. The model training method comprises the following steps: acquiring initial state information and target state information of a silicon wafer to be processed; through an action decision model, according to the initial state information and the target state information, machining action information for the machining machine table is generated; determining an award parameter corresponding to the processing action information, wherein the award parameter represents the processing quality and efficiency when the processing machine processes the to-be-processed silicon wafer based on the processing action information; if the reward parameter is not more than the preset condition, updating the initial action decision model according to the reward parameter to obtain an updated action decision model; and based on the updated action decision model, returning to execute the step of generating the processing action information through the action decision model according to the initial state information and the target state information until the reward parameter is greater than the preset condition, and obtaining a target action decision model. According to the invention, the processing machine table can be accurately adjusted.

A silicon wafer drying improvement method and apparatus based on a D-LKA network model. The method comprises: acquiring image data of a dried silicon wafer and drying parameter data; using a D-LKA network model to preprocess the image data so as to extract water marks and other non-compliance features on the surface of the silicon wafer; using the D-LKA network model to perform feature learning on the preprocessed image data; determining whether the features of the surface state of the silicon wafer satisfy a condition; and acquiring control parameters of a corresponding silicon wafer drying process on the basis of different features of the surface state of the silicon wafer, and when the silicon wafer needs to be re-dried, invoking corresponding drying parameters by means of the D-LKA network model on the basis of the features of the surface of the silicon wafer, optimizing the drying parameters and transmitting the optimized drying parameters to a circulating hot air system, and drying the silicon wafer again. The D-LKA network model is applied to the silicon wafer drying process, so that unmanned silicon wafer screening is achieved, the drying parameters are optimized, the labor and time costs are low, the silicon wafer production efficiency is high, and the quality of the silicon wafer is high.

The invention belongs to the technical field of photovoltaic cells, and particularly relates to a back contact photovoltaic cell, a back contact photovoltaic cell assembly and a preparation method, and the method comprises the steps: providing an N-type silicon wafer which is provided with a double-sided texturing structure, and the textured surface is of a pyramid structure after texturing; boron diffusion is carried out on the backlight surface of the silicon wafer to form a P + doping layer, and meanwhile, a lightly doped P-type region is formed on the illuminated surface of the silicon wafer through diffusion and dissipation; performing laser film opening on the backlight surface P + doping layer to form P region and N region structures which are distributed in a staggered manner; depositing a tunneling oxide layer and a phosphorus-doped amorphous silicon layer in the N region, and annealing the tunneling oxide layer and the phosphorus-doped amorphous silicon layer to form an N + polycrystalline silicon layer; printing etching slurry on the surface of the P region, performing etching slurry film opening, removing phosphorosilicate glass and forming an isolation gap between the P region and the N region; and the film is opened by printing etching slurry, so that the suede cannot generate thermal damage.

The invention belongs to the technical field of solar cell anti-aging, and provides an anti-attenuation film layer of a cell and a preparation method thereof.The anti-attenuation film layer comprises at least one silicon oxide layer, at least two silicon oxynitride layers, at least three silicon nitride layers, a first structural layer, at least two aluminum oxide layers and a doping layer which are sequentially arranged on the upper surface of crystalline silicon from top to bottom, the refractive index of the first structure layer is 1.8-2.1, and the refractive index of the bottommost layer of silicon nitride is 2.4-3.0. The bottommost aluminum oxide layer is subjected to dark annealing, so that the hydrogen content in aluminum oxide and the hydrogen content among three silicon nitride film layers are reduced; due to the increase of the high refractive index of the silicon nitride layer III, the parasitic absorption ratio of short-wave ultraviolet light in the film layer is increased, and the incidence amount of the ultraviolet light is reduced. According to the invention, the conduction rate of hydrogen into the silicon wafer body is reduced, the concentration content of free hydrogen at the interface is sequentially reduced, and the penetration angle of ultraviolet light is reduced, so that the ultraviolet attenuation resistance of the cell is realized.

The utility model discloses a copper-containing metal electrode solar cell and a solar cell module, and belongs to the technical field of solar cells, the copper-containing metal electrode solar cell comprises a silicon wafer, a first semiconductor layer, a second semiconductor layer, a conductive film layer, a copper-containing metal fine gate electrode and protective ink; a second semiconductor opening region is formed between the adjacent first semiconductor layers; an isolation groove is formed in the conductive film layer corresponding to the edge area of the second semiconductor opening area; the conductive film layer corresponding to each first semiconductor layer and each second semiconductor layer is provided with a copper-containing metal fine gate electrode; and the protective ink covers the copper-containing metal fine gate electrode, and / or the protective ink covers the isolation groove. According to the utility model, the long-term reliability of the module is improved, the technical requirements on packaging materials are reduced, the product cost is effectively reduced, and the application scene of packaging the copper-containing metal electrode solar cell into the module is expanded.

The invention relates to the technical field of semiconductor processing, and particularly discloses silicon wafer cleaning equipment which comprises a cleaning tank; the carrying table is arranged in the cleaning tank; the driving part is connected with the carrying platform and is used for driving the carrying platform to do reciprocating rectilinear motion in the vertical and horizontal directions; the supporting plate is arranged on the carrying table, the supporting plate is elastically connected with the carrying table, and the supporting plate and the carrying table can generate relative displacement in the horizontal direction; the cleaning box is separably arranged on the supporting plate and used for containing a plurality of silicon wafers, and liquid can pass through the four sides of the cleaning box. The silicon wafer cleaning device can drive a silicon wafer to ascend, descend and horizontally move in the cleaning tank, the contact degree between the silicon wafer and cleaning liquid is improved, and therefore the cleaning effect is improved.

The invention belongs to the field of silicon wafer edge polishing, and particularly relates to a device and a method for quickly replacing grinding drum cloth for polishing the edge of a 12-inch silicon wafer. A device lower main body is arranged below the device upper main body, the bottom end of the device lower main body is fixedly connected with the top end of the grinding drum cloth main body, and a convenient-to-replace mechanism is arranged between the device upper main body and the device lower main body; the convenient-to-replace mechanism comprises a connecting and fixing head; through the design of a mechanism convenient to replace, the function of convenient replacement is achieved, and the problems that when an existing device is used for polishing a silicon wafer, the grinding drum cloth is in contact with the silicon wafer for polishing, the grinding drum cloth is damaged after long-term use and needs to be replaced, and the polishing efficiency is high are solved. The problems that an existing device is not provided with an assembly convenient to replace, so that the difficulty is large during follow-up replacement, and operation is inconvenient are solved, and convenience is improved.

The invention provides a silicon wafer stress lossless non-contact measurement method and device, and the method comprises the steps: generating a near-infrared femtosecond pulse; the optical power of the near-infrared femtosecond pulse is sufficient to penetrate through an object to be detected for imaging; enabling the near-infrared femtosecond pulse to penetrate through the to-be-measured object, applying stress to the interior of the to-be-measured object, and receiving a light pulse signal of transmission light; analyzing and reconstructing a light pulse signal of the transmission light, and constructing an interference image sequence penetrating through the to-be-detected object; and based on the interference image sequence of the to-be-measured object, determining a principal stress difference value at each point on the to-be-measured object. According to the invention, the stress condition of each point on the to-be-detected object can be accurately detected, and the problems that fixed-point measurement is difficult to realize and the number of detection frames is low in the prior art are solved.

The invention discloses an instrument capable of being separated through light control and a preparation method and application of the instrument, and belongs to the technical field of biomedical engineering and flexible electronics. The instrument capable of being separated through light control comprises a flexible substrate layer, an electrode layer and a gel integration layer, the preparation method comprises the following steps: (1) forming an electrode pattern on a silicon wafer through photoetching, and carrying out oxygen plasma treatment to prepare a hydrophilic surface; (2) spin-coating a water-soluble polymer solution to form a sacrificial layer; (3) spin-coating silicone rubber pre-polymerized liquid and curing to form a flexible substrate layer; (4) dissolving the sacrificial layer with water to realize demolding, and embedding a patterned conductive material into the surface to form an electrode layer; and (5) coating the photo-responsive adhesive hydrogel pre-polymerization liquid, and performing cross-linking curing to form a gel integration layer, thereby obtaining the photo-responsive adhesive hydrogel. Through integrated structural design and functional material integration, the brain-computer interface ECoG electrode with high flexibility, high adhesion, high conductivity and controllable debonding capacity and the like is provided, and a technical basis and an application platform are provided for a next-generation intelligent implantable brain-computer system.

The invention provides a preparation method of a surface structure of a back contact battery, which relates to the technical field of back contact batteries, and comprises the following steps: S1, carrying out double-sided polishing on the surface of a silicon wafer: firstly carrying out rough polishing, removing a damaged layer on the surface of the silicon wafer, then cleaning with acid and ozone, then carrying out fine polishing, then cleaning with a mixed solution of hydrogen peroxide and alkali, and then carrying out acid pickling with ozone, then cleaning with a mixed solution of acid and hydrogen peroxide, and finally washing and drying; sequentially depositing a tunneling oxide layer and amorphous silicon on a single surface at high temperature; and performing high-temperature diffusion on the surface to form a crystallized first semiconductor region and a mask layer BSG. According to the invention, the specific suede structure is formed on the front surface, and the polished surface is formed on the back isolation base region, so that high reflectivity of the back isolation base region is ensured, the specific suede structure on the front surface can be independently designed, and meanwhile, a double-surface ozone oxidation process is added; therefore, the open-circuit voltage and the short-circuit current of the cell are improved, and the photoelectric conversion efficiency of the cell is improved.

The invention discloses an LTO film thickness uniformity optimization method through an APCVD method, and particularly relates to the technical field of semiconductor manufacturing, and the method comprises the following steps: S1, prefabricating a silicon wafer; s2, selecting a tungsten filament ring; s3, installing a tungsten filament ring; s4, depositing an LTO thin film; s5, measuring the thickness of the LTO thin film of the silicon wafer; and S6, confirming the service life of the tungsten filament ring. According to the LTO film thickness uniformity optimization method through the APCVD method, the silicon wafer is chamfered, stress concentration and dislocation are reduced, wafer edge breakage and inward movement of thermal stress defects are effectively prevented, a more stable substrate is provided for follow-up film deposition, a tungsten filament ring of a specific specification is selected and correctly installed, and the uniformity of the thickness of the LTO film is improved. The diffusion and transmission conditions of gas in the APCVD process can be improved, the problems of stacking faults, crystal points, self-doping and the like after epitaxy caused by non-uniform films are reduced, and the consistency and reliability of device performance are improved.