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4738 results about "Silicon chip" patented technology

Package having very thin semiconductor chip, multichip module assembled by the package, and method for manufacturing the same

A semiconductor package of this invention has an insulating substrates, wiring layers disposed on the surface of the insulating substrate, a semiconductor chip disposed in a device hole provided in the insulating substrate, inner-joint-conductors for connecting at least part of the bonding pads on the surface of the semiconductor chip to the corresponding inner-joint-conductors and connection lands connected to the wiring layers. The device hole is provided so that it goes through the center of the insulating substrate. The semiconductor chip is thinner than the insulating substrate. Then, this semiconductor chip is disposed in the device hole such that a bottom thereof is flush with a bottom plane of the insulating substrate. Further, this invention provides a MCM in which plural pieces of the thin semiconductor packages are laminated. In the MCM, the semiconductor packages are laminated such that top and bottom faces of the thin silicon chip are inverted. Predetermined connection lands are electrically connected to each other through a connecting conductor. This MCM has a high mechanical strength in its stacked structure and there is a low possibility that crack may occur in the package due to stress in the bending direction.

Biometric access control and time and attendance network including configurable system-on-chip (CSOC) processors with embedded programmable logic

A biometric access control and time and attendance system comprises an integrated network including one or more remote access devices in electronic communication with a computer database. Each remote access device comprises a silicon chip based system and preferably includes a biometric input device, a liquid crystal display (LCD), computer processing capabilities based on embedded system architecture with configurable system-on-chip (CSOC) technology, and an electrical output for controlling a door lock or the like. The use of CSOC architecture in lieu of conventional personal computer technology (e.g. mother boards, hard drives, video controllers and the like) allows for a more compact and cost efficient design. A plurality of remote access devices is configured for communication with a primary computer database wherein data corresponding to biometric samples for all authorized users is stored. In an embodiment wherein the biometric input devices comprise fingerprint scanners, the devices are configured to facilitate fingerprint identification by incorporating an auto-targeting capability that enables the user to simply place his or her finger on the fingerprint scanner whereafter the system adjusts the scanned image by automatically shifting the scanned image data to a properly targeted position thereby enabling the system compare the scanned print to the biometric samples in the system's data storage memory. Auto-targeting capability eliminates the requirement for manual targeting present in systems of the background art thereby improving system performance and minimizing reliance on human interaction. The present invention contemplates the use of auto-targeting with other biometric systems, such as facial recognition and/or retinal scanning systems, or any other biometric identification technology.

Method for preparing super-hydrophobic antireflex micron and nano composite structure surface

The invention belongs to the technical field of preparing the surface of a composite structure, and in particular relates to a method for preparing super-hydrophobic antireflective silicon surface with a micron and nanometer composite structure. The method comprises the following steps: cleaning a silicon chip; preparing a micron-level silicon island and a gridding structure on the surface of the silicon chip; carrying out catalytic etching taking silver or aurum nanoparticles as blockage; obtaining the surface of the micron and nanometer composite structure; and carrying out chemical modification of the surface of the composite structure. A static contact angle between the super-hydrophobic antireflective material surface prepared by the method and water is more than 150 degrees, and a static rolling angle of water is less than 3 degrees. The surface has superior antireflective performance, and in particular, the light reflectivity within the wavelength range between 800 and 1,100 nm is less than 3 percent. With application of the method, the super-hydrophobic antireflective silicon surface of the micron and nanometer composite structure can be produced on scale, can be widely applied to a solar cell, a microfluidic chip, a photoelectric device, and the like, and has good industrial application prospect.

Integrated silicon chip for testing acceleration, pressure and temperature, and manufacturing method thereof

The invention relates to an integrated silicon chip for testing acceleration, pressure and temperature, and the manufacturing method thereof. The invention is characterized in manufacturing the pressure sensor, temperature sensor and accelerometers of thermoelectric pile on to one chip by the same micro processing technology. The acceleration is detected by adopting thermal convection type accelerometers, using polysilicon resistor as heater, using a thermoelectric pile composed of two pairs of metals (such as aluminium and tungsten-titanium) and P type or N type polysilicon to detect the temperature difference in the sealed cavity caused by acceleration. The high accurate absolute pressure sensor is manufactured by using silicon nitride film with low stress as the core structure layer of the pressure sensor chip, and forming force sensitive resistor track by polysilicon film, forming vacuum reference cavity by TEOS bolt in LPCVD furnace. At the same time, the temperature sensor is composed by using polysilicon thermistor to detect temperature change. The integrated chip achieves the advantages of microminiaturization, low cost, high precision, high reliability and high stability.

Producing method of selective emitter double-faced PERC crystalline silicon solar cell

The invention relates to a producing method of a selective emitter double-faced PERC crystalline silicon solar cell. The producing method is characterized by comprising the first step of removing affected layers of a silicon chip and conducting texturization and cleansing on the silicon chip, the second step of conducting diffusion to form a pn junction and eliminating phosphorosilicate glass in positive side of the silicon chip and the pn junction in the reverse side of the silicon chip after the diffusion; the third step of conducting deposition of aluminum oxide/silicon nitride laminated passivated film on the reverse side of the silicon chip and conducting deposition of a silicon nitride antireflection film on the positive side of the silicon chip; the fourth step of using an optical maser to conduct routing on the reverse side of the silicon chip to obtain a routing slot; the fifth step of using a phosphorous source to coat the positive side of the silicon chip; the six step of conducting laser doping on the positive side of the silicon chip to obtain a main guard line and a subsidiary guard line doped with the laser; the seventh step of conducting photoinduction on electronickelling/copper/silver electrode, conducting connections between the reverse side of the cell with a cathode of an external power supply, conducting electroplating on the positive and reverse sides of the cell simultaneously, and conducting electroplating of three metals of nickel/copper/silver in sequence; the eighth step of conducting annealing on the electroplated cell. According to the producing method of the selective emitter double-faced PERC crystalline silicon solar cell, the problem that an aluminum grid line is hard to be aligned with a laser windowing grid when a silk screen is used to conduct reverse printing of the double-faced PERC cell is solved.

Quasi-one-dimensional metal oxide nano-material biosensor and method for manufacturing same

The invention relates to a quasi-one-dimensional metal oxide nano-material biosensor and a method for manufacturing the same. The sensor comprises a silicon chip, a silicon dioxide oxidation layer grown on the silicon chip, a grid electrode, a source electrode, a drain electrode and a microfluid channel; and a quasi-one-dimensional metal oxide semiconductor nano-material is connected with the source electrode and the drain electrode to form a conduction channel. A process for the quasi-one-dimensional metal oxide nano-material biosensor comprises the following steps: firstly, synthesizing thequasi-one-dimensional metal oxide semiconductor nano-material; secondly, adopting a micro-nanometer photolithography standard process and a top-down method to manufacture the quasi-one-dimensional metal oxide semiconductor nano-material and a field effect transistor in array; thirdly, using polydimethylsiloxane to manufacture the microfluid channel; finally, performing surface modification on thequasi-one-dimensional metal oxide semiconductor nano-material, modifying a joining unilayer combined with a target molecule through a self-assembling method, and connecting biological molecules on the surface of the nano-material through joining molecules so as to detect a symbolic molecule of a disease. The quasi-one-dimensional metal oxide nano-material biosensor has the characteristics of rapid response, high sensitivity, strong selectivity, no labeled molecule and the like.

Flip-chip integrated encapsulation structure of LED and method thereof

The invention provides a novel light emitting diode (LED) encapsulation structure which directly adopts a silicon dice substrate as both a surface mounting bracket and a radiation channel of an integrated structure support of an LED chip; a front electrode connecting layer is arranged on the front surface of the silicon dice substrate; the front electrode connecting layer on the front surface of the silicon dice substrate is connected with an electrode metal bonding pad at the back of the silicon dice substrate through a lead of a silicon groove side-wall or a lead of a through-hole of the silicon dice substrate; and at least one LED chip is welded directly by flip-chip on the front electrode connecting layer of the silicon dice substrate with an optical source through a metal bump. The invention also provides a method for manufacturing the LED encapsulation structure. The invention avoids steps of die bonding and gold-wire welding and enhances the connection reliability of chips and especially the connection reliability of multi-chip modules; and the invention leads the encapsulation of high-power LED and especially the encapsulation of multi-chip module to be miniaturized and also leads power-supply drive and circuits of LED protection and the like to be integrated on the silicon dice so as to provide a systematic and integrated encapsulation proposal for high-power LED illumination.

Deep silicon etching method

ActiveCN101962773AImprove the selection ratioFast etch rateSemiconductor/solid-state device manufacturingPulse power supplySilicon chip
The invention provides a deep silicon etching method. The method comprises a step of etching a silicon chip surface which is not covered by a photoresist layer first to form an etched surface and a side wall which is vertical to the etched surface basically; and the method also comprises the following steps of: a first depositing step, namely performing isotropic deposition for covering a barrierlayer on the etched surface, the side wall and the surface of the photoresist layer; a first etching step, namely performing anisotropic etching for removing the barrier layer covered on the etched surface so as to expose the etched surface, wherein the photoresist layer is prevented from being etched by the barrier layer covered on the photoresist layer; a second etching step, namely performing the isotropic etching for etching the exposed etched surface, wherein the side wall is prevented from being etched by the barrier layer covered on the side wall and the photoresist layer is not damaged in the isotropic etching; and repeating the depositing step, the first etching step and the second etching step circularly until reaching a predetermined etching depth. The method does not need complex equipment such as a low-frequency pulse power supply and the like, contributes to maintenance, and reduces equipment cost.
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