7561 results about "Silicon chip" patented technology

The present disclosure relates to the technical field of back contact solar cells, and in particular relates to a combined passivation back contact solar cell having front wide band gap doping, and a preparation method therefor. The solar cell comprises a silicon wafer, and a first semiconductor layer, a second semiconductor layer and a third semiconductor layer arranged on the front face of the silicon wafer. The third semiconductor layer comprises a second tunneling oxide layer and a third doped polycrystalline silicon layer, provided in sequence from inside to outside. The third doped polycrystalline silicon layer is a doped polycrystalline silicon layer containing a first doping element and a second doping element, the first doping element being phosphorus, and the second doping element comprising any one of carbon and oxygen. Furthermore, the band gap width of the third doped polycrystalline silicon layer is ≥1.6eV. The present disclosure, while ensuring a passivation effect, can greatly decrease device investment costs, greatly reduce parasitic absorption of a third semiconductor layer on the front surface of a cell, and increase short-circuit current of the cell, thereby increasing cell conversion efficiency.

The invention discloses a solar silicon wafer visual detection method, and particularly relates to the technical field of silicon wafer detection. The method comprises the following steps: acquiring optical images of different incident angles, synchronously acquiring infrared transmission images, performing normalization processing, edge enhancement filtering and self-adaptive threshold segmentation on the acquired multi-angle images, extracting suspected crack areas, and respectively calculating a gray gradient change rate and a stress abnormal degree, so as to obtain a suspected crack area; calculating a crack credibility score according to the gray gradient change rate and the stress abnormal degree through a weighted scoring method, and comparing the crack credibility score with a preset crack detection threshold value to distinguish real hidden cracks and stress pseudo defects; if the credibility score is lower than the threshold value, secondary sampling is carried out by adjusting the illumination angle, and the judgment result is further optimized; according to the method, the false rejection rate caused by lattice stress pseudo defect misjudgment is effectively reduced, meanwhile, missing detection of real subfissures is avoided, and the accuracy, stability and production yield of silicon wafer defect detection are improved, so that the long-term reliability of a photovoltaic module is enhanced.

The present disclosure belongs to the technical field of the preparation of hybrid passivated back-contact cells, and specifically relates to a short-process preparation method for a hybrid passivated back-contact cell and the use thereof. The short-process preparation method comprises: S1, texturing both surfaces of a silicon wafer; S2, subjecting the front surface of the silicon wafer to phosphorus diffusion, so as to form a third semiconductor diffusion region, wherein the process of phosphorus diffusion comprises the steps of first performing low-temperature diffusion and then performing cooling and discharging, and during the period, heating is not performed to promote diffusion; S3, removing a diffusion layer that detours to and coats the back surface and a phosphorosilicate glass layer on the front surface, which are both obtained in S2; S4, sequentially depositing a first semiconductor layer and a mask layer on the back surface obtained in S3, and subjecting same to high-temperature annealing crystallization at the same time; S5, forming a second semiconductor opening region; and S6, forming an anti-reflection layer on the front surface of the silicon wafer. In the present disclosure, a passivation effect is good, and the film density is better; moreover, defects such as film holes are effectively ameliorated, the cell conversion efficiency and the cell yield are substantially improved, and the technological process is greatly simplified, thereby greatly reducing the equipment investment cost.

The invention is applicable to the field of photovoltaic technology, and provides a solar cell, a cell assembly and a photovoltaic system.The solar cell comprises a silicon substrate, the silicon substrate is provided with a backlight face and a light facing face which are oppositely arranged, a plurality of grid lines and a plurality of microarrays are arranged on the backlight face side by side in the first direction, and the grid lines extend in the second direction; the microarray comprises a plurality of arranged microstructure units, an included angle is formed between the microarray and the grid line, and the first direction is crossed with the second direction; the length of the silicon substrate in the second direction is L, the range of the two side edges, parallel to the first direction, of the silicon substrate extending towards the center line by L / 9 is an edge area, the included angle in the edge area is alpha, the included angle in the area close to the position of the center line is beta, and the angle of alpha is larger than that of beta. The absorption path of light in the silicon wafer is increased, the diffuse reflection effect of reflected light of backlight surfaces in different areas is promoted, and therefore the absorption efficiency of the light is improved.

The invention relates to the technical field of solar cells, and particularly discloses a TBC solar cell structure and a preparation method thereof, and the preparation method comprises the steps of double-sided polishing, deposition and diffusion, laser treatment, etching treatment, acid pickling and texturing, deposition passivation and antireflection film, screen printing of an electrode, sintering and the like on a silicon wafer. Wherein the laser processing comprises at least one of a BSG layer process of a non-metal electrode area of a laser scanning P area and a PSG layer process of a non-metal electrode area of a laser scanning N area. According to the TBC solar cell, the secondary process is carried out on the non-metal electrode area on the back face of the cell piece through the laser, effective thinning of the poly layer of the non-metal electrode area of the TBC solar cell is achieved, the problems of optical parasitic absorption and current loss caused by the fact that the poly layer is too thick in the prior art are solved, and the conversion efficiency and the overall performance of the cell are improved.

The invention provides a light-emitting diode chip and a preparation method thereof, and the light-emitting diode chip comprises a conductive silicon wafer, a metal bonding layer, an N-type conductive metal layer, a first insulation protection layer, a P-type conductive metal layer, a P-type reflection metal layer, a current blocking layer, a current expansion layer, and an epitaxial layer which are stacked from bottom to top. The projection of the edge of the P-type conductive metal layer on the current expansion layer is located in the projection of the isolation groove on the current expansion layer, and the ratio of the distance between the projection of the edge of the P-type conductive metal layer on the current expansion layer and the projection of the edge of the isolation groove on the current expansion layer to the width of the isolation groove is 1 / 3-2 / 3. The isolation groove and the cutting wall are arranged on the current expansion layer, and the distance proportion relation between the edge of the P-type conductive metal layer and the isolation groove is favorable for controlling the distribution of current in the light-emitting diode chip, so that the current is prevented from being excessively concentrated, the current is more uniformly expanded to the epitaxial layer, and the overall light-emitting efficiency and stability of the light-emitting diode chip are improved.

The present disclosure belongs to the technical field of back contact cells, and specifically relates to a back contact cell capable of reducing back parasitic absorption and a manufacturing method therefor. The back contact cell comprises a silicon wafer having a front surface and a back surface, and a first semiconductor layer provided on the back surface of the silicon wafer, the back surface of the silicon wafer being an inverted pyramid textured structure; the first semiconductor layer comprises a tunneling oxide layer and a first doped polycrystalline silicon layer; the inverted pyramid textured structure has alternate flat surfaces and pits sunken in the silicon wafer; the first doped polycrystalline silicon layer comprises a polycrystalline inner layer, a polycrystalline silicon middle layer and a polycrystalline silicon outer layer, the polycrystalline silicon inner layer, the polycrystalline silicon middle layer and the polycrystalline silicon outer layer all being doped with phosphorus, and carbon and / or oxygen; in the polycrystalline silicon inner layer, the polycrystalline silicon middle layer and the polycrystalline silicon outer layer, the amount of doped oxygen gradually decreasing, and the amount of doped carbon and the amount of doped phosphorus gradually increasing. The present disclosure can reduce the parasitic absorption of the back surface while ensuring passivation performance and conductivity, thereby helping to increase short-circuit current density and cell conversion efficiency.

The invention relates to the technical field of nanoimprint, in particular to a preparation device and method of an elastomer imprint head, and the device comprises a base, a silicon wafer, a silica gel pad, a metal positioning sheet, a quartz sheet and a top cover; the embossment of the silicon wafer is adjusted in vacuum to form a central convex surface of the embossing head, and the elastomer embossing head with a specific curvature is prepared by combining an ultraviolet curing process. The impressing head is attached from the center to the edge during impressing so as to discharge bubbles, the edge is separated preferentially during demolding so as to reduce demolding force, the impressing head is matched with a semiconductor stepping process, and the yield is increased to 98% or above. The method has the technical advantages that the method can be compatible with a stepping imprinting manufacturing process, flaws in an imprinting structure can be effectively reduced through a special contact and demolding mode, and the yield is increased.

The invention discloses an automatic transverse and longitudinal splitting device and method for a flexible assembly battery piece. The automatic transverse and longitudinal splitting device comprises a rack, a conveying mechanism, a first splitting mechanism and a second splitting mechanism, and the battery pieces are sequentially conveyed to pass through the first splitting mechanism and the second splitting mechanism through the conveying mechanism; the protection layer and the silicon wafer are fractured along the scratches from the first direction through a first wafer splitting mechanism, so that the battery piece is split into a plurality of pieces which are connected through adhesive glue; and then the protective layer and the silicon wafer are broken along the scratches from a second direction through a second wafer breaking mechanism, so that the plurality of battery pieces are split into a plurality of small battery pieces which are connected with one another through adhesive glue. According to the invention, the protective layer and the silicon wafer in the three-layer structure of the battery piece can be cracked without cracking the adhesive, so that the cracked battery piece can be kept in an adhesion state, and conditions are provided for subsequent cracking, shaping and distance-expanding film coating production. According to the invention, the automation degree is high, and the productivity and the product quality can be effectively improved.

The invention provides a method for determining the volatilization behavior of antimony, a silicon single crystal rod, a silicon wafer and a solar cell, and the method comprises the steps: determining the volatilization behavior of antimony in a leading and releasing stage and / or an equal-diameter stage: in the leading and releasing stage, pulling out a small end from molten silicon; the total feeding amount and the initial antimony concentration are obtained; the mass, the phosphorus-antimony concentration and the phosphorus concentration of the small head are obtained; according to the total feeding amount, the phosphorus-antimony concentration, the initial antimony concentration and the phosphorus concentration, the volatilization amount of antimony in the small end pulling stage is calculated; in the equal-diameter stage, the actual resistivity of the silicon rod at multiple positions is obtained; converting the actual resistivity at the plurality of positions into actual phosphorus and antimony concentrations; acquiring the actual phosphorus concentration at each position; calculating the actual antimony concentration at each position according to the actual phosphorus-antimony concentration and the actual phosphorus concentration; and according to the actual antimony concentration, the effective segregation coefficient of antimony, the initial phosphorus concentration and the solidification fraction, the volatilization coefficient of antimony in the equal-diameter stage is fitted. By means of the method, the volatilization behavior of antimony in the single crystal pulling process can be determined.

The invention provides a silicon bridge chip packaging method and a silicon bridge chip packaging structure, which can reduce the manufacturing cost and improve the heat dissipation effect of a packaging body. A silicon through hole and a first dielectric substance layer are manufactured on the first surface of a silicon wafer, a groove is manufactured by avoiding the silicon through hole, a silicon bridge chip is mounted in the groove, a rewiring layer is arranged on the first surface of the silicon wafer, and the silicon bridge chip is packaged by the rewiring layer. Welding salient points are arranged on the rewiring layer, and the welding salient points are connected to the silicon bridge chip through lines on the rewiring layer; at least two chips are connected with the welding bumps, so that the chips are connected through the silicon bridge chip, the first surface of the silicon wafer is subjected to plastic packaging, the second surface, away from the silicon bridge chip, of the silicon wafer is thinned until the bottom of the silicon through hole is exposed, then a second dielectric substance layer is manufactured, and metal bumps are arranged; and thinning the plastic packaging layer on the first surface of the silicon wafer to expose the back surface of the chip, cutting the silicon wafer into single packaging bodies, inversely welding the single packaging bodies on the first surface of the substrate through the metal bumps, and arranging solder balls on the second surface of the substrate.

The invention relates to the technical field of semiconductor material preparation, and provides a method for controlling the resistivity of a fifth main group element doped crystal bar, crystal pulling time is distinguished in different crystal pulling stages, the volatilization coefficient of doped elements in different time periods is adjusted, the volatilization amount of the doped elements in each time interval is calculated more accurately, and the resistivity of the doped crystal bar is controlled. Therefore, the amount of doping elements required for controlling the resistance can be calculated more accurately, the resistance of the crystal bar can be adjusted more effectively and more accurately, the resistance difference between the head and the tail of the single-crystal crystal bar can be better reduced, meanwhile, through timely adjustment of the control process of the grade and the ending volatilization amount, the supplementary doping condition in the crystal pulling process is defined, and the crystal pulling efficiency is improved. And the resistance hit rate of the crystal bar is improved, and the head and tail resistance difference is reduced, so that the resistivity of each part of the crystal bar is accurately controlled, and the consistency of subsequent silicon wafer product quality is ensured.

The invention discloses a preparation method of a solar cell and the solar cell, and belongs to the photovoltaic field. The preparation method of the solar cell comprises the following steps: forming an alkali-resistant film layer on the front surface of a silicon substrate; forming a first tunneling layer and a first doping layer on the back surface of the silicon substrate; removing the first doping layer, the first tunneling layer and a part of the silicon substrate outside the first region; forming a second tunneling layer and a second doping layer on the back surface, wherein the doping types of the second doping layer and the first doping layer are opposite; removing the second doping layer, the second tunneling layer and a part of the silicon substrate outside the second region; removing the mask layer; and forming a first electrode in contact with the first doped layer in the first region, and forming a second electrode in contact with the second doped layer in the second region. According to the invention, the mask layer protects the front surface in the subsequent polishing process and the like, so that a thinner original silicon wafer can be selected, the two doping layers can be accurately divided and isolated on the back surface, and the purposes of reducing the cost, improving the process yield and improving the cell performance are achieved.

The present application relates to the technical field of back contact cells, and in particular to a back contact cell and a manufacturing method therefor. The back contact cell comprises a silicon wafer, a first semiconductor layer, a second semiconductor layer, and a conductive film layer, wherein isolation grooves are formed in the conductive film layer. The back contact cell further comprises a plurality of insulating ink layers which are all disposed between the second semiconductor layer and the conductive film layer and arranged at intervals along a back surface in an X-axis direction, wherein the insulating ink layers are in direct contact with the second semiconductor layer, and in the X-axis direction, the insulating ink layers stretch across the edges of the side surfaces of second semiconductor opening regions and each have two ends extending respectively. The insulating ink layer satisfies the following conditions: the surface pencil hardness is not less than 2H, the resistivity is greater than 1e11Ω·cm, and the mass content of volatile substances in raw materials of the insulating ink layer is not greater than 5%. The present application can effectively avoid electric leakage and improve the cell conversion efficiency and the cell yield, and the technological process of manufacturing is simpler.

The invention provides a back contact solar cell and a solar cell module, the back contact solar cell comprises a silicon wafer and a grid line structure, and the grid line structure comprises main grid lines and fine grid lines connected with the main grid lines. The grid line structure comprises a plurality of middle grid line sub-structures arranged in the first direction, a first edge grid line sub-structure closest to the first edge and a second edge grid line sub-structure closest to the second edge. The distance between the center line of the main grid line of the first edge grid line substructure and the center line of the main grid line of the adjacent middle grid line substructure is larger than the distance between the center lines of the main grid lines of any two adjacent middle grid line substructures. The distance between the center line of the main grid line of the second edge grid line substructure and the center line of the main grid line of the adjacent middle grid line substructure is larger than the distance between the center lines of any two adjacent middle grid line substructures. The back contact solar cell solves the problem of damage caused by stress concentration at the edge of the cell.

The invention relates to a wide-temperature high-precision optical acceleration sensitive chip and sensor based on a microcavity interferometer principle and a manufacturing method thereof, the wide-temperature high-precision optical acceleration sensitive chip comprises a first substrate, a second substrate and a third substrate, an optical fiber mounting seat and a light through hole are formed on the first substrate, a beam structure and an inertial mass block are processed on the second substrate, and the beam structure is arranged on the third substrate. The first substrate, the second substrate and the third substrate are all made of double-polished super-flat silicon wafers, a single-mode optical fiber assembly is fixed to the optical fiber installation base, the end face of the single-mode optical fiber assembly is subjected to precise grinding and is perpendicular to the axial direction of an optical fiber core, and a first cavity mirror is formed by means of the end face of the side, facing the light through hole, of the inertial mass block. A second cavity mirror is formed on the end face of the single-mode optical fiber assembly, the first cavity mirror and the second cavity mirror form an F-P interference cavity, and the first substrate, the second substrate and the third substrate are connected through the silicon-silicon bonding technology.

The invention provides a back contact solar cell and a preparation method thereof, and relates to the technical field of back contact solar cells. The preparation method of the back contact solar cell comprises the steps that an isolation area, a P area and an N area are arranged on the back face of a silicon wafer, and the isolation area is located between the P area and the N area; forming a silicon dioxide mask layer only on the isolation region; after a silicon dioxide mask layer is formed on the isolation region, a P-type polycrystalline silicon layer is formed in the P region; after a silicon dioxide mask layer is formed on the isolation region, an N-type polycrystalline silicon layer is formed in the N region; and removing the silicon dioxide mask layer after the P-type polycrystalline silicon layer and the N-type polycrystalline silicon layer are formed. According to the scheme, high-temperature diffusion of impurity atoms can be blocked, and the problem that the photoelectric conversion efficiency of the battery is reduced due to the fact that boron and phosphorus impurity atoms exist at the junction of the P region and the N region at the same time is effectively solved.

The invention provides a preparation method of an island and beam film structure micro differential pressure sensor with an IC (Integrated Circuit), which comprises the following steps: arranging an N-type buried layer, a P-type buried layer and an island film structure on an SOI (Silicon On Insulator) silicon wafer, then connecting the SOI silicon wafer with a double-parabolic silicon wafer, and arranging a medium isolation groove, an N-type buried layer connecting region, a P well, a P-type buried layer connecting region, a sensitive resistor, a P-type base region, an N-type base region, an N-type emitter region and a P-type emitter region on the SOI silicon wafer. According to the invention, the preparation of the complementary bipolar transistor double-buried layer is completed by combining a semiconductor manufacturing technology and an MEMS manufacturing technology under the condition of not using an epitaxial process; the process flow is integrally simplified, and the preparation efficiency is improved.

The invention relates to a polishing process for improving local flatness of a silicon wafer, which belongs to the technical field of semiconductor manufacturing, and comprises the following operation steps of: 1, pretreating the silicon wafer, cleaning the silicon wafer, activating the surface of the silicon wafer, removing surface impurities and an oxide layer, and preparing for subsequent polishing; secondly, partition parameter setting is conducted, the wafer is scanned, the surface of the wafer is divided into a plurality of different areas, and independent polishing parameters are set for each area according to the material characteristics, the thickness and the preset flatness target of each area; and thirdly, dynamic polishing is conducted, specifically, multi-axis linkage polishing equipment is adopted, and the movement tracks and working parameters of the polishing head in different areas are dynamically adjusted in real time according to preset partition parameters. Through silicon wafer pretreatment, partition parameter setting and dynamic polishing process monitoring and feedback adjustment mechanisms, polishing process parameters can be accurately controlled, deviation in the polishing process can be corrected in time, and stability and consistency of polishing quality are ensured.

The invention discloses a preparation method of a solar cell, and the method comprises the following steps: placing an N-type silicon wafer in a furnace tube of a diffusion furnace, and introducing nitrogen and oxygen into the furnace tube to form a first oxide layer on the surface of the silicon wafer; boron trichloride, oxygen and nitrogen are introduced into the furnace tube, so that a boron diffusion layer is formed on the surface, away from the silicon wafer, of the first oxide layer; introducing nitrogen into the furnace tube, and controlling the temperature of the furnace tube to be a first temperature so as to carry out oxygen-free propulsion of the boron element; introducing nitrogen and oxygen into the furnace tube, and controlling the temperature of the furnace tube to rise from the first temperature to a second temperature so as to carry out aerobic propulsion of the boron element; dry oxygen and wet oxygen are alternately introduced into the furnace tube for multiple times to form a second oxide layer; the temperature in the furnace tube is reduced, and dry oxygen continues to be introduced into the furnace tube; and nitrogen is introduced into the furnace tube, the temperature in the furnace tube is reduced, and boron diffusion of the silicon wafer is completed. According to the preparation method of the solar cell, the silicon wafer can have low surface concentration shallow junctions and uniform sheet resistance.

The invention relates to the technical field of heterojunction solar cells, and particularly discloses a selective electrode contact heterojunction cell preparation method and a heterojunction cell, and the method comprises the steps: carrying out the first texturing of a silicon wafer substrate, carrying out the mask layer preparation of the textured silicon wafer, and carrying out the first patterning processing of the silicon wafer. Performing slotting treatment on two sides of the silicon wafer based on picosecond laser, performing secondary texturing on the silicon wafer, placing the cleaned silicon wafer in a second texturing mixed solution so as to generate a large textured pyramid structure on the inner bottom surface of a groove in the two sides of the silicon wafer, and removing the first mask layer from the silicon wafer after secondary texturing to obtain a second textured pyramid structure; sequentially depositing a plurality of layers including an intrinsic amorphous silicon layer and the like on the two surfaces of the silicon wafer, printing a second mask layer in a counterpoint manner in other areas of the silicon wafer which is provided with the groove in the first time of patterning based on exposure and development, electroplating a copper grid line on the silicon wafer, and sequentially removing the second mask layer and a copper seed layer on the silicon wafer after electroplating the grid line; the selective electrode contact copper grid line heterojunction solar cell is obtained, the problem of grid separation of the copper grid lines is solved, and the cell efficiency is improved.

The invention provides a silicon wafer and a preparation method thereof, and a solar cell and a preparation method thereof. The silicon wafer is provided with a first surface and a second surface which are opposite, the first surface is provided with a suede structure, and at least one part of the second surface is provided with an irregular hill-shaped structure. The preparation method of the silicon wafer comprises the following steps that acid etching is carried out on the first surface of the silicon wafer to be textured, then alkali texturing is carried out, so that a textured structure is formed on the first surface, and the textured structure can comprise a plurality of pyramid units; and immersing the silicon wafer subjected to alkali texturing into an alkali solution containing an organic polymer additive (such as polyoxyethylene), and finely adjusting the textured structure of the silicon wafer through etching of the alkali solution containing the organic polymer additive so as to form at least one concave part with a light trapping effect on at least one tower surface of the pyramid unit. The silicon wafer and the solar cell not only have excellent light trapping performance, but also do not affect the subsequent passivation effect, thereby effectively improving the current and efficiency of the solar cell.

The invention discloses a hybrid passivation back contact battery and a preparation method thereof, the battery comprises a silicon wafer, the silicon wafer comprises a first surface and a second surface which are oppositely arranged, the second surface comprises a first area and a second area, and the area of the first area is larger than that of the second area; the heterostructure comprises a first passivation layer and a first doping layer which are at least stacked on the first region; the first electrode structure is located on the first doping layer in the heterostructure; the first passivation structure comprises a tunneling oxide layer and a second doping layer which are stacked on the second region; the second electrode structure is located on the second doping layer in the first passivation structure, and the first electrode structure and the second electrode structure are electrically isolated through an isolation groove; and the second passivation structure is located on the first surface of the silicon wafer. The passivation effect of the HTBC battery is good, and the photoelectric conversion efficiency can be remarkably improved; and the preparation process of the battery is simple, few in process steps and low in equipment cost.

According to the deformation detection integrated micro-nano sensor, a substrate is an SOI silicon wafer and comprises bottom layer silicon (1), a buried oxide layer (2) and top layer silicon (3) which are sequentially stacked and attached from bottom to top, a detection unit is arranged on the top layer silicon (3) and comprises a deformation detection unit (4), a temperature detection unit (5) and a vibration detection unit (6); the final detection value of the deformation takes a deformation parameter detected by the deformation detection unit (4) as basic data, and meanwhile, a temperature parameter detected by the temperature detection unit (5) and a vibration parameter detected by the vibration detection unit (6) are used for providing compensation for the deformation parameter detected by the deformation detection unit (4); the invention further provides a manufacturing method and a detection method. The piezoresistive effect of the semiconductor is used for detecting the strain, and the measurement sensitivity is remarkably improved.

The utility model discloses a silicon wafer degumming frame and a degumming cleaning machine, and belongs to the technical field of silicon wafer degumming. The silicon wafer degumming frame comprises a frame body, the frame body is used for loading a silicon wafer, and a guide shaft is arranged on an end plate of the frame body; the bearing mechanism is connected to the guide shaft in a sliding manner, and the bearing mechanism is used for bearing the bottom of the silicon wafer; the clamping mechanism is connected to the guide shaft in a sliding mode, and the clamping mechanism is used for clamping the side face of the silicon wafer; and the locking mechanism is connected to the frame body, and the locking mechanism is used for locking the bearing mechanism.

A recycling system and a recycling method for a photovoltaic cell module. The recycling system for the photovoltaic cell module comprises a pyrolysis device (410), a separation device (500), and a gasification device (600); a discharge port of the pyrolysis device (410) is communicated with a feed port of the separation device (500); the separation device (500) is used for separating silicon cells from pyrolyzed solid materials; a discharge port of the separation device (500) is communicated with a feed port of the gasification device (600), so that the separated silicon cells enter the gasification device (600); the gasification device (600) is used for gasifying silver and aluminum on the silicon cells. The gasification device (600) is used to gasify silver and aluminum on the silicon cells, so that a pure silicon wafer is obtained; the silicon cells are treated without using a chemical medicinal liquid, so that no acid-base wastewater containing metal ions is generated. Therefore, the recycling difficulty of the photovoltaic cell module can be reduced.

The present application belongs to the technical field of the preparation of hybrid passivated back-contact cells, and specifically relates to a hybrid passivated back-contact cell and a method for preparing same by means of one-shot annealing. The preparation method comprises: S101, providing a silicon wafer with both surfaces polished and cleaned; S102, forming a first semiconductor layer and a mask layer on the back surface of the silicon wafer, wherein annealing is not performed during the forming process of the first semiconductor layer; S103, forming a second semiconductor opening region; S104, performing texturing and cleaning, and forming a textured surface at the same time; S105, then forming a third semiconductor layer on the front surface of the silicon wafer, wherein the forming process of the third semiconductor layer comprises second in-situ doping deposition; after the second in-situ doping deposition, performing one-shot annealing on the first semiconductor layer and the third semiconductor layer at a low pressure; then depositing an anti-reflection layer; and then cleaning same; and S106, depositing a second semiconductor layer. In the present application, annealing is performed only once in the whole process, and therefore the equipment cost is greatly reduced, and both the short-circuit current and conversion efficiency of a cell are improved.

The invention provides a method for detecting silicon single crystal COP free area distribution, and relates to the technical field of silicon single crystal quality detection.The method comprises the steps that a silicon wafer to be detected is cleaned to obtain a first silicon wafer; uniformly smearing a transition metal ion solution on the surface of the first silicon wafer to obtain a second silicon wafer; placing the second silicon wafer in a high-temperature environment, and performing heat treatment under three temperature gradients to obtain a third silicon wafer; wherein in the first stage, transition metal ions are diffused to the surface layer of the silicon wafer to activate oxygen precipitates in a Pv region, in the second stage, the transition metal ions are promoted to be diffused into the silicon wafer to develop a Pi low-oxygen region, and in the third stage, nuclei coalescence in a B-band region is activated at high temperature to form a differential arrangement ring; cleaning the third silicon wafer through a mixed acid solution to obtain a fourth silicon wafer; and placing the fourth silicon wafer in a preferential corrosion liquid for preferential corrosion, and carrying out COP free area distribution detection on the obtained detection sample wafer. According to the scheme, the definition of each region boundary can be improved, so that the detection accuracy of COP free region distribution is improved.

The invention discloses a photovoltaic cell preparation method for improving ALD passivation and a photovoltaic cell, and belongs to the technical field of photovoltaic cells. The preparation method comprises the following steps: performing texturing, front boron diffusion, oxidation, back etching and polishing on a silicon wafer, preparing a back tunneling oxide layer and an amorphous silicon layer, performing acid pickling, removing the tunneling oxide layers on the back and the side surfaces through cleaning, preparing front and back passivation films, printing electrodes and the like, washing with water: washing with a cleaning solution containing potassium hydroxide and hydrogen peroxide, washing with water, pickling, and washing with water; repeating the steps; and cleaning with the oxidizing liquid again, and washing with water. According to the invention, through the improvement of the processing technology of the tunneling oxide layer and the amorphous silicon back winding plating, the yield of the battery production line is improved, the control of the production line is simpler and more convenient, the promotion of the passivation of the oxide layer before ALD is more stable, and the battery conversion efficiency of the production line is further improved.

The invention discloses a combined passivation back contact battery which comprises an N-type silicon wafer, a second intrinsic amorphous silicon layer, a microcrystalline silicon layer, an anti-reflection layer, a second semiconductor opening region, a first semiconductor opening region and a transition region, the anti-reflection layer is a single-layer amorphous silicon carbonitride layer or a laminated structure composed of an amorphous silicon carbide layer and an amorphous silicon carbonitride layer, and the second semiconductor opening area is composed of a first intrinsic amorphous silicon layer, a P-type amorphous silicon layer, a transparent conductive film and a metal electrode which are sequentially arranged on the back face of the silicon wafer. The first semiconductor opening area is composed of a tunneling oxide layer, an N-type polycrystalline silicon layer, a transparent conductive film and a metal electrode which are sequentially arranged on the back face of the silicon wafer, and an opening is etched in the transparent conductive film on the surface of the transition area to form an insulation groove. Amorphous silicon carbonitride or amorphous silicon carbide / amorphous silicon carbonitride laminated layers are adopted as the anti-reflection layers, so that reflection loss is reduced, the reliability and durability of the cell are improved, and the conversion efficiency of the cell is improved.