504 results about "Silicon chip" patented technology

The utility model relates to monocrystalline silicon processing technical field, and disclose a cutting silicon core blanking device for monocrystalline silicon processing, including guide table, guide chute, protective layer, transport device, conveyer belt, fixed clamp holder, adjustable clamp holder, limit hole, screw shaft, clamping layer, nut, in the utility model, when the monocrystalline silicon rod is cut by diamond wire and forms the silicon wafer blanking, the silicon wafer can be buffered and received by the protective layer and downwardly rolls and guides, and the fixed clamp holder and adjustable clamp holder on the conveyer belt correspond to the position of guide chute, at this time, the silicon wafer can roll down and fall into the fixed clamp holder and adjustable clamp holder between the guide chute and be collected, and the clamping layer between the fixed clamp holder and adjustable clamp holder can clamp and protect the falling silicon wafer, and the adjustable clamp holder can be located outside the screw shaft and slide and adjust to adapt to the silicon wafer thickness, when the transport device drives the conveyer belt and starts conveying, the silicon wafer between the fixed clamp holder and adjustable clamp holder can be automatically collected and conveyed.

The utility model discloses a silicon wafer center positioning structure, including draw together bottom platform, one rear end draw together arm and two side edge draw together arms, install draw together driving wheel and draw together driven wheel on draw together bottom platform, and transmission connection has draw together synchronous belt between draw together driving wheel and draw together driven wheel, and the lower extreme of rear end draw together arm is fixed in one side of draw together synchronous belt, and rear end draw together arm removes along the front -back direction, and one side of draw together synchronous belt is connected with draw together fixed plate, and draw together fixed plate is provided with the inclined draw together guide slot, and install draw together guide wheel on side edge draw together arm, and draw together guide wheel is in draw together guide slot, and side edge draw together arm removes along left -right direction. This silicon wafer center positioning structure is used to draw together and position the silicon wafer after turning over and turning, controls three directions draw together arm to draw together to the middle part of track under the condition of single motor drive, arranges the silicon wafer and positions, and the preparation of subsequent pasting rubber strip is prepared for photographing detection.

The application relates to the technical field of photovoltaic cells, and particularly provides a cleaning machine. The application aims to solve the problems of low efficiency of manual detection and removal of over-etched pieces, and pollution of the pieces and breakage of the pieces caused by manual taking and placing of the pieces during detection. To this end, the application provides a cleaning machine, which comprises a first cleaning mechanism and a second cleaning mechanism, the second cleaning mechanism comprises opposite conveying sides and collecting sides; a removal device is arranged between the first cleaning mechanism and the second cleaning mechanism and comprises a lifting assembly and a third cleaning mechanism; a transition component is connected between the second cleaning mechanism and the removal device and is provided with a normal piece flow inlet and an over-etched piece flow inlet; an over-etched piece collecting device is arranged on the collecting side; the lifting assembly is used for lifting the normal silicon pieces on the third cleaning mechanism into the normal piece flow inlet and making the over-etched pieces fall into the over-etched piece collecting device through the over-etched piece flow inlet. The application can automatically guide the over-etched pieces out of the machine, improve the removal efficiency of the over-etched pieces, and avoid the problems of pollution and breakage of the pieces.

The utility model discloses a cooling liquid circulating device for silicon wafer cutting, including processing box, the cutting assembly is installed on the inside wall upper end of processing box, the side wall of processing box is connected with the supporting plate, is installed with drive mechanism on the supporting plate, is installed with filter mechanism on drive mechanism and processing box, the outside of processing box is connected with cooling mechanism, when moving back, the filter plate will move to the storage box, and the scraper will clean the upper end surface of filter plate, and the impurity falls to the inclined plate below the push plate, realizes the effect of delaying filter plate blockage, reduces the frequency of filter plate cleaning replacement, and the impurity is pushed to the bottom end of the inclined plate by the push plate, realizes the accumulation of the impurity, simultaneously, when pushing back, the connecting plate will push the waste liquid filtered below the filter plate, and the filtered waste liquid is pushed into the drain pipe, and then flows into the cooling box, realizes the effect of collecting and cooling of the filtered waste liquid.

This utility model relates to the technical field of photovoltaic panel dismantling equipment, and discloses a photovoltaic panel edge-removing device, including a U-shaped block. A fixing block is fixedly connected to the inner wall of the U-shaped block, and a motor is fixedly connected inside the fixing block. A worm gear is fixedly installed at the output end of the motor. A U-shaped plate is rotatably connected to the outer wall of the worm gear, and the outer wall of the U-shaped plate is fixedly connected to the outer wall of the fixing block. A worm wheel is meshed with the tooth end of the worm gear, and a connecting rod is fixedly connected inside the worm wheel. The outer wall of the connecting rod is rotatably connected to the inside of the U-shaped plate. A clamping block is fixedly connected to the outer wall of the worm wheel, and a driving assembly is provided on the outer wall of the U-shaped block. In this utility model, through the mutual cooperation between the first hydraulic cylinder, U-shaped block, fixing block, motor, worm gear, U-shaped plate, worm wheel, connecting rod, and clamping block, dismantling efficiency is improved, continuous automated operation is achieved, and the recovery rate and integrity of key materials such as silicon wafers are significantly improved.

This invention relates to the field of vapor phase etching (VPE) apparatus technology, specifically a double-sided VPE apparatus for semiconductor silicon wafers. The apparatus includes a VPE apparatus body, a silicon wafer transfer mechanism at the upper end of the apparatus body, an etching chamber fixedly mounted on the outer side of the apparatus body, and a mounting base fixedly mounted on the upper end of the etching chamber. By combining the VPE mechanism with a central air-guiding mechanism, stable adsorption of the semiconductor silicon wafer is ensured during the etching process, avoiding vibration and improving etching efficiency and precision. A Bernoulli-style chuck structure is formed by the cooperation of the air-guiding support stage and the central stage, stably "fixing" the silicon wafer above the air-guiding support stage, minimizing contact with the semiconductor silicon wafer, avoiding physical damage and contamination, and simultaneously enabling multi-directional airflow distribution to meet auxiliary heat dissipation needs for the semiconductor silicon wafer, further improving the accuracy and etching efficiency of the VPE process.

A transparent wood surface imprinting optical device is provided. A preparation method for the device includes cleaning and drying surfaces of transparent wood, spin-coating polymethyl methacrylate (PMMA) on a substrate of the transparent wood to obtain a PMMA layer, and spin-coating an ultraviolet (UV) glue on the PMMA layer to obtain a UV glue layer; placing the transparent wood on a silicon wafer, attaching a transparent grating array imprinting template on the UV glue layer, exposing the UV glue layer, and removing the transparent grating array imprinting after the exposing, thereby to obtain a grating-structure-based transparent wood; and replacing the grating structure imprinting template by a lattice structure imprinting template to prepare lattice-structure-based transparent wood. The diffraction efficiency of the grating structure and the lattice structure on the transparent wood are greater and more stable than those of PMMA substrates.

A display pixel compensation circuit device using a dual-slope includes N channel multiplexers respectively coupled to sensing lines of corresponding channels; a sensing current conveyor configured to sense, on a target sensing line selected by control signals, a drain current of a target pixel's driving thin-film transistor; a noise current conveyor configured to sense, on an adjacent sensing line, panel noise, the adjacent sensing line being next to the target sensing line; and dual-slope error-detection circuitry configured to derive a pixel error from outputs of the two conveyors, convert the error into a sign value and an error value, and store these in a memory. In subsequent frames, the error value is arithmetically added to or subtracted from the digital pixel signal according to the sign value and supplied to respective channels, enabling real-time multi-bit correction with reduced silicon area and improved power efficiency.

This invention discloses a wet cleaning process for Topcon solar cells adapted to poly annealing, relating to the field of solar cells. The process includes alkaline polishing to control the oxide layer thickness, with intra-wafer thickness uniformity ≤ ±0.2nm and inter-wafer consistency ≤ ±0.15nm. The RCA cleaning process sequentially includes poly-coating removal cleaning, water washing, pre-cleaning, water washing, pre-acid washing, water washing, post-acid washing, water washing, pre-dehydration, and drying. The pre-cleaning involves immersing the monocrystalline silicon wafer in a 3.5%~4% (w / w) H2O2 mixed aqueous solution at 60℃~72℃ for 100s~120s. The post-acid washing involves immersing the monocrystalline silicon wafer in a 6%~8% (w / w) HF and 1%~2% (w / w) HCl mixed aqueous solution at room temperature for 100s~120s. By optimizing and adjusting the RCA cleaning process and the concentration ratio of the cleaning solution in the cleaning tank, the reaction is prevented from reaching the weak points of the oxide layer and further reacting with the doped crystalline silicon. At the same time, the cleaning process is optimized to ensure that the back surface of the silicon wafer retains a high doping concentration, reduce the surface transport resistance, and improve the fairing (FF).

This invention relates to the field of semiconductor cleaning technology and discloses a cleaning agent for semiconductor silicon wafers and its preparation method. This cleaning agent aims to solve the problem that traditional strong alkaline or phosphate-based wet electronic chemical cleaning agents easily corrode the silicon wafer surface, damage the crystal lattice, and thus affect electrical performance. This cleaning agent utilizes a multi-component synergistic effect: a surfactant system composed of alkyl glycosides and sophorolipids enhances particle wetting and stripping; lipase and silicon-pharmacoprotein precisely catalyze the removal of specific contaminants; sodium gluconate complexes metal ions; gelatin-polyacrylamide copolymer disperses contaminants to prevent secondary contamination; glycerol and trehalose maintain enzyme activity; and ultrapure water ensures the system meets the electronic-grade purity standards for wet electronic chemicals. Overall, it avoids strong alkaline corrosion, maintains the integrity of the silicon wafer lattice, and improves particle removal efficiency, meeting the high standards required for wet electronic chemical-based silicon wafer cleaning agents in advanced processes.

This invention discloses a method for preparing diamond rare-earth europium (EEUR) color core particles, belonging to the field of non-metallic element materials. The method involves coating a europium oxide suspension onto a single polished silicon wafer, followed by microwave plasma chemical vapor deposition (CPCVD) to form EEUR color core particles. This method allows for the growth of EEUR color core particles on the surface of a diamond film. The absence of obvious traces of Eu₂O₃ nanoparticles on the surface of the EEUR color core particles indicates that the diamond implantation solution within the europium oxide particles rapidly forms the EEUR color core particles during CPCVD, resulting in the diamond core ultimately covering the europium oxide particles, thus forming a core-shell structure, i.e., the diamond rare-earth europium color core particles. The obtained EEUR color core particles are mostly irregularly shaped with a diameter of approximately 8 μm.

The present application relates to the technical field of silicon wafer production, and discloses a cleaning and drying method and system for silicon wafers, which comprises the following steps: pre-cleaning silicon wafers after being cut; loading the pre-cleaned silicon wafers into a silicon wafer basket; immersing the silicon wafer basket into a cleaning tank to perform main cleaning on the silicon wafers; sending the silicon wafer basket after the main cleaning into a closed drying cavity, measuring the in-situ wetting angle of the contact area between the edge of the silicon wafer and the clamping tooth of the silicon wafer basket by using an optical wetting angle measuring instrument in the closed drying cavity; matching the value of the in-situ wetting angle obtained by detection with a plurality of preset wetting angle intervals, and controlling the infrared radiation array to irradiate and dry the silicon wafer basket according to the drying strategy corresponding to the matched wetting angle interval; sampling the dried silicon wafers, performing the same texturing and thermal oxidation treatment on the sampled silicon wafers, and detecting whether the treated silicon wafers are abnormal; and grading the silicon wafer batches without abnormalities into the warehouse. The method can improve the production yield of silicon wafers.

The present disclosure relates to the field of photovoltaic technology, and particularly relates to a method for drawing a single crystal silicon rod and a silicon wafer. The method comprises sequentially performed melting, seeding, shoulder-removing and constant-diameter processes. In the constant-diameter process, the following steps are implemented: setting a target furnace pressure and a preset upper limit value of a dry pump opening; adjusting the dry pump opening to control an actual furnace pressure in the furnace at the target furnace pressure; when the current opening of the dry pump is lower than the preset upper limit value, increasing the flow of protective gas into the single crystal furnace, and returning to perform the step of adjusting the dry pump opening based on the furnace pressure change until the opening of the dry pump is greater than or equal to the preset upper limit value. The present disclosure is at least beneficial to improving the electrical performance and yield of the single crystal silicon rod.

The application relates to a photovoltaic flower basket, which comprises two oppositely spaced side plates, connecting rods arranged between the side plates, connecting plates and supporting rods. The two ends of the connecting rods and the supporting rods in a first direction are connected to the side plates. The connecting plate has opposite first and second surfaces, the first surface is connected to the connecting rod, and a plurality of partition plates are arranged on the second surface, and a placing station for placing materials is formed between each adjacent partition plate. Two adjacent connecting plates arranged oppositely on the second surface form a working group. There are multiple working groups, and a supporting rod is arranged between the two connecting plates of each working group. The connecting rods are arranged between two adjacent working groups, and the two connecting plates arranged oppositely on the two first surfaces are connected to the same connecting rod. The photovoltaic flower basket can be used for placing multiple rows of cut silicon wafers, and has the advantages of low production cost and simple assembly.

This disclosure relates to a silicon wafer sorting system and electronic device. The system includes: a feeding module, a detection module, a sorting module, a first conveying component, and a second conveying component. The feeding module, the detection module, and the sorting module are sequentially connected via the first conveying component. The detection module is also connected to the sorting module via the second conveying component. The feeding module is used to transfer a target silicon wafer to be detected to the detection module via the first conveying component. The detection module is used to transfer the normal silicon wafer to the sorting module via the first conveying component if the target silicon wafer is determined to be a normal silicon wafer; or, if the target silicon wafer is determined to be an abnormal silicon wafer, transfer the abnormal silicon wafer to the sorting module via the second conveying component.

This utility model discloses a silicon substrate, a solar cell, and a photovoltaic module, relating to the field of solar cell technology, to solve the problem that after initial silicon wafers are treated with laser thermal cracking, excessive edge stress leads to a high breakage rate and significant performance degradation during subsequent solar cell fabrication. The silicon substrate includes a first surface and a second surface opposite to each other, and a plurality of side surfaces connecting the first and second surfaces; the side surfaces include a first side surface, wherein at least a portion of the first side surface has a first protrusion, one end of the first protrusion being close to the first surface, and the other end of the first protrusion being close to the second surface; along the direction from the first surface to the second surface, the distance between any point on the first protrusion and the first side surface first increases and then decreases.

The application provides a pre-cut layer for semiconductor silicon ingot slurry multi-wire cutting, a preparation method and application thereof. The pre-cut layer is an epoxy resin-based composite material, and comprises the following components in percentage by mass: 30-40% of an epoxy resin matrix, 3-7% of a toughening agent, 12-16% of a curing agent, 0.5-1.5% of an accelerator, and 40-50% of inorganic hard fillers. The pre-cut layer is pasted on the entry port end face of the semiconductor silicon ingot to be cut, and the pre-cut layer and the semiconductor silicon ingot are cut by using a slurry multi-wire cutting process. In the pre-cut layer stage, low-speed slow feeding is adopted to realize rough grinding of the slurry and in-situ slow release of fine SiC, so that the slurry particle size is quickly stabilized. After entering the silicon ingot cutting stage, high-speed fast feeding is switched to ensure the cutting efficiency. The slurry cutting force is uniform and stable throughout the process, the taper problem of thin entry port and thick exit port is eliminated from the root, and the silicon wafer cutting quality and yield are significantly improved.

The present invention relates to a microfluidic chip for an inhalation sprayer. A semi-closed internal cavity is formed by a silicon wafer 1 and a glass sheet 2 by means of anodic bonding, and comprises an inlet end 3 and an outlet end 4; the outlet end comprises a left outlet 41 and a right outlet 42, the left outlet and the right outlet being axisymmetric with respect to the central axis X of the microfluidic chip, and the axis Y of the left outlet and the axis Y' of the right outlet jointly meeting the central axis X at a point A; the outlet end comprises a cutting start line U0, the vertical distance from the point A to the cutting start line U0 being L; the outlet end further comprises a cutting buffer line U1, a fluid in the microfluidic chip being ejected from the cutting buffer line U1, the vertical distance from the cutting buffer line U1 to the cutting start line U0 being a cutting buffer distance L', and L'≤L, so as to ensure that the fluid collides and sprays outside the chip; moreover, the cutting buffer distance can protect the integrity of the outlet end when the microfluidic chip is cut, thus improving the overall quality and yield of microfluidic chips, and reducing costs.

The present disclosure relates to a secondary chamfering method, a secondary chamfering system, a computing device and a medium. In an aspect, a secondary chamfering method is provided, which comprises: measuring a thickness of a silicon wafer to be secondary chamfered to determine whether the measured value is a desired value, wherein the desired value is determined according to a groove type of a correction groove of a grinding wheel used for secondary chamfering; adjusting the thickness of the silicon wafer to reach the desired value when the measured value is not the desired value; and secondary chamfering the adjusted silicon wafer by using the correction groove. Thus, the edge of the incoming silicon wafer with thickness fluctuation can reach the desired shape after secondary chamfering processing.

This disclosure provides a method, system, and epitaxial wafer for improving particulate contamination of silicon wafers during epitaxy. The method includes: selecting at least one test silicon wafer from a batch of silicon wafers to be processed, and determining a target power range to be applied to the epitaxial furnace based on the test results of the test silicon wafer; adjusting the effective power applied to the epitaxial furnace to the target power range before the silicon wafer to be processed is fed into the epitaxial chamber of the epitaxial furnace, so that the temperature inside the epitaxial chamber is within a target temperature range; maintaining the effective power of the epitaxial furnace within the target power range until the silicon wafer to be processed enters the epitaxial chamber, thereby using the target temperature range to suppress thermal deformation of the silicon wafer to be processed; and growing an epitaxial layer on the surface of the silicon wafer to be processed after it enters the epitaxial chamber. This disclosure can effectively reduce particulate contamination of the silicon wafer to be processed during epitaxy.

The embodiments of the present application provide a silicon wafer, a silicon rod, a cell, and a cell assembly. At least one surface of the silicon wafer is provided with a plurality of stripes; the stripes extend with reference to a first direction, and the plurality of stripes are arranged at intervals in a second direction; the peak-to-valley height difference Rt of the surface profile of the middle region of the surface satisfies: 2 μm ≤ Rt ≤ 8.5 μm; the first direction is the extension direction of a first side edge of the silicon wafer, and the second direction is the extension direction of a second side edge of the silicon wafer; and the middle region refers to a region at least L / 3 away from the first side edge of the silicon wafer in the second direction, wherein L is the length of the second side edge. The flatness of the surface of the silicon wafer is relatively uniform, which can improve the photoelectric conversion efficiency of a cell to which the silicon wafer is applied.

The present invention relates to the field of solar cells. Disclosed is a method for preparing a TBC solar cell having an edge wrap-around plating layer. In the present invention, an insulating dielectric film is pre-constructed at the edge of a silicon wafer by means of a special combined process of "direct oxidation-indirect deposition-high-temperature annealing" and "high-temperature densification + boron doping", so that an edge wrap-around plating region is insulated and isolated from a silicon wafer substrate. Therefore, even if the edge of a finished TBC solar cell has a wrap-around plating layer, a wrap-around plating portion will not produce significant electric leakage. Secondly, the insulating dielectric film also has an excellent passivation effect, and can further passivate a side region of the silicon wafer, thereby being conducive to improving the electrical performance of the cell. Finally, compared with a conventional TBC solar cell of which the entire edge is a pyramid textured surface, part of the edge of the silicon wafer of the present invention is a pyramid textured surface and the remaining part of the edge of the silicon wafer is a polished surface. The silicon wafer having a textured edge is more prone to fragmentation under the action of an external force, and the polished surface is more conducive to improving the yield of the solar cell.

This invention relates to the field of semiconductor material testing technology, specifically a single-crystal silicon wafer slip line detection system and method, comprising: a light source module emitting light signals of different wavelengths and polarization angles to scan the silicon wafer; a silicon wafer scanning module mounting the silicon wafer under test, adjusting the position of the silicon wafer under test, and executing a scanning trajectory to scan the silicon wafer with light signals; a signal acquisition and processing module receiving the light signals transmitted through the silicon wafer under test, performing preprocessing to obtain DU values ​​at different wavelengths and polarization angles, and sending them to an industrial control computer; the industrial control computer reconstructing the strain field based on the DU values ​​using a strain field reconstruction algorithm to generate a strain field distribution map; and identifying slip lines based on the strain field distribution map using a convolutional neural network model. This solution enables non-contact, non-destructive, and high-resolution slip line detection, thereby improving detection accuracy and efficiency.

The utility model relates to a circulating silicon wafer material receiving mechanism, including support, surface sets up sliding rod, rotatably be provided with pulley on the sliding rod, conveying component sets up on the support, the conveying component includes two sprocket setting on the support, the chain around two sprocket setting and the motor of connecting sprocket, movable bottom plate, connects the chain, material box sets up on the movable bottom plate, wherein, the movable bottom plate opens the limit hole, the pin shaft of chain extends and goes into the limit hole, the rotation axis of pulley is perpendicular to the length direction of chain, the movable bottom plate sets up at least two, the utility model discloses all material box reciprocating circulation movement on the support along the same path, can set up two and above material box on the support and work simultaneously without producing interference, greatly promote the work efficiency of material receiving mechanism.

The application relates to the field of photoetching, and discloses a silicon wafer alignment method, a device and a standard wafer. The method comprises the following steps: when a standard wafer is moved from a measuring end to an exposure end along a workpiece table of a photoetching machine, controlling light to be irradiated to the standard wafer and the workpiece table through a photo mask; determining the relative position of the workpiece table and the photo mask; determining the relative position of the standard wafer and the photo mask; determining the relative position of the standard wafer and the workpiece table according to the relative position of the workpiece table and the photo mask and the relative position of the standard wafer and the photo mask; determining the position deviation of the standard wafer and the workpiece table according to the initial position deviation of the standard wafer at the measuring end and the workpiece table and the relative position of the standard wafer and the workpiece table; determining the position deviation of a to-be-aligned silicon wafer and the workpiece table based on the position deviation, and aligning the to-be-aligned silicon wafer. The method obtains the position deviation of the standard wafer and the workpiece table by means of the standard wafer, and then aligns the to-be-aligned silicon wafer based on the position deviation, so that the to-be-aligned silicon wafer can be prevented from generating deviation at the exposure end.

The application discloses a kind of silicon chip alignment system's surveying and calibrating method, device, system, equipment and medium.The method comprises: in response to the calibration operation of the target imaging position of mark in reference mark plate, obtain the image after the target imaging position of mark is calibrated, wherein the mark on the reference mark plate is engraved for calibration, and the mark in the image collected under the target imaging position is complete mark;In response to the operation corresponding to surveying and calibrating scheme, the image after the target imaging position of mark is calibrated is surveyed and calibrated, and the surveying and calibrating result corresponding to surveying and calibrating scheme is obtained.The above technical solution calibrates the target imaging position of mark in reference mark plate, so that the mark in the collected image is complete, improves the quality of acquisition image, and then executes surveying and calibrating scheme through high-quality image, so that the surveying and calibrating result is more accurate.

A method for manufacturing a silicon epitaxial wafer comprising a phosphorus-doped silicon wafer and an epitaxial layer provided on a surface of the silicon wafer, wherein the method comprises: forming (S2) an oxide layer on a back side of the silicon wafer cut (S1) from a single-crystal ingot produced by a Czochralski process; removing (S3) the oxide layer present on an outer circumference of the silicon wafer; argon annealing (S4), wherein the silicon wafer is subjected to heat treatment in an argon gas atmosphere after removal of the oxide layer; and forming the epitaxial layer on the surface of the silicon wafer after argon annealing, wherein the formation of the epitaxial layer comprises: pre-baking (S5), wherein the silicon wafer is subjected to heat treatment in a gas atmosphere comprising hydrogen and hydrogen chloride to etch an outer layer of the silicon wafer;and growth (S6) of the epitaxial layer on the surface of the silicon wafer after pre-baking, wherein during argon annealing (S4) clusters of phosphorus and oxygen present on an outer layer of the silicon wafer are dissolved in a solid solution, and during pre-baking (S5) a thickness of the outer layer of the silicon wafer removed by etching is made smaller than a thickness of the outer layer where the clusters are dissolved in the solid solution during argon annealing.;

The application provides a low-corrosion TOPCon silver paste, a preparation method and application thereof, and belongs to the field of solar cells. The TOPCon silver paste is composed of the following components: 40-70 parts of silver powder, 5-25 parts of silver-coated tungsten, 1-5 parts of glass material, 1-5 parts of modified nano calcium carbonate, 10-15 parts of organic carrier, and 0.5-2 parts of organic additive. The modified nano calcium carbonate is uniformly dispersed on the surface of the glass powder through physical adsorption and chemical bonding, can reduce the corrosion of the silver paste to the surface of the silicon wafer, and maintains the integrity of the surface of the silicon wafer. Meanwhile, the modified nano calcium carbonate forms a dense conductive network in the sintering process, reduces the contact resistance, and improves the conversion efficiency of the battery. In addition, the modified nano calcium carbonate improves the interfacial bonding force between the silver paste and the silicon wafer, enhances the adhesion and tensile strength of the silver paste. Therefore, the corrosion resistance, conductivity and mechanical properties of the silver paste for the TOPCon battery are improved.

A method for inducing the ordered arrangement of ZnS nanospheres includes the following steps: S1, Preparation of ZnS nanospheres: ZnS nanospheres of 60-120 nm are prepared using a hydrothermal method. After multiple washings and centrifugation, pure ZnS nanospheres are obtained. S2, Preparation of a ZnS mixed solution: The ZnS nanospheres prepared in step S1 are dispersed in a mixed solution of water, ethanol, and a surfactant, and the solution is ultrasonically vibrated to obtain a ZnS mixed solution. S3, Dropping the film: The heating platform is heated to 30-60°C and maintained at a constant temperature. A pipette is used to draw 50-200 μL of the ZnS mixed solution from step S2 and drop it onto a clean silicon wafer. After the solvent evaporates, the sample is removed to obtain an ordered pattern. This invention provides a simple and widely applicable method for inducing the ordered arrangement of nanospheres.

The application discloses a kind of high double-side rate silver paste for solar TopCon back fine grid, belong to solar cell technical field.The silver paste is by micron, submicron, nanometer spherical silver powder, glass powder, organic dispersant, thixotropic agent, silicone oil, organic solvent, titanate additive and organic carrier according to specific ratio composition.By adding 0.4%~0.7% titanate additive, cooperate with multistage silver powder grading and low corrosion glass powder system, effectively solve the narrow line width printing easy to block net, virtual printing broken grid problem, reduce the poly layer corrosion and carrier recombination of silicon wafer.The silver paste printing stability, grid line height-width ratio is optimal, light transmittance is good, can significantly improve the double-side rate of battery and photoelectric conversion efficiency, provides high-performance back fine grid conductive paste scheme for N-type high-efficiency photovoltaic cell.