3123 results about "Silicon chip" patented technology

The invention relates to a polishing process for improving local flatness of a silicon wafer, which belongs to the technical field of semiconductor manufacturing, and comprises the following operation steps of: 1, pretreating the silicon wafer, cleaning the silicon wafer, activating the surface of the silicon wafer, removing surface impurities and an oxide layer, and preparing for subsequent polishing; secondly, partition parameter setting is conducted, the wafer is scanned, the surface of the wafer is divided into a plurality of different areas, and independent polishing parameters are set for each area according to the material characteristics, the thickness and the preset flatness target of each area; and thirdly, dynamic polishing is conducted, specifically, multi-axis linkage polishing equipment is adopted, and the movement tracks and working parameters of the polishing head in different areas are dynamically adjusted in real time according to preset partition parameters. Through silicon wafer pretreatment, partition parameter setting and dynamic polishing process monitoring and feedback adjustment mechanisms, polishing process parameters can be accurately controlled, deviation in the polishing process can be corrected in time, and stability and consistency of polishing quality are ensured.

The invention provides a preparation method of an inertial sensor and the sensor. The preparation method comprises the following steps: sequentially forming a first cavity and a first oxide layer on a first silicon wafer; bonding the first silicon wafer and a second silicon wafer, wherein the second silicon wafer is a low-resistance silicon wafer; forming an inertia sensitive structure in the second silicon wafer; correspondingly forming a second cavity on a third silicon wafer, wherein the third silicon wafer is a low-resistance silicon wafer; bonding the third silicon wafer and the second silicon wafer; an isolation groove penetrating through the third silicon wafer is formed through etching, a conductive silicon column and an electric signal isolation ring are formed, and the conductive silicon column is connected with the inertia sensitive structure; and forming a sealing insulating layer on the surface of the third silicon wafer, and forming a signal lead-out pin in the sealing insulating layer. According to the scheme, thermal stress caused by thermal expansion coefficient mismatch among the three layers of wafers is reduced through an all-silicon wafer level packaging process, and the full-temperature characteristic of the device is greatly enhanced; and the preparation process flow is optimized, the process control difficulty is reduced, and the preparation cost is reduced.

The CPO system packaging method provided by the embodiment of the invention comprises the following steps: by taking a high-resistance silicon wafer as a base material, completing processing of a silicon intermediate layer through spiral micro-channel etching, silicon through hole preparation, electroplating hole filling and back thinning; integrating the silicon optical chip and the electronic chip to the silicon interposer through the diamond micro bump array containing the copper core; installing a piezoelectric micropump at a corresponding fluid interface in the silicon intermediate layer, and filling adaptive liquid into the communicated flow channels in a vacuum environment; and after the reliability verification test is passed, carrying out system packaging by adopting an anti-static shielding bag. The CPO system adopting the packaging process has the advantages of high heat dissipation efficiency, ultrahigh integration precision and strong environmental adaptability.

The invention relates to a photovoltaic monocrystalline silicon material resistivity uniformity evaluation method, and belongs to the technical field of photovoltaic material detection. The method comprises the following steps: evaluating all-form resistivity and doping uniformity of a photovoltaic single crystal silicon rod, a single crystal silicon wafer and a single crystal silicon square wafer; carrying out standardized point distribution on the monocrystalline silicon wafer by using a concentric circular ring and a small circle, and calculating in-plane uniformity by using a triple integral derivation equation; the monocrystalline silicon square pieces are distributed in the form of grid small squares, and in-plane uniformity is calculated by means of a triple integral derivation equation; and for the axial direction of the silicon rod, the uniformity is quantified by utilizing range and variance models through the resistivity of the head, middle and tail wafers. Meanwhile, a continuous grid is generated through interpolation, and a 3D color mapping curved surface diagram with plane projection is drawn to visually present distribution. According to axial and in-plane uniformity results, silicon wafers are classified and graded, the doping uniformity of monocrystalline silicon is accurately reflected, and a support is provided for quality control, process optimization and silicon wafer sorting of photovoltaic monocrystalline silicon.

The invention provides a cutting height adjusting method and device of a cutting knife, wafer processing equipment and a medium, and relates to the technical field of wafer processing equipment.The method comprises the steps that the surface height difference between a sample silicon wafer on an auxiliary workbench and a to-be-processed wafer on a main working disc is measured; after the cutting knife cuts the sample silicon wafer to form a cutting mark, calculating a cutting depth value corresponding to the cutting mark; calculating the surface height information of the sample silicon wafer according to the cutting depth value of the cutting mark and the height information corresponding to the lowest point of the cutting knife when the cutting knife cuts the sample silicon wafer on the auxiliary workbench; and according to a preset cutting depth value, the surface height information of the sample silicon wafer and the surface height difference between the sample silicon wafer on the auxiliary workbench and the to-be-processed wafer, target cutting height information of the cutting knife when the cutting knife cuts the to-be-processed wafer is determined. After the height of the cutting knife is adjusted according to the target cutting height information, the cutting mark cut by the cutting knife has high-precision cutting depth.

The invention relates to a preparation method of a silicon single crystal rod and a silicon wafer. Comprising a melting stage, a temperature adjusting stage, a welding stage, a seeding stage, a shouldering stage, an equal-diameter stage, an ending stage and a breaking stage which are carried out in sequence, in the equal-diameter stage, the pulling speed is controlled to be within a first pulling speed range, and the solid-liquid interface temperature gradient is controlled to be within a first gradient range; wherein the range of the first pulling speed ranges from 0.5 mm / min to 1.1 mm / min; the first gradient range is 3 DEG C / cm to 5 DEG C / cm. By reducing the temperature gradient of a solid-liquid interface and lowering the crystal pulling rate, the stability of a thermal field is enhanced, and sufficient conditions are provided for the composite reaction of Sii and V, so that the impurity capturing efficiency is improved, the internal purity of the crystal is improved, and the impurities are effectively removed.

The invention belongs to the technical field of back contact cells, and particularly relates to a back contact cell manufacturing method for improving passivation performance and a back contact cell thereof, and the method comprises the steps: S2, depositing a first semiconductor layer and a phosphorosilicate glass layer on the back surface of a silicon wafer, and reserving the first semiconductor layer and the phosphorosilicate glass layer as a first mask layer; s3, performing texturing cleaning on the front surface of the silicon wafer; the first mask layer is removed in the final cleaning process after texturing; s4, forming a passivation layer and an anti-reflection layer on the front surface of the silicon wafer; s5, coating the back surface to form a second mask layer; s6, forming a second semiconductor opening region; and S7, texturing or polishing the second semiconductor opening area on the back surface, and cleaning by using an HF solution with the mass concentration of 0.5%-5% to remove the second mask layer and the winding plating layer generated in the front surface coating process in the S4. The back surface winding plating layer does not need to be removed, damage to the first semiconductor layer and the front surface film layer can be avoided, the overall passivation level can be improved, and therefore the battery efficiency is improved.

The invention discloses a rotary carrying working platform for a hold-down tool of a battery piece, relates to the technical field of carrying working platforms, and solves the problem of low efficiency of rotary carrying operation of the battery piece. And meanwhile, the problems that the precision is low and wrong welding is easy to occur when the battery piece hold-down clamp and the silicon wafer are subjected to series welding are solved. The invention discloses a rotary carrying working platform for a hold-down clamp of a battery piece. The rotary carrying working platform comprises an equipment substrate, the lifting conveying assemblies are mounted on the two sides of the top of the equipment base plate; the rotary carrying platform structure is mounted in the center of the top of the equipment base plate and located between the two lifting conveying assemblies; and the suction pressure clamp is magnetically fixed at the top of the lifting conveying assembly. According to the invention, the efficiency can be doubled, meanwhile, the position correction operation can be automatically carried out on the battery piece hold-down tool and the silicon wafer structure, the accuracy of series welding of the battery piece hold-down tool and the silicon wafer is ensured, and the problem that the quality of the battery piece is influenced by wrong welding and the like is avoided.

The invention provides a model training method, a silicon wafer processing method, a silicon wafer processing device, a storage medium and equipment. The model training method comprises the following steps: acquiring initial state information and target state information of a silicon wafer to be processed; through an action decision model, according to the initial state information and the target state information, machining action information for the machining machine table is generated; determining an award parameter corresponding to the processing action information, wherein the award parameter represents the processing quality and efficiency when the processing machine processes the to-be-processed silicon wafer based on the processing action information; if the reward parameter is not more than the preset condition, updating the initial action decision model according to the reward parameter to obtain an updated action decision model; and based on the updated action decision model, returning to execute the step of generating the processing action information through the action decision model according to the initial state information and the target state information until the reward parameter is greater than the preset condition, and obtaining a target action decision model. According to the invention, the processing machine table can be accurately adjusted.

The invention relates to the technical field of semiconductor processing, and particularly discloses silicon wafer cleaning equipment which comprises a cleaning tank; the carrying table is arranged in the cleaning tank; the driving part is connected with the carrying platform and is used for driving the carrying platform to do reciprocating rectilinear motion in the vertical and horizontal directions; the supporting plate is arranged on the carrying table, the supporting plate is elastically connected with the carrying table, and the supporting plate and the carrying table can generate relative displacement in the horizontal direction; the cleaning box is separably arranged on the supporting plate and used for containing a plurality of silicon wafers, and liquid can pass through the four sides of the cleaning box. The silicon wafer cleaning device can drive a silicon wafer to ascend, descend and horizontally move in the cleaning tank, the contact degree between the silicon wafer and cleaning liquid is improved, and therefore the cleaning effect is improved.

The invention provides a preparation method of a surface structure of a back contact battery, which relates to the technical field of back contact batteries, and comprises the following steps: S1, carrying out double-sided polishing on the surface of a silicon wafer: firstly carrying out rough polishing, removing a damaged layer on the surface of the silicon wafer, then cleaning with acid and ozone, then carrying out fine polishing, then cleaning with a mixed solution of hydrogen peroxide and alkali, and then carrying out acid pickling with ozone, then cleaning with a mixed solution of acid and hydrogen peroxide, and finally washing and drying; sequentially depositing a tunneling oxide layer and amorphous silicon on a single surface at high temperature; and performing high-temperature diffusion on the surface to form a crystallized first semiconductor region and a mask layer BSG. According to the invention, the specific suede structure is formed on the front surface, and the polished surface is formed on the back isolation base region, so that high reflectivity of the back isolation base region is ensured, the specific suede structure on the front surface can be independently designed, and meanwhile, a double-surface ozone oxidation process is added; therefore, the open-circuit voltage and the short-circuit current of the cell are improved, and the photoelectric conversion efficiency of the cell is improved.

An unloading device (3) and an inspection line. The unloading device (3) comprises a conveyor mechanism, an unloading mechanism (31) and stacking mechanisms (32), wherein the conveyor mechanism comprises two groups of parallel material-conveying assemblies (33); the unloading mechanism (31) comprises a support (311) and two unloading conveyor belts (312) arranged on the support (311), the two unloading conveyor belts (312) correspond to the two groups of material-conveying assemblies (33) on a one-to-one basis, each unloading conveyor belt (312) is arranged above the corresponding material-conveying assembly (33), and the support (311) is provided with a plurality of suction members (313) corresponding to each unloading conveyor belt (312); and each unloading conveyor belt (312) is correspondingly provided with a stacking mechanism (32), the stacking mechanism (32) is arranged at the end of the unloading conveyor belt (312) away from the corresponding material-conveying assembly (33), the stacking mechanism (32) comprises a receiving base plate (321), and the receiving base plate (321) is configured to stack products. The unloading device (3) and the inspection line can convey each inspected silicon wafer to the corresponding stacking mechanism (32), thereby completing the unloading operation of silicon wafers; moreover, the structure is simple, and the utilization rate and efficiency of the inspection line can be further improved.

The invention relates to the technical field of semiconductor material precision machining, and discloses a 12-inch silicon wafer double-sided polishing upper and lower surface removal amount monitoring system and method, and the system comprises a macroscopic thickness monitoring unit, a microcosmic contact state decoupling sensing unit and a data processing controller. The method comprises the following steps: synchronously acquiring a total thickness signal of a silicon wafer, an acoustic emission signal of an upper / lower fixed disc side and a fluid dynamic pressure signal; the method comprises the following steps: constructing a lubrication state correction coefficient by utilizing fluid dynamic pressure, and carrying out nonlinear correction on a mechanical friction energy index extracted by acoustic emission to obtain an effective vector removal index representing real cutting capacity; and the removal distribution ratio of the upper surface and the lower surface is calculated, and the independent absolute removal amount of the upper surface and the lower surface is obtained through decoupling in combination with the total thickness variation. According to the method, by eliminating the interference of a fluid'water cushion effect 'on a friction signal, visualization and closed-loop feedback control of a single-face removal behavior in the double-face polishing process are achieved, and the problem of silicon wafer warping caused by removal asymmetry is effectively solved.

The invention discloses conductive silver paste for a solar cell and application of the conductive silver paste, and belongs to the technical field of conductive silver paste. According to the invention, the prepared silver paste is printed on a silicon wafer cell in a silk-screen printing manner, so that the good rheological property of printing can be obtained. And a rheometer is introduced for testing, and an SEM scanning electron microscope is introduced for checking the surface appearance of the silver grid line. The invention discloses a TOPCon silicon wafer for a silicon solar cell, which comprises the following components in percentage by weight: 82-90% of silver powder, 20-30% of glass powder and 20-30% of organic carrier. 2-5% of glass powder; and 8-13% of an organic carrier. The conductive silver paste with good rheological property is prepared by using a mixture of polyamide wax and hydrogenated castor oil in a mass ratio of 1: 1 as a thixotropic agent. The main grid silver paste for the silicon solar cell provided by the invention can be well matched with step-by-step printing of a cell piece, different proportions of the binder and the thixotropic agent are used, the photoelectric conversion efficiency is high, the peeling strength of the main grid is high, and the step-by-step printing main grid paste requirements of current different types of paste and cell pieces can be well met.

The invention relates to a method and device for controlling the nanometer morphology of a double-sided thinned silicon wafer, and the method comprises the steps: obtaining the warping degree data of each position on the double-sided thinned silicon wafer, and obtaining a warping degree data curve; performing multi-stage differential smoothing processing on the warping degree data curve to obtain morphology parameters of the silicon wafer after double-sided thinning; and comparing the morphology parameters of the silicon wafer after double-sided thinning with a preset morphology parameter threshold value, and adjusting parameters of double-sided thinning equipment according to a comparison result. Batch production of defective products can be avoided.

The invention discloses intermediate processing equipment for a negative photoresist coating process, and relates to the technical field of photoresist coating related auxiliary equipment for chip production, and the intermediate processing equipment comprises a first curing tunnel, a second curing tunnel, a pair of detection assemblies, a pair of translation assemblies and an overturning assembly. The first curing tunnel is provided with a plurality of silicon wafer inlet and outlet assemblies. The second curing tunnel is arranged on one side of the first curing tunnel in parallel. And the detection assembly is used for measuring the thickness of the photoresist on the silicon wafer. The translation assembly is used for moving the silicon wafer between the first curing tunnel and the second curing tunnel. The overturning assembly is used for transferring the silicon wafer from the conveying tail end of the second conveying belt conveyor to the conveying starting end of the first conveying belt conveyor and overturning the silicon wafer at the same time. According to the invention, thickness detection can be carried out while a large number of silicon wafers of which the front surfaces are coated with photoresist are cured, the silicon wafers are translated or overturned between the two curing tunnels, and the silicon wafers of which the back surfaces can be coated with the photoresist are sent back to a photoresist coating machine in time.

The present invention discloses a tellurium-lead-lithium oxide glass powder for BC cell N-region conductive paste and its preparation method, belonging to the field of photovoltaic silver paste. The glass powder adopts components with high Pb, Te, and Li: aTeO2 - bPbO - cLi2O - dBi2O3 - eWO3 - fZnO - gSiO2 - hNa2O; where a + b + c + d + e + f + g + h = 1, 0.2 < a < 0.4, 0.1 < b < 0.4, 0.1 < c < 0.25, 0 < d < 0.1, 0 < e < 0.1, 0 < f < 0.1, 0 < g < 0.1, 0 < h < 0.05, and a + b > 0.5, and the ratio of c to h is (3 - 10):1. By controlling the specific Pb, Te, and Li contents and the specific Li / Na ratio in the present invention, a strong corrosion effect on the poly layer of the cell is achieved, enabling more silver ions dissolved in the glass liquid to recrystallize on the surface of the silicon wafer, thereby achieving good ohmic contact.

The utility model discloses semiconductor process equipment, which comprises a chamber module (100) and a transmission device (200), the chamber module (100) comprises a plurality of process chambers, and the plurality of process chambers comprise a first process chamber (101), a second process chamber (102), a third process chamber (103) and a fourth process chamber (104); the transmission device (200) is used for conveying a silicon wafer, so that the silicon wafer sequentially passes through the first process chamber (101), the second process chamber (102), the third process chamber (103) and the fourth process chamber (104) to be processed; the chamber module (100) comprises at least one stack type chamber structure, and the stack type chamber structure comprises at least two process chambers which are stacked in sequence. According to the scheme, the problem of large occupied area of semiconductor process equipment in the prior art can be solved.

The invention discloses a cutting and polishing combined machining treatment method suitable for polycrystalline silicon. The method comprises the following steps: step 1, silicon ingot pretreatment: loading historical process data of a silicon ingot in combination with a block chain technology, generating a machining parameter packet, and issuing the machining parameter packet to cutting and polishing equipment to form a machining quantization instruction set; a plasma channel is formed through combination of femtosecond laser focusing and high-frequency electromagnetic field constraint for cutting, annular laser is synchronously used for deep micro-area fusion polishing, and the surface roughness of the cut silicon wafer is reduced by means of argon protection and the surface tension self-leveling effect; 3, polishing: immersing the anode of the silicon wafer into TEMPO / [EMIM] [BF] electrolyte, and regulating and controlling by using pulse voltage; 4, cleaning and drying, wherein megasonic assisted nanobubble ultrapure water is adopted for flushing, and Malangori drying is carried out; and 5, quality control: verifying the surface appearance and the subsurface defect density, and carrying out secondary processing flow on the abnormal silicon wafer.

The invention provides a multi-slice high-speed series welding machine device which comprises a complete machine and further comprises an input part at the head section of the complete machine, a strip winding part is arranged in the input part, and a welding part is arranged in the middle section of the complete machine. The welding part comprises a silicon wafer transmission unit, a silicon wafer connection unit, a pressing net input unit, a pressing net body, a glue injection unit, a pressing net backflow unit, a welding unit and a belt manufacturing unit which are arranged on one side of the belt winding part, and a welding output part is arranged at the tail section of the whole machine; the pressing net body comprises an outer frame structure, a pressing strip, a gluing structure, a glue storage structure and a glue filling structure which are arranged on the pressing net backflow unit, through the double-rail design, the two battery piece connecting modules and the drawstring assembly which are arranged in parallel are adopted, welding of double-row battery strings is completed cooperatively, and compared with a traditional single-row welding mode, the welding efficiency is remarkably improved, and the production cost is reduced. And through optimization of material distribution, net pressing backflow, feeding carrying and the like, efficient operation and continuous production of the equipment are guaranteed, and the device is particularly suitable for large-scale and efficient battery piece welding operation.

The present invention discloses a four-position full-cell solar silicon wafer printer, including a base, an infeed guide rail, a detection camera assembly, a turntable assembly, a lifting module, a UVW correction alignment mechanism, and an outfeed guide rail. The UVW mechanism comprises two Y-axis modules, one X-axis module, a printing platform, a steel mesh frame, and a printing squeegee kit. The Y / X-axis modules are under the platform, their drive ends connected to the steel mesh frame. The squeegee kit moves left-right on the platform. It uses the Y / X-axis modules and detection camera to realize X, Y, θ three-axis motion, ensuring steel mesh-silicon wafer alignment and optimizing printing directions.

The invention discloses an AOI back inspection reflection inhibition method based on black flannelette pasting, and relates to the technical field of AOI detection, and the method comprises the steps: placing a to-be-detected silicon wafer on a silver gray aluminum material carrying platform; starting the AOI equipment to collect a background image; black flannelette is selected as a reflection inhibition material; black flannelette is attached to the center detection area of the silver gray aluminum material carrying table, and the light source perpendicular incidence area is of a double-layer structure formed by combining a bottom-layer reflective sticker and surface-layer black flannelette. After surface mounting is completed, the background image is collected again; and performing defect identification on the acquired background image, and outputting a detection report. According to the invention, through the physical light absorption characteristic of the black flannelette, the average gray value of the reflection area of the carrying platform is reduced, the high-intensity mirror reflection interference is effectively eliminated, the difference between the background gray level and the edge gray level of the silicon wafer after mounting is obvious, image analysis software can realize accurate edge searching by setting the minimum identification gray level threshold, and meanwhile, the edge searching precision is improved. The black flannelette can improve the background gray scale stability and reduce the interference of gray scale fluctuation on a threshold segmentation algorithm.

The utility model relates to the technical field of silicon wafer cleaning, in particular to a silicon wafer cleaning flower basket which comprises two supporting side plates, two supporting bottom plates, two connecting plates and a plurality of supporting strips, the two supporting side plates are oppositely arranged in parallel, the supporting bottom plates are arranged at the bottoms of the supporting side plates respectively, and the connecting plates are connected with the supporting strips. The connecting plates are connected between the two supporting side plates, the two ends, opposite to each other, of the supporting side plates are each provided with one connecting plate, the supporting strips are connected to the supporting side plates, the multiple supporting strips are evenly distributed in the length direction of the supporting side plates, protrusions are integrally formed on the supporting strips, and the protrusions are arranged on the supporting side plates. The protrusions are located on the opposite surfaces of the two supporting strips, the protrusions are arranged in a semi-cylindrical shape, the multiple protrusions are evenly distributed in the length direction of the supporting side plate, and an elastic buffer layer is arranged between every two adjacent supporting strips. According to the invention, the problem that the production efficiency and the product quality are affected due to the fact that the silicon wafers are adhered to the flower basket is solved.

The utility model is suitable for the technical field of solar cells, and provides a back contact solar cell, a cell assembly and a photovoltaic system. The back contact solar cell comprises a silicon wafer, the silicon wafer is provided with a front surface and a back surface which are oppositely arranged, the back surface comprises a first doped region, the first doped region is a P-type doped region or an N-type doped region, the first doped region is provided with a suede, the suede comprises a plurality of cone-like structures, each cone-like structure is provided with a conical surface and a conical top, and a concave part is formed at the joint of the adjacent cone-like structures; and the thickness of the first doping layer in the concave part is greater than the thickness of the first doping layer in the cone top. According to the back contact solar cell of the utility model, the thickness of the first doping layer at the concave part is greater than the thickness of the first doping layer at the cone top, so that the thickness distribution of the doping layers on the suede surface is more beneficial to the improvement of the cell efficiency.

The invention belongs to the technical field of semiconductor material detection, and particularly relates to a method for representing micro-defects of a near-perfect czochralski silicon wafer by regulating and controlling near-surface copper concentration. The invention discloses a method for representing micro-defects of a near-perfect czochralski silicon wafer by regulating and controlling the concentration of near-surface copper. The method specifically comprises the following steps: (S.1) cleaning the silicon wafer and immersing the silicon wafer into a copper nitrate solution for standing; (S.2) rinsing the silicon wafer with ionized water, taking out the silicon wafer and airing the silicon wafer; (S.3) performing high-temperature heat treatment on the silicon wafer for a period of time, and quickly cooling; (S.4) carrying out chemical polishing on the cooled silicon wafer; (S.5) horizontally placing the silicon wafer in the corrosive liquid; and (S.6) observing the surface of the silicon wafer by using an optical microscope or a scanning electron microscope so as to display the microdefects. According to the invention, copper precipitates at different depths are observed after copper is introduced at high temperature, so that the microdefect condition of the silicon wafer can be reflected. The method can clearly display the micro-defects in the nearly perfect czochralski silicon wafer, and has high detection efficiency and accuracy. The method is easy to operate, low in cost and suitable for silicon wafer microdefect detection in large-scale production.

The invention provides a photovoltaic monocrystalline silicon wafer and a solar cell comprising the same, and belongs to the technical field of solar cells, in particular to the technical field of photovoltaic silicon wafers. The resistivity of the silicon wafer is 50 to 500 omega.cm; the oxygen content of the silicon wafer is less than or equal to 8 * 10 < 17 > atom / cm < 3 >, preferably 1.5 * 10 < 17 > to 6 * 10 < 17 > atom / cm < 3 >. A battery prepared from the silicon wafer provided by the invention is high in photoelectric conversion efficiency concentration ratio.

The invention discloses an unsupervised silicon wafer surface defect detection method and device based on hierarchical clustering, relates to the field of image processing and computer vision, and utilizes an unsupervised clustering technology to detect silicon wafer surface defects. The method comprises the following steps: extracting multi-scale features from a plurality of normal silicon wafer images through a pre-trained convolutional neural network; integrating the multi-scale features of the plurality of pictures by adopting a hierarchical fusion strategy; constructing a feature memory library by using a clustering algorithm, and generating a clustering center; generating patch features for the test image through a consistent fusion process; through comparative supervision, normal patches are close to a clustering center, and abnormal patches are pushed away; calculating the distance between the patch and the clustering center, and judging abnormity; and mapping the position of the abnormal patch, and positioning scratches, cracks, pollution or recesses. According to the method, through an unsupervised mode, a large amount of defect labeling data is not needed, the data preparation cost is effectively reduced, and the accuracy and robustness of silicon wafer surface defect detection are remarkably improved.

The invention discloses an atomic layer deposition method and structure for an aluminum fluoride enhanced aluminum oxide passivation layer of a TOPCon solar cell. The method comprises the steps that after a boron-doped layer is formed on the front face of a crystal silicon wafer, a passivation layer is formed on the boron-doped layer through an atomic layer deposition technology, specifically, Al2O3 deposition circulation is conducted with trimethyl aluminum as an aluminum source and H2O as an oxygen source, AlF3 deposition circulation with aluminum chloride as the aluminum source and HF or NH4F as a fluorine source is periodically inserted, the proportion of the number of deposition circulation times of AlF3 to the number of deposition circulation times of Al2O3 is 1: (1-10), and the passivation layer is formed on the boron-doped layer through the atomic layer deposition technology. And an alternating layer structure with the total thickness of 5-10 nm is formed. According to the invention, an AlF3 layer is periodically inserted in an Al2O3 deposition cycle, so that an Al2O3 / AlF3 superlattice structure is formed. According to the structure, the interface passivation effect is remarkably improved, hydrogen atom overflow is reduced, and the ultraviolet aging resistance is enhanced. The method is compatible with an existing ALD production line, is suitable for high-efficiency TOPCon battery manufacturing, and has a good industrial application prospect.

The application discloses a silicon wafer cutting method and a silicon wafer, relates to the technical field of silicon wafer cutting, and is used for reducing the damage of a cutting line to a silicon wafer in the process of lifting the silicon wafer. The silicon wafer cutting method comprises the following steps: providing a silicon rod and a carrier plate; driving the silicon rod to move downward relative to a cutting line, so that the cutting line cuts the silicon rod to obtain a plurality of silicon wafers; and lifting the silicon wafers upward relative to the cutting line, wherein the movement mode of the cutting line in the carrier plate and the movement mode of the cutting line after the cutting line is separated from the carrier plate are different.

The utility model discloses a silicon wafer drying device, and relates to the field of photovoltaic technology. The silicon wafer drying device comprises a conveying mechanism and a drying mechanism, the conveying mechanism is used for bearing and conveying silicon wafers, the conveying mechanism is provided with a first conveying section and a second conveying section which are sequentially arranged in the silicon wafer conveying direction, and the silicon wafers have different inclination directions when being borne by the first conveying section and the second conveying section. And the drying mechanism is used for drying the silicon wafers on the conveying mechanism. As the silicon wafers have different inclined directions when being carried by the first conveying section and the second conveying section, even if the silicon wafers are conveyed on the first conveying section, dead angles which are difficult to dry possibly exist, but when the silicon wafers are conveyed to the second conveying section, water in the dead angles possibly flows out or the dead angles are exposed, so that the silicon wafers are not dried. And the dead angles are easily dried in the second conveying section. Therefore, according to the silicon wafer drying device provided by the embodiment of the invention, the inclination angle of the silicon wafer is adjusted in the drying process, so that the overall drying effect is improved.