4738 results about "Silicon chip" patented technology

A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is less than or closely matches that of the substrate. The conductive structure may include concentric via fill areas having differing materials disposed concentrically therein, a core of the substrate material surrounded by an annular ring of conductive material, a core of CTE-matched non-conductive material surrounded by an annular ring of conductive material, a conductive via having an inner void with low CTE, or a full fill of a conductive composite material such as a metal-ceramic paste which has been sintered or fused.

A semiconductor package of this invention has an insulating substrates, wiring layers disposed on the surface of the insulating substrate, a semiconductor chip disposed in a device hole provided in the insulating substrate, inner-joint-conductors for connecting at least part of the bonding pads on the surface of the semiconductor chip to the corresponding inner-joint-conductors and connection lands connected to the wiring layers. The device hole is provided so that it goes through the center of the insulating substrate. The semiconductor chip is thinner than the insulating substrate. Then, this semiconductor chip is disposed in the device hole such that a bottom thereof is flush with a bottom plane of the insulating substrate. Further, this invention provides a MCM in which plural pieces of the thin semiconductor packages are laminated. In the MCM, the semiconductor packages are laminated such that top and bottom faces of the thin silicon chip are inverted. Predetermined connection lands are electrically connected to each other through a connecting conductor. This MCM has a high mechanical strength in its stacked structure and there is a low possibility that crack may occur in the package due to stress in the bending direction.

Conductive through vias are formed in electronic devices and electronic device carrier, such as, a silicon chip carrier. An annulus cavity is etched into the silicon carrier from the top side of the carrier and the cavity is filled with insulating material to form an isolation collar around a silicon core region. An insulating layer with at least one wiring level, having a portion in contact with the silicon core region, is formed on the top side of the carrier. Silicon is removed from the back side of the carrier sufficient to expose the distal portion of the isolation collar. The core region is etched out to expose the portion of the wiring level in contact with the silicon core region to form an empty via. The via is filled with conductive material in contact with the exposed portion of the wiring level to form a conductive through via to the wiring level. A solder bump formed, for example, from low melt C4 solder, is formed on the conductive via exposed on the carrier back side. The process acts to make the conductive via fill step independent of the via isolation step.

An acoustic transducer comprising a substrate; and a diaphragm formed by depositing a micromachined membrane onto the substrate. The diaphragm is formed as a single silicon chip using a CMOS MEMS (microelectromechanical systems) semiconductor fabrication process. The curling of the diaphragm during fabrication is reduced by depositing the micromachined membrane for the diaphragm in a serpentine-spring configuration with alternating longer and shorter arms. As a microspeaker, the acoustic transducer of the present invention converts a digital audio input signal directly into a sound wave, resulting in a very high quality sound reproduction at a lower cost of production in comparison to conventional acoustic transducers. The micromachined diaphragm may also be used in microphone applications.

A biometric access control and time and attendance system comprises an integrated network including one or more remote access devices in electronic communication with a computer database. Each remote access device comprises a silicon chip based system and preferably includes a biometric input device, a liquid crystal display (LCD), computer processing capabilities based on embedded system architecture with configurable system-on-chip (CSOC) technology, and an electrical output for controlling a door lock or the like. The use of CSOC architecture in lieu of conventional personal computer technology (e.g. mother boards, hard drives, video controllers and the like) allows for a more compact and cost efficient design. A plurality of remote access devices is configured for communication with a primary computer database wherein data corresponding to biometric samples for all authorized users is stored. In an embodiment wherein the biometric input devices comprise fingerprint scanners, the devices are configured to facilitate fingerprint identification by incorporating an auto-targeting capability that enables the user to simply place his or her finger on the fingerprint scanner whereafter the system adjusts the scanned image by automatically shifting the scanned image data to a properly targeted position thereby enabling the system compare the scanned print to the biometric samples in the system's data storage memory. Auto-targeting capability eliminates the requirement for manual targeting present in systems of the background art thereby improving system performance and minimizing reliance on human interaction. The present invention contemplates the use of auto-targeting with other biometric systems, such as facial recognition and/or retinal scanning systems, or any other biometric identification technology.

A high speed bidirectional data rate conversion circuit converts 1× data rate signals from attached devices on port A and port B to 2× data rate signals on bus C and further converts 2× high speed data rate signals on bus C to 1× data rate signals on ports A and B for memory devices attached to ports A and B. The usage of pass gate switches and combination of latches and counters is used to permit proper synchronization of the data signals, and to further generate strobe signals at both system bus and memory bus sides, and to further generate data mask signals for writing to the memory bus side of the circuit. The collection of such switching elements and latches are provided on a single silicon chip which includes of the functions of the invention.

The invention discloses a preparation method of a graphene-carbon nanotube compound film based on a three-dimensional network appearance. The method comprises the step of: transferring and stamping graphene and a carbon nanotube onto glass, a tantalum sheet, a silicon chip, a stainless steel plate or a polyethylene glycol terephthalate substrate in the mass ratio (1-10):1 through spraying deposition or vacuum suction filtration, wherein the grapheme is graphene oxide prepared by using an improved Hummers method; and a preparation method of a carbon nanotube solution comprises the following steps of: mixing acids; dispersing surfactants such as sodium lauryl sulfate, sodium dodecyl benzene sulfonate and hexadecyl trimethyl ammonium bromide in an auxiliary way, and the like. The graphene-carbon nanotube compound film prepared by adopting the method has the advantages of adjustable transmission and surface resistance, high uniformity, high stability, simple preparation method process and the like, and can be loaded on a rigid substrate as well as a flexible substrate.

A device and method for hermetically sealing a medical device is provided. In one aspect, a silicon device is coupled to a sensor, such as a pressure transducer, which benefits from having direct contact with its environment, which in many cases, is the human body. Thus, a method to hermetically seal the non-sensing portion of a silicon device while allowing the sensing portion (e.g. the pressure transducer) to have direct contact with the body is provided. In one aspect, a silicon chip, a gold preform and a metallic housing are each primed for sealing and are assembled. The assembly is then heated to react the gold preform to the silicon chip and to form a molten gold-silicon alloy in-situ to bind the metallic housing to the non-sensing portion of the silicon chip. In this way, the non-sensing portion of the silicon chip is hermetically sealed and protected from exposure, while still permitting exposure of the sensing portion to the environment.

A low-current FN channel scheme for erase, program, program-inhibit and read operations is disclosed for NAND NVM memories. This invention discloses a block array architecture and 3-step half-page program algorithm to achieve less error rate of NAND cell threshold voltage level. Thus, the error correction code capability requirement can be reduced, thus the program yield can be increased to reduce the overall NAND die cost at advanced nodes below 20 nm. As a result, this NAND array can still use the LV, compact PGM buffer for saving in the silicon area and power consumption. In addition, the simpler on-chip state-machine design can be achieved with the superior quality of less program errors.

The invention provides a method for manufacturing and integrating a multichannel high-sensitive biosensor. The method comprises the following steps: firstly, based on an SOI silicon chip, adopting a top-down method to manufacture an FET field effect transistor of a silicon nanometer wire; secondly, utilizing polydimethylsiloxane (PDMS) to manufacture a plurality of microfluid channels; and finally, modifying the silicon nanometer wires in different microfluid channels to allow the silicon nanometer wire to be modified with different detecting antibodies and small molecules for detecting different target molecules. The sensor manufacture by the method can be used for simultaneously detecting relevant factors (such as DNA, RNA, protein and the like) or virus of different types of diseases and has the characteristics of high sensitivity, stability, easy integration and the like.

The invention belongs to the technical field of preparing the surface of a composite structure, and in particular relates to a method for preparing super-hydrophobic antireflective silicon surface with a micron and nanometer composite structure. The method comprises the following steps: cleaning a silicon chip; preparing a micron-level silicon island and a gridding structure on the surface of the silicon chip; carrying out catalytic etching taking silver or aurum nanoparticles as blockage; obtaining the surface of the micron and nanometer composite structure; and carrying out chemical modification of the surface of the composite structure. A static contact angle between the super-hydrophobic antireflective material surface prepared by the method and water is more than 150 degrees, and a static rolling angle of water is less than 3 degrees. The surface has superior antireflective performance, and in particular, the light reflectivity within the wavelength range between 800 and 1,100 nm is less than 3 percent. With application of the method, the super-hydrophobic antireflective silicon surface of the micron and nanometer composite structure can be produced on scale, can be widely applied to a solar cell, a microfluidic chip, a photoelectric device, and the like, and has good industrial application prospect.

The invention relates to an integrated silicon chip for testing acceleration, pressure and temperature, and the manufacturing method thereof. The invention is characterized in manufacturing the pressure sensor, temperature sensor and accelerometers of thermoelectric pile on to one chip by the same micro processing technology. The acceleration is detected by adopting thermal convection type accelerometers, using polysilicon resistor as heater, using a thermoelectric pile composed of two pairs of metals (such as aluminium and tungsten-titanium) and P type or N type polysilicon to detect the temperature difference in the sealed cavity caused by acceleration. The high accurate absolute pressure sensor is manufactured by using silicon nitride film with low stress as the core structure layer of the pressure sensor chip, and forming force sensitive resistor track by polysilicon film, forming vacuum reference cavity by TEOS bolt in LPCVD furnace. At the same time, the temperature sensor is composed by using polysilicon thermistor to detect temperature change. The integrated chip achieves the advantages of microminiaturization, low cost, high precision, high reliability and high stability.

A step-by-step projection photo-etching machine double shift exposure ultra precise positioning silicon chip bench system, comprising a silicon chip bench positioning unit operating in the exposure station, and a silicon chip bench positioning unit operating in the preliminary treatment station, each positioning unit includes a silicon chip carrying device. The system can increase the exposure efficiency without the problem of overlapping and interference in the working space. It also realizes simplified structure, and high reliability and positioning precision.

An IR detector in the form of a thermopile including one or more thermocouples on a dielectric membrane supported by a silicon substrate. Each thermocouple is composed of two materials, at least one of which is p-doped or n-doped single crystal silicon. The device is formed in an SOI process. The device is advantageous as the use of single crystal silicon reduces the noise in the output signal, allows higher reproducibility of the geometrical and physical properties of the layer and in addition, the use of an SOI process allows a temperature sensor, as well as circuitry to be fabricated on the same chip. The detector can also have an IR filter wafer bonded onto it and/or have arrays of thermopiles to increase the sensitivity. The devices can also be integrated with an IR source on the same silicon chip and packaged to form a complete and miniaturised NDIR sensor.

A cylindrical bonding structure and its method of manufacture. The cylindrical bonding structure is formed over the bonding pad of a silicon chip and the chip is flipped over to connect with a substrate board in the process of forming a flip-chip package. The cylindrical bonding structure mainly includes a conductive pillar and a solder cap. The conductive pillar is formed over the bonding pad of the silicon chip and the solder cap is attached to the upper end of the conductive pillar. The solder cap has a melting point lower than the conductive pillar. The solder cap can be configured into a cylindrical, spherical or hemispherical shape. To fabricate the cylindrical bonding structure, a patterned mask layer having a plurality of openings that correspond in position to the bonding pads on the wafer is formed over a silicon wafer. Conductive material is deposited into the openings to form conductive pillars and finally a solder cap is attached to the end of each conductive pillar.

The invention discloses a silicon chip shallow trench isolation etching method which is used for etch groove on silicon. The method comprises the following steps: A. upper layer silicon etching step; B. oxide layer etching step, which is used for etching the oxide layer between upper layer silicon and base silicon and is also used for etching partial base silicon for the top fillet etching preparation; C. base silicon etching step which is used for etching groove on silicon base and to form slippery top fillet at the junctional position of oxide layer and silicon base on the sidewall of groove. The etching process gas used in the Step B is mixed gas consisting of HBr gas and CHF3 gas. The etching process gas is ionized into active groups like Br*, CHF*, etc., and can form the top fillet during Step C. The method has the advantages of simple process with less steps, low cost and slippery top fillet formation of etching groove, and is applicable to shallow trench isolation etching and other etchings of various type of semiconductor silicon wafers.

The invention relates to a producing method of a selective emitter double-faced PERC crystalline silicon solar cell. The producing method is characterized by comprising the first step of removing affected layers of a silicon chip and conducting texturization and cleansing on the silicon chip, the second step of conducting diffusion to form a pn junction and eliminating phosphorosilicate glass in positive side of the silicon chip and the pn junction in the reverse side of the silicon chip after the diffusion; the third step of conducting deposition of aluminum oxide/silicon nitride laminated passivated film on the reverse side of the silicon chip and conducting deposition of a silicon nitride antireflection film on the positive side of the silicon chip; the fourth step of using an optical maser to conduct routing on the reverse side of the silicon chip to obtain a routing slot; the fifth step of using a phosphorous source to coat the positive side of the silicon chip; the six step of conducting laser doping on the positive side of the silicon chip to obtain a main guard line and a subsidiary guard line doped with the laser; the seventh step of conducting photoinduction on electronickelling/copper/silver electrode, conducting connections between the reverse side of the cell with a cathode of an external power supply, conducting electroplating on the positive and reverse sides of the cell simultaneously, and conducting electroplating of three metals of nickel/copper/silver in sequence; the eighth step of conducting annealing on the electroplated cell. According to the producing method of the selective emitter double-faced PERC crystalline silicon solar cell, the problem that an aluminum grid line is hard to be aligned with a laser windowing grid when a silk screen is used to conduct reverse printing of the double-faced PERC cell is solved.

This document pertains generally to the field of nerve regeneration and more particularly to functional recovery after nerve injury or transection. For example, this document provides a silicon chip device coupled with field effect (or other types of) transistors, growth permissive chemical substrates, and trophic molecules that together can enable the rapid and successful regeneration of injured nerves. Such devices can be used to stimulate continually the transected target tissue to create an environment that is highly conducive to growth and reinnervation.

The invention is concerned with the making method of the selective emitter crystal silicon solar cell including high thickness doping diffusion. It is to form the electrode window on the silicon dioxide layer of the crystal silicon chip with the printer technique cauterant, next is to conduct high thickness doping diffusion in the POCl3 atmosphere of the electrode window sector. The invention is with low cost but high productivity.

The invention relates to a detecting system, in particular to a solar cell silicon chip detecting system. The detecting system comprises a silicon chip conveying device; the silicon chip conveying device is provided with a feeding area, an exposure area and a sorting area along the silicon chip conveying device in sequence; the feeding area is used for arranging the silicon chips on the silicon chip conveying device; the exposure area is provided with a detecting and imaging system arranged above the silicon chips and a limiting mechanism used for limiting the silicon chips; and the sorting area is used for putting the silicon chips with different weight into corresponding material-receiving box. Compared with the prior art, the system has the beneficial effects that by adopting the structure, the detecting system can realize sorting to the silicon chips by only needing arranging the silicon chips into a feeding box of the feeding area, and is simple and practical.

The invention discloses a maskless method for preparing black silicon by deep reactive ion etching, which comprises the following steps: performing initialization and plasma stability on equipment adopted by the method for preparing the black silicon so as to make plasma perform glow discharge; and controlling technological parameters for preparing the black silicon by deep reactive ion etching, and adopting etching and passivating modes to alternately process a silicon chip, wherein the parameters comprise plasma gas flow, panel etching power, panel passivating power, coil power, and etching and passivating cycle and temperature. The maskless method directly performs plasma processing on the surface of the silicon chip, and can generate large-range high-intensity nanostructures on the surface of the silicon chip in case of no nano mask by adjusting and selecting proper etching technological parameters. Meanwhile, the method for preparing the black silicon has high efficiency and low cost, and can be integrated with other micro-fabrication technology.

The invention discloses a method for cutting silicon chips, which comprises the following steps: controlling a pay-off spool driving motor, a take-up spool driving motor, a first guide wheel driving motor and a second guide wheel driving motor to rotate synchronously and inversely by a control system after the pay-off spool driving motor drives a pay-off spool to positively pay off wires for 250m-270m; and controlling the four motors to rotate positively again by the control system after the take-up spool driving motor drives a take-up spool to reversely pay off wires for 60m-70m. A silicon rod is cut back and forth in this way repeatedly like a saw blade dragging type, and because a cutting line moves forward for a certain distance and then moves backward for a certain distance, the utilization ratio of the cutting line is efficiently enhanced without breaking the cutting line. Because the silicon rod is cut back and forth, the thickness up and down each silicon chip is uneven when cutting the silicon rod positively, but the direction of each silicon chip can be effectively corrected in reverse cutting, and thus the thickness difference up and down each silicon chip is greatly reduced so as to enhance the quality of the silicon chips.

The waste cutting suspension recovering process features that the waste linear cutting sand pulp from silicon chip processing is multiple stage treated through the steps of solid-liquid separation, initial filtering of the suspension, final filtering of the suspension, and concentrating and drying of the suspension. The process has recovered polyethylene glycol-base or oil-base suspension possess performance the same as or near that of new material and capacity of being reused. The present invention raises material using efficiency, lowers silicon chip producing cost and avoids environmental pollution caused by exhausting waste linear cutting sand pulp.

The invention relates to a quasi-one-dimensional metal oxide nano-material biosensor and a method for manufacturing the same. The sensor comprises a silicon chip, a silicon dioxide oxidation layer grown on the silicon chip, a grid electrode, a source electrode, a drain electrode and a microfluid channel; and a quasi-one-dimensional metal oxide semiconductor nano-material is connected with the source electrode and the drain electrode to form a conduction channel. A process for the quasi-one-dimensional metal oxide nano-material biosensor comprises the following steps: firstly, synthesizing thequasi-one-dimensional metal oxide semiconductor nano-material; secondly, adopting a micro-nanometer photolithography standard process and a top-down method to manufacture the quasi-one-dimensional metal oxide semiconductor nano-material and a field effect transistor in array; thirdly, using polydimethylsiloxane to manufacture the microfluid channel; finally, performing surface modification on thequasi-one-dimensional metal oxide semiconductor nano-material, modifying a joining unilayer combined with a target molecule through a self-assembling method, and connecting biological molecules on the surface of the nano-material through joining molecules so as to detect a symbolic molecule of a disease. The quasi-one-dimensional metal oxide nano-material biosensor has the characteristics of rapid response, high sensitivity, strong selectivity, no labeled molecule and the like.

The invention relates to a preparation method for a graphene-based surface enhanced Raman scattering (SERS) probe. Compared with the traditional SERS probe using metal nanoparticle sol as an enhanced substrate, the SERS probe adopts a graphene-metal nanoparticle composite structure as a surface enhanced Raman substrate, wherein the SERS signal is obviously enhanced and the metal nanoparticles on the surface of the graphene are uniform and controllable. The main reason is that as gold nanoparticles exist on the surface of a silicon wafer dispersively, sufficient 'hot points' cannot be generated among the particles, and the gold nanoparticles gather on the surface of graphene oxide, the electromagnetic enhanced effect is achieved and stronger SERS effect is achieved.

The invention provides a silicon chip aligning semaphore acquisition and processing system. The system can achieve the functions of gathering, filtering, modulating and demodulation from light signal to electric signal in real-time, synchronizing gathering and processing of location data, satisfy silicon chip alignment function of light scribing device through fitting processing of sample-taking signal. The invention also provides a processing method fir silicon chip aligning signal. The method adapts high order non-linearity signal fitting mould to obtain firstly envelope parameter of sample-taking signal in multiplestep fitting processing method and translates high order non-linearity signal fitting mould into 1 order linearity mould to obtain phase information of sample-taking signal.

The invention provides a method for defect detection and surface measurement of a silicon wafer. According to the method, the phase-measuring deflectometry(PMD) is used for surface measurement of a silicon wafer. The PMD-based mirror object three-dimensional surface measurement method is a highly-sensitive, high-precision, quick and incoherent optical full-field measurement technology, and an experimental device is simple and mainly comprises a computer, a digital camera and a display screen. When the PMD is used for surface measurement of the silicon wafer, the surface gradient distribution of the silicon wafer can be directly obtained, the surface curvature distribution of the silicon wafer can be obtained so long as gradient derivation is performed, defects are detected through curvature distribution, the surface height data of the silicon wafer can be obtained through gradient integration, and accordingly, the three-dimensional shape can be observed. The invention has the main gain that the high-precision and quick full-field measurement technology is provided to realize surface defect detection and surface measurement of the silicon wafer.

The invention provides a novel light emitting diode (LED) encapsulation structure which directly adopts a silicon dice substrate as both a surface mounting bracket and a radiation channel of an integrated structure support of an LED chip; a front electrode connecting layer is arranged on the front surface of the silicon dice substrate; the front electrode connecting layer on the front surface of the silicon dice substrate is connected with an electrode metal bonding pad at the back of the silicon dice substrate through a lead of a silicon groove side-wall or a lead of a through-hole of the silicon dice substrate; and at least one LED chip is welded directly by flip-chip on the front electrode connecting layer of the silicon dice substrate with an optical source through a metal bump. The invention also provides a method for manufacturing the LED encapsulation structure. The invention avoids steps of die bonding and gold-wire welding and enhances the connection reliability of chips and especially the connection reliability of multi-chip modules; and the invention leads the encapsulation of high-power LED and especially the encapsulation of multi-chip module to be miniaturized and also leads power-supply drive and circuits of LED protection and the like to be integrated on the silicon dice so as to provide a systematic and integrated encapsulation proposal for high-power LED illumination.

The invention provides a deep silicon etching method. The method comprises a step of etching a silicon chip surface which is not covered by a photoresist layer first to form an etched surface and a side wall which is vertical to the etched surface basically; and the method also comprises the following steps of: a first depositing step, namely performing isotropic deposition for covering a barrierlayer on the etched surface, the side wall and the surface of the photoresist layer; a first etching step, namely performing anisotropic etching for removing the barrier layer covered on the etched surface so as to expose the etched surface, wherein the photoresist layer is prevented from being etched by the barrier layer covered on the photoresist layer; a second etching step, namely performing the isotropic etching for etching the exposed etched surface, wherein the side wall is prevented from being etched by the barrier layer covered on the side wall and the photoresist layer is not damaged in the isotropic etching; and repeating the depositing step, the first etching step and the second etching step circularly until reaching a predetermined etching depth. The method does not need complex equipment such as a low-frequency pulse power supply and the like, contributes to maintenance, and reduces equipment cost.

Methods and compositions for electro-chemical-mechanical polishing (e-CMP) of silicon chip interconnect materials, such as copper, are provided. The methods include the use of compositions according to the invention in combination with pads having various configurations.