246 results about "Wafer stacking" patented technology

The invention relates to the technical field of semiconductor manufacturing, in particular to an automatic loading and unloading control system for semiconductor material plates. A clamping force dynamic control module; the path planning and obstacle avoidance module is used for dividing safety levels of loading and unloading areas on the basis of material plate stacking parameters, and generating an obstacle avoidance track by adopting an improved path search algorithm; optimizing an acceleration curve of the path according to the joint load data of the mechanical arm; the closed-loop verification module is used for carrying out deviation comparison on the actual pose of the tail end of the mechanical arm and the target coordinates, and if the deviation exceeds the limit, the visual positioning and morphology detection module is triggered to cooperatively reset to the path planning and obstacle avoidance module; the visual positioning and morphology detection module and the closed loop verification module are executed in sequence, and output parameters of the previous module serve as input parameters of the next module. Through close cooperation of the modules, efficient and accurate automatic loading and unloading control is achieved, the automation level is improved, and operation safety and accuracy are guaranteed.

The utility model discloses a silicon wafer stacking box and a silicon wafer transfer device, the silicon wafer stacking box comprises a bottom plate, baffle plates and an adjusting assembly, the baffle plates are provided with a plurality of wafer placing spaces for placing silicon wafers, the wafer placing spaces are defined above the bottom plate, at least one of the two oppositely arranged baffle plates is connected with the adjusting assembly, and the adjusting assembly is connected with the baffle plates. The adjusting assembly comprises an elastic piece and a driving piece, the elastic piece applies elastic force close to the wafer containing space to the baffle, the driving piece is used for applying acting force away from the wafer containing space to the baffle, the silicon wafer transfer device comprises a silicon wafer stacking box, and the driving piece can enable the baffle to overcome the elastic force of the elastic piece to be opened so that silicon wafers can be loaded and unloaded conveniently. After the driving piece removes driving of the baffle, the baffle is automatically tightened inwards under the action of the elastic force of the elastic piece, and the silicon wafers are aligned and tightly attached to the baffle under the action of the elastic force, so that the silicon wafers are kept stable in the transfer process, and the silicon wafers are prevented from being damaged due to friction and collision between the silicon wafers.

According to the preparation method of the heterogeneous wafer structure provided by the embodiment of the invention, the first bonding structure is provided; the first bonding structure comprises a first single crystal wafer, a first dielectric layer and a second single crystal wafer which are sequentially stacked, and a defect layer is arranged in the first single crystal wafer; providing a wafer structure; the wafer structure comprises a third single crystal wafer and a second dielectric layer located on the third single crystal wafer; etching the wafer structure from the surface of the second dielectric layer to form a symmetrical groove structure located on the surface of the third single crystal wafer; the depth of the symmetrical groove structure is equal to the thickness of the second dielectric layer; bonding the first bonding structure and the wafer structure to obtain a second bonding structure; the second bonding structure is subjected to annealing treatment, so that the second bonding structure is peeled off along the defect layer, the heterogeneous wafer structure is obtained, the annealing temperature of preparation of the heterogeneous wafer structure is effectively improved through the method, and the bonding strength and the reuse frequency of the heterogeneous wafer structure are increased.

In a general aspect, a superconducting quantum processing unit (QPU) includes a plurality of multi-layered cap wafers. In some cases, a quantum processing unit includes quantum processor chips attached to multi-layered cap wafers. Each of the quantum processor chips includes a plurality of qubit devices. The multi-layered cap wafers are configured to provide communication between the quantum processor chips and a control system. Each of the multi-layered cap wafers includes a respective wafer stack that includes a plurality of layers. The plurality of layers of each respective wafer stack includes a first end layer residing closest to a respective quantum processor chip; a second end layer residing farthest from the respective quantum processor chip; and an intermediate layer residing between the first and second end layers. The intermediate layer includes at least one of: a plurality of Purcell filters, a plurality of reflective attenuators, or a plurality of frequency-specific filters.

The invention belongs to the technical field of semiconductor processing, and particularly relates to a method for improving 3D wafer stacking electric leakage and a semiconductor structure. A wafer is provided, the wafer comprises a substrate layer and an oxide layer, one side of the oxide layer is a bonding surface, and one side of the substrate layer is a bottom surface; a metal interconnection structure is arranged in the oxide layer, a through hole is formed in the oxide layer from the bonding surface side, and the through hole is communicated with the metal interconnection structure and is filled with a conductor layer; the bonding surfaces of one wafer and the other wafer are opposite, and the conductor layers of the two wafers are communicated; a TSV through hole is formed in the bottom face of any wafer in the direction of the metal interconnection structure, and the TSV through hole is communicated with the metal interconnection structure; depositing an oxidation deposition layer in the TSV through hole, wherein the oxidation deposition layer at least covers the side wall of the TSV through hole; and depositing a TSV through hole conductor layer in the TSV through hole, wherein the TSV through hole conductor layer is communicated with the metal interconnection structure. Through a simple process, the problem of electric leakage of the TSV is solved, and the reliability of the semiconductor device can be improved.

The invention discloses a wafer automatic orientation stacking device based on visual identification, and belongs to the technical field of component manufacturing automation. The device comprises a control unit, a visual unit and a motion unit. The moving unit comprises a three-dimensional moving platform, a feeding disc, a receiving disc, a suction nozzle and a rotating motor; the visual unit comprises a light source and a camera. The camera is used for collecting images of the wafers in the feeding disc, the control unit is used for processing the images, the position and the direction of each wafer are accurately recognized, then the movement unit and the rotating motor are driven, the suction nozzle picks up the wafers and carries out rotation correction, and finally directional stacking is carried out on the receiving disc at the height calculated in a self-adaptive mode. The problems that manual stacking is low in efficiency and poor in consistency and existing equipment cannot carry out accurate directional stacking on wafers with similar lengths and widths are solved, and full automation, high precision and high stability of wafer stacking are achieved.

The invention provides a semiconductor structure and a forming method thereof, and relates to the technical field of semiconductors. The semiconductor structure comprises a wafer lamination layer, a conductive material layer and a first stress adjusting layer, wherein the wafer lamination layer comprises a bottom layer wafer and at least one wafer which is sequentially stacked on the bottom layer wafer along a first direction, each wafer comprises a welding pad, two adjacent wafers are correspondingly bonded through the welding pads, and the first direction is a direction perpendicular to the surface of the bottom layer wafer; a conductive material layer covers one surface, far away from the bottom wafer, of the wafer lamination layer; the first stress adjusting layer is located on the face, away from the wafer lamination layer, of the conductive material layer, and the first stress adjusting layer at least covers the edge of the conductive material layer. According to the semiconductor structure, the first stress adjusting layer covers the conductive material layer, so that the warping phenomenon of the wafer lamination layer can be improved, and the flatness of the wafer lamination layer is further improved.

An electrical connector assembly includes a housing having a mating interface configured to be mated with a mating electrical connector assembly. Wafer assemblies are received in a cavity of the housing arranged in a wafer stack. Each wafer assembly includes a leadframe, a wafer body holding the leadframe, cables coupled to the leadframe, a ground frames coupled to the wafer body to provide electrical shielding for the leadframe, and ferrules surrounding the ends of the cables and electrically connected to the ground frames. Each ferrule has a solder layer along an interior of the ferrule coupled to a cable shield. Each ferrule includes shield connecting elements terminated to the ground frames to electrically connect the ferrule to the ground frames.

A semiconductor device may include a plurality of single-photon avalanche diode (SPAD) pixels. The semiconductor device may be a backside device that includes a sensor wafer stacked with an integrated passive component (IPC) wafer. The sensor wafer may include the SPAD pixels in an array across the sensor wafer. The IPC wafer may include active microcells that include quench resistors and dummy microcells that omit or disconnect the quench resistors. The sensor wafer may be bonded to the IPC wafer through hybrid bonding. The regions with active microcells may form active areas of the semiconductor device, while the regions with dummy microcells may form inactive areas. In this way, the active areas and inactive areas of the semiconductor device may be configurable by adjusting the active and dummy microcells of the IPC wafer.

The invention discloses a chip interconnection packaging structure and a computing chip, the chip interconnection packaging structure comprises a plurality of wafers, the plurality of wafers are stacked, each wafer comprises a photoelectric conversion circuit, an optical waveguide and a signal contact, the photoelectric conversion circuit is connected with the signal contact through the optical waveguide, and the photoelectric conversion circuit is connected with the signal contact through the optical waveguide. The photoelectric conversion circuit is configured to convert an electric signal into an optical signal, the signal contacts on the adjacent wafers are connected, so that the optical waveguides in the adjacent wafers are communicated, the optical waveguides in each wafer are arranged to comprise a photopolymerization liquid working medium, and the photopolymerization liquid working medium transmits the optical signal. According to the chip interconnection packaging structure, the optical signal channels in the wafers are communicated through the photopolymerization liquid working medium, heat convection is generated when the chip works, the soaking effect in the chip interconnection packaging structure is achieved, and therefore the performance of the chip can be further improved by improving the signal transmission rate and the chip heat dissipation effect at the same time, and the influence of temperature on the chip calculation capacity is reduced.

The invention relates to a visual wafer scanning system and method, and the system comprises a fixed platform and a camera. The fixing platform is used for fixing a wafer clamping plug; the camera is movably arranged on the fixed platform, and the camera can shoot wafer slots in different areas in the wafer clamping plug when moving to different positions, so that all the wafer slots in the wafer clamping plug are shot in different images respectively. According to the visual wafer scanning system, full-automatic and high-precision detection of wafer arrangement in a wafer clamping plug is realized through an innovative mobile shooting and image splicing technology in combination with an intelligent image recognition algorithm. The device overcomes the limitation of the existing photoelectric sensor and fixed visual angle visual detection, can identify tiny anomalies such as wafer lamination, dislocation and the like, and remarkably improves the reliability and the automation level of the production process.

The invention discloses a three-dimensional stacked chip and a test method. The three-dimensional stacked chip comprises at least two wafers to be tested; the at least two to-be-tested wafers comprise a first to-be-tested wafer and a second to-be-tested wafer, and the first to-be-tested wafer and the second to-be-tested wafer are stacked and connected through a connecting layer; the first to-be-tested wafer is provided with a first test circuit, and the second to-be-tested wafer is provided with a second test circuit and a comparison circuit. The first test circuit is used for writing test data into the first wafer to be tested; the second test circuit is used for copying the test data to the second wafer to be tested through the connecting layer; and the comparison circuit is used for comparing the copied test data with to-be-compared data in the second to-be-tested wafer and outputting comparison information for judging whether the connection layer is abnormal or not. The test of the connection layer can be realized, and the test coverage rate and the simultaneous test number are improved.

A method of processing a substrate that includes: forming an infrared (IR) absorbing separation layer over a first substrate; forming one or more layers over the IR absorbing separation layer; bonding the first substrate and a second substrate at a bonding interface between the one or more layers and the second substrate using a direct bonding technique to form a wafer stack; exposing the wafer stack to an infrared (IR) light irradiation to separate the first substrate from the one or more layers.

The invention relates to the technical field of chip packaging, in particular to a distributed bonding packaging method for improving the wafer stacking yield. Comprising the following steps: S1, stripping Fail Die on a first wafer; s2, a second wafer and a Good Die are provided, and the Good Die is mixed and bonded to the second wafer; s3, carrying out hybrid bonding on the first wafer and the second wafer, wherein the Good Die is located in the Fail Die region stripped from the first wafer; s4, thinning the back surface of the first wafer until the Good Die region is exposed; s5, etching the silicon layer of the first wafer, and exposing the TSV structure in the first wafer; s6, after cleaning, filling is conducted through a PECVD technology; and S7, through CMP polishing and cleaning, Cu is exposed. Compared with the prior art, a distributed bonding mode of bonding the good die with the wafer of which the fail die is excavated is adopted, so that the overall yield of wafer-level bonding is improved. Compared with the bonding after the wafer is directly repaired, the distributed bonding has the advantage that the steps of glue pasting Die for repairing the wafer and subsequent coplanar adjustment are omitted.

The invention relates to the technical field of semiconductor material processing, in particular to a wafer overturning and bonding mechanism and a wafer bonding method. Comprising a first carrying platform on which a first wafer disc is configured and which is used for selectively clamping or releasing a first wafer; a second carrying platform which is provided with a second wafer disc and is used for selectively clamping a second wafer; the connecting part is used for connecting the first carrying table and the second carrying table; the first carrying table and / or the second carrying table can swing relative to the connecting part, so that the included angle between the first carrying table and the second carrying table is kept at 0-180 degrees; when the included angle between the first carrying table and the second carrying table is kept at 0 degree, the first wafer and the second wafer are attached to form a wafer overlapping body; the wafer overlapping body is clamped by the second wafer disc, and when the included angle between the first carrying table and the second carrying table is larger than 0 degree, the position of the wafer overlapping body relative to the second wafer disc is fixed. Double-layer and multi-layer wafer bonding can be carried out in a vacuum environment, and the vacuum degree in the bonding chamber can be kept stable.

A method for debonding a wafer from a bonded wafer stack is disclosed. Initially, a light-absorbing layer is placed on a carrier. A wafer is then attached to the light-absorbing layer of the carrier via an adhesive layer to form a bonded wafer stack. After processing the wafer has been processed, a light pulse from a flashlamp is applied to a non-wafer side of the carrier to heat the light-absorbing layer and the adhesive layer in order to loosen the wafer from the bonded wafer stack. Finally, the wafer is removed from the bonded wafer stack.

The invention relates to the field of photovoltaic equipment, and discloses a high-productivity PECVD (Plasma Enhanced Chemical Vapor Deposition) system suitable for plating various film layers and a coating process thereof, and the PECVD system comprises a sheet feeding preheating cavity, a one-stop coating module and a cooling sheet discharging cavity which are sequentially connected through gate valves. The sheet inlet preheating cavity comprises a sheet inlet and outlet stacking cavity and a heating plate, and the cooling sheet outlet cavity comprises a sheet inlet and outlet stacking cavity and a cooling plate. The one-stop film coating module comprises an isolation cavity and a plurality of process cavities for coating different film layers, and the isolation cavity is arranged between two adjacent process cavities through a gate valve; and each process cavity comprises a plurality of deposition cavities which are communicated with one another and can work independently. And a stack lifting mechanism is arranged in each of the in-and-out wafer stack cavity and the isolation cavity. The coating process adopts the PECVD system and comprises the following steps: S1, feeding and preheating; s2, film coating is conducted, specifically, a one-stop film coating mode is adopted for film coating, and an isolation process is set; and S3, cooling and discharging. According to the invention, the length of a production line can be shortened, the equipment and land occupation cost is saved, and the productivity efficiency can be improved.

A memory testing method and a computer system based on wafer stacking architecture are disclosed. The memory testing method is applied to a computer system based on wafer stacking architecture. The computer system is a three-dimensional wafer product formed by a memory wafer layer, a logic circuit layer and a substrate. When performing memory testing, the memory devices in the memory wafer layer are divided into a plurality of memory sub-blocks, each of which is tested separately. First, a data table is established in one memory sub-block. Then, a plurality of different initial values prepared in advance are provided, and a proof-of-work operation is performed to generate a plurality of operation results corresponding to each initial value by performing multiple read / write operations on the data table. The judgment module obtains the operation results from the operation module and compares them with the corresponding known solutions to calculate the error rate of the tested memory sub-block.

The invention relates to the technical field of underwater acoustic transmitting transducers, and particularly discloses a curved longitudinal vibration type underwater acoustic transmitting transducer based on a 3D printing technology and a preparation method thereof, the curved longitudinal vibration type underwater acoustic transmitting transducer comprises a metal shell, a plurality of groups of rigid foam plastic, a plurality of groups of piezoelectric ceramic wafer piles, a plurality of prestressed bolts, a metal mass block and a transmitting end with a cavity, each group of piezoelectric ceramic wafer stack is composed of forward polarization piezoelectric ceramics and negative polarization piezoelectric ceramics, the polarization directions of the forward polarization piezoelectric ceramics and the negative polarization piezoelectric ceramics are opposite, and brass gaskets are arranged in the middle and on the two sides of each group of piezoelectric ceramic wafer stack respectively and used for leading out electrodes; according to the underwater acoustic transmitting transducer, the transmitting end is manufactured through the 3D printing technology, the integrality is high, the influence of secondary assembly on work of the underwater acoustic transmitting transducer is reduced, and good work stability of the underwater acoustic transmitting transducer can be guaranteed.

An electronic assembly is disclosed. The electronic assembly includes a first attachment layer, a second attachment layer, a first interposer redistribution layer, a second interposer redistribution layer, at least one of a thermal spreader layer or a thermal management layer, and an interposer cavity. The interposer further includes an interconnect header fixed within the interposer cavity comprising a plurality of interconnect filaments configured to electrically couple to at least one of the first interposer redistribution layer or the second interposer redistribution layer. The interconnect header is generated by applying electrically conductive filaments on a plurality of wafers, thinning the wafers, stacking the wafers, attaching the wafers into a wafer stack, and dicing the wafer stack.

The invention discloses a manufacturing method of a three-dimensional system chip based on an aluminum nitride bonding structure and the three-dimensional system chip, and belongs to the field of advanced packaging of semiconductors. The manufacturing method comprises the following steps: providing a mother wafer, wherein the surface of the mother wafer is provided with a mother core metal electrode array; providing at least one sub-core particle, wherein the surface of the sub-core particle is provided with a sub-core metal electrode array; forming an aluminum nitride bonding layer in a non-electrode interconnection area on the surface of the mother wafer and / or the surfaces of the sub core particles; and stacking and aligning the sub-core particles and the mother wafer, and bonding through the aluminum nitride bonding layer, so that the mother core metal electrode array and the sub-core metal electrode array are vertically interconnected. According to the invention, aluminum nitride is used as a bonding and filling medium, and has the characteristics of high insulativity and high thermal conductivity, so that high-density and high-reliability electrical interconnection is realized, an efficient heat dissipation channel is provided for the high-power-consumption core particles, and the technical problem that heat dissipation and insulation in traditional three-dimensional integration are difficult to collaboratively optimize is solved.

The invention provides a semiconductor packaging structure and a preparation method, the semiconductor packaging structure comprises a circuit substrate and a second chip unit bonded on the surface of the circuit substrate, the second chip unit comprises multiple layers of stacked first chip units, and each first chip unit comprises a first chip and a second chip which are bonded up and down. A two-layer chip bonding structure is adopted as a single stacking unit, and compared with a single-layer chip, the structural strength is improved, so that larger internal stress can be borne during bonding, and buckling deformation is avoided. Besides, the preparation method adopts the technological process of bonding the wafers first and then cutting out the chip stacking units, so that the working efficiency and the productivity can be improved, particularly, multiple layers of wafers are stacked to form the wafer stacking body and then the second chip units are directly cut out, the subsequent process of stacking the first chip units one by one is omitted, and the production cost is reduced. And the manufacturing efficiency is further improved.

Representative implementations of devices and techniques provide correction for a defective die in a wafer-to-wafer stack or a die stack. A correction die is coupled to a die of the stack with the defective die. The correction die electrically replaces the defective die. Optionally, a dummy die can be coupled to other die stacks of a wafer-to-wafer stack to adjust a height of the stacks.

A batch-type apparatus for atomic layer etching (ALE), which is capable of ALE-processing several wafers at the same time, and an ALE method and a semiconductor device manufacturing method based on the batch-type apparatus, are provided. The batch-type apparatus for ALE includes a wafer stacking container in which a plurality of wafers are arranged in a vertical direction, an inner tube extending in the vertical direction, a plurality of nozzles arranged in a first outer portion in the inner tube in a horizontal direction, and a heater surrounding the inner tube and configured to adjust a temperature in the inner tube, wherein gas injection holes are formed corresponding to a height of the plurality of wafers in each of the plurality of nozzles, and a gas outlet is formed in a second outer portion in the inner tube, opposite to the first outer portion.

The invention relates to a wafer stacking method and a wafer stacking structure. In the wafer stacking method, a first wafer structure and a second wafer structure are firstly formed and then stacked and bonded, a metal bonding pad is preset on one side of the first wafer structure before the first wafer structure and the second wafer structure are stacked and bonded, and a metal bonding pad is preset on one side of the second wafer structure after the first wafer structure and the second wafer structure are stacked and bonded. According to the technical scheme, a metal bonding pad does not need to be manufactured, a high-temperature process for manufacturing the metal bonding pad is avoided, wafer buckling deformation caused by the high-temperature process can be avoided, the risks of film layer breakage and machine alarm can be reduced, and multi-layer wafer level stacking can be achieved. The wafer stacking structure can be formed by adopting the wafer stacking method.

A semiconductor device and a semiconductor die are disclosed. The semiconductor device includes: a SPAD wafer containing SPAD dies formed thereon with respective SPAD arrays; a TDC wafer containing TDC dies formed thereon with respective TDC arrays; and a logic wafer containing logic dies formed thereon with respective peripheral logic circuits. The SPAD wafer, TDC wafer and logic wafer are bonded in the sequence set forth. The TDC arrays and peripheral logic circuits are arranged on the TDC and logic wafers, respectively, and the SPAD arrays are bonded to the TDC arrays. The three wafers are bonded and integrated together to form the semiconductor device using a multi-wafer stacking technique. The increased integration of the semiconductor device means an increased fill factor of SPAD arrays for same size, resulting in improved photon detection efficiency of the semiconductor device and improved detection performance of single-photon detectors fabricated from the semiconductor device.

The invention belongs to the technical field of semiconductor equipment, and particularly relates to a wafer mapping mechanism for detecting the placement state of wafers in a wafer cassette, which comprises two groups of correlation sensor assemblies, and each group of correlation sensor assembly comprises a transmitting end structure and a receiving end structure, the transmitting end structures of the two sets of correlation sensor assemblies are installed on the lifting cavity door, and the receiving end structures of the two sets of correlation sensor assemblies are installed on the inner side face of the side wall, away from the lifting cavity door, of the lifting equipment cavity. Projections of light rays emitted by the transmitting end structures of the two groups of correlation sensor assemblies on a vertical plane intersect but are not parallel. Through cooperative arrangement of the two groups of correlation sensor assemblies, two groups of detection data can be adopted for comparison, and comprehensive logic judgment is performed, so that the scanning time can be effectively shortened, the defect that wafer crossing or lamination is possibly misreported when the wafer box is inclined is effectively avoided, the accuracy and efficiency of an identification result are improved, the mounting structure is relatively simple, and the practicability is high. Adjustment and maintenance are convenient.

The invention discloses a carrying device based on wafer detection and a coordinate position compensation system, a transfer mechanical assembly comprises a rotating platform and a multi-section type mechanical arm, the rotating movement of the multi-section type mechanical arm is realized through the rotation of the rotating platform, and the multi-section type mechanical arm realizes the telescopic movement in the extension direction; the front end part of the multi-section type mechanical arm is arranged to be of a plane type structure and is used for bearing the wafer, and the multi-section type mechanical arm is used for correcting the carrying position during operation; the bearing assembly comprises a shell part and a bearing seat at the bottom, a plurality of groups of limiting grooves are formed in the horizontal direction where the shell part is located, so that each group of wafers are stacked and borne on each layer of limiting groove, and a gap between every two adjacent wafers is used for insertion of a multi-section type mechanical arm. While the device carries the wafer, the correction process is not based on the mechanical structure specific size such as the rotating arm length of the mechanical arm, and can be completed only through three-point plane teaching. The method is simple, and mechanical errors do not need to be compensated.

The invention belongs to the field of semiconductor device manufacturing, and particularly relates to a bonding chip manufacturing method and an electrical property improved bonding chip. Comprising the steps of S1, stacking and bonding at least a first wafer and a second wafer to form a wafer stacking structure; s2, etching to form a silicon through hole conductive pattern layer; s3, forming a barrier layer / seed crystal layer on the outer surface of the wafer stacking structure and the surface of the silicon through hole conductive pattern layer in a mode that no gap is generated on the side edge of the bonding layer of the wafer stacking structure; and S4, electrochemical deposition is carried out, and a copper plating layer is formed. According to the invention, the bonding gap of the stacked wafer and the special morphology of the side wall do not need to be considered, and the conventional Bamp of the single wafer can be applied; according to the process formula of S PVD and Cu electrochemical electroplating, the period of process development is greatly shortened, and the process difficulty is greatly reduced.

The present invention is a temporary adhesive for wafer processing, which is used for temporarily bonding a wafer to a support. This temporary adhesive for wafer processing is composed of a curable silicone resin composition which can be cured by a hydrosilylation reaction. This curable silicone resin composition is a temporary adhesive for wafer processing, which characteristically contains an organopolysiloxane that has in each molecule only one alkenyl group or only one silicon atom-bonded hydrogen atom (SiH group). It is thereby possible to provide a temporary adhesive for wafer processing, a wafer laminate, and a method for producing thin wafers using same, which support an improved productivity for thin wafers, wherein, inter alia, an adequate substrate retention is exhibited post-bonding even when a substrate with high level differences is used; a high process compatibility is exhibited with wafer backside grinding processes, TSV formation processes, and wafer backside wiring processes; facile peeling is exhibited in peeling processes even after passage post-bonding through a lengthy high-temperature heating process in air; and the residue on the substrate post-peeling exhibits an excellent cleanability.