96 results about "Wafer stacking" patented technology

The invention discloses a wafer automatic orientation stacking device based on visual identification, and belongs to the technical field of component manufacturing automation. The device comprises a control unit, a visual unit and a motion unit. The moving unit comprises a three-dimensional moving platform, a feeding disc, a receiving disc, a suction nozzle and a rotating motor; the visual unit comprises a light source and a camera. The camera is used for collecting images of the wafers in the feeding disc, the control unit is used for processing the images, the position and the direction of each wafer are accurately recognized, then the movement unit and the rotating motor are driven, the suction nozzle picks up the wafers and carries out rotation correction, and finally directional stacking is carried out on the receiving disc at the height calculated in a self-adaptive mode. The problems that manual stacking is low in efficiency and poor in consistency and existing equipment cannot carry out accurate directional stacking on wafers with similar lengths and widths are solved, and full automation, high precision and high stability of wafer stacking are achieved.

The invention discloses a chip interconnection packaging structure and a computing chip, the chip interconnection packaging structure comprises a plurality of wafers, the plurality of wafers are stacked, each wafer comprises a photoelectric conversion circuit, an optical waveguide and a signal contact, the photoelectric conversion circuit is connected with the signal contact through the optical waveguide, and the photoelectric conversion circuit is connected with the signal contact through the optical waveguide. The photoelectric conversion circuit is configured to convert an electric signal into an optical signal, the signal contacts on the adjacent wafers are connected, so that the optical waveguides in the adjacent wafers are communicated, the optical waveguides in each wafer are arranged to comprise a photopolymerization liquid working medium, and the photopolymerization liquid working medium transmits the optical signal. According to the chip interconnection packaging structure, the optical signal channels in the wafers are communicated through the photopolymerization liquid working medium, heat convection is generated when the chip works, the soaking effect in the chip interconnection packaging structure is achieved, and therefore the performance of the chip can be further improved by improving the signal transmission rate and the chip heat dissipation effect at the same time, and the influence of temperature on the chip calculation capacity is reduced.

The invention discloses a manufacturing method of a three-dimensional system chip based on an aluminum nitride bonding structure and the three-dimensional system chip, and belongs to the field of advanced packaging of semiconductors. The manufacturing method comprises the following steps: providing a mother wafer, wherein the surface of the mother wafer is provided with a mother core metal electrode array; providing at least one sub-core particle, wherein the surface of the sub-core particle is provided with a sub-core metal electrode array; forming an aluminum nitride bonding layer in a non-electrode interconnection area on the surface of the mother wafer and / or the surfaces of the sub core particles; and stacking and aligning the sub-core particles and the mother wafer, and bonding through the aluminum nitride bonding layer, so that the mother core metal electrode array and the sub-core metal electrode array are vertically interconnected. According to the invention, aluminum nitride is used as a bonding and filling medium, and has the characteristics of high insulativity and high thermal conductivity, so that high-density and high-reliability electrical interconnection is realized, an efficient heat dissipation channel is provided for the high-power-consumption core particles, and the technical problem that heat dissipation and insulation in traditional three-dimensional integration are difficult to collaboratively optimize is solved.

The invention provides a semiconductor packaging structure and a preparation method, the semiconductor packaging structure comprises a circuit substrate and a second chip unit bonded on the surface of the circuit substrate, the second chip unit comprises multiple layers of stacked first chip units, and each first chip unit comprises a first chip and a second chip which are bonded up and down. A two-layer chip bonding structure is adopted as a single stacking unit, and compared with a single-layer chip, the structural strength is improved, so that larger internal stress can be borne during bonding, and buckling deformation is avoided. Besides, the preparation method adopts the technological process of bonding the wafers first and then cutting out the chip stacking units, so that the working efficiency and the productivity can be improved, particularly, multiple layers of wafers are stacked to form the wafer stacking body and then the second chip units are directly cut out, the subsequent process of stacking the first chip units one by one is omitted, and the production cost is reduced. And the manufacturing efficiency is further improved.

The invention relates to a wafer stacking method and a wafer stacking structure. In the wafer stacking method, a first wafer structure and a second wafer structure are firstly formed and then stacked and bonded, a metal bonding pad is preset on one side of the first wafer structure before the first wafer structure and the second wafer structure are stacked and bonded, and a metal bonding pad is preset on one side of the second wafer structure after the first wafer structure and the second wafer structure are stacked and bonded. According to the technical scheme, a metal bonding pad does not need to be manufactured, a high-temperature process for manufacturing the metal bonding pad is avoided, wafer buckling deformation caused by the high-temperature process can be avoided, the risks of film layer breakage and machine alarm can be reduced, and multi-layer wafer level stacking can be achieved. The wafer stacking structure can be formed by adopting the wafer stacking method.

The invention belongs to the technical field of semiconductor equipment, and particularly relates to a wafer mapping mechanism for detecting the placement state of wafers in a wafer cassette, which comprises two groups of correlation sensor assemblies, and each group of correlation sensor assembly comprises a transmitting end structure and a receiving end structure, the transmitting end structures of the two sets of correlation sensor assemblies are installed on the lifting cavity door, and the receiving end structures of the two sets of correlation sensor assemblies are installed on the inner side face of the side wall, away from the lifting cavity door, of the lifting equipment cavity. Projections of light rays emitted by the transmitting end structures of the two groups of correlation sensor assemblies on a vertical plane intersect but are not parallel. Through cooperative arrangement of the two groups of correlation sensor assemblies, two groups of detection data can be adopted for comparison, and comprehensive logic judgment is performed, so that the scanning time can be effectively shortened, the defect that wafer crossing or lamination is possibly misreported when the wafer box is inclined is effectively avoided, the accuracy and efficiency of an identification result are improved, the mounting structure is relatively simple, and the practicability is high. Adjustment and maintenance are convenient.

The invention discloses a carrying device based on wafer detection and a coordinate position compensation system, a transfer mechanical assembly comprises a rotating platform and a multi-section type mechanical arm, the rotating movement of the multi-section type mechanical arm is realized through the rotation of the rotating platform, and the multi-section type mechanical arm realizes the telescopic movement in the extension direction; the front end part of the multi-section type mechanical arm is arranged to be of a plane type structure and is used for bearing the wafer, and the multi-section type mechanical arm is used for correcting the carrying position during operation; the bearing assembly comprises a shell part and a bearing seat at the bottom, a plurality of groups of limiting grooves are formed in the horizontal direction where the shell part is located, so that each group of wafers are stacked and borne on each layer of limiting groove, and a gap between every two adjacent wafers is used for insertion of a multi-section type mechanical arm. While the device carries the wafer, the correction process is not based on the mechanical structure specific size such as the rotating arm length of the mechanical arm, and can be completed only through three-point plane teaching. The method is simple, and mechanical errors do not need to be compensated.

The present invention is a temporary adhesive for wafer processing, which is used for temporarily bonding a wafer to a support. This temporary adhesive for wafer processing is composed of a curable silicone resin composition which can be cured by a hydrosilylation reaction. This curable silicone resin composition is a temporary adhesive for wafer processing, which characteristically contains an organopolysiloxane that has in each molecule only one alkenyl group or only one silicon atom-bonded hydrogen atom (SiH group). It is thereby possible to provide a temporary adhesive for wafer processing, a wafer laminate, and a method for producing thin wafers using same, which support an improved productivity for thin wafers, wherein, inter alia, an adequate substrate retention is exhibited post-bonding even when a substrate with high level differences is used; a high process compatibility is exhibited with wafer backside grinding processes, TSV formation processes, and wafer backside wiring processes; facile peeling is exhibited in peeling processes even after passage post-bonding through a lengthy high-temperature heating process in air; and the residue on the substrate post-peeling exhibits an excellent cleanability.

The invention provides a novel carrier wafer manufacturing method based on chip wafer bonding recombination. The novel carrier wafer manufacturing method comprises the following steps: bonding a chip into a carrier wafer with a groove structure in a manner that the front surface of the chip faces downwards through a fusion bonding process; enabling the back surface of the chip to face outwards, and thinning from the back surface to realize fine planarization thinning of the whole thickness of the chip; taking the chip and the carrier wafer with the groove structure as a whole, and carrying out fusion bonding on the chip and the carrier wafer with another wafer; thinning and planarizing the carrier wafer with the groove structure from the back surface through grinding and chemical mechanical grinding so as to remove a non-groove part and expose the front surface of the chip; interconnected copper conductive holes / welding pads are formed on the front surface of a chip through a copper Damascus process, and secondary chemical mechanical grinding is carried out, so that the final mixed-bonded copper welding pads form a shallow dish shape. According to the invention, the technical optimization of chip-to-wafer stacking is realized, and the process maturity is improved.

The application provides a wafer feeding mechanism, and relates to the technical field of automatic wafer feeding machinery, and comprises a mounting plate fixedly installed on a crystal vibration point glue machine, the upper surface of the mounting plate is provided with a gap distribution assembly for wafer conveying and receiving feeding, the gap distribution assembly comprises a plurality of guide grooves which are uniformly distributed in a circle and arranged on one side of the upper surface of the mounting plate, wherein the inner walls of every four adjacent guide grooves are movably connected with sliding frame plates, and the upper surfaces of the sliding frame plates are fixedly connected with positioning discs. The positioning gear connected by the fixed shaft between the two side plates is sleeved with the rack strip with a uniformly installed limiting support plate on the surface, the driving structure provides power for the rack strip, wafer feeding and conveying are carried out at equal intervals, wafer feeding and conveying can be carried out at equal intervals, wafer stacking and mutual influence are prevented, and the quality of crystal vibration point glue is reduced.

The invention discloses a method for processing the surface of a cavity on a silicon substrate, which belongs to the technical field of semiconductor manufacturing and micro electro mechanical systems, and comprises the following steps of: forming a central hole distribution area and an edge hole-free area on the surface of a silicon wafer by using a hard mask and an etching process; placing the isolation pad between the edge non-hole areas of the two silicon wafers, and aligning the central hole distribution areas of the two silicon wafers to form a silicon wafer-isolation pad-silicon wafer stacked structure; the isolation pad does not shield the central hole flow channel; and placing the stacked silicon wafers and the isolation pad in a hydrogen atmosphere for annealing treatment to form a uniform cavity. According to the invention, the defects of many surface defects, high roughness and poor process stability of the silicon substrate cavity caused by the edge effect of the hydrogen flow field in the existing SON process are overcome, the optimized hydrogen flow channel is formed through wafer stacking, the hydrogen density distribution is improved, the reaction probability of oxygen atoms and silicon atoms is reduced, and the stable preparation of the high-quality and high-consistency cavity is realized.

The invention provides a method for bonding wafers stacked with high aspect ratio microstructures, a first wafer and a second wafer are provided, the high aspect ratio microstructures are stacked on the surface of the first wafer or the second wafer, and the first wafer and the second wafer are cleaned and dried before being bonded. The cleaning and drying treatment comprises the following steps: pre-cleaning at normal temperature; performing infiltration treatment on the pre-cleaned first wafer and the pre-cleaned second wafer by using an IPA solution, and after the infiltration treatment is completed, putting the first wafer and the second wafer into a supercritical drying cavity, and introducing gas to perform supercritical drying treatment; the cleaned and dried first wafer and second wafer are pre-bonded, and according to the bonding method for the wafers stacked with the high aspect ratio microstructures, the cleaning efficiency is guaranteed, meanwhile, residues of water stains in the high aspect ratio microstructures are reduced, the cleaning effect is improved, and the yield of bonded products is guaranteed.

The utility model provides a discharging and transferring device of a degumming machine, and aims to solve the problems of low efficiency and high misoperation rate caused by adopting a manual transferring and reshaping degumming mode for silicon wafer stack treatment after discharging of the degumming machine in the prior art. The device mainly comprises a discharging platform, a transfer manipulator, a degumming machine discharging water tank, a feeding line and a processing workbench, according to the utility model, a silicon wafer stack is transferred through the six-shaft manipulator, and the silicon wafer shovel at the free end of the tail shaft integrates a swirl nozzle, a bucket and a clamping function; the processing workbench integrates the shaping and degumming functions of a silicon wafer stack, the six-axis mechanical arm, the processing workbench, the feeding line in the field and the discharging water tank cooperate with one another, silicon wafers can be automatically transferred, shaped and degummed, the production efficiency is improved, and manual intervention is reduced. And meanwhile, in the treatment process of the silicon wafer stack, the flexible cushion block and the correction sponge roller are adopted, so that the damage to the surface of the silicon wafer is avoided.

The application discloses a wafer stacking structure and a preparation method thereof. The wafer stacking structure comprises a bearing substrate and a first spliced wafer. The bearing substrate has a first size, and the first spliced wafer is bonded to the surface of the bearing substrate and comprises a plurality of spliced structures. The plurality of spliced structures are closely arranged on the bearing substrate and jointly cover the entire surface of the bearing substrate, and a light-emitting diode structure is formed on each spliced structure. Each spliced structure is formed by cutting a growth substrate with a second size to a preset shape after an epitaxial layer is grown on the growth substrate. The first size is larger than the second size. The first spliced wafer contained in the wafer stacking structure of the application is formed by splicing the spliced structures. The spliced structures are formed by cutting a growth substrate with a small size to form an epitaxial layer, and have good growth quality. Therefore, the wafer stacking structure formed by the spliced structures also has high product quality.

Various embodiments of the present disclosure are directed towards a processing tool. The processing tool includes a housing structure defining a chamber. A first plate is disposed in the chamber. A first plasma exclusion zone (PEZ) ring is disposed on the first plate. A second plate is disposed in the chamber and underlies the first plate. A second PEZ ring is disposed on the second plate. The second PEZ ring comprises a PEZ ring notch that extends inwardly from a circumferential edge of the second PEZ ring.

Disclosed is an integrated circuit device. In some aspects, a device includes a first wafer including a first dielectric layer, a first set of bonding pads disposed in the first dielectric layer and a first circuit disposed on the first dielectric layer, and a second wafer including a second dielectric layer, a second set of bonding pads disposed in the second dielectric layer and a second circuit disposed on the second dielectric layer. The device further includes through-vias including at least one power via in the second wafer, and a backside power distribution network (BSPDN) layer disposed on the second wafer. The first set of bonding pads is bonded with the second set of bonding pads.

This invention provides a single-power-source battery cell stacking machine, including a frame, an anode wafer feeding device, a cathode wafer feeding device, an anode wafer picking and placing device, a cathode wafer picking and placing device, a membrane placement device, a stacking device, and a drive device. By setting up an anode wafer picking area, an anode wafer transfer area, an anode wafer stacking area, a cathode wafer picking area, a cathode wafer transfer area, a cathode wafer stacking area, and a diaphragm placement area on the frame, the anode wafer picking and placing device and the cathode wafer picking and placing device respectively handle the picking and placing of anode and cathode wafers. The stacking device moves between the anode wafer stacking area, the diaphragm placement area, and the cathode wafer stacking area, stacking and pressing the anode wafers, diaphragm strips, and cathode wafers layer by layer. In this design, multiple motion mechanisms for picking and placing anode wafers, picking and placing cathode wafers, and stacking diaphragms use the same power source, with unified control of actions to ensure consistency and improve stacking quality.

A semiconductor package may include: a base wafer; a plurality of lower core wafers stacked on the base wafer; an upper core wafer on the plurality of lower core wafers; an oxide structure covering side surfaces of the plurality of lower core wafers and the upper core wafer; and a molded structure configured to cover the side surfaces of the oxide structure and spaced apart from the plurality of lower core wafers and the upper core wafer, the oxide structure being inserted between the molded structure and the plurality of lower core wafers and the upper core wafer. Each of the base wafer and the plurality of lower core wafers may include a through electrode, and the upper core wafer may include an insulating layer disposed on its bottom surface and pads disposed in the insulating layer. The oxide structure may expose an edge portion of the top surface of the base wafer.

The utility model discloses a photovoltaic silicon wafer cleaning separation mechanism, which comprises a storage rack, a storage cavity for stacking photovoltaic silicon wafers, and a discharge port on the side of the storage rack, which is in communication with the storage cavity; a conveyor belt assembly is arranged at the discharge port of the storage rack in a preset first direction, and is used for receiving and transmitting the photovoltaic silicon wafers output by the storage rack; a negative pressure generating device is arranged above the inside of the storage cavity, and is used for extracting the fluid above the photovoltaic silicon wafer stack in the storage cavity to form a negative pressure adsorption area; a separation device comprises at least one first nozzle unit for directing the output of fluid towards the side edge of the photovoltaic silicon wafer stack in the storage cavity; the negative pressure generated by the negative pressure adsorption area and the directional jet of the first nozzle unit work together to form a separation effect between adjacent photovoltaic silicon wafers; the utility model can solve the problem of poor separation efficiency and cleaning effect of the existing photovoltaic silicon wafer separation and cleaning equipment.

A wafer processing method includes emitting a laser beam along an annular line that is a predetermined distance inward of the outer circumferential edge of the first wafer to form, in the first wafer, an annular first modified layer and a first crack extending from the first modified layer to make an appearance on the front surface, thereby causing the first wafer to become warped at an outer circumferential region thereof that lies closer to the outer circumferential edge than does the first modified layer and the first crack; bonding the front surface of the first wafer to a second wafer to form a bonded wafer stack; and grinding a rear surface of the first wafer of the bonded wafer stack to thin the first wafer to a finish thickness.

The present application relates to the technical field of silicon wafer production, and particularly relates to a silicon wafer loading system, which comprises a slicing conveying device and a climbing conveying device. When the slicing conveying device conveys, the silicon rods stacked together after slicing are carried to the first conveying belt, then two groups of clamping conveying assemblies are driven to move close to each other, so as to clamp the side of the silicon wafer stacked horizontally. In this way, the horizontally stacked silicon wafer is conveyed forward under clamping, and the silicon wafer cannot be displaced vertically to the stacking direction, so that the effect of discharging the silicon wafer piece by piece in front is ensured. When the climbing conveying device conveys, the segment of the first horizontal belt between the two groups of upper pulleys is elongated or shortened along with the vertical conveying mechanism and the climbing conveying mechanism moving forward and backward. The trajectory difference of the first horizontal belt caused by the horizontal movement of the middle pulley is equal to the distance variable between the two groups of upper pulleys. Therefore, the two ends of the first horizontal belt are always connected with the climbing conveying mechanism and the second horizontal conveying mechanism, and the discontinuous conveying route is avoided, so that the conveying efficiency is ensured.

The utility model provides a silicon wafer shaping and degumming mechanism for a degumming machine, and aims to solve the problems that the traditional manual operation is low in efficiency and the silicon wafer is easy to damage. The device mainly comprises a shaping workbench, a plurality of cavities in the shaping workbench, a shaping assembly and a degumming assembly. According to the utility model, after the silicon wafer stack is transferred into the cavity through the external manipulator, the shaping and degumming treatment of the silicon wafer stack can be efficiently and accurately completed through the cooperative work of the shaping assembly and the degumming assembly, so that the production efficiency and the product quality are remarkably improved, and the device has a wide application prospect.

A method for processing a substrate, comprising: forming an infrared (IR) absorption separation layer on a first substrate; forming one or more layers on the IR absorption separation layer; forming a wafer stack by joining the first substrate and the second substrate at the bonding interface between one or more layers and the second substrate using a direct bonding technique; and separating the first substrate from one or more layers by irradiating the wafer stack with infrared (IR) light.

The invention discloses a full 3D printing integrated multi-size wafer lamination manufacturing method and structure, and the method comprises the steps: S1, PVDF patterning: preparing a PVDF solution, and directly writing the PVDF solution on the surface of a selected silicon wafer through a piezoelectric ink-jet 3D printer to form a PVDF pattern; s2, conducting metal slurry patterning: preparing conducting metal slurry, forming a conducting metal slurry pattern by adopting piezoelectric ink jet and aerosol jet dual-mode 3D printing, covering a part of the PVDF pattern, exposing a PVDF functional area and forming a conducting circuit; and S3, performing OC protection layer patterning: performing direct writing on the OC layer by adopting a non-contact micro-dot glue valve to realize OC protection layer patterning, and covering a lower conductive metal slurry pattern and a PVDF pattern. According to the preparation method and the structure, 3D printing additive manufacturing and a high-precision slit coating technology are integrated on a 4-12-inch wafer, a square piece and the like, and three layers of materials including PVDF, conductive metal slurry and an OC protection adhesive layer are obtained through the graphical lamination preparation method and the structure.

The application discloses integrated circuits, chip-to-wafer stacking structures and manufacturing methods thereof. In the manufacturing process of the C2W stacking structure, a buffer layer structure is formed below the medium layer before at least one step of forming the medium layer for filling between the bare chips. The breaking elongation of the buffer layer structure is higher than that of the medium layer, and the thermal expansion coefficient of the buffer layer structure is higher than that of the medium layer. The buffer layer structure can eliminate part of thermal stress by its elastic strain to relieve stress accumulation between the medium layers, reduce the occurrence of delamination and improve the yield rate without generating excessive stress.

The present disclosure provides a method for forming a semiconductor device. A first wafer including a first substrate and a first interconnection layer formed on the first substrate is provided. A second wafer including a second substrate and a second interconnection layer formed on the second substrate is provided. The second wafer is stacked on the first wafer. A thinning process is performed on the second substrate of the second wafer. An edge trimming process is performed to remove portions of the second interconnection layer and the second substrate along a perimeter of the second wafer, wherein the edge trimming process results in the first wafer having a recessed surface. A protective layer, surrounding a sidewall of the thinned and edge-trimmed second wafer, is formed on the recessed surface to form a wafer stack structure.

The disclosure provides a processing method of a multi-wafer stack structure, and relates to the technical field of semiconductors, which comprises the following steps: bonding a first wafer on a second wafer to form a stack structure; thinning an epitaxial layer in the first wafer to a first preset thickness; trimming the stack structure, so that a sidewall of the stack structure exposes at least part of an internal structure; forming a wrapping layer on the stack structure, the wrapping layer covering a surface of the thinned epitaxial layer, and the wrapping layer covering the sidewall of the stack structure to cover the exposed structure on the sidewall; and removing the wrapping layer on the surface of the epitaxial layer by using a grinding process. The method increases the stability of the wrapping layer covering the exposed metal layer, and improves the problems of metal exposure and pollution.

Various aspects relate to electronic memory devices and mechanisms for communicating with electronic memory devices. A plurality of stacked semiconductor wafers forms a wafer stack. A logic base die is configured to support the plurality of stacked semiconductor wafers. At least one through silicon via is formed through the plurality of stacked semiconductor wafers, wherein the at least one through silicon via is configured to form an inductive coil that is configured to provide a communication interface to the plurality of stacked semiconductor wafers.

A method of testing a semiconductor device includes providing a first wafer that includes a first surface, a second surface that is allocated at an opposite side of the first surface, a first electrode penetrating the first wafer from the first surface to the second surface, and a pad formed on the first surface and coupled electrically with the first electrode, providing a second wafer that includes a second electrode penetrating the second wafer, stacking the first wafer onto the second wafer to connect the first electrode with the second electrode such that the second surface of the first wafer faces the second wafer, probing a needle to the pad, and supplying, in such a state that the first wafer is stacked on the second wafer, a test signal to the first electrode to input the test signal into the second wafer via the first electrode and the second electrode.

The invention relates to the technical field of wafer processing, in particular to a wafer stacking structure forming method and a wafer stacking structure. The forming method comprises the following steps: sequentially stacking N wafers to form a wafer stacking structure; the stacking of any ith wafer from the bottom to the top and the (i-1) th wafer comprises the following steps: trimming the partial thickness of the ith wafer inwards from the edge, so that the trimmed ith wafer forms a boss structure, the boss structure comprises a base body part and a boss part, and the horizontal size of the base body part is larger than that of the boss part; enabling the boss part to face the surface of the (i-1) th wafer, and forming a stacked intermediate with a tower-shaped structure with the (i-1) th wafer; the stacked intermediate is thinned, and the whole thickness of the base body part is removed; and repeating the steps until the (i = N) th wafer is stacked. According to the forming method, the tower-shaped structure instead of a columnar structure is finally formed, so that a large effective area of the wafer is saved, and the loss of the effective area of the wafer is reduced.