148 results about "Wafer stacking" patented technology

The invention discloses a wafer automatic orientation stacking device based on visual identification, and belongs to the technical field of component manufacturing automation. The device comprises a control unit, a visual unit and a motion unit. The moving unit comprises a three-dimensional moving platform, a feeding disc, a receiving disc, a suction nozzle and a rotating motor; the visual unit comprises a light source and a camera. The camera is used for collecting images of the wafers in the feeding disc, the control unit is used for processing the images, the position and the direction of each wafer are accurately recognized, then the movement unit and the rotating motor are driven, the suction nozzle picks up the wafers and carries out rotation correction, and finally directional stacking is carried out on the receiving disc at the height calculated in a self-adaptive mode. The problems that manual stacking is low in efficiency and poor in consistency and existing equipment cannot carry out accurate directional stacking on wafers with similar lengths and widths are solved, and full automation, high precision and high stability of wafer stacking are achieved.

The invention provides a semiconductor structure and a forming method thereof, and relates to the technical field of semiconductors. The semiconductor structure comprises a wafer lamination layer, a conductive material layer and a first stress adjusting layer, wherein the wafer lamination layer comprises a bottom layer wafer and at least one wafer which is sequentially stacked on the bottom layer wafer along a first direction, each wafer comprises a welding pad, two adjacent wafers are correspondingly bonded through the welding pads, and the first direction is a direction perpendicular to the surface of the bottom layer wafer; a conductive material layer covers one surface, far away from the bottom wafer, of the wafer lamination layer; the first stress adjusting layer is located on the face, away from the wafer lamination layer, of the conductive material layer, and the first stress adjusting layer at least covers the edge of the conductive material layer. According to the semiconductor structure, the first stress adjusting layer covers the conductive material layer, so that the warping phenomenon of the wafer lamination layer can be improved, and the flatness of the wafer lamination layer is further improved.

A semiconductor device may include a plurality of single-photon avalanche diode (SPAD) pixels. The semiconductor device may be a backside device that includes a sensor wafer stacked with an integrated passive component (IPC) wafer. The sensor wafer may include the SPAD pixels in an array across the sensor wafer. The IPC wafer may include active microcells that include quench resistors and dummy microcells that omit or disconnect the quench resistors. The sensor wafer may be bonded to the IPC wafer through hybrid bonding. The regions with active microcells may form active areas of the semiconductor device, while the regions with dummy microcells may form inactive areas. In this way, the active areas and inactive areas of the semiconductor device may be configurable by adjusting the active and dummy microcells of the IPC wafer.

The invention discloses a chip interconnection packaging structure and a computing chip, the chip interconnection packaging structure comprises a plurality of wafers, the plurality of wafers are stacked, each wafer comprises a photoelectric conversion circuit, an optical waveguide and a signal contact, the photoelectric conversion circuit is connected with the signal contact through the optical waveguide, and the photoelectric conversion circuit is connected with the signal contact through the optical waveguide. The photoelectric conversion circuit is configured to convert an electric signal into an optical signal, the signal contacts on the adjacent wafers are connected, so that the optical waveguides in the adjacent wafers are communicated, the optical waveguides in each wafer are arranged to comprise a photopolymerization liquid working medium, and the photopolymerization liquid working medium transmits the optical signal. According to the chip interconnection packaging structure, the optical signal channels in the wafers are communicated through the photopolymerization liquid working medium, heat convection is generated when the chip works, the soaking effect in the chip interconnection packaging structure is achieved, and therefore the performance of the chip can be further improved by improving the signal transmission rate and the chip heat dissipation effect at the same time, and the influence of temperature on the chip calculation capacity is reduced.

The invention relates to a visual wafer scanning system and method, and the system comprises a fixed platform and a camera. The fixing platform is used for fixing a wafer clamping plug; the camera is movably arranged on the fixed platform, and the camera can shoot wafer slots in different areas in the wafer clamping plug when moving to different positions, so that all the wafer slots in the wafer clamping plug are shot in different images respectively. According to the visual wafer scanning system, full-automatic and high-precision detection of wafer arrangement in a wafer clamping plug is realized through an innovative mobile shooting and image splicing technology in combination with an intelligent image recognition algorithm. The device overcomes the limitation of the existing photoelectric sensor and fixed visual angle visual detection, can identify tiny anomalies such as wafer lamination, dislocation and the like, and remarkably improves the reliability and the automation level of the production process.

The invention relates to the technical field of underwater acoustic transmitting transducers, and particularly discloses a curved longitudinal vibration type underwater acoustic transmitting transducer based on a 3D printing technology and a preparation method thereof, the curved longitudinal vibration type underwater acoustic transmitting transducer comprises a metal shell, a plurality of groups of rigid foam plastic, a plurality of groups of piezoelectric ceramic wafer piles, a plurality of prestressed bolts, a metal mass block and a transmitting end with a cavity, each group of piezoelectric ceramic wafer stack is composed of forward polarization piezoelectric ceramics and negative polarization piezoelectric ceramics, the polarization directions of the forward polarization piezoelectric ceramics and the negative polarization piezoelectric ceramics are opposite, and brass gaskets are arranged in the middle and on the two sides of each group of piezoelectric ceramic wafer stack respectively and used for leading out electrodes; according to the underwater acoustic transmitting transducer, the transmitting end is manufactured through the 3D printing technology, the integrality is high, the influence of secondary assembly on work of the underwater acoustic transmitting transducer is reduced, and good work stability of the underwater acoustic transmitting transducer can be guaranteed.

The invention discloses a manufacturing method of a three-dimensional system chip based on an aluminum nitride bonding structure and the three-dimensional system chip, and belongs to the field of advanced packaging of semiconductors. The manufacturing method comprises the following steps: providing a mother wafer, wherein the surface of the mother wafer is provided with a mother core metal electrode array; providing at least one sub-core particle, wherein the surface of the sub-core particle is provided with a sub-core metal electrode array; forming an aluminum nitride bonding layer in a non-electrode interconnection area on the surface of the mother wafer and / or the surfaces of the sub core particles; and stacking and aligning the sub-core particles and the mother wafer, and bonding through the aluminum nitride bonding layer, so that the mother core metal electrode array and the sub-core metal electrode array are vertically interconnected. According to the invention, aluminum nitride is used as a bonding and filling medium, and has the characteristics of high insulativity and high thermal conductivity, so that high-density and high-reliability electrical interconnection is realized, an efficient heat dissipation channel is provided for the high-power-consumption core particles, and the technical problem that heat dissipation and insulation in traditional three-dimensional integration are difficult to collaboratively optimize is solved.

The invention provides a semiconductor packaging structure and a preparation method, the semiconductor packaging structure comprises a circuit substrate and a second chip unit bonded on the surface of the circuit substrate, the second chip unit comprises multiple layers of stacked first chip units, and each first chip unit comprises a first chip and a second chip which are bonded up and down. A two-layer chip bonding structure is adopted as a single stacking unit, and compared with a single-layer chip, the structural strength is improved, so that larger internal stress can be borne during bonding, and buckling deformation is avoided. Besides, the preparation method adopts the technological process of bonding the wafers first and then cutting out the chip stacking units, so that the working efficiency and the productivity can be improved, particularly, multiple layers of wafers are stacked to form the wafer stacking body and then the second chip units are directly cut out, the subsequent process of stacking the first chip units one by one is omitted, and the production cost is reduced. And the manufacturing efficiency is further improved.

The invention relates to a wafer stacking method and a wafer stacking structure. In the wafer stacking method, a first wafer structure and a second wafer structure are firstly formed and then stacked and bonded, a metal bonding pad is preset on one side of the first wafer structure before the first wafer structure and the second wafer structure are stacked and bonded, and a metal bonding pad is preset on one side of the second wafer structure after the first wafer structure and the second wafer structure are stacked and bonded. According to the technical scheme, a metal bonding pad does not need to be manufactured, a high-temperature process for manufacturing the metal bonding pad is avoided, wafer buckling deformation caused by the high-temperature process can be avoided, the risks of film layer breakage and machine alarm can be reduced, and multi-layer wafer level stacking can be achieved. The wafer stacking structure can be formed by adopting the wafer stacking method.

The invention belongs to the technical field of semiconductor equipment, and particularly relates to a wafer mapping mechanism for detecting the placement state of wafers in a wafer cassette, which comprises two groups of correlation sensor assemblies, and each group of correlation sensor assembly comprises a transmitting end structure and a receiving end structure, the transmitting end structures of the two sets of correlation sensor assemblies are installed on the lifting cavity door, and the receiving end structures of the two sets of correlation sensor assemblies are installed on the inner side face of the side wall, away from the lifting cavity door, of the lifting equipment cavity. Projections of light rays emitted by the transmitting end structures of the two groups of correlation sensor assemblies on a vertical plane intersect but are not parallel. Through cooperative arrangement of the two groups of correlation sensor assemblies, two groups of detection data can be adopted for comparison, and comprehensive logic judgment is performed, so that the scanning time can be effectively shortened, the defect that wafer crossing or lamination is possibly misreported when the wafer box is inclined is effectively avoided, the accuracy and efficiency of an identification result are improved, the mounting structure is relatively simple, and the practicability is high. Adjustment and maintenance are convenient.

The invention discloses a carrying device based on wafer detection and a coordinate position compensation system, a transfer mechanical assembly comprises a rotating platform and a multi-section type mechanical arm, the rotating movement of the multi-section type mechanical arm is realized through the rotation of the rotating platform, and the multi-section type mechanical arm realizes the telescopic movement in the extension direction; the front end part of the multi-section type mechanical arm is arranged to be of a plane type structure and is used for bearing the wafer, and the multi-section type mechanical arm is used for correcting the carrying position during operation; the bearing assembly comprises a shell part and a bearing seat at the bottom, a plurality of groups of limiting grooves are formed in the horizontal direction where the shell part is located, so that each group of wafers are stacked and borne on each layer of limiting groove, and a gap between every two adjacent wafers is used for insertion of a multi-section type mechanical arm. While the device carries the wafer, the correction process is not based on the mechanical structure specific size such as the rotating arm length of the mechanical arm, and can be completed only through three-point plane teaching. The method is simple, and mechanical errors do not need to be compensated.

The present invention is a temporary adhesive for wafer processing, which is used for temporarily bonding a wafer to a support. This temporary adhesive for wafer processing is composed of a curable silicone resin composition which can be cured by a hydrosilylation reaction. This curable silicone resin composition is a temporary adhesive for wafer processing, which characteristically contains an organopolysiloxane that has in each molecule only one alkenyl group or only one silicon atom-bonded hydrogen atom (SiH group). It is thereby possible to provide a temporary adhesive for wafer processing, a wafer laminate, and a method for producing thin wafers using same, which support an improved productivity for thin wafers, wherein, inter alia, an adequate substrate retention is exhibited post-bonding even when a substrate with high level differences is used; a high process compatibility is exhibited with wafer backside grinding processes, TSV formation processes, and wafer backside wiring processes; facile peeling is exhibited in peeling processes even after passage post-bonding through a lengthy high-temperature heating process in air; and the residue on the substrate post-peeling exhibits an excellent cleanability.

The invention provides a novel carrier wafer manufacturing method based on chip wafer bonding recombination. The novel carrier wafer manufacturing method comprises the following steps: bonding a chip into a carrier wafer with a groove structure in a manner that the front surface of the chip faces downwards through a fusion bonding process; enabling the back surface of the chip to face outwards, and thinning from the back surface to realize fine planarization thinning of the whole thickness of the chip; taking the chip and the carrier wafer with the groove structure as a whole, and carrying out fusion bonding on the chip and the carrier wafer with another wafer; thinning and planarizing the carrier wafer with the groove structure from the back surface through grinding and chemical mechanical grinding so as to remove a non-groove part and expose the front surface of the chip; interconnected copper conductive holes / welding pads are formed on the front surface of a chip through a copper Damascus process, and secondary chemical mechanical grinding is carried out, so that the final mixed-bonded copper welding pads form a shallow dish shape. According to the invention, the technical optimization of chip-to-wafer stacking is realized, and the process maturity is improved.

The application provides a wafer feeding mechanism, and relates to the technical field of automatic wafer feeding machinery, and comprises a mounting plate fixedly installed on a crystal vibration point glue machine, the upper surface of the mounting plate is provided with a gap distribution assembly for wafer conveying and receiving feeding, the gap distribution assembly comprises a plurality of guide grooves which are uniformly distributed in a circle and arranged on one side of the upper surface of the mounting plate, wherein the inner walls of every four adjacent guide grooves are movably connected with sliding frame plates, and the upper surfaces of the sliding frame plates are fixedly connected with positioning discs. The positioning gear connected by the fixed shaft between the two side plates is sleeved with the rack strip with a uniformly installed limiting support plate on the surface, the driving structure provides power for the rack strip, wafer feeding and conveying are carried out at equal intervals, wafer feeding and conveying can be carried out at equal intervals, wafer stacking and mutual influence are prevented, and the quality of crystal vibration point glue is reduced.

Methods, systems, and devices for section yielding in stacked memory architectures are described. A system that implements a stacked semiconductor architecture may include wafers that are divided into die units having multiple sections, and the sections may be coupled as die unit section stacks through a stack of wafers. After stacking the semiconductor wafers (e.g., before or after singulation of die stacks from the stacked wafers), functionality of the die unit section stacks may be evaluated. If a die unit section stack is found to include an error or relatively low performance, the die unit section stack may be disabled, such that other die unit section stacks of a stacked die assembly may be operated (e.g., operated in accordance with a capacity or throughput associated with the remaining memory die unit section stacks).

The invention discloses a method for processing the surface of a cavity on a silicon substrate, which belongs to the technical field of semiconductor manufacturing and micro electro mechanical systems, and comprises the following steps of: forming a central hole distribution area and an edge hole-free area on the surface of a silicon wafer by using a hard mask and an etching process; placing the isolation pad between the edge non-hole areas of the two silicon wafers, and aligning the central hole distribution areas of the two silicon wafers to form a silicon wafer-isolation pad-silicon wafer stacked structure; the isolation pad does not shield the central hole flow channel; and placing the stacked silicon wafers and the isolation pad in a hydrogen atmosphere for annealing treatment to form a uniform cavity. According to the invention, the defects of many surface defects, high roughness and poor process stability of the silicon substrate cavity caused by the edge effect of the hydrogen flow field in the existing SON process are overcome, the optimized hydrogen flow channel is formed through wafer stacking, the hydrogen density distribution is improved, the reaction probability of oxygen atoms and silicon atoms is reduced, and the stable preparation of the high-quality and high-consistency cavity is realized.

The invention provides a method for bonding wafers stacked with high aspect ratio microstructures, a first wafer and a second wafer are provided, the high aspect ratio microstructures are stacked on the surface of the first wafer or the second wafer, and the first wafer and the second wafer are cleaned and dried before being bonded. The cleaning and drying treatment comprises the following steps: pre-cleaning at normal temperature; performing infiltration treatment on the pre-cleaned first wafer and the pre-cleaned second wafer by using an IPA solution, and after the infiltration treatment is completed, putting the first wafer and the second wafer into a supercritical drying cavity, and introducing gas to perform supercritical drying treatment; the cleaned and dried first wafer and second wafer are pre-bonded, and according to the bonding method for the wafers stacked with the high aspect ratio microstructures, the cleaning efficiency is guaranteed, meanwhile, residues of water stains in the high aspect ratio microstructures are reduced, the cleaning effect is improved, and the yield of bonded products is guaranteed.

The utility model provides a discharging and transferring device of a degumming machine, and aims to solve the problems of low efficiency and high misoperation rate caused by adopting a manual transferring and reshaping degumming mode for silicon wafer stack treatment after discharging of the degumming machine in the prior art. The device mainly comprises a discharging platform, a transfer manipulator, a degumming machine discharging water tank, a feeding line and a processing workbench, according to the utility model, a silicon wafer stack is transferred through the six-shaft manipulator, and the silicon wafer shovel at the free end of the tail shaft integrates a swirl nozzle, a bucket and a clamping function; the processing workbench integrates the shaping and degumming functions of a silicon wafer stack, the six-axis mechanical arm, the processing workbench, the feeding line in the field and the discharging water tank cooperate with one another, silicon wafers can be automatically transferred, shaped and degummed, the production efficiency is improved, and manual intervention is reduced. And meanwhile, in the treatment process of the silicon wafer stack, the flexible cushion block and the correction sponge roller are adopted, so that the damage to the surface of the silicon wafer is avoided.

The application discloses a wafer stacking structure and a preparation method thereof. The wafer stacking structure comprises a bearing substrate and a first spliced wafer. The bearing substrate has a first size, and the first spliced wafer is bonded to the surface of the bearing substrate and comprises a plurality of spliced structures. The plurality of spliced structures are closely arranged on the bearing substrate and jointly cover the entire surface of the bearing substrate, and a light-emitting diode structure is formed on each spliced structure. Each spliced structure is formed by cutting a growth substrate with a second size to a preset shape after an epitaxial layer is grown on the growth substrate. The first size is larger than the second size. The first spliced wafer contained in the wafer stacking structure of the application is formed by splicing the spliced structures. The spliced structures are formed by cutting a growth substrate with a small size to form an epitaxial layer, and have good growth quality. Therefore, the wafer stacking structure formed by the spliced structures also has high product quality.

Bonded wafer device structures, such as a wafer-on-wafer (WoW) structures, and methods of fabricating bonded wafer device structures, including an array of contact pads formed in an interconnect level of at least one wafer of the bonded wafer device structure. The array of contact pads formed in an interconnect level of at least one wafer may have an array pattern that corresponds to an array pattern of contact pads that is subsequently formed over a surface of the bonded wafer structure. The array of contact pads formed in an interconnect level of at least one wafer of the bonded wafer device structure may enable improved testing of individual wafers, including circuit probe testing, prior to the wafer being stacked and bonded to one or more additional wafers to form a bonded wafer structure.

The present invention provides a film stacking device, a laminating device, and a battery production line, wherein the film stacking device includes: a feeding mechanism for providing a diaphragm; a cutting mechanism disposed downstream of the feeding mechanism, the cutting mechanism for cutting the diaphragm; a film laying mechanism disposed downstream of the cutting mechanism, the film laying mechanism including a first frame, a roller, a first drive structure, and a second drive structure, the first drive structure for driving the roller to move horizontally relative to the first frame, the roller having a first position close to the cutting mechanism and a second position away from the cutting mechanism, the roller having a film-grabbing state and a release state, and the second drive structure for driving the roller to rotate in the first direction or the second direction. In the above structure, only one feeding mechanism can be disposed on the side of the laminating table to achieve the laying of the diaphragm in two directions, thereby reducing the space occupied by the film stacking device in the horizontal direction and not occupying additional vertical space, making the overall volume of the film stacking device smaller.

Various embodiments of the present disclosure are directed towards a processing tool. The processing tool includes a housing structure defining a chamber. A first plate is disposed in the chamber. A first plasma exclusion zone (PEZ) ring is disposed on the first plate. A second plate is disposed in the chamber and underlies the first plate. A second PEZ ring is disposed on the second plate. The second PEZ ring comprises a PEZ ring notch that extends inwardly from a circumferential edge of the second PEZ ring.

Provided herein include various examples of a method for manufacturing aspects of flow cell. The method may include performing chemical processes on a surface of the patterned wafer to prepare the surface of the patterned, singulating the wafer into individual dies, orienting each die on a temporary substrate, where the orienting creates spaces between each individual die, and molding a material over the spaces to create a hybrid wafer comprised of glass and molded material. The method may also include bonding two of the hybrid wafers together, forming a bonded wafer stack.

The invention provides a storage chip and a preparation method of the storage chip, the storage chip provided by the invention comprises a storage wafer and a control wafer, and the storage wafer and the control wafer are stacked and are in bonding connection through a three-dimensional heterogeneous integrated structure; the storage wafer comprises a first substrate and a plurality of storage units, the control wafer comprises a second substrate and a plurality of control units, and the control units are connected with the storage units and control the storage units to perform read-write operation; the storage wafer comprises a magnetoresistive random access memory; the control wafer includes at least one of a carbon nanotube transistor and a two-dimensional material-based transistor. The memory chip has the characteristics of low power consumption and high data transmission speed, the preparation process of the control wafer is convenient to be compatible with the subsequent process of the chip, and the product reliability is high.

Disclosed is an integrated circuit device. In some aspects, a device includes a first wafer including a first dielectric layer, a first set of bonding pads disposed in the first dielectric layer and a first circuit disposed on the first dielectric layer, and a second wafer including a second dielectric layer, a second set of bonding pads disposed in the second dielectric layer and a second circuit disposed on the second dielectric layer. The device further includes through-vias including at least one power via in the second wafer, and a backside power distribution network (BSPDN) layer disposed on the second wafer. The first set of bonding pads is bonded with the second set of bonding pads.

This invention provides a single-power-source battery cell stacking machine, including a frame, an anode wafer feeding device, a cathode wafer feeding device, an anode wafer picking and placing device, a cathode wafer picking and placing device, a membrane placement device, a stacking device, and a drive device. By setting up an anode wafer picking area, an anode wafer transfer area, an anode wafer stacking area, a cathode wafer picking area, a cathode wafer transfer area, a cathode wafer stacking area, and a diaphragm placement area on the frame, the anode wafer picking and placing device and the cathode wafer picking and placing device respectively handle the picking and placing of anode and cathode wafers. The stacking device moves between the anode wafer stacking area, the diaphragm placement area, and the cathode wafer stacking area, stacking and pressing the anode wafers, diaphragm strips, and cathode wafers layer by layer. In this design, multiple motion mechanisms for picking and placing anode wafers, picking and placing cathode wafers, and stacking diaphragms use the same power source, with unified control of actions to ensure consistency and improve stacking quality.

A semiconductor package may include: a base wafer; a plurality of lower core wafers stacked on the base wafer; an upper core wafer on the plurality of lower core wafers; an oxide structure covering side surfaces of the plurality of lower core wafers and the upper core wafer; and a molded structure configured to cover the side surfaces of the oxide structure and spaced apart from the plurality of lower core wafers and the upper core wafer, the oxide structure being inserted between the molded structure and the plurality of lower core wafers and the upper core wafer. Each of the base wafer and the plurality of lower core wafers may include a through electrode, and the upper core wafer may include an insulating layer disposed on its bottom surface and pads disposed in the insulating layer. The oxide structure may expose an edge portion of the top surface of the base wafer.

The present disclosure relates to methods, devices, systems, and techniques for managing a high bandwidth memory (HBM). An example semiconductor device includes a control die and wafers stacked together along a first direction. Each of the wafers includes a semiconductor substrate extending along a second direction perpendicular to the first direction and semiconductor structures on a side of the semiconductor substrate. The control die is coupled to the semiconductor structures of each of the wafers by contact structures extending through a corresponding semiconductor substrate of at least one of the wafers along the first direction.

There is provided a method for providing a coated graphene layer structure (410) on a silicon-containing wafer (435), the method comprising: (1) providing a wafer stack (420) comprising, in order, a transparent substrate (400), a nitride layer (405), a graphene layer structure (410), and a dielectric passivation layer (415) wherein the dielectric passivation layer (415) has an exposed upper surface; (2) forming or adhering (300) a further layer (435) onto the exposed upper surface of the dielectric passivation layer (415); and (3) removing the substrate (400) by laser lift-off 305 to expose a surface of the nitride layer (405) remote from the graphene layer structure (410); wherein the nitride layer (405) of the wafer stack (420) comprises a first surface directly adjacent to the substrate (400) and a second surface directly adjacent to the graphene layer structure (410), and wherein the first surface and the second surface are each independently formed of aluminum nitride or boron nitride; and wherein: the method further comprises wafer bonding (130, Fig. 2) the exposed surface of the nitride layer to the surface (235b ', Fig. 2) of the silicon-containing wafer (235, Fig. 2) after the step (125, Fig. 2) of removing the substrate (225, Fig. 2); or the step of forming or adhering includes wafer bonding (300), and the further layer is a silicon-containing wafer (435). The laminate (440) is suitable for manufacturing an electronic device (460).

The utility model discloses a photovoltaic silicon wafer cleaning separation mechanism, which comprises a storage rack, a storage cavity for stacking photovoltaic silicon wafers, and a discharge port on the side of the storage rack, which is in communication with the storage cavity; a conveyor belt assembly is arranged at the discharge port of the storage rack in a preset first direction, and is used for receiving and transmitting the photovoltaic silicon wafers output by the storage rack; a negative pressure generating device is arranged above the inside of the storage cavity, and is used for extracting the fluid above the photovoltaic silicon wafer stack in the storage cavity to form a negative pressure adsorption area; a separation device comprises at least one first nozzle unit for directing the output of fluid towards the side edge of the photovoltaic silicon wafer stack in the storage cavity; the negative pressure generated by the negative pressure adsorption area and the directional jet of the first nozzle unit work together to form a separation effect between adjacent photovoltaic silicon wafers; the utility model can solve the problem of poor separation efficiency and cleaning effect of the existing photovoltaic silicon wafer separation and cleaning equipment.