330 results about "Signal delay" patented technology

Disclosed in the present invention are an automatic delay calibration method for a smart speaker system, a device, and a storage medium. The method comprises: initializing a smart speaker system and performing environmental testing to preliminarily configure system parameters; exciting a target sound channel and playing a target test signal; locating a first test signal on the basis of a voice activity detection (VAD) algorithm, determining the start and end of the first test signal, and identifying a time difference of the first test signal to obtain a delay of main channels; locating a time of arrival of a second test signal on the basis of a fast peak search algorithm, and identifying a delay of a subwoofer; and performing delay calibration on the subwoofer and the main channels, and dynamically adjusting delay calibration parameters of the channels on the basis of a delay calibration amount, thereby achieving accurate time alignment between the subwoofer and the main channels. The present invention solves the problem of low-frequency signal delays that are difficult to process in conventional technologies, and particularly makes a breakthrough progress in the coordination of a subwoofer and other sound channels.

The invention relates to the related technical field of robot fault detection, in particular to an industrial robot real-time fault detection method and system, and the method comprises the steps: analyzing the operation state of an industrial robot based on a communication state signal, determining a motion domain and sensing domain synchronization factor, configuring a cross-domain feature vector and a performance feature vector, and carrying out the fusion, the deep belief network is used for drawing up the fault probability graph and identifying the feature identifier to achieve fault reminding, the technical problems that a fault response strategy is fixed, complex and changeable industrial scene requirements are difficult to adapt, and fault reminding cannot be effectively conducted in time are solved, cross-domain feature vectors and performance feature vectors are constructed, and the fault reminding efficiency is improved. The method has the technical effects that the serial control sequence is dynamically verified, multi-scale decomposition is combined, signal delay fluctuation and retransmission frequency are accurately extracted, a deep belief network is used for fusing time sequence and spatial features to identify fault types, fault reminding is carried out through a fault probability distribution map, and the operation safety of the industrial robot is guaranteed.

The invention relates to the technical field of automobile fault detection, and discloses a self-adaptive optimization method and system of an automobile fault detection system and a storage medium. The method comprises the following steps: performing real-time detection on attitude data based on a preset inclination angle threshold value and steering signal delay, and generating angular velocity sensing data and a vibration interference identification result; performing characteristic decomposition on the attitude data stream, identifying abnormal fluctuation, judging whether a potential fault signal exists or not, updating the calibration frequency of the vehicle-mounted sensor, and obtaining adjusted parameter configuration information; a fusion result of the attitude data is analyzed, an evaluation index of deviation correction precision is calculated, a real-time feedback mechanism is constructed based on the evaluation index, and a fault signal correction scheme is generated; and constructing a continuous detection cycle, analyzing the matching effect of the calibration frequency and the steering signal delay, and if the deviation correction precision does not reach a first preset standard, iteratively processing the attitude data. According to the invention, the precision and response speed of adaptive optimization of the automobile fault detection system are improved.

A switching circuit includes a power switch, a first driver configured to drive the power switch based on a first input signal, a delay circuit configured to output a delayed input signal, and a second driver configured to drive the power switch based on the delayed input signal. The first driver has a first driving strength and is configured to drive the power switch in a first stage of operation. The delayed input signal is delayed by a delay value relative to a second input signal. The second driver has a second driving strength higher than the first driving strength and is configured to drive the power switch in a second stage of operation, which is subsequent to the first stage of operation.

The invention discloses a packaging structure, a packaging method and an electronic component, and relates to the technical field of semiconductors, and the packaging structure comprises a first chip, a second chip, a first electric connection part, a second electric connection part and a rewiring layer. Through the superposition cross layout of the first chip and the second chip, while the integration level is ensured, the wiring space is expanded by using the radial distribution of the non-overlapping area, and the coverage connection of the re-wiring layer is matched, so that the high-density interconnection is realized, and the parasitic inductance and parasitic capacitance are reduced; meanwhile, the signal transmission path is shortened through the combination of the cross layout and the rewiring layer, and the parasitic inductance and the parasitic capacitance are further reduced; besides, paths of different signals can be physically isolated through independent distribution of the non-overlapping areas, parasitic inductance and parasitic capacitance are further reduced, signal delay, reflection and coupling interference are reduced, and the problem of poor signal transmission performance caused by wiring limitation in traditional packaging is effectively solved.

The application provides a vehicle control method and device, a storage medium and a vehicle, and belongs to the technical field of vehicles. In the case where the brake energy recovery function of the vehicle is in an activated state, a first available brake energy recovery capability value is input into a first prediction model, so that a second available brake energy recovery capability value at a second time can be predicted. Then, based on the first available brake energy recovery capability value, the second available brake energy recovery capability value and a brake pedal opening degree, a first brake energy recovery torque request value at a first time is determined, and in combination with a first coasting energy recovery torque, a first motor actual execution torque is obtained. Finally, based on the first motor actual execution torque and a second brake energy recovery torque request value at the second time, it is determined whether to disable the brake energy recovery function at the second time, so that the influence of CAN signal delay can be eliminated to a certain extent, and the brake energy recovery function can be prevented from being abnormally disabled.

The invention provides a radar multi-target tracking and imaging echo simulation method and system, and belongs to the technical field of radar echo simulation. The method comprises the following steps of: pushing the position and the motion state of a radar platform and RCS point set data of a plurality of targets to an impact function generation FPGA (Field Programmable Gate Array), and latching data through the FPGA to form a multi-target data set when a radar signal is detected; point set data, postures and world coordinates of the targets in the multi-target data set are split into a plurality of calculation instances, sub-range profile data of each calculation instance are calculated in parallel, the sub-range profile data of the multiple calculation instances are merged and superposed into range profile data of a single target, similarly, range profile data of all the targets are calculated in parallel, and the range profile data of all the targets are calculated in parallel; and after obtaining multi-target range profile data, carrying out convolution on the multi-target range profile data and a radar signal, after obtaining a convolution signal, carrying out signal delay and multi-branch amplitude-phase modulation, and outputting the amplitude-phase modulated convolution signal. According to the invention, signal echo simulation can be carried out in parallel pipeline, and high-quality large-scene echo signals are output.

The application discloses a motion intention recognition method based on a TASS optimizer, and relates to the fields of artificial intelligence and rehabilitation robots. The method first collects surface electromyography signals of lower limbs of a subject, performs data preprocessing, constructs a Transformer model, designs a TASS optimizer to train the model, extrapolates a gradient compensation signal delay, combines a gradient to help weight escape a local minimum value, establishes a sparse mechanism to selectively attenuate momentum and prevent momentum stagnation, introduces gradient confidence weighting to dynamically adjust a learning rate, and finally uses slow weight reasoning to recognize motion intention. Compared with the prior art, the application can realize time sequence alignment, accelerate model convergence, adapt to muscle intermittent activation, and improve the generalization ability of the model.

Embodiments of the present invention disclose a memory device and a method of operating a memory device. Embodiments disclosed herein relate to reducing power consumption of a memory device when transitioning from a sleep state to an operational state. In one aspect, the memory device includes a memory cell for storing data. In one aspect, the memory device includes an output driver configured to generate an output signal indicative of the stored data in response to a sleep tracking signal indicating that the memory cell is in an operational state, and to generate an output signal having a predetermined voltage independent of the stored data in response to the sleep tracking signal indicating that the memory cell is in a sleep state. In one aspect, the sleep tracking signal is delayed from a sleep control signal, causing the memory cell to operate in either the sleep state or the operational state.

A display module, a manufacturing method thereof, a display panel and a display device are provided. The display module comprises a substrate and a first circuit layer. The first circuit layer is arranged on one side of the substrate. The first circuit layer comprises a first pixel circuit part, a second pixel circuit part and a gate drive circuit arranged between the first pixel circuit part and the second pixel circuit part. The first pixel circuit part and the second pixel circuit part are electrically connected with the gate drive circuit. By arranging the gate drive circuit between the two pixel circuit parts, the maximum length of the conductive path between the gate drive circuit and the light emitting unit can be reduced, and the signal delay can be reduced.

A monitoring apparatus for monitoring propagation delay of a signal along a path through an integrated circuit is disclosed. The monitoring device comprises a delay device configured to receive the signal and to generate a delayed signal, the delayed signal being a version of the received signal that is time delayed with respect to the received signal, a detection window device configured to generate a detection window signal based on a clock signal of the integrated circuit, and a determination device configured to determine the detection window signal based on the clock signal. The determination means is configured to determine whether a value of the received signal differs from a value of the delayed signal during a time defined by the detection window signal, and to generate a determination signal based on the determination.

The invention provides a DRAM (Dynamic Random Access Memory) data reading time sequence calibration method and device, and the method comprises the steps that in a DRAM initialization stage, a DRAM controller writes specific data into a fixed address, sends a reading instruction, and receives a fed-back data gating signal and a data signal; carrying out delay processing on the data strobe signal, delaying the data strobe signal into a plurality of data strobe signals with different delay values, and selectively outputting the data strobe signals by using a multiplexer; the asynchronous FIFO module is used for receiving a data signal, and the multiplexer selects an output data strobe signal as a write clock signal of the asynchronous FIFO module; after the asynchronous FIFO module receives the data signal, a DARM system clock signal is used as a read clock signal of the FIFO module, and FIFO read data is output; and comparing the FIFO read data with target data, and when the comparison result is inconsistent, adjusting a control signal of the multiplexer until the comparison result of the FIFO read data and specific data is consistent.

The invention relates to the technical field of roadbed engineering monitoring, in particular to a roadbed engineering settlement deformation monitoring device and method, and the device comprises an optical fiber sensor network, a data collection module, a signal processing module, a model matching module, a frequency analysis module, a data fusion module, an early warning trigger module and a prediction report module. The optical fiber sensor network is deployed in a roadbed to collect an optical signal delay sequence, fluctuation characteristics are extracted through data collection and signal processing, settlement acceleration risks are judged through model matching, the speed trend is determined through frequency analysis, historical and real-time data are integrated through data fusion, an alarm is triggered when an early warning module exceeds a threshold value, and a risk assessment report is generated through a prediction module. According to the device, roadbed three-dimensional global monitoring and full-process automation are achieved, monitoring blind areas are eliminated, early warning lag is shortened, and accurate support is provided for roadbed stability operation and maintenance.

A memory device includes a physical layer (PHY) interface, and a memory cell array. The PHY interface includes a phase adjusting circuit configured to generate a plurality of phase-shifted clock signals and a phase-shifted training clock signal based on a clock signal and configured to delay the clock signal based on a plurality of comparison signals output from a comparator, the comparator configured to compare training data with each of a first reference voltage and a second reference voltage based on the plurality of phase-shifted clock signals and the phase-shifted training clock signal to output the plurality of comparison signals, the plurality of comparison signals including first comparison signals based on the plurality of phase-shifted clock signals, and second comparison signals based on the plurality of phase-shifted clock signals and the phase-shifted training clock signal, and a decoder configured to perform a duo-binary decoding on the first comparison signals.

The invention discloses an MOS / IGBT (Metal Oxide Semiconductor / Insulated Gate Bipolar Transistor) driving circuit for giving a driving current in real time according to a target driving waveform, and relates to the technical field of MOS / IGBT driving control, comprising a PWM (Pulse Width Modulation) signal generation module for generating an original PWM signal; the delay circuit module is used for delaying the original PWM signal to obtain a target driving waveform with a target switching speed; the operational amplifier negative feedback circuit module comprises an input positive electrode, an input negative electrode and an output pin, the input positive electrode is used for accessing a target driving waveform, the input negative electrode is connected with a grid electrode of the MOS / IGBT device, and the output pin is connected with an input end of the current driving circuit module; and a target driving waveform is compared and amplified by the operational amplifier negative feedback circuit module and is subjected to current amplification by the current driving circuit module to drive the MOS / IGBT device. According to the invention, all power tubes in the system can have consistent switching speed, and even power tubes of different models can be driven to have consistent waveforms, so that the efficiency and stability of the whole system are improved.

The invention discloses an electromagnetic vortex wave radar system feed network delay measurement and correction method. The method comprises the following steps: establishing a multi-channel electromagnetic vortex wave radar system feed network length and signal delay model; establishing an inter-channel signal delay measurement system of the electromagnetic vortex wave radar system; the method comprises the following steps: performing matched filtering on multi-channel echo signals in an inter-channel signal delay measurement system of an electromagnetic vortex wave radar system to obtain a one-dimensional distance image, obtaining an inter-channel signal delay integer part compensation sequence according to the one-dimensional distance image, and performing up-sampling on the one-dimensional distance image to obtain an inter-channel signal delay fractional part compensation sequence; and correcting the inter-channel signal time delay integer part compensation sequence through a signal time delay integer part correction method, and correcting the inter-channel signal time delay fractional part compensation sequence through a fractional part signal time delay correction method of Lagrange interpolation. According to the invention, measurement and compensation of signal delay inconsistency between channels of the multi-channel electromagnetic vortex wave radar system are realized.

Disclosed are method and electronic components for: i) electronically extracting a sequence of values from a measurement signal corresponding to a position of a moving object, wherein the sequence of values indicates the position of the moving object at corresponding time increments; ii) electronically determining at least one of an estimate for a velocity of the moving object and an estimate for an acceleration of the moving the object based on a plurality of the values in the sequence of values; and iii) electronically correcting a value in the sequence of values to substantially reduce the effect of processing and signal delays based on one or both of the velocity and acceleration estimates.

The utility model relates to the technical field of H-bridge drive circuits, and discloses a high-reliability H-bridge dead-zone generation circuit, which comprises two AND gates for preventing two MOS (Metal Oxide Semiconductor) transistors on the same side of the circuit from being switched on at the same time; the exclusive-OR gate can distinguish input signal directions and output response control signals; the Schmitt trigger is used for converting the curve waveform into a PWM (Pulse Width Modulation) square wave signal and inhibiting noise and interference in an input signal; the RC time delay circuit is connected with the Schmitt trigger and is used for realizing signal delay; the two AND gates comprise a first AND gate and a second AND gate; the first AND gate and the second AND gate are electrically connected with the exclusive-OR gate, and the exclusive-OR gate and the first AND gate are electrically connected with the Schmitt trigger; according to the utility model, the formation of dead zone time is realized through RC time delay and Schmidt characteristics, the condition of circuit damage caused by simultaneous conduction of the H-bridge drive circuit in the working process is avoided, the hardware cost is lower, and the reliability is higher than the reliability realized by software.

This disclosure provides a data processing circuit and a semiconductor memory. The data processing circuit includes a parallel-to-serial conversion module for receiving an initial data signal and performing parallel-to-serial conversion on the initial data signal to generate a data signal to be processed and an auxiliary data signal. The initial data signal is a parallel data signal, while the data signal to be processed and the auxiliary data signal are both serial data signals, with the auxiliary data signal delayed by one unit time interval compared to the data signal to be processed. A first driving module receives the data signal to be processed, enhances its driving capability, and outputs a target data signal to a data port. A second driving module receives the data signal to be processed and the auxiliary data signal, and when the potentials of the data signal to be processed and the auxiliary data signal are the same, performs de-emphasis processing on the target data signal. This circuit can reduce the impact of channel loss on signal quality.

The application provides a radar multi-target tracking and imaging echo simulation method and system, and belongs to the technical field of radar echo simulation. The method pushes the position and motion state of a radar platform and RCS point set data of multiple targets to an impact function generation FPGA. When a radar signal is detected, the FPGA latches data to form a multi-target data set. The point set data, attitude and world coordinates of the targets in the multi-target data set are split into multiple calculation instances, the sub-range image data of each calculation instance is calculated in parallel, and the sub-range image data of the multiple calculation instances is combined and superimposed into the range image data of a single target. Similarly, the range image data of all targets is calculated in parallel, and the multi-target range image data is convolved with the radar signal. After the convolution signal is obtained, signal delay and multi-branch amplitude-phase modulation are performed, and the amplitude-phase modulated convolution signal is output. The application can perform signal echo simulation in parallel and output high-quality large-scene echo signals.

An ultrasound imaging transducer receives echo data from a matrix of elements distributed in two or more dimensions. Received echo data is delayed using an analog delay circuit consisting of an array of signal storage capacitors addressed by input and output switches addressed by input and output counters. The output of the ARAM is digitized by an analog to digital converter (ADC). Digital data is processed and streamed to a base system for further processing to form and display an image. The input counter address update phase is programable in quanta less than or equal to one half the input counter address update period. The output counter address update phase is held at a fixed phase relationship to the ADC sampling clock. The signal delay through the ARAM is controlled by the summation of two or more controls.

The invention discloses a stacked structure of a hybrid packaging technology and a manufacturing method thereof, and relates to the technical field of semiconductor manufacturing, the stacked structure of the hybrid packaging technology and the manufacturing method thereof comprise a second bare chip and a carrier plate, the second bare chip is arranged in an inverted mode, a rewiring layer is arranged at the bottom of the second bare chip, and the rewiring layer is arranged on the carrier plate. A second bare chip solder bump is arranged at the bottom of the rewiring layer, the second bare chip solder bump is connected with a pin at the top end of the carrier plate, and bottom filling glue is filled at the periphery of the second bare chip solder bump between the rewiring layer and the carrier plate; according to the invention, the chips are stacked on the other chip, and compared with routing and inverted mounting of two chips on the same plane, the layout area of the carrier plate is saved, and the wiring distance of a circuit is reduced, so that signal delay, electromagnetic interference and resistance are reduced, and power consumption and voltage drop are reduced; and a routing technology is flexibly used and combined with flip packaging, so that the overall packaging difficulty and cost are reduced.

The utility model discloses a cable pair stranding machine, including base, the base top is fixed with support, one side fixed bearing seat at support top end, the other side fixed first bevel gear at support top end, bearing rotation is connected with the pivot in bearing inside, one end of pivot is installed with drive mechanism, the pivot other end axle body penetrates first bevel gear center, the axle body fixed with fixed base of pivot penetration first bevel gear, both sides of fixed base all rotation is connected with the reel, the axle body fixed with second bevel gear of reel near rotation junction, second bevel gear and first bevel gear meshing connection, the end of pivot near fixed base is fixed with the stranding reel, adopts the rigid meshing transmission of first bevel gear and second bevel gear, the speed ratio relation of forced binding reel rotation and revolution, avoids the signal delay and coordination error of electronic synchronous system, ensures double wire core pay-off length absolute synchronization, eliminates the tension imbalance and pitch fluctuation from the root, promotes the stranding accuracy.

The application relates to the technical field of chip design, and particularly discloses a routing method and system based on timing criticality, which abstracts physical layout into a node network, constructs a weighted cost function of total wiring length and critical path length, adopts a minimum spanning tree algorithm to iteratively expand a path and record a parasitic parameter, calculates a merging cost value based on the product of the length of a coincident path and the timing criticality of a node, generates a virtual node by merging a node pair with the maximum benefit, and cyclically optimizes until a convergence condition is met, so that the dual objectives of wiring resource optimization and timing critical path delay reduction are achieved. The method is based on a more accurate time delay model, defines a target function which comprehensively considers the overall routing cost and the routing cost of a timing critical load node, makes timing analysis more accurate, reduces the signal delay and the size of a clock cycle of a load node according to the criticality of the load node, and effectively increases the running speed of a chip.

The application discloses a voltage-controlled oscillator and electronic equipment, the voltage-controlled oscillator comprises a sampling module, a voltage lifting module and an oscillator module; the sampling module is connected with the voltage lifting module, and the voltage lifting module is connected with the oscillator module; wherein the sampling module is used for inputting a clock signal and maintaining a voltage unchanged during a low voltage period of the clock signal; the voltage lifting module is used for lifting an input voltage signal; the oscillator module comprises a frequency control unit and an inverter chain; the frequency control unit is used for controlling an oscillation frequency and performing a one-phase transformation on a signal; the inverter chain is used for performing a signal delay and inversion; and the inverter chain comprises a plurality of inverter devices connected in sequence. The voltage-controlled oscillator does not need to use a power supply voltage as a control voltage, the oscillation amplitude is more stable, and sampling application can be conveniently and efficiently realized. The application can be widely applied in the technical field of electronic equipment.

The application discloses an inverter wired parallel machine high-frequency synchronization method, which is used for realizing power frequency synchronization and high-frequency carrier wave synchronization through a group of power frequency synchronization signals and comprises the following steps: circuit configuration; after a plurality of inverters are connected in parallel in a master-slave working mode, output ends are connected to load equipment; a master device sends a power frequency synchronization signal to a slave device; the slave device detects the power frequency synchronization signal; a phase difference of a high-frequency carrier wave signal between the slave device and the master device is calculated; and the slave device adjusts a high-frequency carrier wave frequency of itself according to the phase difference. Compared with a traditional scheme, the number of IO ports is reduced, the circuit structure is simplified, and the requirement of circuit components is reduced. Meanwhile, the synchronization signal is accurately captured through the capture function of a master control unit, synchronization information is acquired, the carrier wave frequency of the slave device is adjusted through a software algorithm, parallel connection is realized, the influence of signal delay of a hardware circuit on parallel connection is greatly weakened, the universality is higher, the reliability is higher, and the parallel connection effect is better.

The invention discloses an OFPGA chip packaging structure, which comprises an OFPGA silicon chip main body and a glass substrate, TGV through holes, fine pitch waveguides and coupling gratings are arranged on the glass substrate, and the OFPGA silicon chip main body and the glass substrate are bonded through micro salient points and covalent bonds to realize mechanical fixation and signal interconnection; the glass substrate realizes vertical electrical interconnection through high-density TGV through holes, optical signal transmission is realized through fine-pitch waveguides and coupling gratings, and the micro convex points are metal convex structures formed on the glass substrate. The space utilization rate is greatly increased; ultra-short-distance electric signal transmission in the vertical direction is achieved through the high-density TGV through holes, and signal delay is greatly reduced; the thermal stress after bonding is effectively reduced by means of the similar thermal expansion coefficient characteristic of the glass substrate and the silicon chip, and the stability of photoelectric signal separation transmission is ensured by combining high-precision matching interconnection of the TGV through holes and the micro convex points.

The invention discloses a galvanometer performance parameter acquisition method. A main control board sends a starting signal, an image acquisition signal and a rotation signal to a line laser, a camera and a driving mechanism in a galvanometer; the camera collects a laser strip image; the laser strip image and the sending time of the image acquisition signal are stored in an associated mode; the galvanometer is reset, the main control board delays the image acquisition signal for multiple times, and multiple images are repeatedly acquired; sorting the plurality of images according to image acquisition signal emission moments and extracting characteristic lines of laser strips; calculating a pixel distance Si between the feature lines in two adjacent images; obtaining a response time parameter, a rotation parameter and a deflection precision parameter of the galvanometer according to Si; according to the method, images are acquired for multiple times in a camera delay image acquisition mode, and after all the images are sequenced according to time, laser stripes in all the images can reflect moving tracks of the laser stripes; the method has the characteristics of being high in automation degree and accurate in calculation.

This invention relates to the field of lidar technology, and provides an optical phased array lidar optoelectronic module, including a substrate, an optical chip, an electrical chip, and a main control circuit. The optical chip is integrated on the substrate, the electrical chip is packaged on the side of the optical chip away from the substrate, and the main control circuit is integrated on the substrate. The main control circuit and the optical chip are spaced apart and electrically connected. The direct integration of the optical chip and the electrical chip significantly reduces the number of wires and the overall size. The short and consistent trace distance between the optical chip and the electrical chip not only reduces signal attenuation and interference during transmission but also improves signal integrity and transmission efficiency. It helps eliminate signal delay and phase mismatch caused by differences in trace length, solving the technical problems of large size, high trace resistance, and poor consistency between different channels in existing optical phased array lidar optoelectronic modules. This reduces packaging costs and complexity, and improves packaging reliability and stability.

The utility model discloses a narrow-strip high-performance memory strip board which comprises a memory strip board circuit board, a first BGA particle, a second BGA particle, a third BGA particle and a fourth BGA particle are arranged on the front face of the memory strip board circuit board, and a fifth BGA particle, a sixth BGA particle, a seventh BGA particle and an eighth BGA particle are arranged on the back face of the memory strip board circuit board. The board width of the memory strip board circuit board is smaller than or equal to 28 mm, the number of layers of the memory strip board circuit board is eight, L1, L3, L6 and L8 are wiring layers, and L2, L4, L5 and L7 are a power supply layer and a grounding layer. Particles are distributed on the front face and the back face, the board width is reduced, the number of wiring layers is reduced, the cost is reduced, meanwhile, the signal transmission path is shortened, address lines are in cross connection through L3 / L6 layers, data lines are in layered wiring, signal delay and attenuation are remarkably reduced, the copper foil fully covers the power supply layer, stable power supply is ensured, electromagnetic interference is reduced, and the signal-to-noise ratio is improved.