136 results about "Delay-locked loop" patented technology

A digital frequency synthesizer includes a delay-locked loop (DLL) that generates time-delayed versions of a reference clock signal, a clock divider that executes an integer-division operation on one delayed clock signal to generate an integer-divided clock signal, and control circuitry that generates fractional data for enabling a fractional division. The digital frequency synthesizer further includes a first clock selector that selects one delayed clock signal as a DLL clock signal based on the fractional data, a delay chain that generates time-delayed versions of the DLL clock signal, and a second clock selector that selects one delayed clock signal as a selected clock signal based on the fractional data. A rising edge of the integer-divided clock signal is adjusted based on the selected clock signal to generate a fractional-divided clock signal that is a fractional-divided version of the reference clock signal.

The invention relates to the technical field of serial communication, in particular to a high-speed clock recovery method and device based on an adjustable delay chain, and the method comprises the steps: generating a recovery clock initial phase; a multi-stage programmable delay chain is adopted, and a phase-locked loop or delay-locked loop structure is combined, so that the initial phase of a recovered clock is finely adjusted and locked, and phase capture and clock edge alignment are performed; based on a multi-path recovery structure, a path with the minimum error is selected from the delay paths through a preset phase error detection mechanism to serve as an output channel; environment parameters of the environment are collected, parameters of the multi-stage programmable delay chain are dynamically adjusted, and high-speed clock recovery is completed. According to the method, the edge capture precision, the system jitter tolerance and the working frequency range of the recovered clock are remarkably improved, and then the phase consistency, the anti-interference capability and the overall data receiving reliability of the recovered clock in the high-speed communication system are effectively improved.

The invention belongs to the field of communication and navigation, and relates to a synchronization module of a communication and navigation integrated receiver, the receiver and a signal processing method. The synchronization module has two signal paths: one is used for synchronizing a received signal for a communication service; the other loop is a navigation tracking loop which comprises a delay locking loop and a frequency locking loop and is used for estimating time delay for navigation service; the delay locked loop comprises a real-time branch, a lead branch and a delay branch. Mixing the received signal with a local carrier, and filtering to obtain an intermediate frequency signal; multiplying the intermediate frequency signal by a reference signal, and performing coherent integration to obtain an integration result; calculating autocorrelation function values of the three branches through an integral result; calculating time delay; calculating the time delay to obtain a time delay estimation value, and transmitting the time delay estimation value to a time synchronization module and a reference signal generation module; and obtaining a frequency offset estimation value according to an integration result, and transmitting the frequency offset estimation value to a frequency synchronization module and a carrier generation module. The problem that an existing synchronization module cannot be compatible with communication and navigation synchronization is solved.

The embodiment of the invention provides a delay-locked loop, a control method thereof and a memory. The delay-locked loop includes: a phase detection circuit configured to receive a reference clock signal and a feedback clock signal, and generate an instruction signal by comparing phases of the reference clock signal and the feedback clock signal; the time delay circuit is connected with the phase detection circuit and is configured to receive the instruction signal and output the received instruction signal in a delayed manner; the control circuit is connected with the delay circuit and is configured to receive the instruction signal output in a delayed manner and generate a control signal according to the instruction signal; and the clock adjustment circuit is connected with the control circuit and the phase detection circuit, and is configured to receive the control signal and the reference clock signal, and output a feedback clock signal based on the control signal and the reference clock signal.

A phase-locked loop or delay locked loop provides a coarse alignment between an input clock and an output clock. A latch receiver circuit provides an indicator of a delay error between the input clock and the output clock. The delay error is used by a control circuit or state machine to adjust a fine delay that affects the output clock signal timing relative to the input clock signal. The fine delay is adjusted to minimize the timing difference between the output clock signal and the input clock signal.

The invention relates to a delay locked loop circuit comprising: a voltage controlled delay line (VCDL); a phase detector circuit configured to process the first and last output signals of the VCDL to provide: i) an uplink pulse signal; and ii) a downlink pulse signal; a charge pump configured to provide a feedback voltage signal based on the uplink pulse signal and the downlink pulse signal; a phase signal processor configured to process the uplink pulse signal and the downlink pulse signal to provide a delay code lock signal representing whether the first output signal is out of phase with the last output signal by 2 [pi] radian; and a delay code setter configured to provide a delay code setting signal representing one candidate delay code in the sequence of different candidate delay codes. When the delay locked loop circuit is in a calibration operation mode: the fixed voltage source provides a fixed voltage signal as a control voltage signal of the voltage controlled delay line; when the delay code lock signal indicates that the first output signal and the last output signal have no out-of-phase 2 [pi] radians: the delay code setter applies a delay code setting signal to the VCDL such that the delay code setter sequentially applies different candidate delay codes to the voltage controlled delay line until a selected delay code is allocated; and when the delay locked loop circuit is in an active operation mode: the charge pump provides a feedback voltage signal as a control voltage signal of the voltage controlled delay line; and the VCDL uses the selected delay code as the delay code.

A method of navigating user equipment in motion relies upon local signals of opportunity for mapping landmarks. The signals of opportunity include synchronization signals and reference signals used to identify sources of the received signals, the respective carrier phases, the respective code phases, and the Doppler frequency for each received signal. A reference signal locked loop, a phase locked loop, and a delay locked loop utilize inherent channel gain from an acquisition step to provide navigation observable data.

The invention discloses a carrier ring auxiliary code delay phase-locked loop tracking method, system and device and a medium, and belongs to the technical field of signal tracking, and the method comprises the steps: obtaining a digital intermediate frequency signal, and constructing a code loop model; executing code tracking through the code loop model to obtain a code phase error measurement value, and determining a relationship between a carrier-to-noise ratio and a noise covariance; a measurement noise covariance matrix model is obtained through combination of a code phase error measurement value and a carrier-to-noise ratio dynamic state and is used for first adjustment of a filter. According to the invention, a measurement noise covariance matrix is dynamically adjusted based on real-time carrier-to-noise ratio estimation, so that the filter can accurately adapt to signal quality change, fully trust an accurate measurement value when a signal is strong, greatly reduce tracking jitter, achieve higher pseudo-range measurement precision, and automatically reduce dependence on the measurement value under noise interference when a signal is weak. In turn, the method depends on smooth prior model prediction.

The invention relates to a clock phase detection circuit and method, a delay phase-locked loop, a chip and electronic equipment, and the circuit comprises a frequency division module which is used for carrying out the frequency division processing of a reference clock signal selected from a plurality of input clock signals with the same frequency and different phases, and generating a frequency division clock signal; the clock driving module is used for grouping a plurality of input clock signals with the same frequency and different phases to generate at least two groups of input clock signals; the detection module is used for generating a detection signal according to a time interval between the reference clock signal and the feedback clock signal based on the frequency division clock signal and the at least two groups of input clock signals; wherein the feedback clock signal is an input clock signal of the previous phase of the reference clock signal. According to the invention, on the premise of not introducing an additional clock source, the detection of the clock phase can be quickly realized by using a plurality of input clock signals with the same frequency and different phases.

The present disclosure relates to a circuit (400) comprising: a delay-locked loop circuit (402) comprising a charge pump (406) configured to generate a bias voltage and a voltage-controlled delay line (408) controlled by the bias voltage, the voltage-controlled delay line comprising at least one transistor; a threshold voltage generator (410) for generating a signal representing a threshold voltage of the transistor; and a monitoring circuit (412) configured to: receive the signal representing the threshold voltage; supply, in sequence, a plurality of supply voltages to the delay-locked loop circuit (402); receive, for each supply voltage, a respective bias voltage generated by the charge pump (406); and determine, for each supply voltage, the corresponding behavior of the bias voltage with respect to the threshold voltage.and selecting one of the many supply voltages as the operating supply voltage, if the respective behavior of the bias voltage meets a predetermined criterion.

The application relates to a delay-locked loop circuit, comprising: a variable delay line for delaying an initial clock signal to generate a delayed clock signal; a control circuit connected with the variable delay line, for controlling the variable delay line to perform delay adjustment in a first mode, and for controlling the variable delay line to perform delay adjustment in a second mode when the delayed clock signal meets a preset condition; wherein the step value of each delay adjustment in the first mode is a first step value, the step value of each delay adjustment in the second mode is a second step value, and the second step value is greater than the first step value. By judging whether the delayed clock signal meets the preset condition, the actual state of the delayed clock signal can be obtained, different strategies are adopted to adjust the delay of the variable delay line, so that the output of the delay-locked loop circuit can dynamically and adaptively track the timing change of the delayed clock signal, and the matching degree between the initial clock signal CK and the drifted DQS signal is improved.

The present invention provides a delay locked loop (DLL) that can complete the process of adjusting the delay of an internal clock signal within a predetermined execution period. The DLL includes a DLL control circuit and a delay line circuit. The DLL control circuit sets the delay amount based on the phase difference between an input clock signal and an output clock signal. The delay line circuit performs a delay operation on the input clock signal according to the delay amount, thereby generating the output clock signal. The delay line circuit includes a plurality of delay units, each delay unit includes at least one delay element, and one of the delay units includes a greater number of delay elements than another delay unit.

A temperature sensing device including a first temperature sensor having a first resistor and a first capacitor and generating a first voltage applied to at least one of the first resistor or the first capacitor based on a first clock signal and a second clock signal generated by delaying the first clock signal, a second temperature sensor having a second resistor and a second capacitor and generating a second voltage applied to at least one of the second resistor or the second capacitor based on the first and second clock signals, a controller generating code data based on the first voltage and the second voltage and generating a control signal based on the code data, and a delay locked loop circuit delaying the first clock signal based on the control signal to generate the second clock signal may be provided.

Technical solutions improve GNSS receiver performance by combining pilot and data components of the GNSS signal to enhance the accuracy of a DLL, PLL or FLL of the receiver. A receiver receives a GNSS signal, removes a carrier component and provides in-phase and quadrature data and pilot signals. Data circuits can process the in-phase and quadrature data signals for data early and date late offsets and pilot circuits can process the in-phase and quadrature pilot signals for pilot early and pilot late offsets. The data early and data late signals can be combined to provide a data error difference and pilot early and pilot late signals can be combined to provide a pilot error difference. A summing circuit can combine pilot and data error differences to provide a delay lock loop (DLL) error signal.

The application discloses a time-to-digital converter based on pulse stretching. The time-to-digital converter structure combines frequency multiplication delay locked loop, pulse stretching circuit and calibration circuit, guarantees high resolution, effectively increases the range of the time-to-digital converter, and can reduce the influence of PVT. The calibration circuit has simple structure, low calibration cost, and is suitable for the calibration of the pulse stretching circuit. In addition, the calibration algorithm for the static phase error of the frequency multiplication delay locked loop only needs to increase a 1bit counter, the additional circuit cost is very small, and the influence of the static phase error of the frequency multiplication delay locked loop can be overcome.

The present invention discloses a clock signal selection circuit, which includes a delay chain circuit and a delay locked loop for the clock selection signal. The above clock signal selection circuit includes a negative edge D flip-flop, a first low-level latch, and a selection unit. The selection unit is used to receive a first clock signal and a second clock signal, and the second clock signal is a delayed signal of the first clock signal. The negative edge D flip-flop has its signal input terminal connected to an external control circuit, its clock control terminal is used to receive an externally input trigger signal, and its signal output terminal is connected to the signal input terminal of the first low-level latch. The clock control terminal of the first low-level latch is used to receive the second clock signal, and its signal output terminal is connected to the selection unit to control the selection unit to output the first clock signal or the second clock signal. The control signal is processed by the negative edge D flip-flop and the first low-level latch to control the operation of the selection unit, avoiding the selection unit from outputting the second clock signal when the second clock signal is at a high level, so as to avoid the generation of glitches.

A delay locked loop circuit comprising: a voltage-controlled delay line (VCDL); a phase detector circuit that is configured to process a first and a last output signal of the VCDL in order to provide: i) an up-pulse signal; and ii) a down-phase signal; a charge pump that is configured to provide a feedback voltage signal based on the up-pulse signal and the down-pulse signal; a phase signal processor that is configured to process the up-pulse signal and the down-pulse signal in order to provide a delay code locking signal, which is representative of whether or not the first output signal is 2Π radians out of phase with the last output signal; a delay code setter that is configured to provide a delay code setting signal that represents one of a sequence of different candidate delay codes. When the delay locked loop circuit is in a calibration mode of operation: a fixed voltage source provides a fixed voltage signal as a control-voltage signal for the voltage-controlled delay line; while the delay code locking signal represents the first output signal not being 2Π radians out of phase with the last output signal: the delay code setter applies the delay code setting signal to the VCDL such that it sequentially applies different candidate delay codes to the voltage-controlled delay line until a selected-delay-code is assigned; and when the delay locked loop circuit is in the active mode of operation: a charge pump provides a feedback voltage signal as the control-voltage signal for the voltage-controlled delay line; and the VCDL uses the selected-delay-code as the delay code.

The invention belongs to the field of global navigation satellite systems, and discloses a PPP-B2b-based high-precision time service method, which mainly comprises a PPP resolving module, a loop filter and a constant-temperature crystal oscillator + DDS (Direct Digital Synthesizer) combined circuit. The PPP resolving module is equivalent to a phase frequency detector in a delay locking loop, realizes a real-time precise point single positioning function by adopting double-frequency observed quantity and precise correction of a Beidou satellite navigation system, and outputs a precise clock error; a loop filter is equivalent to a loop filter in a carrier ring, a second-order frequency-locked loop is adopted to assist a third-order phase-locked loop structure, and frequency ramp-up excitation can be stably tracked; the combination of the constant-temperature crystal oscillator and the DDS is equivalent to a numerical control oscillator (NCO), and the precise adjustment of the clock frequency can be realized. Compared with a traditional high-precision time service terminal, the high-precision time service terminal does not depend on GPS observed quantity and precise correction information of the internet, a relatively low constant-temperature crystal oscillator instead of an atomic clock is adopted as a clock source, and the quantization error problem of second pulse output is solved.

A global navigation satellite system (GNSS) receiver for improving accuracy of a GNSS position estimation using a sigma-delta based fractional interpolation in a delay-locked loop is provided. The GNSS receiver includes a correlator, a code phase discriminator, a first loop filter, a code numerically controlled oscillator, and a sigma-delta modulator. The correlator correlates a GNSS C / A signal received from a satellite with a locally generated GNSS C / A code by multiplying the locally generated GNSS C / A code with incoming data samples. The code phase discriminator determines a delay between the locally generated GNSS C / A code and the GNSS C / A signal received from the satellite. The first loop filter averages the delay measured by the code phase discriminator. The code numerically controlled oscillator generates the local GNSS C / A code based on a unique CA code that corresponds to the satellite. The sigma-delta modulator imparts a fractional delay to the locally generated GNSS C / A code based on an output of the first loop filter.

A delay locked loop and a phase locking method thereof are provided. The delay locked loop includes a first frequency divider, a delay string, a frequency multiplier, a second frequency divider, a phase detection and control circuit, and a setting signal generator. The first frequency divider generates a frequency-divided reference frequency signal. The second frequency divider divides the output frequency signal to generate complementary first and second feedback frequency signals, and selects the first feedback frequency signal or the second feedback frequency signal according to the setting signal to generate a selected feedback frequency signal. The phase detection and control circuit compares the phases of the selected feedback frequency signal and the frequency-divided reference frequency signal to generate a delay control signal. The setting signal generator samples the first feedback frequency signal with respect to the frequency-divided reference frequency signal to generate a setting signal.

The present application discloses a signal anti-interference method, device, equipment, and storage medium, including: acquiring a signal to be processed, performing time-domain to frequency-domain conversion and data windowing processing on the signal to be processed to obtain a preprocessed signal; performing inverse frequency-domain filtering processing on the preprocessed signal to obtain a filtered signal; processing the filtered signal according to a frequency-domain interference suppression algorithm to obtain an anti-narrowband interference signal; performing forward interference signal elimination processing on the signal to be processed to obtain a processed anti-spoofing interference signal; processing the signal to be processed according to the narrow correlation delay lock loop method to obtain an anti-multipath interference signal; performing fusion processing on the anti-narrowband interference signal, anti-spoofing interference signal, and anti-multipath interference signal to obtain an anti-interference signal. It can comprehensively enhance the signal anti-interference ability, cope with various interferences by integrating multiple processing means, adapt to complex interference scenarios, and ensure stable and reliable signal transmission.

The invention provides a delay lock loop and a semiconductor memory device. The delay lock loop can complete a program for adjusting the delay of an internal clock signal in a predetermined execution period. The delay lock loop includes a DLL control circuit and a delay line circuit. The DLL control circuit sets a delay amount according to a phase difference between the input clock signal and the output clock signal. The delay line circuit performs a delay action on an input clock pulse signal according to the delay amount so as to generate an output clock pulse signal. The delay line circuit includes a plurality of delay units, each delay unit includes at least one delay device, and the number of the delay devices included in one of the delay units is greater than the number of the delay devices included in the other of the delay units.

The application discloses a discontinuous random time hopping pulse pseudolite signal tracking method based on carrier phase correction, and belongs to the field of satellite navigation auxiliary enhancement. The method first down-converts the received pseudolite signal to an intermediate frequency by using a receiver local oscillator; then carries out effective time slot signal interception and invalid time slot interference cutting on the pseudolite signal converted to the intermediate frequency by using a random time hopping pulse generation and control module in the receiver; then generates a carrier phase correction value of the signal in the effective time slot by using the pulse position information provided by the random time hopping pulse generation and control module and the carrier Doppler information fed back by the rear end; then further generates a cosine and sine result of the carrier phase correction value, and uses the result to continuously correct the carrier phase instantaneous value in the effective time slot; finally, the method realizes accurate tracking on the pseudolite signal after carrier phase correction by using a delay lock loop and a phase lock loop.

Disclosed are a pulse generator and a pulse generation method based on a multi-phase delay-locked loop and a high-precision NOR gate. The pulse generator based on a multi-phase delay-locked loop and a high-precision NOR gate according to the present invention comprises: a delay-locked loop module that generates and outputs a phase of an input clock as a plurality of half-phase delay signals; a NOR edge-combining module including a plurality of NOR gates which generate, through pulse-edge combining using the plurality of half-phase delay signals, a specific pulse that satisfies a predetermined condition; a multiplexer that receives, from the NOR edge-combining module, specific pulses classified according to respective conditions, and selects and outputs a specific pulse corresponding to a pulse-selection signal received from a digital block among the received specific pulses; and a pulse-repetition-interval gating module that generates an output pulse by combining the specific pulse outputted from the multiplexer with a pulse-repetition-interval signal.

An example apparatus includes a clock input circuit to provide an internal clock signal based on an external clock signal, and a command decoder configured to provide a command signal based on a received command. The example apparatus further includes an internal clock generator having DLL circuit to receive the internal clock signal and the command signal and to provide a phase-adjusted internal clock signal based on the internal clock signal. In response to receipt of the command signal, the DLL circuit enables provision of the phase-adjusted internal clock signal to an input / output circuit and stops provision of the phase-adjusted internal clock signal after a count of clock cycles of the internal clock signal exceeds a predetermined count value. The predetermined count value is based on a signal propagation time of the internal clock signal from the output of the internal clock circuit to an output of the input / output circuit.

This application relates to methods and apparatus for delay locked loops (DLLs). A DLL circuit includes a variable delay line, a phase detector and a delay controller. The DLL circuit is operable in a DLL mode in which a reference clock signal is input to the variable delay line and the delay controller controls a delay setting to achieve phase lock between the reference signal and an output signal. The DLL circuit is also operable in a frequency-locked-loop (FLL) mode, in which part of variable delay line is configured as a controlled oscillator to provide an oscillator signal, a frequency monitor determines a frequency relationship between the reference clock signal and the oscillator signal and the delay controller controls the delay setting to achieve frequency lock. The DLL circuit may configured to operate in the frequency-locked-loop mode on start-up and then transition to the DLL mode.

A delay-locked-loop (DLL) circuit 200 includes a variable delay line 101, a phase detector 103 and a delay controller 104. The circuit is operable in a delay-locked mode in which a reference clock sig

Provided are a delay locked loop circuit and an operating method, for providing an output clock signal to a bidirectional data strobe (DQS). The delay locked loop circuit includes: a first delay line, configured to delay an input clock signal to generate the output clock signal; a second delay line, configured to receive the output clock signal and delay the output clock signal to generate a feedback clock signal; a phase comparator, configured to compare phases of the input clock signal and the feedback clock signal to adjust a delay of the first delay line; and a control circuit, controlling the second delay line, configured to adjust a delay of the second delay line to be aligned to a delay of an off-chip driver (OCD) coupled to the DQS.

A pulse generator comprises a circuit configured to generate a coarse pulse width (CPW) signal, a first delay unit configured to generate a first delayed coarse pulse width signal, a delay locked loop circuit configured to generate a first subphase signal and a second subphase signal, a first analog interpolator, a second analog interpolator, and an amplifier having a first input connected to the first analog interpolator and a second input connected to the second analog interpolator and configured to generate a fine pulse width modulation signal.

The invention relates to an open-loop modulation transmitter with a harmonic suppression switched capacitor power amplifier. The transmitter comprises a sixteen-phase delay locked loop, a binary frequency shift keying modulator and the harmonic suppression switched capacitor power amplifier. The sixteen-phase delay locked loop provides sixteen paths of clock signals with equal phase difference to the binary frequency shift keying modulator, and the sixteen paths of clock signals are used as input signals of the binary frequency shift keying modulator; the binary frequency shift keying modulator is connected with the harmonic suppression switched capacitor power amplifier and provides a modulation signal for the harmonic suppression switched capacitor power amplifier; and the harmonic suppression switched capacitor power amplifier is used for amplifying the modulation signal and suppressing a harmonic component so as to output the modulation signal after harmonic suppression. According to the invention, high data rate transmission can be supported, the higher harmonic suppression capability is provided, the design requirement of a matching network can be relaxed while the frequency spectrum purity is ensured, the chip area is reduced, and the system cost is reduced.