46 results about "Delay-locked loop" patented technology

The invention relates to the technical field of serial communication, in particular to a high-speed clock recovery method and device based on an adjustable delay chain, and the method comprises the steps: generating a recovery clock initial phase; a multi-stage programmable delay chain is adopted, and a phase-locked loop or delay-locked loop structure is combined, so that the initial phase of a recovered clock is finely adjusted and locked, and phase capture and clock edge alignment are performed; based on a multi-path recovery structure, a path with the minimum error is selected from the delay paths through a preset phase error detection mechanism to serve as an output channel; environment parameters of the environment are collected, parameters of the multi-stage programmable delay chain are dynamically adjusted, and high-speed clock recovery is completed. According to the method, the edge capture precision, the system jitter tolerance and the working frequency range of the recovered clock are remarkably improved, and then the phase consistency, the anti-interference capability and the overall data receiving reliability of the recovered clock in the high-speed communication system are effectively improved.

The invention discloses a carrier ring auxiliary code delay phase-locked loop tracking method, system and device and a medium, and belongs to the technical field of signal tracking, and the method comprises the steps: obtaining a digital intermediate frequency signal, and constructing a code loop model; executing code tracking through the code loop model to obtain a code phase error measurement value, and determining a relationship between a carrier-to-noise ratio and a noise covariance; a measurement noise covariance matrix model is obtained through combination of a code phase error measurement value and a carrier-to-noise ratio dynamic state and is used for first adjustment of a filter. According to the invention, a measurement noise covariance matrix is dynamically adjusted based on real-time carrier-to-noise ratio estimation, so that the filter can accurately adapt to signal quality change, fully trust an accurate measurement value when a signal is strong, greatly reduce tracking jitter, achieve higher pseudo-range measurement precision, and automatically reduce dependence on the measurement value under noise interference when a signal is weak. In turn, the method depends on smooth prior model prediction.

The application relates to a delay-locked loop circuit, comprising: a variable delay line for delaying an initial clock signal to generate a delayed clock signal; a control circuit connected with the variable delay line, for controlling the variable delay line to perform delay adjustment in a first mode, and for controlling the variable delay line to perform delay adjustment in a second mode when the delayed clock signal meets a preset condition; wherein the step value of each delay adjustment in the first mode is a first step value, the step value of each delay adjustment in the second mode is a second step value, and the second step value is greater than the first step value. By judging whether the delayed clock signal meets the preset condition, the actual state of the delayed clock signal can be obtained, different strategies are adopted to adjust the delay of the variable delay line, so that the output of the delay-locked loop circuit can dynamically and adaptively track the timing change of the delayed clock signal, and the matching degree between the initial clock signal CK and the drifted DQS signal is improved.

The application discloses a time-to-digital converter based on pulse stretching. The time-to-digital converter structure combines frequency multiplication delay locked loop, pulse stretching circuit and calibration circuit, guarantees high resolution, effectively increases the range of the time-to-digital converter, and can reduce the influence of PVT. The calibration circuit has simple structure, low calibration cost, and is suitable for the calibration of the pulse stretching circuit. In addition, the calibration algorithm for the static phase error of the frequency multiplication delay locked loop only needs to increase a 1bit counter, the additional circuit cost is very small, and the influence of the static phase error of the frequency multiplication delay locked loop can be overcome.

The application discloses a discontinuous random time hopping pulse pseudolite signal tracking method based on carrier phase correction, and belongs to the field of satellite navigation auxiliary enhancement. The method first down-converts the received pseudolite signal to an intermediate frequency by using a receiver local oscillator; then carries out effective time slot signal interception and invalid time slot interference cutting on the pseudolite signal converted to the intermediate frequency by using a random time hopping pulse generation and control module in the receiver; then generates a carrier phase correction value of the signal in the effective time slot by using the pulse position information provided by the random time hopping pulse generation and control module and the carrier Doppler information fed back by the rear end; then further generates a cosine and sine result of the carrier phase correction value, and uses the result to continuously correct the carrier phase instantaneous value in the effective time slot; finally, the method realizes accurate tracking on the pseudolite signal after carrier phase correction by using a delay lock loop and a phase lock loop.

Disclosed are a pulse generator and a pulse generation method based on a multi-phase delay-locked loop and a high-precision NOR gate. The pulse generator based on a multi-phase delay-locked loop and a high-precision NOR gate according to the present invention comprises: a delay-locked loop module that generates and outputs a phase of an input clock as a plurality of half-phase delay signals; a NOR edge-combining module including a plurality of NOR gates which generate, through pulse-edge combining using the plurality of half-phase delay signals, a specific pulse that satisfies a predetermined condition; a multiplexer that receives, from the NOR edge-combining module, specific pulses classified according to respective conditions, and selects and outputs a specific pulse corresponding to a pulse-selection signal received from a digital block among the received specific pulses; and a pulse-repetition-interval gating module that generates an output pulse by combining the specific pulse outputted from the multiplexer with a pulse-repetition-interval signal.

A delay-locked-loop (DLL) circuit 200 includes a variable delay line 101, a phase detector 103 and a delay controller 104. The circuit is operable in a delay-locked mode in which a reference clock sig

Provided are a delay locked loop circuit and an operating method, for providing an output clock signal to a bidirectional data strobe (DQS). The delay locked loop circuit includes: a first delay line, configured to delay an input clock signal to generate the output clock signal; a second delay line, configured to receive the output clock signal and delay the output clock signal to generate a feedback clock signal; a phase comparator, configured to compare phases of the input clock signal and the feedback clock signal to adjust a delay of the first delay line; and a control circuit, controlling the second delay line, configured to adjust a delay of the second delay line to be aligned to a delay of an off-chip driver (OCD) coupled to the DQS.

A pulse generator comprises a circuit configured to generate a coarse pulse width (CPW) signal, a first delay unit configured to generate a first delayed coarse pulse width signal, a delay locked loop circuit configured to generate a first subphase signal and a second subphase signal, a first analog interpolator, a second analog interpolator, and an amplifier having a first input connected to the first analog interpolator and a second input connected to the second analog interpolator and configured to generate a fine pulse width modulation signal.

The invention relates to an open-loop modulation transmitter with a harmonic suppression switched capacitor power amplifier. The transmitter comprises a sixteen-phase delay locked loop, a binary frequency shift keying modulator and the harmonic suppression switched capacitor power amplifier. The sixteen-phase delay locked loop provides sixteen paths of clock signals with equal phase difference to the binary frequency shift keying modulator, and the sixteen paths of clock signals are used as input signals of the binary frequency shift keying modulator; the binary frequency shift keying modulator is connected with the harmonic suppression switched capacitor power amplifier and provides a modulation signal for the harmonic suppression switched capacitor power amplifier; and the harmonic suppression switched capacitor power amplifier is used for amplifying the modulation signal and suppressing a harmonic component so as to output the modulation signal after harmonic suppression. According to the invention, high data rate transmission can be supported, the higher harmonic suppression capability is provided, the design requirement of a matching network can be relaxed while the frequency spectrum purity is ensured, the chip area is reduced, and the system cost is reduced.

A delay-locked loop (DLL) is provided that ensures that the phase outputs that are provided as inputs to the harmonic rejection mixer (HRM) are sufficiently accurate to allow the HRM to effectively cancel out the spurious harmonic frequencies, thereby improving HRM parameters. The phase detector of the DLL can be programmable to provide a “knob” that can be used post layout to adjust the output phase differences of the DLL to make them more precise. This feature overcomes issues with mismatches in silicon that in the past have affected the ability of the DLL to settle precisely to the desired phases. This, in turn, loosens design and manufacturing constraints that are currently employed to ensure that the DLLs settle precisely to the desired phases. Additionally, logic gates are eliminated from the phase detector and replaced with resistors to reduce current consumption and further looser design and manufacturing constraints.

This application discloses a method and system for tracking spread spectrum signals, belonging to the field of signal processing. This application generates a spread spectrum digital signal by oversampling the acquired spread spectrum modulated signal. In-phase and quadrature components are generated by mixing, despreading, and coherent integration of this digital signal. Frequency and phase error information are calculated based on the components at continuous time intervals to correct the local carrier. The corrected local carrier is then used to mix the signal to baseband. An adjustable fractional delay is applied, and the instantaneous correlation energy peak is searched to determine the target fractional delay, thereby obtaining code phase error information. After correcting the local pseudocode using this code phase error information, the corrected local carrier and local pseudocode are used to initialize a narrow-bandwidth frequency-locked loop, phase-locked loop, and delay-locked loop, thus initiating precise tracking. This enables high-precision and stable locking of the spread spectrum signal in a short time.

Provided is a pulse generation circuit that receives a clock signal and outputs a delayed pulse signal, including: a first delay-locked loop circuit that receives the clock signal and generates a first delay signal obtained by delaying the clock signal; a second delay-locked loop circuit that generates a second delay signal with reference to the first delay signal; and an output circuit that outputs the delayed pulse signal according to the first delay signal and the second delay signal. The second delay-locked loop circuit may have: a second charge pump that outputs a current according to the clock signal and the delayed pulse signal; and a second delay circuit that outputs the second delay signal obtained by delaying the clock signal according to a current output by the second charge pump.

This disclosure is generally directed to a delay locked loop (DLL) to generate an output clock signal with a desired phase value. The DLL may include circuitry to delay an input clock signal with a number of delay cells to generate the output clock signal with the desired phase value. The DLL may provide the output clock signal aligned (e.g., nearly aligned) with data signals of a circuit, such as a memory device, to compensate for various delays of the circuit. The DLL may generate the output clock signal by performing a single-step measure initialization process or a 2-step measure initialization process to determine the number of the delay cells. The DLL may generate complementary clock signals and, in some case, quadrature clock signals, based on an input clock signal to perform the 2-step measure initialization process.

The application discloses a parallel demodulation timing synchronization method for high-speed coherent spread spectrum, and relates to the field of wideband satellite communication covert communication and anti-jamming communication systems. The application adopts parallel processing demodulation to reduce processing clock, adopts a mode of adjusting the timing error of a spread spectrum communication delay-locked loop output to realize tracking timing synchronization of the spread spectrum communication, and the mode is that multiple parallel outputs are adopted to reduce processing clock, and the output clock of resampling is adjusted to realize synchronization of the local clock and the received data clock, which is beneficial to low signal-to-noise ratio demodulation, suitable for high chip rate or high bandwidth spread spectrum, and can be used for wideband satellite spread spectrum communication.

Methods, systems, and devices for a jitter impedance delay lock loop are described. A delay lock loop circuit may be configured to align a clock signal and a data strobe signal. The delay lock loop circuit may include a variable delay component configured to receive the clock signal and output an aligned clock signal. The delay lock loop circuit may include a phase detector configured to determine whether the clock signal is aligned with the data strobe signal and output an indication to increase or decrease a delay to the clock signal. The variable delay component may increase or decrease the delay based on the indication from the phase detector. The delay lock loop circuit may include a control component configured to restrict the increase or decrease of the delay such that the delay does not exceed a threshold.

A phase-locked loop or delay locked loop provides a coarse alignment between an input clock and an output clock. A latch receiver circuit provides an indicator of a delay error between the input clock and the output clock. The delay error is used by a control circuit or state machine to adjust a fine delay that affects the output clock signal timing relative to the input clock signal. The fine delay is adjusted to minimize the timing difference between the output clock signal and the input clock signal.

The application discloses a timing synchronization method and system for UQPSK-DSSS signals, and belongs to the field of communication signal processing. The application replaces the traditional digital interpolation with zero value interpolation, shaping filtering and extraction units at the sending end, reduces the general system jitter caused by non-integer oversampling, and guarantees the stability of normal tracking work after loop locking. The application adds a timing deviation estimation module and a symbol interpolation module at the receiving end. In the case that there is large jitter in the non-integer oversampling signal system, the UQPSK-DSSS signal has the characteristics of complete alignment of coupling, and the code ring NCO phase accumulation in the delay locked loop has the characteristics of stability. Only the code ring NCO phase accumulation is used to realize the joint demodulation of the measurement and control link and the data transmission link, without too many calculation processes. The application estimates the normalized timing error estimation value of the accurate non-spread spectrum branch by using the code ring NCO phase accumulation, and realizes the accurate bit timing synchronization of the signal under the low oversampling rate by means of the symbol interpolation operation.

An apparatus, system, and method for improved memory control are provided. A circuit can include controller circuitry configured to determine, based on a speed of silicon of a memory, a read strobe code that adjusts a data clock to account for a difference between a reference clock and a data clock in terms of a number of unit intervals (UIs) and a read strobe code, a receive delay locked loop to receive the difference and delay the data clock by the number of UI and read strobe codes resulting in a delayed data clock, and a sampling amplifier to sample data from the memory based on the delayed data clock.

The invention belongs to the field of integrated circuit design, and discloses a high-resolution numerical control delay line circuit architecture which comprises at least one coarse tuning delay unit and at least one fine tuning delay unit which are in cascade connection. The fine tuning delay unit is composed of a plurality of parallel configurable delay branches, and each branch is composed of a control switch and a phase inverter which are connected in series. Different numbers of branches are selected to be conducted through digital control words, the total equivalent conduction resistance and the load capacitance are changed, and fine-grained delay adjustment is achieved. The delay adjustment range of the fine adjustment unit is equal to the minimum step length of one coarse adjustment unit, the resolution can be improved by increasing the number of parallel inverters, and the delay linearity is effectively controlled. The architecture has the advantages of high resolution, excellent linearity, low power consumption and small area, and is suitable for application scenes such as delay locked loops, high-speed serial interfaces and on-chip test circuits.

A lock-detection circuit designed for integration into a phase-locked loop or a delay-locked loop includes a first signal-duration filter processing an up signal (UP) to generate a filtered UP signal containing segments that exceed a minimum duration, and a second signal-duration filter handling a down signal (DN) to produce a filtered DN signal with segments surpassing the minimum duration. Additionally, the circuit includes first and second timers receiving the filtered signals, and an output logic circuit triggering a LOCK detected signal when both timers are activated. The minimum duration is set to exceed spikes in the UP and DN signals, accounting for jitter, and is longer than the expected duration of a phase error correcting pulse when the loop is in lock.

A memory controller in an integrated circuit system performs bidirectional data transfer between the memory controller and a memory module at a clock frequency. The data transmission in the first direction adopts a first pulse amplitude modulation level, and the data transmission in the second direction adopts a second pulse amplitude modulation level. When an indication of an increase in the first direction data transfer demand is received, the memory controller raises the first pulse amplitude modulation level to a target pulse amplitude modulation level for the first direction data transfer while maintaining the clock frequency and the second pulse amplitude modulation level unchanged in the second direction. According to the invention, under the condition that the clock frequency and the second pulse amplitude modulation level are kept unchanged, the data transmission rate in the first direction is increased by improving the first pulse amplitude modulation level; therefore, the negative effect of increasing the re-locking time required by the phase-locked loop or the delay-locked loop due to the change of the clock frequency can be avoided.

A delay locked loop device is provided, which includes a receiver, a delay line, a frequency detection and control circuit, a phase detector, and a delay control circuit. The receiver compares an input clock signal and a reference voltage to generate a first signal, and generate a reference clock signal based on the input clock signal. The delay line delays the first signal to generate a second signal based on a delay control signal. The frequency detection and control circuit detects an operating frequency of the reference clock signal to generate an enable signal. The phase detector detects, in response to the enable signal, a phase difference between the reference clock signal and a feedback clock signal to generate a phase detection result. The delay control circuit is configured to generate the delay control signal for the delay line based on the phase detection result.

A hybrid delay-locked loop Includes: a digital control loop including a digital phase detector having a dead zone; and an analog control loop including an analog phase detector that operates in the dead zone.

A lock-detection circuit designed for integration into a phase-locked loop or a delay-locked loop includes a first signal-duration filter processing an up signal (UP) to generate a filtered UP signal containing segments that exceed a minimum duration, and a second signal-duration filter handling a down signal (DN) to produce a filtered DN signal with segments surpassing the minimum duration. Additionally, the circuit includes first and second timers receiving the filtered signals, and an output logic circuit triggering a LOCK detected signal when both timers are activated. The minimum duration is set to exceed spikes in the UP and DN signals, accounting for jitter, and is longer than the expected duration of a phase error correcting pulse when the loop is in lock.

A delay locked loop (DLL) circuit includes a voltage-controlled delay line (VCDL) that applies a time delay to a clock-in signal to provide a first output signal and a last output signal. The magnitude of the time delay is based on the control-voltage signal and a delay code. The DLL circuit includes a feedback circuit configured to provide a feedback voltage signal based on the phase difference between the first output signal and the last output signal. In a calibration mode: a fixed voltage source provides a fixed voltage signal as the control-voltage signal for the VCDL; and a delay code setter applies a delay code setting signal to the VCDL to identify a selected-delay-code as the code. In an active mode: the feedback circuit provides the feedback voltage signal as the control-voltage signal for the VCDL; and the VCDL uses the selected-delay-code as the delay code.

A delay locked loop (DLL) includes a phase detector having a first input, a second input, and an output, and a first delay path coupled between an input of the DLL and the first input of the phase detector, wherein the first delay path includes a first delay circuit. The first delay circuit includes first delay buffers coupled in series and load capacitors, wherein each of the load capacitors is coupled to an output of a respective one of the first delay buffers. The DLL also includes a second delay path coupled between the input of the DLL and the second input of the phase detector, wherein the second delay path includes a one-cycle delay circuit and a second delay circuit coupled in series. The DLL also includes a control circuit coupled to the output of the phase detector, the first delay circuit, and the second delay circuit.

A delay locked loop device is provided, which includes a receiver, a delay line, a frequency detection and control circuit, a phase detector, and a delay control circuit. The receiver compares an input clock signal and a reference voltage to generate a first signal, and generate a reference clock signal based on the input clock signal. The delay line delays the first signal to generate a second signal based on a delay control signal. The frequency detection and control circuit detects an operating frequency of the reference clock signal to generate an enable signal. The phase detector detects, in response to the enable signal, a phase difference between the reference clock signal and a feedback clock signal to generate a phase detection result. The delay control circuit is configured to generate the delay control signal for the delay line based on the phase detection result.

Disclosed are a memory device and a clock locking method thereof. The clock locking method of the memory device can include performing an initial locking operation in a delay-locked loop circuit before an internal voltage is stabilized, monitoring a clock skew between a reference clock and a feedback clock using a window detection circuit after the internal voltage is stabilized, and performing a re-locking operation in the delay-locked loop circuit using a dynamic delay control corresponding to the clock skew.

The present application provides a delay-locked loop circuit and a method for measuring the delay of the delay-locked loop circuit. A delay-locked loop (DLL) circuit is introduced, which includes a delay line, a pattern injection circuit, a pattern detection circuit and a counter. The delay line can align the phase of a reference clock signal with the phase of a feedback clock signal. The pattern injection circuit injects a predetermined pattern into the reference clock signal to generate an injected reference clock signal and asserts the injected reference clock signal to the delay line. The pattern detection circuit detects the predetermined pattern in the feedback clock signal. The counter determines the delay of the delay-locked loop circuit according to a first timing when the injected reference clock signal is asserted to the delay line and a second timing when the predetermined pattern is detected in the feedback clock signal. A method for measuring the delay of the DLL circuit is also introduced.