170results about How to "Lower forward voltage drop" patented technology

A trench Schottky barrier rectifier includes an cathode electrode at a face of a semiconductor substrate and an multiple epitaxial structure in drift region which in combination provide high blocking voltage capability with low reverse-biased leakage current and low forward voltage. The multiple structure of the drift region contains a concentration of first conductivity dopants therein which comprises two or three different uniform value from a Schottky rectifying junction formed between the anode electrode and the drift region. The thickness of the insulating region (e.g., SiO2) in the MOS-filled trenches is greater than 1000 Å to simultaneously inhibit field crowing and increase the breakdown voltage of the device. The multiple epi structure is preferably formed by epitaxial growth from the cathode region and doped in-situ.

A cascaded synchronous bootstrap supply circuit with reduced voltage drop between the cascaded bootstrap capacitors by replacing bootstrap diodes with gallium nitride (GaN) transistors. GaN transistors have a much lower forward voltage drop than diodes, thus providing a cascaded gate driver bootstrap supply circuit with a reduced drop in bootstrap capacitor voltage, which is particularly important as the number of levels increases.

A normally-off type field-controlled channel GaN heterojunction diode belongs to the technical field of semiconductor devices. The invention adopts the technology of combining insulating layer-groove, modulation doping and groove-modulation doping to change the conductive channel structure of the existing GaN heterojunction diode, and convert the original normally-on spontaneously polarized GaN heterojunction The junction conductive channel is changed into a normally-off field-controlled conductive channel combining spontaneous polarization and piezoelectric polarization in the present invention, which realizes the field-controlled characteristics of the GaN heterojunction diode conductive channel and reduces the forward conduction resistance and enhanced reverse cut-off capability. The invention has lower forward conduction resistance and power consumption, stronger reverse cut-off ability, and is compatible with AlGaN/GaN HEMT power switching device technology, which is beneficial to the application of the device.

The invention relates to a fast recovery epitaxial diode comprising a metal cathode layer, an N + substrate silicon chip, a first epitaxial layer, a second epitaxial layer, a third epitaxial layer, wherein the above-mentioned parts are successively connected. A mesa silicon groove penetrates the third epitaxial layer and is extended into the second epitaxial layer; a glass passivation layer that is arranged inside the mesa silicon groove and is provided with a window is extended to the top surface of the third epitaxial layer; and a metal anode layer that is arranged at the upper portion of the glass passivation layer passes through the window that is arranged on the glass passivation layer and then is connected with the third epitaxial layer. According to the invention, an epitaxial technology is used to accurately control impurity concentration and thickness of all the epitaxial layers; and a mesa channeling technology and a glass passiviation technology are utilized to manufacture a terminal structure, thereby substantially reducing a technology flow. Besides, the fast recovery epitaxial diode has good consistency and repeatability; high quality characteristics including low forward direction voltage drop, super speediness, and soft recovery characteristic and the like of the fast recovery epitaxial diode can be easily realized.

The invention discloses a mains complementation controller for a solar street lamp. The controller comprises a solar cell panel, a charging module, a microprocessor, a constant-current output module, a switching power supply, a voltage detection module and a battery. The invention also discloses a control method of the controller. The controller is skillful and reasonable in structural design, when the electric quantity stored in the battery by the solar energy is insufficient, the controller is switched to a mains supply automatically in a seamless mode, the effect that the solar energy is used preferentially and the mains supply serves as a supplement can be effectively achieved, and charging and discharging can be controlled automatically according to different working parameters and states, so that the charging and the discharging are kept at the optimal states, the utilization efficiency of the solar energy is improved, the energy resources are effectively saved, the whole process is automatic, and the intelligent degree is high. The control method is simple in step, easy to implement, capable of supplying electricity by the battery and achieving seamless switching to the mains supply, effectively guaranteeing the sufficient utilization of solar energy resources, greatly prolonging the service life of the battery and reducing the maintenance cost and beneficial to popularization and application.

In a reverse conducting semiconductor device, which forms a composition circuit, a positive voltage that is higher than a positive voltage of a collector electrode may be applied to an emitter electrode. In this case, in a region of the reverse conducting semiconductor device in which a return diode is formed, a body contact region functions as an anode, a drift contact region functions as a cathode, and current flows from the anode to the cathode. When a voltage having a lower electric potential than the collector electrode is applied to the trench gate electrode at that time, p-type carriers are generated within the cathode and a quantity of carriers increases within the return diode. As a result, a forward voltage drop of the return diode lowers, and constant loss of electric power can be reduced. Electric power loss can be reduced in a power supply device that uses such a composition circuit in which a switching element and the return diode are connected in reverse parallel.

A semiconductor device, including: a semiconductor substrate of the first conductivity type having a first surface and a second surface; a base region of the second conductivity type formed on the first surface of the semiconductor substrate; a guard ring region of the second conductivity type formed around the base region, and having the second type impurity of which concentration is lower than that of the base region; a first electrode formed on the base region; and a second electrode formed on the second surface of the semiconductor substrate, further including a base peripheral region formed around the base region and being connected to the base region, wherein the base peripheral region is deeper than the base region and has the substantially constant depth, and the concentration of the second conductivity type impurity included in the base peripheral region is lower than that included in the base region.

A method for forming semiconductor device, which simultaneously forms a trench MOS transistor device, and an embedded schottky barrier diode (SBD) device in a semiconductor substrate. The embedded SBD device has lower forward voltage drop, which reduces power dissipation. In addition, the voltage bearing ability may be modified easily by virtue of altering the dopant concentration or the width of the voltage bearing dopant region, or the thickness of epitaxial silicon layer. Furthermore, extra cost of purchasing SBD diode may be saved.

The invention relates to a method for controlling the growth of a P-type GaN low-rate dopant, and belongs to the field of preparation of semiconductor materials. According to the method, a low-temperature core-forming layer, an unintentionally doped GaN layer and then a p-type GaN layer are sequentially grown upwards on a substrate with Cp2Mg as the p-type dopant, the non-doped GaN layer is grown for 10 seconds before the growth of the p-type GaN layer, then a CP2Mg source is inlet and grown for 8 seconds, and the growth is repeated for 320-350 periods with the 18 seconds as the single period; and the flow of the CP2Mg is controlled in the range of 35-50 sccm, and the growth temperature is 920-980 DEG C. Based on the method, the Mg atom intermingling efficiency is increased, the self-compensation effect of the Mg atom is restrained, the hole concentration is improved, the crystal quality is improved, and therefore the high-performance p-type GaN material is obtained; and the method provides beneficial assistance for reducing the forward voltage drop of a GaN-based LED (light-emitting device) and prolonging the service life.

The invention discloses an extension method for a material used for a lower positive pressure reduction schottky diode. The invention controls and optimizes the temperature rising time of each step by adjusting the program of temperature rising and the careful cooperation of hydrogen flux to lead the impurities of a wafer from an underlay to be expanded outwards during a heat treatment process and finally lead the transition area of a silicon epitaxial wafer to reach the range of 1.2 to 1.3 micron by expelling the air by hydrogen. The resistance rate uniformity in the wafer is less than 3 percent by adopting the method of the invention, thereby leading the transition area of the wafer to be controlled between 1.0 and 1.3 micron and leading the resistance rate uniformity in a furnace to be less than 5 percent; besides, the repetitiveness and the reproducibility of the resistance rate and the thickness between furnaces are good; the repetitiveness in the furnace and the transition area of the wafer is good; the uniformity and the consistency of the positive pressure reduction and negative pressure reduction of the schottky diode manufactured by the material are good.

A MOS P-N junction diode device includes a substrate having a first conductivity type, a field oxide structure defining a trench structure, a gate structure formed in the trench structure and a doped region having a second conductivity type adjacent to the gate structure in the substrate. The method for manufacturing such diode device includes several ion-implanting steps. After the gate structure is formed by isotropic etching using a patterned photo-resist layer as a mask, an ion-implanting step is performed using the patterned photo-resist layer as a mask to form a deeper doped sub-region. Then, another ion-implanting step is performed using the gate structure as a mask to form a shallower doped sub-region between the gate structure and the deeper doped sub-region. The formed MOS P-N junction diode device has low forward voltage drop, low reverse leakage current, fast reverse recovery time and high reverse voltage tolerance.

The invention mainly aims at providing a low-electric-leakage and low-forward-voltage-drop Schottky diode structure and a manufacturing method of the low-electric-leakage and low-forward-voltage-drop Schottky diode structure. The manufacturing method is characterized in that a terminal is protected with the junction termination extension technology, neutralization modulation is carried out on Schottky main junction depletion regions at the same time, injections of the two terms are carried out at the same time, the breakdown voltage is improved, the good low-electric-leakage effect can be achieved, and the process manufacturing procedure is simple. After the low-electric-leakage and low-forward-voltage-drop Schottky diode structure and the manufacturing method are applied, a low-electrical-resistivity epitaxial wafer can be adopted for manufacturing a Schottky diode, the forward voltage drop is effectively reduced, the high-voltage effect is achieved, and the low-electric-leakage and low-forward-voltage-drop effect is improved. By means of the low-electric-leakage and low-forward-voltage-drop Schottky diode structure and the manufacturing method, the efficient Schottky barrier diode can be obtained; compared with a traditional diode structure, the application scope of the diode is wide.

The invention relates to semiconductor technologies, in particular to a metal oxide semiconductor diode with an accumulation layer.The metal oxide semiconductor diode has the advantages that the metal oxide semiconductor diode is provided with a surface electron accumulation layer structure and a junction field effect transistor structure and accordingly can have low start voltages; the in-vivo electron accumulation layer can be formed on an N-type semiconductor surface which is in contact with a groove 8 after the metal oxide semiconductor diode is forwardly conducted, and the metal oxide semiconductor diode is provided with an N-type region 3 with high doping concentration and accordingly can have low forward voltage drop; transverse electric fields are formed between the N-type region 3 and doped polycrystalline silicon 13 when the metal oxide semiconductor diode is reversely blocked, accordingly, exhaust lines are expanded towards the N-type region 3 in an in-vivo, electric fields of a drift region are distributed in a rectangular manner, and the reverse blocking voltages of the metal oxide semiconductor diode can be increased; the metal oxide semiconductor diode is novel in structure, is high in withstand voltage and low in conduction voltage.

The invention discloses a semiconductor power device with ultralow power consumption, wherein the quantity of photo-etching layers is small, and reverse recovery time is short. The device comprises a semiconductor baseplate, wherein a cellular area and a terminal protection area are disposed on the semiconductor base plate; and cells are disposed in the cellular area. The structure of the cellular area comprises a cellular groove, wherein upper conductive polycrystalline silicon layers and lower conductive polycrystalline silicon layers are disposed in the cellular groove; two sides of the upper conductive polycrystalline silicon layers are symmetrically disposed at extension parts which are located on two sides of the lower conductive polycrystalline silicon layers so as to form a cap-shaped structure. At least two voltage partition rings and at least one stop ring are disposed in the terminal protection area. The conductive polycrystalline silicon layer close to a voltage partition groove of the cellular area is electrically connected to a source electrode of the device; the rest conductive polycrystalline silicon layers in the voltage partition groove are suspended; and a Schottky diode is disposed in a transition area which is located between the cellular area and the terminal protection area. The invention also discloses a method which can be used for manufacture of the semiconductor power device with the ultralow power consumption.

The invention provides a preparation method of a power diode. The preparation method comprises the following steps: providing a substrate and growing an N type layer; forming a terminal protection ring; forming an oxide layer, and performing knot guiding on the terminal protection ring; forming a gate oxide layer, and depositing a polycrystalline silicon layer on the gate oxide layer; forming an N type heavily doped region; forming a P+ region; performing ion bombardment on a wafer, etching photoresist, and enlarging the photo-etched window; forming a P type body region; performing thermal annealing to activate the injected impurities; performing front metallization and back metallization. According to the preparation method of the power diode, the photo-etched window is enlarged by the ion bombardment to the photoresist which is used as a masking layer when being injected to form the P type body region; the ion bombardment time can be adjusted to control the feature size of the polycrystalline silicon photoresist, so as to adjust the length of the P type body region, namely the length of an MOS channel, and optimize the relation between the reverse leakage current and the forward voltage drop of the device.

The invention discloses a novel junction barrier schottky device which comprises a substrate layer, a buffering layer, a drifting layer, a light doping layer, a plurality of restraining areas, a heavy doping layer and a schottky barrier layer, wherein the restraining areas which are separated from each other are located in the light doping layer and the heavy doping layer. When a reverse bias is applied to a semiconductor device, a large-area exhausting region is spread and formed in a semiconductor material of the light doping layer. The invention also provides a manufacturing method for the semiconductor device. The semiconductor device provided by the invention has a low forward voltage drop and a high device-switching speed. Electrical parameter characteristics of the semiconductor device are further optimized.

The invention discloses a novel schottky diode device. The device comprises a substrate layer, a gradual doping buffer layer, a drifting layer and a schottky barrier layer. The invention also provides a manufacturing method of a schottky diode. A semiconductor device provided by the invention has low forward voltage drop, and the electrical parameter characteristic of the device is further optimized.