77 results about "Reverse leakage current" patented technology

The invention discloses a power diode based on an MOF, a preparation method, a 3D chip packaging method and application, belongs to the technical field of electronic materials and power devices, and particularly relates to a composite structure based on an n-Si substrate / an (n-Si)-(ZIF-8) composite layer / an Ag layer, preparation, a 3D chip packaging method and application of the composite structure in the field of power devices. The reverse withstand voltage of the power diode based on the n-Si substrate / ''(n-Si)-(ZIF-8) composite layer'' / Ag layer composite structure exceeds 200V, the forward conduction voltage of the power diode is 0.25-1.5 V, the reverse bias voltage applied to the power diode is 0-200V, the reverse leakage current is basically not increased along with the increase of the reverse bias voltage, and the reverse leakage current is 0.2-2.1 mA (at the reverse voltage-100V). Compared with a conventional power diode based on an n-Si substrate / Ag layer Schottky structure, the performance of the power diode provided by the invention has the advantages that although the forward voltage is basically unchanged, the reverse voltage is increased by 80-400%, the reverse saturation current is reduced by 50-800%, and the highest yield reaches 95%.

MOS junction barrier Schottky diode relates to the technical field of power semiconductor device. N-type substrate, N-type epitaxial layer, deep P region, slot gate, slot gate oxide layer, conductive enhancement region and isolation oxide layer are arranged between cathode metal and anode metal, the lower surface of the N-type substrate is in contact with the cathode metal, the upper surface is in contact with the lower surface of the N-type epitaxial layer, the upper surface of the N-type epitaxial layer is in contact with the P region, the conductive enhancement region is arranged on the outer surface of the slot gate oxide layer and is in contact with the N-type epitaxial layer, part of the slot gate oxide layer, the conductive enhancement region, the isolation oxide layer and part of the deep P region are respectively in contact with part of the anode metal. The MOS junction barrier Schottky diode structure of the application improves the carrier density at the channel, reduces the channel resistance, and further improves the reverse leakage current characteristics and the forward voltage drop by inserting a slot gate MOS structure in the adjacent P region of the traditional junction barrier Schottky (JBS) diode.

The application relates to a semiconductor structure and a preparation method of the semiconductor structure, and the semiconductor structure comprises: a first AlGaN / AlN / GaN heterostructure, a first two-dimensional electron gas channel existing at the interface between the AlN layer and the GaN layer in the first AlGaN / AlN / GaN heterostructure; a second AlGaN / AlN / GaN heterostructure, a second two-dimensional electron gas channel existing at the interface between the AlN layer and the GaN layer in the second AlGaN / AlN / GaN heterostructure; and a third AlGaN / AlN / GaN heterostructure, a third two-dimensional electron gas channel existing at the interface between the AlN layer and the GaN layer in the third AlGaN / AlN / GaN heterostructure; the difference between the electron concentration in the first two-dimensional electron gas channel, the electron concentration in the second two-dimensional electron gas channel and the electron concentration in the third two-dimensional electron gas channel is less than a preset value, thereby adjusting the carrier distribution, so as to achieve the purposes of reducing the device resistance value, reducing the reverse leakage current and reducing the heat generation in the working state of the device.

The invention relates to the field of photovoltaic technology, in particular to a back contact solar cell and a photovoltaic module. The back contact solar cell comprises a substrate, first areas and second areas which are alternately arranged at intervals in the X direction are formed on the backlight face of the substrate, gaps between the adjacent first areas and second areas form third areas, a first doping layer is formed in each first area, a second doping layer is formed in each second area, and a second doping layer is formed in each second area. A third doping layer is formed in each third region; the doping concentration of the third doping layer is greater than the doping concentration of the first doping layer and the doping concentration of the second doping layer; the third doped layer is electrically connected with the adjacent first doped layer and the adjacent second doped layer. Compared with the prior art, the arrangement of the third doping layer is beneficial to generating leakage current under relatively low reverse bias voltage, so that the hot spot temperature of the assembly is remarkably reduced, the reliability of a single battery and the assembly is improved, and the phenomenon of abnormal concentration of reverse leakage current can be avoided.

A semiconductor device includes a substrate, a drift region, a well region, a first shielding region, a junction field effect transistor region, a source region, and a gate structure. The drift region is located in the substrate. The well region is located in the drift region. The first shielding region is located in the drift region, wherein the bottom surface of the first shielding region is lower than the bottom surface of the well region, and the carrier concentration of the first shielding region is higher than that of the well region. The junction field effect transistor region is located in the drift region, the bottom surface of the junction field effect transistor region is lower than the bottom surface of the first shielding region, and the first part of the first shielding region is located between the well region and the junction field effect transistor region. The source region is adjacent to the well region. The gate structure is located on the drift region. As the shielding region is arranged between the junction field effect transistor region and the well region, the problem of reverse leakage current can be obviously solved, and the influence of the reverse leakage current on the power consumption of the element is reduced.

The LDMOS device model comprises a BSIM4 model, a plurality of segmented resistor models which are sequentially connected in series and a plurality of drain substrate diode models, and the segmented resistor models which are sequentially connected in series are connected to a drain electrode of the BSIM4 model in series. A drift region of an LDMOS is simulated through a plurality of segmented resistor models which are sequentially connected in series, and the input end of each segmented resistor model is connected with a corresponding drain substrate diode model. Due to the fact that the segmented resistor models are connected in series, changes of electrical characteristics of drain substrate diodes at different positions of a drift region are simulated, and then the simulation precision of the LDMOS device model on drain substrate parasitic capacitance and gate channel intrinsic capacitance of an LDMOS is improved. And the simulation precision of the reverse leakage current of the drain substrate diode is improved.

The application discloses a power device and a preparation method thereof, and relates to the technical field of semiconductors. The power device comprises a semiconductor substrate, a first buffer layer, a second buffer layer, a third buffer layer, a barrier layer, a passivation layer, a first anode, a dielectric layer, a second anode, a cathode, a protective layer, anode conduction metal, cathode conduction metal and a field plate layer. The application solves the technical problem of large reverse leakage current of the power device.

The application discloses a wide-bandgap power diode with a periodic composite anode, which comprises, from bottom to top, a wide-bandgap semiconductor material substrate layer, a third anode groove, a wide-bandgap semiconductor material epitaxial layer, a periodic first anode groove and a second anode on the wide-bandgap semiconductor material epitaxial layer, a first dielectric layer and a second dielectric layer arranged on the first anode groove and the upper surface of the wide-bandgap semiconductor material epitaxial layer in sequence, the second dielectric layer arranged on the second anode groove and the upper surface of the wide-bandgap semiconductor material epitaxial layer, a third dielectric layer arranged on the third anode groove, and a metal anode and a metal cathode arranged on the upper surface of the wide-bandgap semiconductor material epitaxial layer and the lower surface of the wide-bandgap semiconductor material substrate layer respectively. The application has the performance advantages of high current density, high breakdown voltage, low on-resistance and low reverse leakage current due to the periodic composite anode structure.

The application relates to a kind of detection method, device, system and storage medium of LED lamp bead, comprising the following steps, the electrode of the LED lamp bead is tested, and the initial current value of the LED lamp bead is obtained;Based on the initial current value, the LED lamp bead is applied to step voltage, and voltage-current curve is obtained;The LED lamp bead corresponding to the rated operating point in the voltage-current curve is detected by optical detector, and the light spot image is obtained;Based on the light spot image, the LED lamp bead is tested by reverse voltage, and the reverse leakage current value is obtained;Based on the voltage-current curve, light spot image and reverse leakage current value, the quality of the LED lamp bead is evaluated, and the quality evaluation result of the LED lamp bead is obtained, which solves the technical problem that the traditional detection method is mainly concentrated on simple on-off test or single parameter measurement, and it is difficult to comprehensively reflect the comprehensive performance of LED lamp bead.

This invention discloses a gallium nitride Schottky diode with a quasi-depletion layer, the structure of which, from bottom to top, comprises: a substrate layer, a buffer layer, and an N-type diode. + -GaN contact layer, N ‑ -GaN drift layer, quasi-depletion layer, and anode Schottky contact layer disposed on the quasi-depletion layer and disposed on N + A cathode ohmic contact layer above a GaN contact layer; wherein the doping concentration and thickness of the quasi-depletion layer must satisfy the following: the thickness of the quasi-depletion layer is less than the width of the depletion layer of the diode at zero bias voltage. This invention significantly reduces the turn-on voltage of the diode by setting a highly doped quasi-depletion layer on the surface of the drift layer. With the combination of doping concentration and quasi-depletion layer thickness, the quasi-depletion layer is in a fully depleted state under zero bias voltage, while under reverse bias voltage, based on the characteristic that the quasi-depletion layer is already depleted at zero bias voltage, the reverse voltage is mainly due to the N-type cathode ohmic contact layer below. ‑ The GaN drift layer effectively reduces reverse leakage current.

This invention discloses a nitride PN junction Schottky diode, mainly addressing the problem of low breakdown voltage in existing vertical nitride Schottky diodes. From bottom to top, it includes a cathode (5), a substrate (1), and an n-junction junction. + Al x Ga 1‑x The structure comprises an N-transport layer (2), a scandium-yttrium aluminum nitride / gallium nitride stacked structure (3), a scandium-yttrium aluminum nitride / aluminum nitride stacked structure (4), and an anode (6). The nitride and scandium-yttrium aluminum nitride materials in these two stacked structures (3, 4) are grown sequentially and periodically. Each scandium-yttrium aluminum nitride layer has a thickness of 3nm-50nm, with a constant composition. The total thickness and period of both layers may be the same or different, and the overall scandium composition is 0%-35%, while the yttrium composition is 0%-25%. This invention utilizes the polarization effect of nitride materials to form a vertical PN junction, and leverages the ferroelectric polarization effect of ScYAlN to improve reverse withstand voltage, reduce reverse leakage current, and increase breakdown voltage. It can be used in microwave rectification and power switching circuits.

A method and vertical FET device fabricated in GaN or other suitable material. The device has a selective area implant region comprising an activated impurity configured from a bottom portion of a recessed regions, and substantially free from ion implant damage by using an annealing process. A p-type gate region is configured from the selective area implant region, and each of the recessed regions is characterized by a depth configured to physically separate an n+ type source region and the p-type gate region such that a low reverse leakage gate-source p-n junction is achieved. An extended drain region is configured from a portion of an n-type GaN region underlying the recessed regions. An n+ GaN region is formed by epitaxial growth directly overlying the backside region of the GaN substrate and a backside drain contact region configured from the n+ type GaN region overlying the backside region.

The present application is a vertical light emitting diode structure, which comprises a light emitting diode element, a sidewall insulation layer, a soldering electrode and a metal protection layer. The metal protection layer is electrically connected to the soldering electrode, and covers the crystal grain side edge and the carrier side edge of the light emitting diode element through the sidewall insulation layer. In this way, the potential failure of the sidewall insulation layer during the electroplating or chemical plating process and other harsh processes can be solved by the covering protection of the metal protection layer. In addition, the metal protection layer can provide test points to evaluate the quality of the sidewall insulation layer by detecting the forward bias voltage (Vf) and reverse leakage current (Ir) of the light emitting diode element.

The invention discloses a low-ripple charge pump circuit, and the circuit comprises a non-overlapping clock circuit which is used for generating a first clock signal and a second clock signal which are not overlapped according to an external clock signal; and the charge pump main body circuit is used for boosting the input voltage according to the first clock signal and the second clock signal to form charge pump output voltage and dynamic substrate bias voltage. According to the OTP memory circuit, the loss of reverse leakage current can be effectively reduced by adopting the non-overlapping clock signals, the reverse leakage current caused by conduction of a path between input and output due to simultaneous conduction of the switching tubes of the charge pump is avoided, and the OTP memory circuit can meet the requirements of high stability and low loss of the OTP memory circuit.

The invention discloses a Schottky diode device and a preparation method thereof, and belongs to the technical field of power semiconductors. The Schottky diode device comprises an N-type substrate layer, an N-type buffer layer, a first N-type epitaxial layer, a first P-type region, a second N-type epitaxial layer, a second P-type region, an anode ohmic metal contact layer, an anode Schottky metal contact layer, an anode metal layer and a cathode metal layer. Wherein the upper surface of the second N-type epitaxial layer comprises a plurality of grooves, so that the Schottky metal contact area and the ohmic metal contact area are increased, the conduction voltage drop can be reduced, and the anti-surge capability of the device is improved. According to the double-layer epitaxial structure, the doping concentration at the interface of Schottky metal and a semiconductor is improved, a depletion layer on the Schottky contact surface is narrowed, the hot electron emission current is increased, the effective barrier height is reduced, the tunneling effect is enhanced, and the conduction voltage drop is reduced. While low conduction voltage drop and low reverse leakage current are taken into consideration, the stability and reliability of the device under high surge current are remarkably improved.

The invention discloses a segmented polycrystalline silicon deep groove silicon carbide MOSFET, and belongs to the technical field of semiconductor power devices. According to the device, a P + polycrystalline silicon section connected with a source electrode, a lightly doped Npolycrystalline silicon section and an N + polycrystalline silicon section connected with a grid electrode are sequentially arranged in a deep groove in the depth direction, and the P + polycrystalline silicon section, the lightly doped Npolycrystalline silicon section and the N + polycrystalline silicon section jointly form a polycrystalline silicon diode structure similar to a PIN. The P + polycrystalline silicon section at the bottom of the groove is used for shielding an electric field, the gate-drain coupling capacitance (Cgd) is effectively reduced, and the switching characteristic of the device is improved; meanwhile, by utilizing the characteristic that the reverse leakage current of the PIN structure is obviously increased under the short-circuit temperature rise, the self-adaptive reduction of the gate-source voltage (Vgs) is realized through gate loop resistance voltage division, so that the short-circuit current is inhibited. While voltage resistance and conduction performance of the device are ensured, short-circuit endurance capability and safe turn-off reliability of the device are remarkably improved.

The invention discloses a gallium oxide heterojunction diode with a vertical structure and a preparation method. The gallium oxide heterojunction diode comprises a gallium oxide epitaxial wafer; the P-type oxide is located in the middle area of the upper surface of the gallium oxide epitaxial wafer; the two sides of the P-type oxide are of an arc-shaped structure, and the curvature radius of the arc-shaped structure is smaller than 3 microns. The SiO2 field plates are located on the two sides of the P-type oxide and make contact with the P-type oxide; the anode electrode is located on the P-type oxide and part of the SiO2 field plate; and the cathode electrode is positioned on the lower surface of the gallium oxide epitaxial wafer. According to the device structure designed by the invention, reverse leakage current is effectively inhibited, the breakdown voltage of the device is effectively improved, and the performance and reliability of the device are greatly improved.

The invention discloses a self-blocking type water electrolysis electrode and a preparation method thereof.The electrode comprises a conductive substrate, a Mott phase change functional layer located on the conductive substrate and a monatomic catalyst layer located on the Mott phase change functional layer, the Mott phase change functional layer is composed of strong correlation electron oxide, and the monatomic catalyst layer is composed of a metal oxide and a metal oxide. The defect-rich carbon nitride carrier is subjected to electric field induced metal-insulator phase change under reverse critical potential, and the monatomic catalyst layer is anchored on the defect-rich carbon nitride carrier through M-N4 coordinate bonds by precious metal monatomic atoms. Based on the electronic correlation effect of the Mott phase change function layer in a specific critical electric field, reversible mutation from metallicity to insulativity is achieved, reverse leakage current is restrained to the microampere level, and electrochemical corrosion is fundamentally eradicated; meanwhile, through monatomic dispersion and strong M-N4 coordination bond locking, the metal active center still keeps zero valence state and atomic-scale dispersion under the condition of potential reversal, and'immortalization 'of the catalyst is realized.

The invention discloses a Schottky diode with deep and shallow synergy grooves and a preparation method of the Schottky diode, and relates to the field of power semiconductor devices. The anode metal is formed on the N-drift layer and forms Schottky contact with the N-drift layer; a first trench disposed in the N-drift layer below the anode metal; a second trench disposed in the N-drift layer below the anode metal; wherein the depth of the first groove is greater than that of the second groove. According to the invention, the deeper first groove allows the doping concentration of the drift layer to be improved through the charge balance effect in the device, thereby remarkably reducing the forward conduction voltage drop; the shallower second groove effectively inhibits electric field concentration at the edge of the anode on the surface, weakens a mirror force barrier reduction effect, and further greatly reduces reverse leakage current and improves voltage withstanding consistency; meanwhile, the shallow trench structure is also beneficial to reducing stray capacitance between the anode and the drift layer and improving the performance of the high-frequency switch.

The invention discloses a memristor based on vacuum-assisted drying film formation and a preparation method thereof, and belongs to the technical field of oxide thin film preparation and memristors. According to the method, a BiFeO3 and NiFe2O4 precursor solution is accurately prepared, a precursor is coated by adopting a solution method, the key point is that vacuum auxiliary drying is used for replacing traditional hot stage direct drying, annealing and calcining processes are matched, a compact and uniform n-type BiFeO3 thin film, a p-type NiFe2O4 thin film and a BiFeO3 / NiFe2O4 heterojunction are firstly prepared, and then preparation of the memristor is completed based on an evaporation electrode of the heterojunction. The memristor prepared through the method is small in reverse leakage current, stable in switching characteristic and excellent in cycle performance, good electrical performance is still kept after hundreds of cycles, the problems that in preparation through a traditional solution method, film quality is poor, heterojunction interface bonding is poor, and memristor performance is unstable are solved, and the method is suitable for batch production of high-performance memristors.

The bias current generating circuit includes a current path and a leakage control circuit. The current path is connected between a supply voltage and a ground level. The current path includes a transistor and a resistor. The transistor has a current channel connected in the current path. The resistor has an upper end and a lower end connected in the current path, and a well contact through which a reverse leakage current of the resistor flows. The leakage control circuit is connected to the supply voltage. The leakage control circuit includes a drive transistor to provide a drive voltage to the well contact of the resistor, and to cause the reverse leakage current of the resistor to flow into the leakage control circuit.

The invention belongs to the technical field of ultra-wide bandgap semiconductors, and particularly relates to a power diode device and a preparation method thereof, MXene is adopted as a Schottky anode material, and the series resistance is remarkably reduced by using the ultrahigh conductivity of the MXene, so that the performance of the device in high-frequency and large-current application is improved. Meanwhile, by regulating and controlling the surface terminal and the element composition of the MXene, the flexible adjustment of the work function can be realized, so that the electron affinity of the MXene can be well matched with that of beta-Ga2O3, a higher Schottky barrier and an excellent rectification characteristic can be further obtained, and the reverse leakage current can be inhibited. In addition, as a two-dimensional material, MXene can form a uniform and flat Van der Waals contact interface, so that the damage of a high-energy process is avoided, the surface integrity of beta-Ga2O3 is maintained, the interface state and Fermi level pinning effect are effectively relieved, the barrier height better conforms to the theoretical design, and the Schottky diode with the performance closer to the ideal state can be realized.

This invention discloses a vertical power MOSFET based on n-type gallium oxide and p-type diamond, including n + -Ga2O3 substrate, n ‑ -Ga2O3 drift layer, p-type diamond matrix, n + Source region, source electrode, gate electrode, and drain electrode, where the drain electrode, n + -Ga2O3 substrate, n ‑ -Ga2O3 drift layer, p-type diamond matrix and n + The source regions are set sequentially from bottom to top; n + A gate slot is formed on the upper surface of the source region, and the gate slot extends to n ‑ - The upper surface or interior of the Ga2O3 drift layer; the interior of the gate trench is coated with a gate dielectric layer, and the gate electrode is disposed inside the gate trench and enclosed by the gate dielectric layer; the source electrode is disposed on the n + The upper surface of the source region, excluding n + The region outside the source region; n ‑ - The doping concentration of the Ga2O3 drift layer is less than n + - Doping concentration of the Ga2O3 substrate. This invention uses p-type diamond instead of the difficult-to-achieve p-type gallium oxide to form the p-type base region, which can enhance the breakdown voltage of MOSFET devices, reduce reverse leakage current, improve thermal conductivity, and increase device reliability.

The application discloses a GaN Schottky barrier diode with a polarization terminal structure and a preparation method thereof, and relates to the technical field of semiconductors. + A GaN layer, an n ‑ GaN drift layer, an AlGaN layer, an i-GaN layer and a p-GaN layer; a layer stack composed of the i-GaN layer and the p-GaN layer generates a two-dimensional hole gas through polarization with the AlGaN layer; a normal projection of the layer stack of the AlGaN layer, the i-GaN layer and the p-GaN layer is located in a first region of a normal projection of the n ‑ GaN drift layer; a normal projection of the n ‑ GaN drift layer includes the first region and a second region; an anode is located on the layer stack of the AlGaN layer, the i-GaN layer and the p-GaN layer and extends into the n ‑ GaN drift layer; a normal projection of the anode overlaps with the first region and the second region of the normal projection of the n ‑ GaN drift layer; a cathode is located on the n + GaN layer and is spaced apart from the n ‑ GaN drift layer. The application can reduce reverse leakage current and improve device voltage resistance.

A method of manufacturing a semiconductor device includes performing a first implantation process to form a first doped region in an epitaxial layer. The epitaxial layer and the first doped region have a first conductivity type. The manufacturing method also includes performing a second implantation process to form a first portion of a second doped region in the epitaxial layer. A first portion of the second doped region has a second conductivity type different from the first conductivity type and is adjacent to the first doped region. The manufacturing method also includes performing a third implantation process to form a second portion of a second doped region having a second conductivity type in the epitaxial layer. The second portion of the second doped region is vertically located below the first doped region. The manufacturing method further includes forming an electrode structure. The electrode structure is electrically connected to the first doped region and the second doped region. And under the condition of maintaining relatively low forward voltage, the reverse leakage current is reduced.

The application discloses a gallium oxide field termination power diode based on SOG, which comprises a cathode metal electrode, a substrate layer and a drift layer arranged in sequence from bottom to top; a plurality of P-type SOG dielectric structures are arranged on the drift layer, and an anode metal electrode is arranged between the surface of the P-type SOG dielectric structure and the intervals of the plurality of P-type SOG dielectric structures. The application further provides a preparation method of the gallium oxide field termination power diode based on SOG. The P-type SOG dielectric structure formed by B-doped SOG is used as a field termination, the electric field distribution in the device channel can be modulated, the peak value of the edge electric field of the anode metal electrode is reduced, the breakdown voltage of the device is improved, and the reverse leakage current of the anode metal electrode can be greatly reduced. In addition, the P-type SOG dielectric structure is used to form a P-type dielectric in a physical spin-on SOG mode, damage caused by a glow introduced during equipment deposition is avoided, the preparation process is simple and easy to implement, and the manufacturing cost is effectively reduced.

The application discloses a semiconductor dielectric layer structure and a manufacturing method. The semiconductor dielectric layer structure comprises a semiconductor substrate, an epitaxial layer arranged on the surface of the semiconductor substrate, a plurality of grooves arranged on the epitaxial layer, a first thermal oxidation layer arranged on the surface of the epitaxial layer, in-situ doped polysilicon filled in the grooves, a gate oxide layer formed between the in-situ doped polysilicon and the grooves, a silicon nitride layer arranged on the surface of the first thermal oxidation layer between the adjacent grooves, a second thermal oxidation layer arranged on the surface of the silicon nitride layer, a deposited oxide layer arranged on the surface of the second thermal oxidation layer, a contact hole formed by hollowing out the deposited oxide layer, the second thermal oxidation layer, a part of the first thermal oxidation layer and the silicon nitride layer at the bottom of the second thermal oxidation layer, and the bottom end of the contact hole extending to the surface of the epitaxial layer in the middle part of the bottom end, so that the top of the epitaxial layer is exposed, and the bottom end edge of the bottom part of the contact hole extends to the in-situ doped polysilicon to expose the gate oxide layer of the inner wall of the groove. The application can achieve the purpose of reducing reverse leakage current.

The application provides a Schottky contact super-barrier rectifier, which forms a low electron barrier structure based on an anode metal layer, a first conductive type polysilicon layer, an oxide layer and a second conductive type low electron barrier germanium silicon region, and the low electron barrier structure is an anode structure of the rectifier; when the rectifier is forward conducted, electrons will flow more easily from a cathode to an anode, and a smaller conduction voltage is achieved. Therefore, the rectifier can increase the thickness of the oxide layer without deteriorating the forward conduction voltage and the reverse leakage current; the single particle gate penetration characteristic of the Schottky contact super-barrier rectifier is improved by increasing the thickness of the oxide layer without degrading the basic electrical characteristics, so as to improve the anti-single particle gate penetration performance.

The invention relates to the technical field of semiconductors, and discloses a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a semiconductor substrate layer; an epitaxial layer located on the semiconductor substrate layer; the electric field shielding region and the doped region are located in the epitaxial layer, the doped region is located on the side, away from the semiconductor substrate layer, of the electric field shielding region, and the doped region is exposed out of the surface of the side, away from the semiconductor substrate layer, of the epitaxial layer; the metal layer is located on the surface, deviating from the semiconductor substrate layer, of the epitaxial layer, and at least part of an opposite region between the metal layer and the electric field shielding region does not coincide with the doped region; and the electric field shielding region and the doped region have the same conduction type and are opposite to the conduction type of the epitaxial layer. The reverse voltage withstanding characteristic of the semiconductor structure is improved, and the reverse electric leakage characteristic is reduced.

The utility model provides a groove type Schottky diode and electronic equipment, and relates to the technical field of semiconductors. The groove type Schottky diode comprises an N type epitaxial layer; the groove and the P-type doped regions are located on the surface layer of the epitaxial layer, and the P-type doped regions are located on the two sides of the groove; the shielding layer and the polycrystalline silicon field plate are located in the groove; a metal layer on the surface of the epitaxial layer; wherein Schottky contact is formed between the metal layer and other areas except the P-type doped area. The groove type Schottky diode and the electronic equipment provided by the utility model have the advantage of reducing reverse electric leakage of a device.