108 results about "Reverse leakage current" patented technology

The invention discloses a Schottky diode and a manufacturing method thereof, the Schottky diode comprises a substrate, an epitaxial layer, a cathode layer, a plurality of first ion implantation regions, a plurality of first grooves, a second barrier metal layer and an anode layer, the plurality of first ion implantation regions and the plurality of first grooves are arranged in a main junction region, a first ion implantation region is arranged at the bottom of the first groove, a PN junction is formed between the first ion implantation region and the epitaxial layer, a second ion implantation region is arranged at the bottom of the first groove, a PN junction is formed between the second ion implantation region and the epitaxial layer, and a first barrier metal layer is arranged on the side wall of the first groove; the second barrier metal layer is arranged on one side, far away from the substrate, of the epitaxial layer, is positioned in the main junction region and is connected with the first ion implantation region and the first barrier metal layer; the anode layer is disposed on the second barrier metal layer. Through the above design, the reverse leakage current of the Schottky diode can be greatly reduced, and the forward conduction voltage drop of the Schottky diode can be reduced.

The invention provides an LED test data monitoring method and system, a computer and a storage medium, and the method comprises the following steps: dividing a plurality of first wafer regions, and obtaining a plurality of first crystal grain data sets and a plurality of reverse leakage current data sets through a plurality of first test hardware; determining a plurality of second wafer areas, and obtaining a plurality of second crystal grain data sets through second test hardware; updating the first crystal grain data set into an updated crystal grain data set; calculating a plurality of to-be-evaluated yields based on the reverse leakage current data set and the reverse leakage current threshold; judging whether abnormal first test hardware exists or not based on the to-be-evaluated yield and a yield difference threshold value; and if not, the wafer is conveyed out of the station. The distortion of the test result is reduced by updating the first crystal grain data set; by processing a plurality of to-be-evaluated yield rates, the phenomenon of abnormal yield rate statistics is identified in time, and the deviation among a plurality of test channels is monitored.

The invention discloses a power diode based on an MOF, a preparation method, a 3D chip packaging method and application, belongs to the technical field of electronic materials and power devices, and particularly relates to a composite structure based on an n-Si substrate / an (n-Si)-(ZIF-8) composite layer / an Ag layer, preparation, a 3D chip packaging method and application of the composite structure in the field of power devices. The reverse withstand voltage of the power diode based on the n-Si substrate / ''(n-Si)-(ZIF-8) composite layer'' / Ag layer composite structure exceeds 200V, the forward conduction voltage of the power diode is 0.25-1.5 V, the reverse bias voltage applied to the power diode is 0-200V, the reverse leakage current is basically not increased along with the increase of the reverse bias voltage, and the reverse leakage current is 0.2-2.1 mA (at the reverse voltage-100V). Compared with a conventional power diode based on an n-Si substrate / Ag layer Schottky structure, the performance of the power diode provided by the invention has the advantages that although the forward voltage is basically unchanged, the reverse voltage is increased by 80-400%, the reverse saturation current is reduced by 50-800%, and the highest yield reaches 95%.

MOS junction barrier Schottky diode relates to the technical field of power semiconductor device. N-type substrate, N-type epitaxial layer, deep P region, slot gate, slot gate oxide layer, conductive enhancement region and isolation oxide layer are arranged between cathode metal and anode metal, the lower surface of the N-type substrate is in contact with the cathode metal, the upper surface is in contact with the lower surface of the N-type epitaxial layer, the upper surface of the N-type epitaxial layer is in contact with the P region, the conductive enhancement region is arranged on the outer surface of the slot gate oxide layer and is in contact with the N-type epitaxial layer, part of the slot gate oxide layer, the conductive enhancement region, the isolation oxide layer and part of the deep P region are respectively in contact with part of the anode metal. The MOS junction barrier Schottky diode structure of the application improves the carrier density at the channel, reduces the channel resistance, and further improves the reverse leakage current characteristics and the forward voltage drop by inserting a slot gate MOS structure in the adjacent P region of the traditional junction barrier Schottky (JBS) diode.

The application relates to a semiconductor structure and a preparation method of the semiconductor structure, and the semiconductor structure comprises: a first AlGaN / AlN / GaN heterostructure, a first two-dimensional electron gas channel existing at the interface between the AlN layer and the GaN layer in the first AlGaN / AlN / GaN heterostructure; a second AlGaN / AlN / GaN heterostructure, a second two-dimensional electron gas channel existing at the interface between the AlN layer and the GaN layer in the second AlGaN / AlN / GaN heterostructure; and a third AlGaN / AlN / GaN heterostructure, a third two-dimensional electron gas channel existing at the interface between the AlN layer and the GaN layer in the third AlGaN / AlN / GaN heterostructure; the difference between the electron concentration in the first two-dimensional electron gas channel, the electron concentration in the second two-dimensional electron gas channel and the electron concentration in the third two-dimensional electron gas channel is less than a preset value, thereby adjusting the carrier distribution, so as to achieve the purposes of reducing the device resistance value, reducing the reverse leakage current and reducing the heat generation in the working state of the device.

The invention relates to the technical field of semiconductor power devices, in particular to a gallium oxide Schottky diode and a manufacturing method thereof. The gallium oxide Schottky diode comprises a substrate; the gallium oxide epitaxial layer is arranged on the substrate; the atomic nitrogen processing layer is arranged on the gallium oxide epitaxial layer; the first electrode is arranged on the gallium oxide epitaxial layer, and the second electrode is arranged below the gallium oxide substrate. According to the gallium oxide Schottky diode provided by the invention, the breakdown voltage can be remarkably improved, the oxygen vacancy density is reduced, and the reverse leakage current is reduced.

The invention relates to a three-wire system thermal resistance measurement system and method. The system comprises four groups of transient voltage suppressors, three cables, two constant current sources, a bias resistor, two switches, an output circuit, an output end of a first constant current source and a negative electrode of a first transient voltage suppressor, wherein one end of a first switch is connected with one end of a thermal resistor through a first cable; the other end of the first switch is connected with the negative electrode of the second transient voltage suppressor; the other end of the thermal resistor is grounded through a third cable; the output end of the second constant current source, the negative electrode of the third transient voltage suppressor and one end of the second switch are connected with the other end of the thermal resistor through the biasing resistor and the second cable in sequence; the other end of the second switch is connected with the negative electrode of the fourth transient voltage suppressor; and the output circuit is used for outputting the amplified voltage difference between the output ends of the first constant current source and the second constant current source. The resistance value of the thermal resistor is calculated, high EMC performance is achieved, and measurement errors caused by non-linear reverse leakage current are eliminated.

The invention relates to the field of photovoltaic technology, in particular to a back contact solar cell and a photovoltaic module. The back contact solar cell comprises a substrate, first areas and second areas which are alternately arranged at intervals in the X direction are formed on the backlight face of the substrate, gaps between the adjacent first areas and second areas form third areas, a first doping layer is formed in each first area, a second doping layer is formed in each second area, and a second doping layer is formed in each second area. A third doping layer is formed in each third region; the doping concentration of the third doping layer is greater than the doping concentration of the first doping layer and the doping concentration of the second doping layer; the third doped layer is electrically connected with the adjacent first doped layer and the adjacent second doped layer. Compared with the prior art, the arrangement of the third doping layer is beneficial to generating leakage current under relatively low reverse bias voltage, so that the hot spot temperature of the assembly is remarkably reduced, the reliability of a single battery and the assembly is improved, and the phenomenon of abnormal concentration of reverse leakage current can be avoided.

A semiconductor device includes a substrate, a drift region, a well region, a first shielding region, a junction field effect transistor region, a source region, and a gate structure. The drift region is located in the substrate. The well region is located in the drift region. The first shielding region is located in the drift region, wherein the bottom surface of the first shielding region is lower than the bottom surface of the well region, and the carrier concentration of the first shielding region is higher than that of the well region. The junction field effect transistor region is located in the drift region, the bottom surface of the junction field effect transistor region is lower than the bottom surface of the first shielding region, and the first part of the first shielding region is located between the well region and the junction field effect transistor region. The source region is adjacent to the well region. The gate structure is located on the drift region. As the shielding region is arranged between the junction field effect transistor region and the well region, the problem of reverse leakage current can be obviously solved, and the influence of the reverse leakage current on the power consumption of the element is reduced.

The LDMOS device model comprises a BSIM4 model, a plurality of segmented resistor models which are sequentially connected in series and a plurality of drain substrate diode models, and the segmented resistor models which are sequentially connected in series are connected to a drain electrode of the BSIM4 model in series. A drift region of an LDMOS is simulated through a plurality of segmented resistor models which are sequentially connected in series, and the input end of each segmented resistor model is connected with a corresponding drain substrate diode model. Due to the fact that the segmented resistor models are connected in series, changes of electrical characteristics of drain substrate diodes at different positions of a drift region are simulated, and then the simulation precision of the LDMOS device model on drain substrate parasitic capacitance and gate channel intrinsic capacitance of an LDMOS is improved. And the simulation precision of the reverse leakage current of the drain substrate diode is improved.

The invention provides a gallium oxide Schottky diode structure and a preparation method thereof. The gallium oxide Schottky diode structure comprises a gallium oxide substrate, a gallium oxide epitaxial layer, a second metal layer, a first metal layer and a dielectric layer, wherein the gallium oxide epitaxial layer and the second metal layer are formed on two opposite side surfaces of the gallium oxide substrate, and the first metal layer and the dielectric layer are formed on the gallium oxide epitaxial layer. A trench unit is arranged on one side, far away from the first surface, of the gallium oxide epitaxial layer, the first metal layer is formed on the trench unit and is in contact with the exposed gallium oxide epitaxial layer between the trench unit, and the dielectric layer is formed on the exposed gallium oxide epitaxial layer outside the trench unit and forms a stepped field plate structure with the first metal layer. According to the gallium oxide Schottky diode, the stepped field plate structure and Schottky contact formed by contact of the first metal layer and part of the surface of the gallium oxide epitaxial layer are utilized, the effects of improving the electric field concentration effect of an existing gallium oxide Schottky diode are achieved, the breakdown voltage of the gallium oxide Schottky diode is improved, the reverse leakage current is reduced, and the reliability of the gallium oxide Schottky diode is improved. And the performance of the device is further improved.

The application discloses a power device and a preparation method thereof, and relates to the technical field of semiconductors. The power device comprises a semiconductor substrate, a first buffer layer, a second buffer layer, a third buffer layer, a barrier layer, a passivation layer, a first anode, a dielectric layer, a second anode, a cathode, a protective layer, anode conduction metal, cathode conduction metal and a field plate layer. The application solves the technical problem of large reverse leakage current of the power device.

The application discloses a wide-bandgap power diode with a periodic composite anode, which comprises, from bottom to top, a wide-bandgap semiconductor material substrate layer, a third anode groove, a wide-bandgap semiconductor material epitaxial layer, a periodic first anode groove and a second anode on the wide-bandgap semiconductor material epitaxial layer, a first dielectric layer and a second dielectric layer arranged on the first anode groove and the upper surface of the wide-bandgap semiconductor material epitaxial layer in sequence, the second dielectric layer arranged on the second anode groove and the upper surface of the wide-bandgap semiconductor material epitaxial layer, a third dielectric layer arranged on the third anode groove, and a metal anode and a metal cathode arranged on the upper surface of the wide-bandgap semiconductor material epitaxial layer and the lower surface of the wide-bandgap semiconductor material substrate layer respectively. The application has the performance advantages of high current density, high breakdown voltage, low on-resistance and low reverse leakage current due to the periodic composite anode structure.

The application relates to a kind of detection method, device, system and storage medium of LED lamp bead, comprising the following steps, the electrode of the LED lamp bead is tested, and the initial current value of the LED lamp bead is obtained;Based on the initial current value, the LED lamp bead is applied to step voltage, and voltage-current curve is obtained;The LED lamp bead corresponding to the rated operating point in the voltage-current curve is detected by optical detector, and the light spot image is obtained;Based on the light spot image, the LED lamp bead is tested by reverse voltage, and the reverse leakage current value is obtained;Based on the voltage-current curve, light spot image and reverse leakage current value, the quality of the LED lamp bead is evaluated, and the quality evaluation result of the LED lamp bead is obtained, which solves the technical problem that the traditional detection method is mainly concentrated on simple on-off test or single parameter measurement, and it is difficult to comprehensively reflect the comprehensive performance of LED lamp bead.

This invention discloses a gallium nitride Schottky diode with a quasi-depletion layer, the structure of which, from bottom to top, comprises: a substrate layer, a buffer layer, and an N-type diode. + -GaN contact layer, N ‑ -GaN drift layer, quasi-depletion layer, and anode Schottky contact layer disposed on the quasi-depletion layer and disposed on N + A cathode ohmic contact layer above a GaN contact layer; wherein the doping concentration and thickness of the quasi-depletion layer must satisfy the following: the thickness of the quasi-depletion layer is less than the width of the depletion layer of the diode at zero bias voltage. This invention significantly reduces the turn-on voltage of the diode by setting a highly doped quasi-depletion layer on the surface of the drift layer. With the combination of doping concentration and quasi-depletion layer thickness, the quasi-depletion layer is in a fully depleted state under zero bias voltage, while under reverse bias voltage, based on the characteristic that the quasi-depletion layer is already depleted at zero bias voltage, the reverse voltage is mainly due to the N-type cathode ohmic contact layer below. ‑ The GaN drift layer effectively reduces reverse leakage current.

The present invention belongs to the technical field of back-contact batteries, and specifically relates to a method for manufacturing and applying a combined passivation back-contact battery with a precisely set reverse leakage channel, comprising: S5, using laser crystallization technology to crystallize a portion of a second semiconductor layer superimposed on a first semiconductor layer and near the edge of a first opening region to obtain a crystallized region; S6, forming a second opening region spaced apart from the first opening region; S7, depositing a transparent conductive film layer on the back side; S8, forming an isolation trench, with at least a portion of the isolation trench corresponding to the crystallized region, and the crystallized region, the first doped polysilicon layer, and the transparent conductive film layer forming a reverse leakage channel PN junction. The present invention significantly increases the reverse leakage capacity of the reverse leakage channel PN junction, dispersing the reverse leakage current and reducing the battery hot spot effect, while also achieving higher battery efficiency. The bypass diode can be eliminated, reducing costs, reducing battery attenuation, and increasing power generation.

This invention discloses a nitride PN junction Schottky diode, mainly addressing the problem of low breakdown voltage in existing vertical nitride Schottky diodes. From bottom to top, it includes a cathode (5), a substrate (1), and an n-junction junction. + Al x Ga 1‑x The structure comprises an N-transport layer (2), a scandium-yttrium aluminum nitride / gallium nitride stacked structure (3), a scandium-yttrium aluminum nitride / aluminum nitride stacked structure (4), and an anode (6). The nitride and scandium-yttrium aluminum nitride materials in these two stacked structures (3, 4) are grown sequentially and periodically. Each scandium-yttrium aluminum nitride layer has a thickness of 3nm-50nm, with a constant composition. The total thickness and period of both layers may be the same or different, and the overall scandium composition is 0%-35%, while the yttrium composition is 0%-25%. This invention utilizes the polarization effect of nitride materials to form a vertical PN junction, and leverages the ferroelectric polarization effect of ScYAlN to improve reverse withstand voltage, reduce reverse leakage current, and increase breakdown voltage. It can be used in microwave rectification and power switching circuits.

A method and vertical FET device fabricated in GaN or other suitable material. The device has a selective area implant region comprising an activated impurity configured from a bottom portion of a recessed regions, and substantially free from ion implant damage by using an annealing process. A p-type gate region is configured from the selective area implant region, and each of the recessed regions is characterized by a depth configured to physically separate an n+ type source region and the p-type gate region such that a low reverse leakage gate-source p-n junction is achieved. An extended drain region is configured from a portion of an n-type GaN region underlying the recessed regions. An n+ GaN region is formed by epitaxial growth directly overlying the backside region of the GaN substrate and a backside drain contact region configured from the n+ type GaN region overlying the backside region.

The present invention provides a Schottky diode comprising: an N+ substrate and an N-epitaxial layer located on the N+ substrate; a Schottky metal layer unit, wherein the Schottky metal layer unit covers the surface of the N-epitaxial layer, the Schottky metal layer unit comprising a plurality of Schottky metal layers, and the metals of two adjacent Schottky metal layers are different; an anode metal located on the Schottky metal layer unit; and a cathode metal located on the other surface of the N+ substrate. The present invention also provides a method for preparing a Schottky diode, which can relatively flexibly adjust the Schottky barrier to obtain an ideal forward voltage drop and an acceptable reverse leakage current.

The invention provides a semiconductor structure and a semiconductor device, the semiconductor structure comprises a SiC substrate, a heavily-doped SiC layer, an AlGaN epitaxial layer and a GaN epitaxial layer which are stacked in sequence, the GaN epitaxial layer comprises a heavily-doped layer and a lightly-doped layer which are stacked, and the SiC substrate, the heavily-doped SiC layer, the AlGaN epitaxial layer and the GaN epitaxial layer are of a first conduction type. On one hand, the heavily-doped SiC layer is designed, so that the on-resistance is reduced, and the low turn-on voltage is realized. The design of the graphical heavily-doped SiC layer can further increase the contact area and reduce the interface conduction resistance. And on the other hand, the insertion layer designed by the invention can form a tunnel junction with the heavily doped SiC layer or the AlGaN epitaxial layer, charge circulation can be effectively hindered by using a tunneling mechanism to realize the normally-off characteristic of the semiconductor structure, the threshold voltage can be increased, and the reverse leakage current can be reduced. Insertion layers designed in different epitaxial layers can regulate and control the position of a tunnel junction in the semiconductor structure, and the threshold voltage is further adjusted.

The present application is a vertical light emitting diode structure, which comprises a light emitting diode element, a sidewall insulation layer, a soldering electrode and a metal protection layer. The metal protection layer is electrically connected to the soldering electrode, and covers the crystal grain side edge and the carrier side edge of the light emitting diode element through the sidewall insulation layer. In this way, the potential failure of the sidewall insulation layer during the electroplating or chemical plating process and other harsh processes can be solved by the covering protection of the metal protection layer. In addition, the metal protection layer can provide test points to evaluate the quality of the sidewall insulation layer by detecting the forward bias voltage (Vf) and reverse leakage current (Ir) of the light emitting diode element.

The present invention discloses a semiconductor transducer bridge and its preparation method in the field of semiconductor device technology. The semiconductor transducer bridge comprises: an insulating substrate; a doping layer, arranged above the insulating substrate, the doping layer comprising a P-type lightly doped region, a P-type heavily doped region, and an N-type heavily doped region, the P-type heavily doped region being arranged on both sides of the P-type lightly doped region, and the N-type heavily doped region being arranged on both sides of the P-type heavily doped region; a thin oxide layer, arranged above the doping layer; a silicon nitride layer, arranged above the thin oxide layer; a metal bonding pad, arranged above the silicon nitride layer, the lower part of the metal bonding pad being in contact with the N-type heavily doped layer; and a metal welding layer, arranged below the insulating substrate. The P-type depletion-type device of the semiconductor transducer bridge can provide higher energy to the outside, has low reverse leakage current, and has a long service life; and its P-type heavily doped region is located on both sides of the P-type lightly doped region, thereby improving the packaging efficiency.

The invention discloses a low-ripple charge pump circuit, and the circuit comprises a non-overlapping clock circuit which is used for generating a first clock signal and a second clock signal which are not overlapped according to an external clock signal; and the charge pump main body circuit is used for boosting the input voltage according to the first clock signal and the second clock signal to form charge pump output voltage and dynamic substrate bias voltage. According to the OTP memory circuit, the loss of reverse leakage current can be effectively reduced by adopting the non-overlapping clock signals, the reverse leakage current caused by conduction of a path between input and output due to simultaneous conduction of the switching tubes of the charge pump is avoided, and the OTP memory circuit can meet the requirements of high stability and low loss of the OTP memory circuit.

The invention discloses a Schottky diode device and a preparation method thereof, and belongs to the technical field of power semiconductors. The Schottky diode device comprises an N-type substrate layer, an N-type buffer layer, a first N-type epitaxial layer, a first P-type region, a second N-type epitaxial layer, a second P-type region, an anode ohmic metal contact layer, an anode Schottky metal contact layer, an anode metal layer and a cathode metal layer. Wherein the upper surface of the second N-type epitaxial layer comprises a plurality of grooves, so that the Schottky metal contact area and the ohmic metal contact area are increased, the conduction voltage drop can be reduced, and the anti-surge capability of the device is improved. According to the double-layer epitaxial structure, the doping concentration at the interface of Schottky metal and a semiconductor is improved, a depletion layer on the Schottky contact surface is narrowed, the hot electron emission current is increased, the effective barrier height is reduced, the tunneling effect is enhanced, and the conduction voltage drop is reduced. While low conduction voltage drop and low reverse leakage current are taken into consideration, the stability and reliability of the device under high surge current are remarkably improved.

The invention discloses a segmented polycrystalline silicon deep groove silicon carbide MOSFET, and belongs to the technical field of semiconductor power devices. According to the device, a P + polycrystalline silicon section connected with a source electrode, a lightly doped Npolycrystalline silicon section and an N + polycrystalline silicon section connected with a grid electrode are sequentially arranged in a deep groove in the depth direction, and the P + polycrystalline silicon section, the lightly doped Npolycrystalline silicon section and the N + polycrystalline silicon section jointly form a polycrystalline silicon diode structure similar to a PIN. The P + polycrystalline silicon section at the bottom of the groove is used for shielding an electric field, the gate-drain coupling capacitance (Cgd) is effectively reduced, and the switching characteristic of the device is improved; meanwhile, by utilizing the characteristic that the reverse leakage current of the PIN structure is obviously increased under the short-circuit temperature rise, the self-adaptive reduction of the gate-source voltage (Vgs) is realized through gate loop resistance voltage division, so that the short-circuit current is inhibited. While voltage resistance and conduction performance of the device are ensured, short-circuit endurance capability and safe turn-off reliability of the device are remarkably improved.

The present invention relates to a vertical light-emitting chip and its preparation method, comprising: growing a dissociation layer on a sapphire substrate; growing a dielectric layer on the dissociation layer, forming an array of conical protrusions on the surface of the dielectric layer away from the dissociation layer; covering the conical protrusion array with a buffer layer, with the surface of the buffer layer away from the conical protrusion array being flat; sequentially growing a light-emitting functional layer and a conductive functional layer on the buffer layer; and irradiating the dissociation layer with a laser to peel off the sapphire substrate. Through the above method, the dislocation density of the light-emitting functional layer on the flat sapphire substrate in the vertical light-emitting chip can be reduced, resulting in a high-quality light-emitting functional layer. The vertical light-emitting chip also has an internal quantum efficiency increase of 5%-20%, a light extraction efficiency improvement of 1%-5%, a reduction in reverse leakage current, and an L70 lifetime extension of more than 10%.

The invention discloses a gallium oxide heterojunction diode with a vertical structure and a preparation method. The gallium oxide heterojunction diode comprises a gallium oxide epitaxial wafer; the P-type oxide is located in the middle area of the upper surface of the gallium oxide epitaxial wafer; the two sides of the P-type oxide are of an arc-shaped structure, and the curvature radius of the arc-shaped structure is smaller than 3 microns. The SiO2 field plates are located on the two sides of the P-type oxide and make contact with the P-type oxide; the anode electrode is located on the P-type oxide and part of the SiO2 field plate; and the cathode electrode is positioned on the lower surface of the gallium oxide epitaxial wafer. According to the device structure designed by the invention, reverse leakage current is effectively inhibited, the breakdown voltage of the device is effectively improved, and the performance and reliability of the device are greatly improved.

The invention discloses a self-blocking type water electrolysis electrode and a preparation method thereof.The electrode comprises a conductive substrate, a Mott phase change functional layer located on the conductive substrate and a monatomic catalyst layer located on the Mott phase change functional layer, the Mott phase change functional layer is composed of strong correlation electron oxide, and the monatomic catalyst layer is composed of a metal oxide and a metal oxide. The defect-rich carbon nitride carrier is subjected to electric field induced metal-insulator phase change under reverse critical potential, and the monatomic catalyst layer is anchored on the defect-rich carbon nitride carrier through M-N4 coordinate bonds by precious metal monatomic atoms. Based on the electronic correlation effect of the Mott phase change function layer in a specific critical electric field, reversible mutation from metallicity to insulativity is achieved, reverse leakage current is restrained to the microampere level, and electrochemical corrosion is fundamentally eradicated; meanwhile, through monatomic dispersion and strong M-N4 coordination bond locking, the metal active center still keeps zero valence state and atomic-scale dispersion under the condition of potential reversal, and'immortalization 'of the catalyst is realized.

The invention discloses a Schottky diode with deep and shallow synergy grooves and a preparation method of the Schottky diode, and relates to the field of power semiconductor devices. The anode metal is formed on the N-drift layer and forms Schottky contact with the N-drift layer; a first trench disposed in the N-drift layer below the anode metal; a second trench disposed in the N-drift layer below the anode metal; wherein the depth of the first groove is greater than that of the second groove. According to the invention, the deeper first groove allows the doping concentration of the drift layer to be improved through the charge balance effect in the device, thereby remarkably reducing the forward conduction voltage drop; the shallower second groove effectively inhibits electric field concentration at the edge of the anode on the surface, weakens a mirror force barrier reduction effect, and further greatly reduces reverse leakage current and improves voltage withstanding consistency; meanwhile, the shallow trench structure is also beneficial to reducing stray capacitance between the anode and the drift layer and improving the performance of the high-frequency switch.

The invention discloses a memristor based on vacuum-assisted drying film formation and a preparation method thereof, and belongs to the technical field of oxide thin film preparation and memristors. According to the method, a BiFeO3 and NiFe2O4 precursor solution is accurately prepared, a precursor is coated by adopting a solution method, the key point is that vacuum auxiliary drying is used for replacing traditional hot stage direct drying, annealing and calcining processes are matched, a compact and uniform n-type BiFeO3 thin film, a p-type NiFe2O4 thin film and a BiFeO3 / NiFe2O4 heterojunction are firstly prepared, and then preparation of the memristor is completed based on an evaporation electrode of the heterojunction. The memristor prepared through the method is small in reverse leakage current, stable in switching characteristic and excellent in cycle performance, good electrical performance is still kept after hundreds of cycles, the problems that in preparation through a traditional solution method, film quality is poor, heterojunction interface bonding is poor, and memristor performance is unstable are solved, and the method is suitable for batch production of high-performance memristors.