4results about How to "Reduce forward voltage drop" patented technology

The application provides an inverse-conducting insulated gate bipolar transistor and a preparation method thereof, and belongs to the technical field of power semiconductor devices, and comprises: a first groove is a gate groove, a second groove is an emitter groove, and a third groove is an ineffective gate groove; in the lateral direction parallel to the cell surface, the first groove, the second groove and the third groove are sequentially and spacedly arranged, and the first groove and the second groove are connected through a fourth groove, and the fourth groove is a gate groove; in the longitudinal direction, the second groove is located between two adjacent fourth grooves. The beneficial effects are as follows: the gate groove and the ineffective gate groove are connected through the lateral gate groove, the forward conduction voltage drop and the conduction loss of the device are reduced; the current channel is increased, the current distribution is more uniform, the heat loss is reduced, the reliability and the power density of the device are improved; the emitter groove is used for repeatedly arranging the polysilicon gate and the metal gate in the lateral and longitudinal directions, the regularly arranged diodes and Schottky diodes are formed, and the reverse diode current distribution is more uniform.

The application discloses a SiC MOSFET device with improved diode reverse recovery characteristics and a preparation method thereof, and relates to the technical field of semiconductors.The device comprises, from bottom to top, a drain metal layer, an N-type substrate, a first N-type drift layer, a second N-type drift layer, a P-body region, a P+ contact region, an ohmic contact alloy layer and a source metal layer; a P++ layer extending downward is arranged in the middle of the top surface of the second N-type drift layer; a groove region extending into the P++ layer (4) is arranged on the top surface of the P+ contact region; a gate oxide layer is arranged in the groove region; a filled polysilicon gate is arranged in the gate oxide layer; N+ regions extending downward from the top surface of the P+ contact region into the P-body region are arranged on both sides of the groove region; an isolation medium layer is deposited on the P+ contact region, and the isolation medium layer completely covers the top end surfaces of the polysilicon gate and the gate oxide layer.The application can reduce the deep diffusion of carriers, make the recombination of the carriers better distributed in the surface region of the PN junction, and guarantee the long-term reliability of the device.

The application relates to the technical field of semiconductors, in particular to a super-junction fast recovery diode and a manufacturing method thereof, which comprises a substrate, a buffer layer located on the substrate, a drift layer located on the buffer layer, a P-type region located on the drift layer, and a P column located in the drift layer and on the buffer layer, wherein the bottom of the P column is in contact with the upper edge of the buffer layer, and the top of the P column is not in contact with the lower edge of the P-type region. Through the structural arrangement of the super-junction fast recovery diode, the reverse withstand voltage of the device is greatly improved, the on-state voltage drop is reduced, the reverse recovery performance is enhanced, and the reverse recovery loss is reduced.

The application discloses a semiconductor device and a manufacturing method thereof. The semiconductor device comprises: a substrate semiconductor substrate having a first main surface and a second main surface opposite to the first main surface; an insulated gate bipolar transistor region; a fast recovery diode region; an insulating layer provided with a first contact hole and a second contact hole respectively located in the fast recovery diode region and the insulated gate bipolar transistor region; a first semiconductor region located in the fast recovery diode region; a first titanium film provided in the first contact hole; a second semiconductor region located in the insulated gate bipolar transistor region; a second titanium film provided in the second contact hole; the depth of the first semiconductor region from the first main surface to the semiconductor substrate in a first direction is A, the depth of the second semiconductor region from the first main surface to the semiconductor substrate in the first direction is B, and A and B satisfy the relationship: A <= 0.45B. The technical scheme can improve the reverse recovery performance of the semiconductor device.