9results about How to "Reduce forward voltage drop" patented technology

The invention provides a varied doping high-reliability planar gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the upper side surface of the silicon carbide substrate to form a drift layer; a barrier layer is formed, etching and ion implantation are carried out, and a first N-type region, a second N-type region and a P-type well region are formed; a barrier layer is formed again, etching and ion implantation are carried out, and an N-type source region is formed; a barrier layer is formed again, etching and ion implantation are carried out, and a third N-type region is formed; a barrier layer is formed again, and a gate dielectric layer is formed through etching and deposition; and re-forming a barrier layer, etching, depositing metal, forming a gate metal layer and a source metal layer, and removing the barrier layer to complete preparation. The transverse layout of the on-resistance of the device is accurately controlled, so that the current is uniformly distributed in the device, heat concentration is avoided, and the reliability of the device is improved.

The application provides an inverse-conducting insulated gate bipolar transistor and a preparation method thereof, and belongs to the technical field of power semiconductor devices, and comprises: a first groove is a gate groove, a second groove is an emitter groove, and a third groove is an ineffective gate groove; in the lateral direction parallel to the cell surface, the first groove, the second groove and the third groove are sequentially and spacedly arranged, and the first groove and the second groove are connected through a fourth groove, and the fourth groove is a gate groove; in the longitudinal direction, the second groove is located between two adjacent fourth grooves. The beneficial effects are as follows: the gate groove and the ineffective gate groove are connected through the lateral gate groove, the forward conduction voltage drop and the conduction loss of the device are reduced; the current channel is increased, the current distribution is more uniform, the heat loss is reduced, the reliability and the power density of the device are improved; the emitter groove is used for repeatedly arranging the polysilicon gate and the metal gate in the lateral and longitudinal directions, the regularly arranged diodes and Schottky diodes are formed, and the reverse diode current distribution is more uniform.

The invention discloses a double-groove SiC MOSFET device capable of improving reverse follow current and a preparation method thereof. Relates to the technical field of semiconductors. Comprising the following steps: S100, performing epitaxial growth on an N + substrate layer to form an N-epitaxial layer, and forming a PW region at the top of the N-epitaxial layer through ion implantation; s200, etching the top surface of the PW region to form a plurality of gate trench regions; s300, performing secondary injection in the PW region to form a first P + region, a second P + region, a first N + region and a second N + region; s400, etching a source trench region on the first P + region, forming ohmic contact alloy on the side wall of the source trench region, and forming ohmic contact with the P + region on the two sides of the source trench; s500, depositing a gate oxide layer on the side wall and the groove bottom of the gate groove region, and filling the gate oxide layer through a Poly layer to serve as a gate electrode to be led out; and S600, sequentially forming an isolation dielectric layer, an ohmic contact alloy layer, a Schottky metal layer and a front electrode metal layer on the N-epitaxial layer. According to the invention, the peak electric field at the gate oxide layer is inhibited, and the reliability problem of the gate oxide layer of the trench MOSFET can be improved.

The invention discloses a silicon carbide diode and a preparation method of the silicon carbide diode. The silicon carbide diode provided by the invention comprises a substrate layer, a first epitaxial layer, a second epitaxial layer and an anode metal layer which are stacked in sequence, the first surface of the first epitaxial layer comprises at least one first doped region; the first surface is a surface stacked with the second surface of the second epitaxial layer in the first epitaxial layer; a third surface, opposite to the second surface, in the second epitaxial layer comprises first grooves and second grooves which are arranged at intervals, and the second grooves are in one-to-one correspondence with the first doped regions; and the second epitaxial layer comprises a second doped region corresponding to the bottom of the first groove. According to the embodiment of the invention, the reverse voltage withstanding characteristic and the forward conduction characteristic of the silicon carbide diode are optimized at the same time, and the reliability of the silicon carbide diode is improved.

The application discloses a SiC MOSFET device with improved diode reverse recovery characteristics and a preparation method thereof, and relates to the technical field of semiconductors.The device comprises, from bottom to top, a drain metal layer, an N-type substrate, a first N-type drift layer, a second N-type drift layer, a P-body region, a P+ contact region, an ohmic contact alloy layer and a source metal layer; a P++ layer extending downward is arranged in the middle of the top surface of the second N-type drift layer; a groove region extending into the P++ layer (4) is arranged on the top surface of the P+ contact region; a gate oxide layer is arranged in the groove region; a filled polysilicon gate is arranged in the gate oxide layer; N+ regions extending downward from the top surface of the P+ contact region into the P-body region are arranged on both sides of the groove region; an isolation medium layer is deposited on the P+ contact region, and the isolation medium layer completely covers the top end surfaces of the polysilicon gate and the gate oxide layer.The application can reduce the deep diffusion of carriers, make the recombination of the carriers better distributed in the surface region of the PN junction, and guarantee the long-term reliability of the device.

The present application provides an MPS diode and a method for manufacturing the same, and relates to the field of semiconductor technology. The MPS diode includes: an N-type epitaxial wafer; a terminal region and an active region located on the surface of the N-type epitaxial wafer; wherein the active region includes at least one first P column, the first P column includes a P-type sidewall, a first dielectric layer, an ohmic contact layer, and a second dielectric layer; a passivation protection layer located on the surface of the terminal region; a third dielectric layer and a first metal layer located on the surface of the active region, and a second metal layer located on the back of the epitaxial wafer; wherein the third dielectric layer contacts the second dielectric layer, and the first metal layer is arranged around the third dielectric layer. The MPS diode and the method for manufacturing the same provided by the present application have the advantages of reducing the device area and improving the reliability and robustness of the device.

The invention discloses a semiconductor device and a preparation method thereof, and belongs to the technical field of semiconductors. The semiconductor device comprises a semiconductor body, a first electrode, a second electrode, a first ferroelectric material layer and / or a second ferroelectric material layer. The first electrode is arranged on the first surface of the semiconductor body, the second electrode is arranged on the second surface of the semiconductor body, the first ferroelectric material layer is arranged on the side, away from the semiconductor body, of the first electrode, and / or the second ferroelectric material layer is arranged on the side, away from the semiconductor body, of the second electrode. According to the technical scheme, the device structure is optimized, so that the switching speed of the device is improved, and power consumption is reduced.

The application relates to the technical field of semiconductors, in particular to a super-junction fast recovery diode and a manufacturing method thereof, which comprises a substrate, a buffer layer located on the substrate, a drift layer located on the buffer layer, a P-type region located on the drift layer, and a P column located in the drift layer and on the buffer layer, wherein the bottom of the P column is in contact with the upper edge of the buffer layer, and the top of the P column is not in contact with the lower edge of the P-type region. Through the structural arrangement of the super-junction fast recovery diode, the reverse withstand voltage of the device is greatly improved, the on-state voltage drop is reduced, the reverse recovery performance is enhanced, and the reverse recovery loss is reduced.

The application discloses a semiconductor device and a manufacturing method thereof. The semiconductor device comprises: a substrate semiconductor substrate having a first main surface and a second main surface opposite to the first main surface; an insulated gate bipolar transistor region; a fast recovery diode region; an insulating layer provided with a first contact hole and a second contact hole respectively located in the fast recovery diode region and the insulated gate bipolar transistor region; a first semiconductor region located in the fast recovery diode region; a first titanium film provided in the first contact hole; a second semiconductor region located in the insulated gate bipolar transistor region; a second titanium film provided in the second contact hole; the depth of the first semiconductor region from the first main surface to the semiconductor substrate in a first direction is A, the depth of the second semiconductor region from the first main surface to the semiconductor substrate in the first direction is B, and A and B satisfy the relationship: A <= 0.45B. The technical scheme can improve the reverse recovery performance of the semiconductor device.