Carrier-storing grooved gate IGBT with P-type floating layer

A carrier storage and floating layer technology, applied in the direction of electrical components, circuits, semiconductor devices, etc., can solve the problems of increased forward voltage drop and poor forward conduction characteristics of devices, so as to reduce forward voltage drop, Effect of improving forward conduction characteristics and increasing design margin

Inactive Publication Date: 2010-04-14
UNIV OF ELECTRONIC SCI & TECH OF CHINA
0 Cites 40 Cited by

AI-Extracted Technical Summary

Problems solved by technology

However, due to the introduction of the P-type floating layer, there are two JFET regions "A" and "B", such as Figure 5 As shown, the on-resistance of ...
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Method used

Adopt the novel carrier storage tank gate IGBT structure with P-type floating layer of the present invention, can obtain lower turn-on voltage drop, large forward bias safe operating area (FBSOA) and short circuit safe operating area (SCSOA ), and ca...
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Abstract

The invention relates to a carrier-storing grooved gate IGBT with a P-type floating layer, belonging to the technical field of semiconductor power devices. On a basis of the prior carrier-storing grooved gate bipolar transistor, a P-type floating layer (13) is introduced to almost free a carrier-storing layer from bearing a withstanding voltage and decrease a forward conducted voltage drop; and the P-type floating layer (13) also improves the electric-field integration effect of the bottom of the grooved gate, thereby effectively decreasing an electric filed with a maximum peak value, preventing the bottom of the grooved gate and the vicinity of the high-concentration carrier-storing layer from being broken down by an overhigh electric field and greatly increasing the breakdown voltage of the device. A JFET zone is introduced due to the existence of the P-type floating layer. When the device is forwardly conducted, the resistance of the JFET zone continuously increases along with the continuously increasing voltage of a collector so that the saturation current of the device is decreased, and a lower conducted voltage drop is obtained while maintaining a greater short-circuit safety operation area (SCSOA).

Application Domain

Technology Topic

Image

  • Carrier-storing grooved gate IGBT with P-type floating layer
  • Carrier-storing grooved gate IGBT with P-type floating layer
  • Carrier-storing grooved gate IGBT with P-type floating layer

Examples

  • Experimental program(1)

Example Embodiment

[0037] By adopting the novel carrier storage trench gate IGBT structure with P-type floating layer of the present invention, lower on-voltage drop, large forward bias safe operating area (FBSOA) and short circuit safe operating area (SCSOA) can be obtained, and The breakdown voltage can be further improved, the manufacture is simple, and the design margin is large. With the development of semiconductor technology, more power devices with low voltage drop and high reliability can be produced by using the present invention.
[0038] A carrier storage trench gate IGBT with a P-type floating layer, such as Image 6 shown, each cell includes collector 1, P + Collector region 2, P-type collector region 11, N-type buffer layer 3, N - Base region 4, P-type floating layer 13, gate oxide layer 5, polysilicon gate 6, emitter 7, N + Source Region 9, P + Body region 8 , N-type carrier storage layer 12 . The gate oxide layer 5 and the polysilicon gate 6 form a trench deletion structure, and the trench deletion structure is located in the N - The two sides above the base region 4; the N-type carrier storage layer 12 is surrounded by the trench deletion structure, and is located in the P + body region 8 with the N - Between the base regions 4; the P-type floating layer 13 is located in the N - The upper and both sides of the base region 4 are respectively connected with the oxide layer and N of the lower section of the trench deletion structure. - The base region 4 is connected.
[0039] In the specific implementation, a thin sheet process is used, and the main manufacturing steps are: zone melting N - Preparation of single crystal liner, N-type carrier storage layer injection and push well, P-type base injection and push well, oxidation and photolithography of the Trench window, etched gate Trench, zero-angle injection into the P-type floating layer and Push the well, oxidize the gate and deposit polysilicon, use the oxide layer as a hard mask to reverse the polysilicon, remove the oxide layer covering the source, P + Source Lithography and P + Source injection, N + Source Lithography and N + Source implantation, BPSG deposition, contact hole lithography, metal deposition, complete gate source metallization, backside N-type buffer layer implantation, backside P-type collector region implantation, backside metallization, passivation, etc.
[0040] During the implementation process, certain flexible designs can be made according to the specific situation and the basic structure remains unchanged. For example, the implantation of the P-type base region and the push-well can be placed after the etched gate trench and the P-type floating layer. Manufactured together etc. Semiconductor materials such as silicon carbide, gallium arsenide, indium phosphide or silicon germanium can also be used to replace bulk silicon when fabricating devices.
[0041] With the aid of the two-dimensional simulation software MEDICI simulation tool, the provided carrier storage trench gate IGBT with P-type floating layer (such as Image 6 shown) and conventional trench-gate insulated gate bipolar transistors (such as image 3 shown), conventional carrier storage tank-gate bipolar transistors (such as Figure 4 shown) and trench-gate bipolar transistors with P-type floating layers (such as Figure 5shown) for a simulation comparison. The 1200V trench gate insulated gate bipolar transistor is simulated by simulation. All IGBT collectors in the simulation use the second-generation light punch-through collector structure LPT-II proposed by Mitsubishi (such as Figure 7 shown) and the simulation parameter is P + Dose in collector area 1×1019cm- 3 , the thickness is 2μm; the dose of P-type collector region is 1×10 17 cm- 3 , the thickness is 8 μm; the dose of N-type buffer layer is 1×10 16 cm- 3 , with a thickness of 20 μm; N - Base resistivity 86.5Ω·cm, thickness 100μm; P-type base dose 1×10 17 cm- 3 , junction depth 4μm; N + Dose in emission area 1×10 20 cm- 3 , the junction depth is 1.2 μm; P + Dose in emission area 5×10 19 cm- 3 , the junction depth is 1.3μm; the gate oxide thickness is 60nm. The carrier storage trench gate IGBT with P-type floating layer has a trench gate width of 0.5 μm, a trench gate depth of 10 μm, and a carrier storage layer dose of 5×10 15 ~8×10 16 cm- 3 , the thickness is 5μm, the dose of P-type floating layer is 5×10 17 cm- 3 , junction depth 0.6 ~ 3μm. The trench gate width of the conventional trench gate IGBT is 0.5 μm, and the trench gate depth is 5 μm. The conventional carrier storage trench gate bipolar transistor has a trench gate width of 0.5 μm, a trench gate depth of 5 μm, and a carrier storage layer dose of 1×10 15 cm- 3 , with a thickness of 1 μm. The trench gate bipolar transistor with P-type floating layer has a trench gate width of 0.5 μm, a trench gate depth of 8 μm, and a P-type floating layer dose of 5×10 17 cm- 3 , the junction depth is 1.8 μm. Figure 9 It is a simulation comparison of the breakdown voltage of a carrier storage tank gate IGBT with a P-type floating layer, a conventional trench gate insulated gate bipolar transistor, and a conventional carrier storage tank gate bipolar transistor. As a result, it can be seen from the figure that the breakdown voltage of the conventional carrier storage tank gate bipolar transistor is slightly lower than that of the conventional trench gate type insulated gate bipolar transistor; while the carrier storage tank with the P-type floating layer has a slightly lower breakdown voltage. The gate IGBT achieves a higher breakdown voltage due to the introduction of a floating P-type layer. When the junction depth of the P-type floating layer is 1.8 μm, the breakdown voltage of the novel carrier-storage trench-gate IGBT structure with the P-type floating layer is improved compared with the conventional carrier-storage trench-gate bipolar transistor. Nearly 100V, and as the junction depth of the P-type floating layer increases, the breakdown voltage continues to increase. The provided two-dimensional potential distribution curve of a carrier storage trench gate IGBT with a P-type floating layer (different P-type floating layer junction depths) and a traditional trench gate type insulated gate bipolar transistor is as follows: Figure 10 As shown in (a), it can be seen from the figure that the traditional trench-gate IGBT can withstand the withstand voltage from the depth of the P-type base junction, while the carrier storage trench-gate IGBT with the P-type floating layer can withstand the withstand voltage. The pressure mainly starts from the P-type floating layer. Figure 10 In (b), (c), and (d), the junction depths of the p-type floating layer are 0.6 μm, 1.8 μm and 3 μm, respectively. With the increase of the p-type floating layer, the p-type base junction depth suffers The withstand voltage is reduced, although a thick N-type carrier storage layer with a higher concentration is introduced, but with the protection of the p-type floating layer, the storage layer can hardly withstand the withstand voltage and will not be depleted, so it will not appear too high The peak value of the electric field affects the breakdown voltage. The existence of the P-type floating layer also improves the electric field concentration effect at the bottom of the trench gate, so that the maximum peak electric field is effectively reduced and transferred from the bottom corner of the trench gate to the floating P-type region, thereby greatly increasing the device breakdown voltage. Provided is a novel carrier storage trench gate IGBT structure with a P-type floating layer, a conventional trench-gate insulated gate bipolar transistor, and a trench-gate bipolar transistor with a P-type floating layer in the forward direction. The two-dimensional current distribution curve of the on-time is as follows Figure 11 As shown in the figure, it can be seen from the figure that the traditional trench gate insulated gate bipolar transistor ( Figure 11 (a) A large depletion region appears under the p-type base region (at A) during forward conduction, which limits the current diffusion area and diffusion angle. A trench-gate bipolar transistor with a p-type floating layer ( Figure 11 (b)) the current spreading angle is less than 45 degrees, while the carrier storage trench gate IGBT with P-type floating layer ( Figure 11 The current diffusion angle of (c)) exceeds 45 degrees, and the current diffusion area under the p-type base region is also significantly larger than the other two types of structures. In addition, the trench gate bipolar transistor with P-type floating layer introduces two JEFT regions at the B and C positions, resulting in current concentration and increased voltage drop, while the carrier storage trench gate with P-type floating layer The IGBT has no obvious JFET effect, and the current spreading area is larger and more uniform. Provided are a carrier storage trench gate IGBT with a P-type floating layer (different P-type floating layer junction depths), a conventional trench gate type insulated gate bipolar transistor, and a conventional carrier storage trench gate The forward voltage drop of bipolar transistors and trench-gate bipolar transistors with P-type floating layer under different current densities is as follows: Figure 12 As shown, it can be seen that the trench gate bipolar transistor with the P-type floating layer has the worst forward conduction characteristics due to the influence of the JFET effect, compared with the traditional trench gate insulated gate bipolar transistor and the traditional current carrying Sub-tank gate bipolar transistor, carrier storage tank gate IGBT with P-type floating layer, the forward voltage drop is significantly reduced. With the increase of P-type floating layer, the JFET effect is enhanced, resulting in a certain voltage drop However, when the junction depth is 3 μm, the forward voltage drop is still nearly 16% lower than that of the conventional trench-gate IGBT. Figure 13 is the saturation current curve of the provided novel carrier storage trench gate IGBT structure with P-type floating layer and the traditional trench gate insulated gate bipolar transistor. It can be seen from the figure that with the collector voltage increases, the saturation current of the carrier storage tank gate IGBT with a P-type floating layer and the traditional trench gate insulated gate bipolar transistor are basically the same, and the new type of carrier storage tank with a P-type floating layer. The gate IGBT structure reduces the forward voltage drop without reducing the short-circuit safe operating area (SCSOA).
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

no PUM

Description & Claims & Application Information

We can also present the details of the Description, Claims and Application information to help users get a comprehensive understanding of the technical details of the patent, such as background art, summary of invention, brief description of drawings, description of embodiments, and other original content. On the other hand, users can also determine the specific scope of protection of the technology through the list of claims; as well as understand the changes in the life cycle of the technology with the presentation of the patent timeline. Login to view more.
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Similar technology patents

Groove silicon carbide MPS diode structure and preparation method thereof

Owner:CHINA ZHENHUA GRP YONGGUANG ELECTRONICS CO LTD STATE OWNED NO 873 FACTORY

High withstand voltage and low loss super junction power device

ActiveCN110416294AReduce forward voltage dropHigh forward blocking voltageSemiconductor devicesVoltageSemiconductor
Owner:UNIV OF ELECTRONIC SCI & TECH OF CHINA

Lateral insulated gate bipolar transistor and preparation method thereof

ActiveCN110459596AOptimize carrier distributionReduce forward voltage dropSemiconductor/solid-state device manufacturingSemiconductor devicesCapacitancePower semiconductor device
Owner:UNIV OF ELECTRONIC SCI & TECH OF CHINA

Groove gate type source-leakage composite field plate heterojunction field effect transistor and preparation method thereof

ActiveCN101414623ALarge Drain-Source VoltageImprove breakdown voltageSemiconductor/solid-state device manufacturingSemiconductor devicesHeterojunction field effect transistorComposite field
Owner:XIAN CETC XIDIAN UNIV RADAR TECH COLLABORATIVE INNOVATION INST CO LTD

Classification and recommendation of technical efficacy words

  • Reduce forward voltage drop
  • Improve breakdown voltage

High withstand voltage and low loss super junction power device

ActiveCN110416294AReduce forward voltage dropHigh forward blocking voltageSemiconductor devicesVoltageSemiconductor
Owner:UNIV OF ELECTRONIC SCI & TECH OF CHINA

Lateral insulated gate bipolar transistor and preparation method thereof

ActiveCN110459596AOptimize carrier distributionReduce forward voltage dropSemiconductor/solid-state device manufacturingSemiconductor devicesCapacitancePower semiconductor device
Owner:UNIV OF ELECTRONIC SCI & TECH OF CHINA

Groove silicon carbide MPS diode structure and preparation method thereof

Owner:CHINA ZHENHUA GRP YONGGUANG ELECTRONICS CO LTD STATE OWNED NO 873 FACTORY
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products