196 results about "Safe operating area" patented technology

The invention discloses a switching loss evaluation method and system based on a semi-soft switching modulation technology, and relates to the technical field of information. According to the method, parasitic inductance parameters and buffer capacitance parameters of a device are obtained, a resonant circuit working model is established, an initial voltage waveform and an initial current waveform are obtained by solving the model, and corresponding voltage stress and current stress are calculated; a parasitic inductance parameter and a buffer capacitance parameter of the device are optimized by using a genetic algorithm; adjusting the design of the buffer circuit according to the optimized device parameters, carrying out the simulation of the resonance process again, carrying out the frequency domain analysis of the optimized resonance voltage waveform and resonance current waveform, and optimizing the device parameters and the design of the buffer circuit. And finally, semi-soft switching modulation simulation is carried out, a temperature coefficient mapping relation between simulation switching loss and actually measured switching loss is constructed, an optimal design scheme of the device is determined, the switching loss of the device is effectively reduced, and it is ensured that the device works in a safe working area.

The invention discloses a super junction semiconductor device and a manufacturing method, and belongs to the technical field of semiconductors. The super junction semiconductor device comprises a cellular region, a transition region and a terminal region, and the transition region is located between the cellular region and the terminal region. A first conductive type semiconductor substrate and a first conductive type buffer layer located above the first conductive type semiconductor substrate are arranged at the bottoms of the cellular region, the transition region and the terminal region; the first conduction type multi-time epitaxial layer is positioned above the first conduction type buffer layer; the second conduction type longitudinal strip-shaped region is positioned in the first conduction type multi-time epitaxial layer; and the height of the second conduction type longitudinal strip-shaped region in the terminal region and the transition region is greater than that of the cellular region in the longitudinal direction. When avalanche breakdown occurs, a breakdown point is transferred to a cellular region, the EAS performance of the device is improved, the sensitivity of charge balance in a terminal region is reduced, and the reliability of the device is improved; the reverse voltage withstanding characteristic of the super junction device is optimized, and the safe working area of the device is improved.

The invention discloses a power semiconductor device and a manufacturing method thereof. The device comprises a first base region, a second base region, a field stop region, a plasma storage region and a bottom doped region which are sequentially arranged from top to bottom, wherein a top P region and a terminal field limiting ring are arranged in the first base region. Wherein the first base region is used for optimizing the terminal structure; the second base region is used for improving a self-clamping function and adjusting power consumption and static breakdown voltage; the field termination region is used for terminating an electric field and suppressing current and voltage oscillation; the plasma storage area is used for expanding the safe working area and improving the self-clamping function. By optimizing and compromising the structural parameters of each area, the device can achieve the beneficial effects of self-clamping, low loss, wide safe working area and small terminal size.

The invention relates to a liquid hydrogen superconducting energy storage configuration system and method considering multi-mode safe operation. The system comprises a superconducting energy storage application scene demand module, a superconducting strip performance parameter module, a superconducting magnet structure economic configuration optimization module, a superconducting magnet'electricity-magnetism-heat 'multi-physics field simulation modeling module and a superconducting magnet dynamic safe working area module which are in synergistic effect. According to the method, the minimum energy storage capacity and the maximum magnetic field intensity threshold value are determined according to the superconducting energy storage application scene requirement, the genetic algorithm is adopted to conduct strip use amount minimum parameter optimization on magnet structure parameters, and an electricity-magnetism-heat multi-physics field coupling simulation model is established to quantify the liquid hydrogen cooling requirement. And finally, constructing a dynamic safe working area with the maximum allowable temperature to realize closed-loop control. Compared with the prior art, the multi-mode operation safety of the superconducting energy storage system can be guaranteed, meanwhile, the using amount of superconducting strips and the liquid hydrogen cooling capacity are reduced, and the economic efficiency of the system is improved.

The embodiment of the invention provides a method, a device and a system for compensating anode voltage and output power of a magnetron, and belongs to the technical field of radiators for microwave heating. The method comprises the following steps: acquiring a current temperature and an anode voltage measurement value of a magnetron; calculating a correction voltage according to the current temperature; determining a temperature change rate according to the correction voltage and / or the anode voltage measurement value; performing PID control on the PWM signal of the magnetron according to the temperature change rate and the target voltage value; judging whether the current temperature is within a safe working interval or not; acquiring a current anode voltage value when the current temperature is out of the safe working interval; calculating theoretical output power according to the anode voltage value; calculating a power difference value between the theoretical output power and the actual output power; judging whether the power difference value is greater than or equal to a difference value threshold value; and calculating a target voltage value according to the theoretical output power and the input power under the condition that the difference value is greater than or equal to the difference threshold value.

Systems and methods for transistor protection for battery packs are disclosed. In one aspect, transistors are turned on and off at a duty cycle selected to keep the transistor in a safe operating area (SOA). Such SOAs are generally defined by voltage, current, and time, so by keeping the time limited, high currents or voltages may be better tolerated. In specifically contemplated aspects, a control circuit alternately activates and deactivates driver transistors to toggle a discharge pin, thereby setting the duty cycle.

Disclosed structures include a single-stage and a multi-stage voltage level shifter. Each structure includes multiple transistors, which are optionally all symmetric low-voltage transistors, and the structures are configured to avoid operation outside the safe operating area (SOA) of such transistors. The single-stage voltage level shifter and the first stage of the multi-stage voltage level shifter can be essentially identical. In operation, input voltage pulses (including an input voltage pulse transitioning between a first positive voltage (V1) equal to the voltage rating of the transistors and ground) can be received at source nodes of N-type transistors and, in response, output voltage pulses (including an intermediate output voltage pulse transitioning between V1 and a second positive voltage (V2) that is higher than (e.g., double) V1 and an output voltage pulse that transitions between ground and V2) can be output.

The invention relates to the field of semiconductors, and provides an extended drain MOS (Metal Oxide Semiconductor) device, a manufacturing method and a chip. The extended drain MOS device comprises a substrate, a P-type well region, an N-type deep well region, shallow trench isolation regions, a source region, a drain region and a grid electrode, the shallow trench isolation regions comprise a first shallow trench isolation region, a second shallow trench isolation region and a third shallow trench isolation region, the first shallow trench isolation region is located between the grid electrode and the drain region, the second shallow trench isolation region is located between the drain region and a substrate interface, and the third shallow trench isolation region is located between the source region and the drain region. The third shallow slot isolation region is located between the source region and the substrate interface; the N-type deep well region is located below the first shallow trench isolation region and the drain region, a second P-type well region is arranged in the N-type deep well region, and the second P-type well region is longitudinally connected with the first shallow trench isolation region. The N-type deep well region internally provided with the P-type well region is used as a drift region structure, the breakdown voltage and the safe working region of the device are improved, the manufacturing method of the device is completely compatible with the CMOS technology, and the manufacturing cost is reduced.

The invention discloses a detection method, equipment and medium for a new energy high-power direct-current charging pile, and relates to the technical field of charging pile stability detection, and the method comprises the steps: controlling a direct-current electronic load to generate a load disturbance signal at N characteristic working points, collecting instantaneous value change data through a broadband data collection center, and calculating the stability of the charging pile according to the instantaneous value change data; and based on the dynamic load disturbance signal and the instantaneous value change data, calculating the pulse response characteristics of the to-be-tested DC charging pile at the N characteristic working points through a correlation function analysis method, constructing a dynamic impedance characteristic model, and based on the safe working area three-dimensional boundary map, the electric energy quality indexes of the N characteristic working points and the dynamic impedance characteristic model, calculating the dynamic impedance characteristic of the to-be-tested DC charging pile. And evaluating and diagnosing the comprehensive performance of the direct current charging pile to be tested. According to the direct current charging pile comprehensive performance detection method based on dynamic load disturbance, accurate physical examination of the overall performance of the charging pile is achieved, and the detection depth, precision and predictability are improved.

The invention provides a semiconductor power device with a wide safe operation area and a preparation method thereof, and the device comprises a first groove and a second groove which are respectively formed in different areas of an epitaxial layer; a source polysilicon layer is formed at the bottom of the trench, a third isolation layer, a second isolation layer and a first isolation layer are sequentially formed on the outer side of the source polysilicon layer, an isolation oxide layer and a gate polysilicon layer are sequentially formed on the source polysilicon layer, and a gate oxide layer is formed on the outer side of the gate polysilicon layer; the thickness of the first isolation oxide layer is greater than that of the second isolation oxide layer, and the thickness of the first gate oxide layer is greater than that of the second gate oxide layer. The method has the beneficial effects that the isolation oxide layers with different thicknesses are formed in the device active region division regions, so that the gate-drain capacitance is reduced, and the device switching frequency is improved; meanwhile, the gate oxide layer adopts a single layer to realize different thicknesses in different areas, so that the threshold voltages of the cells in different areas are different, and the safe working area of the power device is widened; and a good compromise between the forward conduction capability and the reverse recovery capability is realized.

The invention discloses a safe working area calculation method, device and system of an MOSFET and a storage medium, and relates to the technical field of semiconductors. The method comprises the following steps: acquiring MOSFET temperature sensitive parameters; obtaining a relation curve between the MOSFET temperature sensitive parameter and the MOSFET junction temperature; acquiring transient thermal impedance of the MOSFET under different duty ratios and different pulse widths; calculating the maximum allowable power loss of the MOSFET under different pulse widths of the single pulse; calculating a safe working area SOA curve coordinate of the MOSFET; and automatically calculating, drawing, storing and outputting a safe working area SOA diagram of the MOSFET on the basis of Qt Widgets. According to the SOA calculation method for the safe working area of the MOSFET, the thermal performance and the electrical performance of the MOSFET are comprehensively considered, the safe working area of the MOSFET is determined through a series of experiments and calculation steps, and the accuracy of a calculation result is improved.

The invention discloses an FCE diode and a manufacturing method thereof. The cathode metal is provided with a trench isolation region, cathode N + regions and cathode P + regions, the cathode N + regions and the cathode P + regions are transversely and alternately arranged, the trench isolation region isolates the cathode N + regions from the cathode P + regions, and the thickness of the trench isolation region exceeds 2 microns of the cathode N + regions and the cathode P + regions And then a plasma storage region, a field stop region, a base region, an anode P region and anode metal are sequentially arranged. The thickened trench isolation region is indispensable for improving the current density uniformity near the cathode, and can weaken low-frequency oscillation and reduce conduction voltage drop; the thickened plasma storage region can weaken low-frequency oscillation, improve the current density uniformity near the anode and reduce reverse recovery energy under severe or extreme conditions; the two measures can also ensure that the base region is greatly thinned on the premise of enlarging the safe working region, so that the loss is reduced. By optimizing and compromising the structural parameters of each area, the FCE diode can achieve the beneficial effects of self-clamping, low loss, uniform current density, no high-frequency oscillation, slight low-frequency oscillation and wide safe working area.

The invention discloses a preparation method of a semiconductor power device, and belongs to the technical field of semiconductors. Comprising the steps that an epitaxial layer and a barrier layer are sequentially arranged on a substrate layer, a groove is formed through photoetching, and a heavily-doped polycrystalline silicon layer is deposited in the groove through thermal oxidation; performing wet etching on the side wall of the groove, and performing thermal oxidation to form a gate oxide layer; the method comprises the following steps of: depositing a heavily doped polycrystalline silicon layer in a groove; performing ion implantation on the epitaxial layer in sequence; an insulating medium layer is formed above the grid polycrystalline silicon and the first isolation layer, a plurality of contact holes are etched inwards, and the distance between each contact hole and the corresponding groove is linearly increased; injecting ions into the bottom of the contact hole, and filling a metal filling layer; arranging a back drain metal layer on the back of the substrate layer; and mirroring and repeating. The manufacturing method has the beneficial effects that the basic unit cells are mirrored and repeated, so that the distance between the grooves and the contact holes is linearly increased, the heating uniformity of the device is improved, the heat dissipation capability is improved, and the safe working area of the device is widened.

To provide a test method for a device under test which is a switching element.SOLUTION: A test method for a device under test includes the steps of: applying a gate voltage of a predetermined first pulse to the device under test; measuring a turn-off loss of the device under test on the basis of a collector current during a rise time thereof, the collector current flowing through the device under test according to the first pulse; and measuring a reverse bias safe operation area of the device under test on the basis of the collector current during a fall time of the collector current according to the first pulse.SELECTED DRAWING: Figure 3

The invention relates to a control device (10, 110) for controlling an electric three-phase machine (12), in particular a steering system (14), comprising at least one reverse polarity protection switch (18, 118) arranged in a power current path (16, 116), at least one driver circuit (22, 122) electrically connected to a control terminal (20, 120) of the reverse polarity protection switch (18, 118) for providing a control voltage for the reverse polarity protection switch (18, 118), and at least one protection circuit (24, 124), wherein the reverse polarity protection switch (18, 118) is provided to absorb at least a large part of the power occurring in a reverse polarity situation, and the protection circuit (24, 124) is provided to adjust the control voltage in the reverse polarity situation such that a voltage drop across the reverse polarity protection switch (18, 118) is limited and the reverse polarity protection switch (18, 118) is protected from damage. 118) is kept in his safe working area. It is proposed that the control device (10, 110) includes a safety circuit (60, 160) which is arranged circuit-wise between the protection circuit (24, 124) and the reverse polarity protection switch (18, 118) and which includes at least one safety switch (62, 162) which is intended to connect the protection circuit (24, 124) to the reverse polarity protection switch (18, 118) in a first switching state and to disconnect it from the reverse polarity protection switch (18, 118) in a second switching state.

The invention provides a crimping type IGBT module accelerated life test device, a related method and a system. The device comprises a press fitting mechanism used for press fitting of a tested IGBT module, a temperature control device arranged on the surface of the tested IGBT module, a cosmic ray irradiation source perpendicular to the plane of the tested IGBT module, and a voltage loading module electrically connected with the tested IGBT module. According to the device, the temperature control device, the voltage loading module and the cosmic ray irradiation source are combined to generate load stress, so that the test process can be accelerated, the IGBT device is easier to fail, and the service life of the device is easier to obtain; according to the test result, the IGBT failure rate characteristic under the special environment factor of the high altitude area and the safe working area under the allowable failure rate can be obtained; meanwhile, the temperature is adjusted through the externally arranged temperature control device, so that the temperature control is more flexible and flexible, the temperature fluctuation is more stable, and the accuracy of the test result is improved.

A power circuit includes a power transistor coupled between input and output nodes and receiving a control signal. A current sensing current senses a power current provided by the power transistor to the output node and generates a sense voltage. A voltage sensing circuit senses a drain-to-source voltage of the power transistor and generates a VDS sense current. A safe operating area (SOA) shaping circuit has a gain set by an adjustable resistance that is dynamically adjusted based upon the VDS sense current, the SOA shaping circuit applying the gain to the sense voltage to produce an adjusted sense voltage. A timing circuit generates an intermediate voltage by comparing the adjusted sense voltage and a first reference. An output comparator asserts a flag in response to the intermediate voltage becoming at least equal to a second reference. The control signal is modified in response to assertion of the flag.

An integrated circuit comprising an n-type drift region, a gate structure directly on a first portion of the n-type drift region, a drain structure formed in a second portion of the n-type drift region, the gate structure and the drain structure being separated by a drift region length, a resist protective oxide (RPO) formed over a portion of the n-type drift region between the gate structure and the drain structure, a field plate contact providing a direct electrical connection to the resist protective oxide.

The invention belongs to the technical field of power semiconductor devices, and relates to a super-junction IGBT device with a split gate structure and a preparation method of the super-junction IGBT device. The device comprises collector metal, a P-type collector, an N-type field stop layer, a super junction N column, a super junction P column, a P-type buried layer, a trench gate structure and a trench emitter structure which are sequentially stacked from bottom to top, and the trench gate structure and the trench emitter structure are connected with an N-type charge storage layer, a P-type base region and an N + emitter region. The P columns / N columns of the device are alternately arranged in the Y direction, the cell width is reduced, meanwhile, the parasitic PMOS introduced by only adding one photoetching plate acts, and the device has high channel density and a wide short-circuit safe working area. In addition, the Miller capacitance of the super-junction IGBT is reduced, the negative gate capacitance effect is suppressed, the surge current of the device is reduced, and the control capability of the gate of the device on dv / dt is improved. According to the invention, an extra path is provided for redundant holes stored in the drift region, the turn-off speed of the device is obviously improved, and the switching loss is reduced.

The application belongs to the technical field of digital signal processing, and particularly discloses a digital signal generation and processing method and system for synchronous rectification, wherein the method comprises the following steps: obtaining the staggered sampling code stream of a synchronous rectification device, and outputting time-aligned voltage and current characteristic values after group delay hard compensation; performing polynomial thermodynamic school correction in combination with discrete shell temperature sampling values; performing physical safety working area boundary checking on the corrected characteristic values, addressing and interpolating output of the target optimal conduction timing value in the irregular lattice space; extracting a feature vector to perform recursive least square prediction, and outputting an overshoot prediction extreme value; performing discrete charge integration in combination with a nonlinear capacitance function, and iteratively outputting a target dead time value based on the charge conservation criterion; and the application has the advantages of accurate control timing, physical boundary safety and dead time self-adaptation.

The application provides a single-point detection device and method for a safe working area of a power MOSFET, and relates to the technical field of semiconductor device testing. The single-point detection device comprises a pulse trigger circuit, a sampling feedback circuit, a driving amplification circuit, a capacitor energy storage circuit and a data collector. The pulse trigger circuit is used for outputting a pulse signal with a preset width according to a conduction time corresponding to a specific test point. The sampling feedback circuit is used for collecting a drain current of the power MOSFET and generating a feedback signal. The driving amplification circuit drives the power MOSFET to be turned on or turned off according to the feedback signal and the pulse signal. The capacitor energy storage circuit provides a target drain-source voltage for the power MOSFET according to a drain-source voltage corresponding to the specific test point. The data collector records waveforms of the drain-source voltage and the drain current of the power MOSFET. The single-point detection device does not need to increase an additional circuit, parameter matching is realized by adjusting devices in the single-point detection device, the test efficiency is improved, and the single-point detection device has the advantages of high efficiency, flexibility, high precision and the like.

The invention provides a power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) wide SOA (Silicon On Architecture) structure preparation process and a chip, a well region is arranged among a plurality of first grooves, a first injection region is arranged in the well region, and a plurality of second injection regions are correspondingly arranged below a part of the well region, so that an MOSFET device with a wider safe working region can be realized; moreover, a proper threshold voltage value is obtained, the overcurrent capability of the SOA can be improved by nearly 2-3 times, and the thermal stability is synchronously reduced.

The embodiment of the invention relates to a protection circuit, a corresponding system and a method. A circuit for protecting a power transistor driven by a driver circuit at a drive electrode wherein the circuit for protection comprises safe operating area monitoring circuitry configured to control operation of the transistor for its safe operating area, the safe operation area monitoring circuitry receives as an input at least a current value proportional to the current flowing through the power transistor, and controls operation of the power transistor for the safe operation area according to the transistor thermal behavior information and at least the current value proportional to the current flowing through the power transistor, the driver circuit is coupled to the transistor to control a value of a junction temperature of the transistor and to output an output signal that controls on and off states of the driver circuit by driving a switch of the power transistor to obtain a given behavior of the junction temperature of the transistor over time within a safe operating region.

The utility model discloses a negative voltage protection circuit, which comprises a negative voltage protection module used for being electrically connected with an input end, and when backward voltage appears in the circuit, the negative voltage protection circuit responds quickly, clamps the backward voltage in a safe working area range of a device and discharges the backward voltage to the ground; the current limiting module is used for limiting the maximum current within a certain threshold value and preventing surge current from causing abnormity of a driving power supply part; the totem pole output and secondary release module is used for driving a driven device and is also used for releasing charges generated on a circuit so as to prevent product damage caused by slow release speed of the circuit; and the forward protection module is used for preventing the device from being damaged when the product is protected and the state is rapidly switched, and ensuring that the device runs in a normal working range. The negative voltage protection circuit does not need an MCU module to detect the input voltage, and the system reliability is improved. And the current-limiting resistor is connected in series with the driving input end, so that surge current is prevented, and the stability of the system is improved.

Semiconductor switches for high voltage operations are described. The semiconductor switch includes a first DE-NMOS FET including a gate coupled to a node of the switch with its source and drain coupled to input and output nodes, respectively. The switch also includes a second DE-NMOS FET with a drain coupled to the node. A gate of the second DE-NMOS FET is configured to receive a signal enabling or disabling the switch. The switch includes a voltage source (e.g., a voltage-controlled voltage source) coupled to the node, which supplies a first voltage at the node. The first voltage is greater than a second voltage at the input node by a predetermined amount such that the first DE-NMOS FET may operate within a safe operating area while supporting high voltage operations. The switch also includes a current source configured to supply current to the voltage source.

The invention provides a semiconductor device. The semiconductor device comprises a substrate; the doped region is positioned in the substrate; and the embedded structure extends downwards from the upper surface of the substrate and at least comprises a contact metal, the contact metal is in contact with the doped region, and the contact metal is configured as an electrode end of the semiconductor device. The doped region is configured as a drain region of the semiconductor device, and the embedded structure is used for improving the withstand voltage of the semiconductor device; when the doped region is configured as a source region of the semiconductor device, the embedded structure is used for improving a safe working region of the semiconductor device.

The disclosed structures include single-stage and multi-stage voltage level shifters. In one embodiment, each structure includes a plurality of transistors, optionally all of which are symmetric low voltage transistors, and the structures are configured to avoid operation outside a safe operating area (SOA) of such transistors. The first stages of the single-stage voltage level shifter and the multi-stage voltage level shifter may be substantially the same. In operation, an input voltage pulse (including an input voltage pulse transitioning between a first positive voltage (V1) equal to a transistor nominal voltage and ground) may be received at a source node of the N-type transistor, and in response, an output voltage pulse (including at V1 and above V1 (e.g., a first positive voltage (V3)) may be received at the source node of the N-type transistor. An intermediate output voltage pulse converted between a second positive voltage (V2), which is twice of V1), and an output voltage pulse converted between ground and V2 may be output.

The application belongs to the technical field of safety evaluation, and specifically discloses a kind of high-frequency operation dynamic safety work area evaluation method, device and equipment. According to the temperature characteristics and degradation information, the second current change rate and the second voltage change rate of SiC MOSFET device under the driving protection circuit are determined respectively through the application. After calculating the target current change rate combined with the first current change rate, and calculating the target voltage change rate combined with the first voltage change rate, the high-frequency operation dynamic safety work area of SiC MOSFET device is evaluated respectively. Through the above-mentioned mode, the root cause of the secondary problem of SiC MOSFET device switching transient is considered, the current change rate and the voltage change rate are selected to represent the switching rate, and the voltage and current overshoot and oscillation of the switching transient are effectively evaluated, and the safety work area is evaluated combined with the temperature characteristics and degradation information, so as to effectively improve the accuracy of evaluating the high-frequency operation dynamic safety work area.

The driving circuit generates a first control signal and a second control signal and outputs the first control signal and the second control signal to respective control electrodes of the first power semiconductor element and the second power semiconductor element which are connected in parallel. The range of the safe operation area of the first power semiconductor element is larger than the range of the safe operation area of the second power semiconductor element. The driving circuit comprises a time delay circuit, a control logic circuit and a buffer. The time delay circuit compares a voltage level of the second control signal with a first reference voltage or compares a drain-source voltage of the first power semiconductor element with a second reference voltage, and generates a first voltage according to a comparison result. The first and second reference voltages are associated with temperatures of the first and second power semiconductor elements. The control logic circuit generates a logic signal according to the first voltage. The buffer generates a first or second control signal according to a logic signal. According to the invention, a relatively large range of a safe working area can be realized.

The present techniques relate to mitigating droop conditions in systems having dynamic voltage and frequency scaling and there is disclosed a method of controlling a dynamic voltage and frequency scaling circuit, comprising: detecting a voltage droop relative to a current nominal voltage and frequency state; responsive to said current nominal voltage and frequency state having a corresponding fallback state in a safe operating zone of voltage and frequency, switching activity from a nominal source to a fallback source; and when a fallback to a safe operating zone is unavailable for said current nominal voltage and frequency state, pausing activity of the dynamic voltage and frequency scaling circuit.