77 results about "Safe operating area" patented technology

The invention discloses a detection method, equipment and medium for a new energy high-power direct-current charging pile, and relates to the technical field of charging pile stability detection, and the method comprises the steps: controlling a direct-current electronic load to generate a load disturbance signal at N characteristic working points, collecting instantaneous value change data through a broadband data collection center, and calculating the stability of the charging pile according to the instantaneous value change data; and based on the dynamic load disturbance signal and the instantaneous value change data, calculating the pulse response characteristics of the to-be-tested DC charging pile at the N characteristic working points through a correlation function analysis method, constructing a dynamic impedance characteristic model, and based on the safe working area three-dimensional boundary map, the electric energy quality indexes of the N characteristic working points and the dynamic impedance characteristic model, calculating the dynamic impedance characteristic of the to-be-tested DC charging pile. And evaluating and diagnosing the comprehensive performance of the direct current charging pile to be tested. According to the direct current charging pile comprehensive performance detection method based on dynamic load disturbance, accurate physical examination of the overall performance of the charging pile is achieved, and the detection depth, precision and predictability are improved.

The invention discloses an FCE diode and a manufacturing method thereof. The cathode metal is provided with a trench isolation region, cathode N + regions and cathode P + regions, the cathode N + regions and the cathode P + regions are transversely and alternately arranged, the trench isolation region isolates the cathode N + regions from the cathode P + regions, and the thickness of the trench isolation region exceeds 2 microns of the cathode N + regions and the cathode P + regions And then a plasma storage region, a field stop region, a base region, an anode P region and anode metal are sequentially arranged. The thickened trench isolation region is indispensable for improving the current density uniformity near the cathode, and can weaken low-frequency oscillation and reduce conduction voltage drop; the thickened plasma storage region can weaken low-frequency oscillation, improve the current density uniformity near the anode and reduce reverse recovery energy under severe or extreme conditions; the two measures can also ensure that the base region is greatly thinned on the premise of enlarging the safe working region, so that the loss is reduced. By optimizing and compromising the structural parameters of each area, the FCE diode can achieve the beneficial effects of self-clamping, low loss, uniform current density, no high-frequency oscillation, slight low-frequency oscillation and wide safe working area.

The application belongs to the technical field of digital signal processing, and particularly discloses a digital signal generation and processing method and system for synchronous rectification, wherein the method comprises the following steps: obtaining the staggered sampling code stream of a synchronous rectification device, and outputting time-aligned voltage and current characteristic values after group delay hard compensation; performing polynomial thermodynamic school correction in combination with discrete shell temperature sampling values; performing physical safety working area boundary checking on the corrected characteristic values, addressing and interpolating output of the target optimal conduction timing value in the irregular lattice space; extracting a feature vector to perform recursive least square prediction, and outputting an overshoot prediction extreme value; performing discrete charge integration in combination with a nonlinear capacitance function, and iteratively outputting a target dead time value based on the charge conservation criterion; and the application has the advantages of accurate control timing, physical boundary safety and dead time self-adaptation.

The application provides a single-point detection device and method for a safe working area of a power MOSFET, and relates to the technical field of semiconductor device testing. The single-point detection device comprises a pulse trigger circuit, a sampling feedback circuit, a driving amplification circuit, a capacitor energy storage circuit and a data collector. The pulse trigger circuit is used for outputting a pulse signal with a preset width according to a conduction time corresponding to a specific test point. The sampling feedback circuit is used for collecting a drain current of the power MOSFET and generating a feedback signal. The driving amplification circuit drives the power MOSFET to be turned on or turned off according to the feedback signal and the pulse signal. The capacitor energy storage circuit provides a target drain-source voltage for the power MOSFET according to a drain-source voltage corresponding to the specific test point. The data collector records waveforms of the drain-source voltage and the drain current of the power MOSFET. The single-point detection device does not need to increase an additional circuit, parameter matching is realized by adjusting devices in the single-point detection device, the test efficiency is improved, and the single-point detection device has the advantages of high efficiency, flexibility, high precision and the like.

The invention provides a power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) wide SOA (Silicon On Architecture) structure preparation process and a chip, a well region is arranged among a plurality of first grooves, a first injection region is arranged in the well region, and a plurality of second injection regions are correspondingly arranged below a part of the well region, so that an MOSFET device with a wider safe working region can be realized; moreover, a proper threshold voltage value is obtained, the overcurrent capability of the SOA can be improved by nearly 2-3 times, and the thermal stability is synchronously reduced.

The embodiment of the invention relates to a protection circuit, a corresponding system and a method. A circuit for protecting a power transistor driven by a driver circuit at a drive electrode wherein the circuit for protection comprises safe operating area monitoring circuitry configured to control operation of the transistor for its safe operating area, the safe operation area monitoring circuitry receives as an input at least a current value proportional to the current flowing through the power transistor, and controls operation of the power transistor for the safe operation area according to the transistor thermal behavior information and at least the current value proportional to the current flowing through the power transistor, the driver circuit is coupled to the transistor to control a value of a junction temperature of the transistor and to output an output signal that controls on and off states of the driver circuit by driving a switch of the power transistor to obtain a given behavior of the junction temperature of the transistor over time within a safe operating region.

The invention provides a semiconductor device. The semiconductor device comprises a substrate; the doped region is positioned in the substrate; and the embedded structure extends downwards from the upper surface of the substrate and at least comprises a contact metal, the contact metal is in contact with the doped region, and the contact metal is configured as an electrode end of the semiconductor device. The doped region is configured as a drain region of the semiconductor device, and the embedded structure is used for improving the withstand voltage of the semiconductor device; when the doped region is configured as a source region of the semiconductor device, the embedded structure is used for improving a safe working region of the semiconductor device.

The application belongs to the technical field of safety evaluation, and specifically discloses a kind of high-frequency operation dynamic safety work area evaluation method, device and equipment. According to the temperature characteristics and degradation information, the second current change rate and the second voltage change rate of SiC MOSFET device under the driving protection circuit are determined respectively through the application. After calculating the target current change rate combined with the first current change rate, and calculating the target voltage change rate combined with the first voltage change rate, the high-frequency operation dynamic safety work area of SiC MOSFET device is evaluated respectively. Through the above-mentioned mode, the root cause of the secondary problem of SiC MOSFET device switching transient is considered, the current change rate and the voltage change rate are selected to represent the switching rate, and the voltage and current overshoot and oscillation of the switching transient are effectively evaluated, and the safety work area is evaluated combined with the temperature characteristics and degradation information, so as to effectively improve the accuracy of evaluating the high-frequency operation dynamic safety work area.

The driving circuit generates a first control signal and a second control signal and outputs the first control signal and the second control signal to respective control electrodes of the first power semiconductor element and the second power semiconductor element which are connected in parallel. The range of the safe operation area of the first power semiconductor element is larger than the range of the safe operation area of the second power semiconductor element. The driving circuit comprises a time delay circuit, a control logic circuit and a buffer. The time delay circuit compares a voltage level of the second control signal with a first reference voltage or compares a drain-source voltage of the first power semiconductor element with a second reference voltage, and generates a first voltage according to a comparison result. The first and second reference voltages are associated with temperatures of the first and second power semiconductor elements. The control logic circuit generates a logic signal according to the first voltage. The buffer generates a first or second control signal according to a logic signal. According to the invention, a relatively large range of a safe working area can be realized.

The application provides a medium-high voltage shield gate power device layout and device. By optimizing a gate contact hole connection mode, the first grooves where the gate contact hole areas are located are arranged at intervals, that is, gate polysilicon interval connection gate contact holes. The safety operating area (SOA) performance of the application can be improved by several times. The first grooves where the gate contact hole areas are located can be selected to be separated by several first grooves according to the required safety operating area (SOA) performance. In addition, a mask plate does not need to be increased, and there is a certain advantage in cost.

The invention relates to the technical field of IGBT (Insulated Gate Bipolar Translator) structures, and discloses a soft-recoverable IGBT structure, which comprises an MOS (Metal Oxide Semiconductor) gate structure positioned on the front surface of a device, a diode anode structure, an n drift layer for bearing the withstand voltage of the device, and a field stop layer positioned below the n drift layer and used for optimizing an internal electric field of the device, a gradually-doped n-type adjusting layer, an IGBT part, a diode part, a p-type collector region and an n-type cathode region are arranged between the n drift layer and the field stop layer, the IGBT part and the diode part are arranged in anti-parallel, the p-type collector region is located on the back surface of the device and serves as the IGBT part, and the n-type cathode region is located on the back surface of the device and serves as the diode part. By introducing the n-type adjusting layer, excellent soft recovery characteristic and dynamic robustness are realized, low overall loss is maintained, and the device has strong recovery capability under extreme conditions (high VCC, high forward current and high temperature). And the tradeoff and tradeoff triangular relationship limitation among the traditional total loss, reverse recovery softness and diode (FWD) recovery safety working area is broken through.

A motor drive circuit comprising: a motor bridge, comprising a bridge arm comprising upper and lower switches for each motor phase, which may be selectively closed to modulate voltage applied to the respective phases to drive signals from a motor control circuit, at least one solid-state-phase-isolation-relay (SSPIR) provided in series in an electrical path connecting a respective phase of the motor to a respective bridge arm, the SSPIR being closed in normal operation so that current can flow in the phase and held open in a fault mode of operation to prevent current flow, a monitoring arrangement for monitoring a current waveform in the phase to identify when it is safe to open the SSPIR without causing damage to the SSPIR due to an avalanche mode, and a control circuit that applies a voltage to each SSPIR that is sufficient to hold the SSPIR closed in normal operation is only opened when the current is in a safe operational area.

The invention discloses an IGBT (Insulated Gate Bipolar Translator) driving control method based on secondary side hardware protection and active clamping, which comprises the following specific steps of: establishing an IGBT digital twin model, and updating junction temperature distribution, saturation voltage drop and theoretical boundaries of a dynamic safe working area under different working conditions in real time through model simulation; in the normal switching process of the IGBT, voltage waveforms and current change rate waveforms in the switching-on and switching-off stages of the IGBT are collected in real time, key parameters are identified, and meanwhile self-adaptive correction is carried out; according to the invention, the conversion from passive protection to active prediction can be realized, the accuracy of protection criteria is greatly improved, the voltage stress and loss of a device are remarkably reduced, false triggering and misjudgment are reduced, the self-diagnosis capability and response speed of a system are improved, the time precision and coordination of protection decisions are ensured, and the reliability of the system is improved. Thermal fatigue and breakdown risks caused by overstress are reduced, so that the service life of the device is prolonged, and the overall reliability and operation efficiency of the power module are improved.

The invention discloses a converter transient voltage active support method based on a protection demand, and belongs to the technical field of power electronics, and the method comprises the steps: obtaining an instantaneous electric stress parameter of a converter, and obtaining a real-time thermal stress state in combination with a thermal response relation of a power semiconductor device; fusing the electric stress parameter and the thermal stress state, and combining the characteristic data of the safe working area to generate a dynamic safe working boundary; meanwhile, transient information of the power grid is detected, and an ideal transient supporting instruction is generated according to the supporting guide rule; and according to the boundary, constraining and reconstructing the instruction, and generating an adaptive transient support instruction by intelligently adjusting the amplitude or change rate of the instruction. According to the method, the electric thermal stress state of the power semiconductor device is sensed in real time to dynamically generate the safe working boundary, intelligent constraint and reconstruction are carried out on the ideal supporting instruction following the power grid guide rule according to the boundary, and the operation safety and reliability of equipment can be ensured while the transient supporting capacity of the converter can be exerted to the maximum extent.

According to the shield gate trench MOSFET device and the preparation method thereof provided by the invention, the first contact hole and the second contact hole with different densities are manufactured in the interlayer dielectric layer of the cellular region, and the distribution density of the first contact hole is low, so that the ion concentration of the channel region of the cell where the first contact hole is located is low, and the threshold voltage is also low; the distribution density of the second contact holes is high, the channel ion concentration of the cells where the second contact holes are located is high, and the threshold voltage is also high, so that when the MOS device works, the cells with low threshold voltage are firstly started to conduct electricity, the cells with high threshold voltage are then started, the later started cells can serve as heat dissipation channels through the time-sharing starting mechanism, heat is dissipated for the cells started firstly, and the heat dissipation efficiency of the MOS device is improved. According to the preparation method, only the layout design of the contact hole mask needs to be adjusted, additional process steps do not need to be added, the reliability of the MOS device is improved, and the application range of the MOS device is widened with extremely low cost.

A switch circuit has a transistor switch (305, 353, 401, 451, 501) and a first MOS transistor (T1, T3, 505), both of a first type, and a second MOS transistor (T2, T4, 517) of a second type that is complementary to the first type, wherein the first type is an NFET or a PFET. The transistor switch (305, 353, 401, 451, 501) has a source (311, 355, 515), a drain (309, 359, 516), and a gate (503), wherein the gate (503) is connected to a first control signal (307, 403, 453, 503) having at least a first voltage state for turning the transistor switch (305, 353, 401, 451, 501) on and a second voltage state for turning the transistor switch (305, 353, 401, 451, 501) off. The first MOS transistor (T1, T3, 505) has a first non-gate terminal (507) connected to receive a second control signal (405, 455, 509), a gate terminal (511) connected to a voltage source that supplies a DC bias voltage, and a second non-gate terminal (513) connected to a first terminal (309, 311, 355, 515, 516) of the transistor switch (305, 353, 401, 451, 501) that is one of the source (311, 355, 515) of the transistor switch (305, 353, 401, 451, 501) and the drain (309, 359, 516) of the transistor switch (305, 353, 401, 451, 501). The second control signal (405, 455, 509) has at least a first voltage state that is inversely related to the first voltage state of the first control signal (307, 403, 453, 503) and a second voltage state that is inversely related to the second voltage state of the first control signal (307, 403, 453, 503). The second MOS transistor (T2, T4, 517) has a first non-gate terminal (519) connected to receive the second control signal (405, 455, 509); a gate terminal (521) connected to the voltage source that supplies the DC bias voltage; and a second non-gate terminal (523) connected to the first terminal of the transistor switch (305, 353, 401, 451, 501). When the first type is the NFET, then the DC bias voltage is less than or equal to the first voltage state of the first control signal (307, 403, 453, 503) and greater than the second voltage state of the first control signal (307, 403, 453, 503); and when the first type is the PFET, then the DC bias voltage is greater than or equal to the first voltage state of the first control signal (307, 403, 453, 503) and less than the second voltage state of the first control signal (307, 403, 453, 503).

A multi-parameter safe operating region constraint design method and simulation system for a dual active bridge converter is disclosed. The method includes: determining the key parameters to be designed; designing transmission power constraints to ensure that the dual active bridge converter can still meet the theoretical maximum allowable power output requirement under maximum phase shift conditions; designing current stress constraints to ensure that the high-voltage side current stress and low-voltage side current stress are within the safe operating range of the corresponding switches in the dual active bridge converter; designing steady-state thermal stress constraints to ensure that the effective value of the current of the switches under continuous operation conditions does not exceed the allowable range of the switches; constructing a multi-parameter safe operating region by finding the intersection of the transmission power constraint, current stress constraint, and steady-state thermal stress constraint in the parameter space of the series inductor and the switching frequency of the switches; and then selecting the required parameters within the multi-parameter safe operating region. This invention provides an intuitive and engineering-operable design basis for parameter selection.

The invention belongs to the technical field of energy scheduling, and discloses a distributed energy collaborative scheduling method and system of an intelligent energy monitoring system. Comprising the steps of collecting state data of an energy storage converter and a power grid electricity price signal, and obtaining system initial data; calculating the instantaneous total power loss and the online estimated value of the junction temperature, and generating a continuous junction temperature time sequence; calculating a global thermal cycle damage value, and updating the health state of the energy storage converter; calculating the current maximum allowable power loss; the maximum allowable power loss and inherent voltage and current constraints are integrated and converted into linear inequality constraints; solving an optimal power scheduling sequence in a finite time domain; extracting a power value of a first time step in the sequence as a power set value, and returning to enter a next circulation process after execution; according to the invention, by introducing the dynamic safe working area constraint, the risk of accidental shutdown caused by overheating of the power device is greatly reduced, and the comprehensive service life of the whole energy storage system is effectively prolonged.

The utility model relates to the technical field of transistor testing, in particular to a verification device for a safe working area of an MOS (Metal Oxide Semiconductor) tube. The verification device comprises a PCB (Printed Circuit Board), an MOS (Metal Oxide Semiconductor) tube pin seat and a verification module, wherein the PCB is provided with an MOS tube pin seat; the resistor R1 and the resistor R2 are connected to a second pin of the MOS tube pin seat in parallel, the other end of the resistor R2 is grounded, and the other end of the resistor R1 is connected to a third pin of the MOS tube pin seat. According to the utility model, the problem that when the SOA working area of the MOS transistor needs to be verified in the research and development design stage, the MOS transistor device needs to be tested after being placed on an equipment board is solved. Therefore, board cutting and current clamping testing are avoided, and the operation process of testing is simplified.

To reduce the cost of systems equipped with hot-swap controller circuits. [Solution] The hot-swap controller IC200 controls multiple transistors connected in parallel. The first gate terminal GATE1 is connected to the gate of the first transistor M1, which is the one with the widest safe operating area among the multiple transistors. The second gate terminal GATE2 is connected to the gate of the second transistor M2, which is a transistor other than the first transistor M1 among the multiple transistors. The gate controller 210 controls the voltage Vg1 of the first gate terminal GATE1 and the voltage Vg2 of the second gate terminal GATE2. When turning on the multiple transistors, the gate controller 210 raises the voltage Vg2 of the second gate terminal GATE2 with a delay compared to the voltage Vg1 of the first gate terminal GATE1.

The invention relates to a power semiconductor device, in particular to a groove type field effect transistor semiconductor device and a manufacturing method thereof, and adopts the technical scheme that a series of second-type grooves extending discontinuously in the Z direction are formed in the upper surface of a first conductive type semiconductor and between first-type grooves, and grooves are formed in the upper surfaces of the second-type grooves; the upper surface metal is downwards filled into the groove, and a second type shield gate electrode is arranged in the second type trench; a first conductive type heavily doped source region is arranged between the grooves on the upper surface of the first conductive type semiconductor, a second conductive type dopant region is arranged below the first conductive type heavily doped source region, and a second conductive type contact heavily doped region is arranged between the second conductive type dopant region and the outer side wall of the lower part of the groove. Compared with an existing device structure, the semiconductor device has the advantages that larger groove density can be achieved, lower on resistance and better switching threshold uniformity are achieved, and the semiconductor device has a large safe working area range and device reliability.

The invention relates to the technical field of semiconductor devices, in particular to a semiconductor device and a production method thereof. The device comprises a first doping type substrate and a plurality of primitive cell regions arranged on the first doping type substrate, the primitive cell region comprises: a channel region comprising a gate trench, a first hydrazine region, a minority carrier barrier layer of a first doping type, and a second doping type regulation layer; the hole diversion region comprises a second hydrazine region and a carrier storage layer of the first doping type; wherein the channel region and the hole diversion region respectively bear circulation paths of electron current and minority carrier hole current in the conduction and switching-on / off processes of the device, so that carrier partition circulation is realized. Carrier partition circulation is achieved, the performance of the device is effectively improved, the device has the excellent carrier storage effect, meanwhile, dV / dt controllability is achieved, the on-state voltage drop and the total switching loss of the device are reduced, and the output capacity and the reverse bias safe working area of the device are remarkably improved.

The invention provides a power semiconductor device control method, electronic equipment and a storage medium. The method comprises the following steps: acquiring a current working state parameter of a target power semiconductor device in real time; wherein the current working state parameter comprises the current junction temperature; determining a performance evaluation weight coefficient according to the current junction temperature, and constructing a weighted objective function in combination with the current working state parameters; performing iterative optimization calculation on the weighted target function under the condition of meeting the constraint of a preset safe working area to obtain a target control parameter; wherein the target control parameters comprise a gate driving voltage amplitude and a gate resistance value; and according to the target control parameter, generating a driving control signal to control the grid electrode of the target power semiconductor device. According to the invention, the driving parameters can be dynamically generated based on the multi-target optimization algorithm by sensing the operation state of the device in real time, and collaborative optimization of the power semiconductor device in a full working condition range is realized.

The invention relates to a reverse conducting insulated gate bipolar transistor and a preparation method thereof, the reverse conducting insulated gate bipolar transistor comprises an n-drift layer, a first n-type adjustment layer, a second n-type adjustment layer and a field stop layer, the n-drift layer, the first n-type adjustment layer, the second n-type adjustment layer and the field stop layer are stacked in sequence; the doping concentration of the first n-type adjustment layer is larger than the doping concentration of the n-drift layer and smaller than the doping concentration of the second n-type adjustment layer, and the doping concentration of the second n-type adjustment layer is smaller than the doping concentration of the field stop layer. By introducing the first n-type adjusting layer and the second n-type adjusting layer, excellent soft recovery characteristics and dynamic robustness are achieved, meanwhile, low overall loss is kept, and the high recovery capacity is achieved under the extreme conditions of high power supply voltage, high forward current, high temperature and the like; and the tradeoff and tradeoff triangular relationship limitation among the total loss of the traditional device, the reverse recovery softness and the diode recovery safety working area is broken through.

A circuit for protection of a power transistor driven at a driving electrode by a driver circuit, wherein the circuit for protection comprises safe operating area monitoring circuitry configured to control operation of the transistor with respect to its safe operating area, which receives as input at least a current value proportional to a current flowing through the power transistor, control the operation of the power transistor with respect to the safe operating area as a function of transistor thermal behavior information and the at least a current value proportional to the current flowing through the power transistor to control the value of a junction temperature of the transistor, and output an output signal that controls on and off states of the driver circuit by a switch driving the power transistor to obtain a given behavior in time of the junction temperature of the transistor within the safe operation area.

A circuit is disclosed. The circuit includes a transformer having a primary winding extending from a first terminal to a second terminal, a capacitor connected between the first terminal and an input terminal, a first switch having a first source terminal and a first drain terminal, the first drain terminal connected to the input terminal, a second switch having a second source terminal and a second drain terminal, the second drain terminal connected to the second terminal and a controller arranged to sense a voltage at the first terminal, compare the sensed voltage to a predetermined threshold, and control a state of the first switch such that when the sensed voltage exceeds the predetermined threshold, the state of the first switch is transitioned from a first on-state to a first off-state, from the first off-state to a second on-state and from the second on-state to a second off-state.

The invention relates to an industrial and commercial energy storage battery active equalization method and a storage medium. The method comprises the following steps: constructing a battery safe working area, collecting dynamic characteristic parameters of each battery unit in real time, training a working condition migration model by using a long short-term memory network, and predicting a unit working condition vector at the next moment; and mapping the current working condition vector to a global feature space to generate a dynamic working condition point, and calculating a working condition migration direction. Determining an equalization critical point by combining a safe working area of the battery, and further calculating equalization potential energy and global unbalance degree of each unit; when all the working condition points are located in a safety area and the global unbalance degree exceeds a threshold value, the electric charge quantity is transferred through a bidirectional DC-DC or a switch matrix; if a working condition point outside the safe working area of the battery exists, the input current is reduced, and the parallel branch balance impedance is switched if necessary. Through dynamic working condition prediction and potential energy quantification, the system safety is improved accurately and actively in a balanced mode, and the problem of battery inconsistency is effectively solved.

The invention provides a shield gate trench MOSFET device and a preparation method thereof, a first contact hole and a second contact hole which are strip-shaped, continuous, alternately arranged and different in transverse width are formed in an interlayer dielectric layer, the transverse width of the second contact hole is larger than that of the first contact hole, and the first contact hole and the second contact hole are communicated with each other. The ion concentration of the channel region of the cell where the second contact hole is located is relatively high, so that the threshold voltage is relatively high; the channel ion concentration of the cell where the first contact hole is located is low, so that the threshold voltage is low, when the MOS device works, the channel of the cell with the low threshold voltage is firstly started for conduction, the channel of the cell with the high threshold voltage is then started for conduction, the cell which is started later can serve as a heat dissipation channel through the time-sharing starting mechanism, heat is dissipated for the cell which is started firstly, and the heat dissipation efficiency is improved. Therefore, the SOA and the heat dissipation capability of the device are remarkably improved, only the shape of the contact hole mask layout needs to be adjusted, additional process steps do not need to be added, the reliability of the MOS device is improved, and the application range of the MOS device is widened with extremely low cost.

Hybrid MOSFET designs in which low ON resistance RON and high transconductance Gm values can be achieved while improving the safe operating area (SOA) of the device. Embodiments accomplish these design goals by adding a sub-gate drift region substantially only under the conductive layer of the gate structure, thereby allowing the drain to be positioned in closer proximity to the source and thus reducing RON and increasing Gm. The sub-gate drift region also reduces the peak drain-side E-field by dividing the E-field into two edges. This aspect helps push out the onset of breakdown mechanisms such as band-to-band tunneling and / or impact ionizations. Another aspect is a stepped gate oxide that is thicker in the drift region, which reduces parasitic CGD and improves the breakdown voltage, BVDSS, thus enhancing device reliability. Hybrid MOSFETs are particularly useful in cascode applications such as for envelope tracking and average power tracking.

The utility model relates to a circuit for increasing the loading capacity of an MOS (Metal Oxide Semiconductor) tube switching system during power supply. The circuit comprises a power supply SA, a PMOS (P-channel Metal Oxide Semiconductor) tube PQ1, a resistor R1, a resistor R2, a diode D1 and a switching circuit for controlling the on / off of the PMOS tube PQ1, the source electrode and the drain electrode of the PMOS tube PQ1 are respectively connected with two power supplies SA with the same voltage, and the grid electrode of the PMOS tube PQ1 is connected with the resistor R1; one end, far away from the PMOS tube PQ1, of the resistor R1 is connected with the switching circuit; the resistor R1 is connected with the diode D1 in parallel, the input end of the diode D1 is connected with the resistor R2, and one end, far away from the diode D1, of the resistor R2 is connected with the power supply SA; the output end of the diode D1 is connected with the grid electrode of the PMOS tube PQ1; the circuit provided by the utility model is simple in structure, effectively avoids the problem that the current is easy to exceed the safe working area of the MOS tube when the MOS tube is quickly turned off, is beneficial to reducing the integrated power consumption and cost of the circuit, and has better practicability.