123 results about "Safe operating area" patented technology

The invention discloses a power semiconductor device and a manufacturing method thereof. The device comprises a first base region, a second base region, a field stop region, a plasma storage region and a bottom doped region which are sequentially arranged from top to bottom, wherein a top P region and a terminal field limiting ring are arranged in the first base region. Wherein the first base region is used for optimizing the terminal structure; the second base region is used for improving a self-clamping function and adjusting power consumption and static breakdown voltage; the field termination region is used for terminating an electric field and suppressing current and voltage oscillation; the plasma storage area is used for expanding the safe working area and improving the self-clamping function. By optimizing and compromising the structural parameters of each area, the device can achieve the beneficial effects of self-clamping, low loss, wide safe working area and small terminal size.

The invention relates to a liquid hydrogen superconducting energy storage configuration system and method considering multi-mode safe operation. The system comprises a superconducting energy storage application scene demand module, a superconducting strip performance parameter module, a superconducting magnet structure economic configuration optimization module, a superconducting magnet'electricity-magnetism-heat 'multi-physics field simulation modeling module and a superconducting magnet dynamic safe working area module which are in synergistic effect. According to the method, the minimum energy storage capacity and the maximum magnetic field intensity threshold value are determined according to the superconducting energy storage application scene requirement, the genetic algorithm is adopted to conduct strip use amount minimum parameter optimization on magnet structure parameters, and an electricity-magnetism-heat multi-physics field coupling simulation model is established to quantify the liquid hydrogen cooling requirement. And finally, constructing a dynamic safe working area with the maximum allowable temperature to realize closed-loop control. Compared with the prior art, the multi-mode operation safety of the superconducting energy storage system can be guaranteed, meanwhile, the using amount of superconducting strips and the liquid hydrogen cooling capacity are reduced, and the economic efficiency of the system is improved.

The embodiment of the invention provides a method, a device and a system for compensating anode voltage and output power of a magnetron, and belongs to the technical field of radiators for microwave heating. The method comprises the following steps: acquiring a current temperature and an anode voltage measurement value of a magnetron; calculating a correction voltage according to the current temperature; determining a temperature change rate according to the correction voltage and / or the anode voltage measurement value; performing PID control on the PWM signal of the magnetron according to the temperature change rate and the target voltage value; judging whether the current temperature is within a safe working interval or not; acquiring a current anode voltage value when the current temperature is out of the safe working interval; calculating theoretical output power according to the anode voltage value; calculating a power difference value between the theoretical output power and the actual output power; judging whether the power difference value is greater than or equal to a difference value threshold value; and calculating a target voltage value according to the theoretical output power and the input power under the condition that the difference value is greater than or equal to the difference threshold value.

Systems and methods for transistor protection for battery packs are disclosed. In one aspect, transistors are turned on and off at a duty cycle selected to keep the transistor in a safe operating area (SOA). Such SOAs are generally defined by voltage, current, and time, so by keeping the time limited, high currents or voltages may be better tolerated. In specifically contemplated aspects, a control circuit alternately activates and deactivates driver transistors to toggle a discharge pin, thereby setting the duty cycle.

The invention discloses a detection method, equipment and medium for a new energy high-power direct-current charging pile, and relates to the technical field of charging pile stability detection, and the method comprises the steps: controlling a direct-current electronic load to generate a load disturbance signal at N characteristic working points, collecting instantaneous value change data through a broadband data collection center, and calculating the stability of the charging pile according to the instantaneous value change data; and based on the dynamic load disturbance signal and the instantaneous value change data, calculating the pulse response characteristics of the to-be-tested DC charging pile at the N characteristic working points through a correlation function analysis method, constructing a dynamic impedance characteristic model, and based on the safe working area three-dimensional boundary map, the electric energy quality indexes of the N characteristic working points and the dynamic impedance characteristic model, calculating the dynamic impedance characteristic of the to-be-tested DC charging pile. And evaluating and diagnosing the comprehensive performance of the direct current charging pile to be tested. According to the direct current charging pile comprehensive performance detection method based on dynamic load disturbance, accurate physical examination of the overall performance of the charging pile is achieved, and the detection depth, precision and predictability are improved.

The invention discloses an FCE diode and a manufacturing method thereof. The cathode metal is provided with a trench isolation region, cathode N + regions and cathode P + regions, the cathode N + regions and the cathode P + regions are transversely and alternately arranged, the trench isolation region isolates the cathode N + regions from the cathode P + regions, and the thickness of the trench isolation region exceeds 2 microns of the cathode N + regions and the cathode P + regions And then a plasma storage region, a field stop region, a base region, an anode P region and anode metal are sequentially arranged. The thickened trench isolation region is indispensable for improving the current density uniformity near the cathode, and can weaken low-frequency oscillation and reduce conduction voltage drop; the thickened plasma storage region can weaken low-frequency oscillation, improve the current density uniformity near the anode and reduce reverse recovery energy under severe or extreme conditions; the two measures can also ensure that the base region is greatly thinned on the premise of enlarging the safe working region, so that the loss is reduced. By optimizing and compromising the structural parameters of each area, the FCE diode can achieve the beneficial effects of self-clamping, low loss, uniform current density, no high-frequency oscillation, slight low-frequency oscillation and wide safe working area.

The application belongs to the technical field of digital signal processing, and particularly discloses a digital signal generation and processing method and system for synchronous rectification, wherein the method comprises the following steps: obtaining the staggered sampling code stream of a synchronous rectification device, and outputting time-aligned voltage and current characteristic values after group delay hard compensation; performing polynomial thermodynamic school correction in combination with discrete shell temperature sampling values; performing physical safety working area boundary checking on the corrected characteristic values, addressing and interpolating output of the target optimal conduction timing value in the irregular lattice space; extracting a feature vector to perform recursive least square prediction, and outputting an overshoot prediction extreme value; performing discrete charge integration in combination with a nonlinear capacitance function, and iteratively outputting a target dead time value based on the charge conservation criterion; and the application has the advantages of accurate control timing, physical boundary safety and dead time self-adaptation.

The application provides a single-point detection device and method for a safe working area of a power MOSFET, and relates to the technical field of semiconductor device testing. The single-point detection device comprises a pulse trigger circuit, a sampling feedback circuit, a driving amplification circuit, a capacitor energy storage circuit and a data collector. The pulse trigger circuit is used for outputting a pulse signal with a preset width according to a conduction time corresponding to a specific test point. The sampling feedback circuit is used for collecting a drain current of the power MOSFET and generating a feedback signal. The driving amplification circuit drives the power MOSFET to be turned on or turned off according to the feedback signal and the pulse signal. The capacitor energy storage circuit provides a target drain-source voltage for the power MOSFET according to a drain-source voltage corresponding to the specific test point. The data collector records waveforms of the drain-source voltage and the drain current of the power MOSFET. The single-point detection device does not need to increase an additional circuit, parameter matching is realized by adjusting devices in the single-point detection device, the test efficiency is improved, and the single-point detection device has the advantages of high efficiency, flexibility, high precision and the like.

The invention provides a power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) wide SOA (Silicon On Architecture) structure preparation process and a chip, a well region is arranged among a plurality of first grooves, a first injection region is arranged in the well region, and a plurality of second injection regions are correspondingly arranged below a part of the well region, so that an MOSFET device with a wider safe working region can be realized; moreover, a proper threshold voltage value is obtained, the overcurrent capability of the SOA can be improved by nearly 2-3 times, and the thermal stability is synchronously reduced.

The embodiment of the invention relates to a protection circuit, a corresponding system and a method. A circuit for protecting a power transistor driven by a driver circuit at a drive electrode wherein the circuit for protection comprises safe operating area monitoring circuitry configured to control operation of the transistor for its safe operating area, the safe operation area monitoring circuitry receives as an input at least a current value proportional to the current flowing through the power transistor, and controls operation of the power transistor for the safe operation area according to the transistor thermal behavior information and at least the current value proportional to the current flowing through the power transistor, the driver circuit is coupled to the transistor to control a value of a junction temperature of the transistor and to output an output signal that controls on and off states of the driver circuit by driving a switch of the power transistor to obtain a given behavior of the junction temperature of the transistor over time within a safe operating region.

The utility model discloses a negative voltage protection circuit, which comprises a negative voltage protection module used for being electrically connected with an input end, and when backward voltage appears in the circuit, the negative voltage protection circuit responds quickly, clamps the backward voltage in a safe working area range of a device and discharges the backward voltage to the ground; the current limiting module is used for limiting the maximum current within a certain threshold value and preventing surge current from causing abnormity of a driving power supply part; the totem pole output and secondary release module is used for driving a driven device and is also used for releasing charges generated on a circuit so as to prevent product damage caused by slow release speed of the circuit; and the forward protection module is used for preventing the device from being damaged when the product is protected and the state is rapidly switched, and ensuring that the device runs in a normal working range. The negative voltage protection circuit does not need an MCU module to detect the input voltage, and the system reliability is improved. And the current-limiting resistor is connected in series with the driving input end, so that surge current is prevented, and the stability of the system is improved.

The invention provides a semiconductor device. The semiconductor device comprises a substrate; the doped region is positioned in the substrate; and the embedded structure extends downwards from the upper surface of the substrate and at least comprises a contact metal, the contact metal is in contact with the doped region, and the contact metal is configured as an electrode end of the semiconductor device. The doped region is configured as a drain region of the semiconductor device, and the embedded structure is used for improving the withstand voltage of the semiconductor device; when the doped region is configured as a source region of the semiconductor device, the embedded structure is used for improving a safe working region of the semiconductor device.

The application belongs to the technical field of safety evaluation, and specifically discloses a kind of high-frequency operation dynamic safety work area evaluation method, device and equipment. According to the temperature characteristics and degradation information, the second current change rate and the second voltage change rate of SiC MOSFET device under the driving protection circuit are determined respectively through the application. After calculating the target current change rate combined with the first current change rate, and calculating the target voltage change rate combined with the first voltage change rate, the high-frequency operation dynamic safety work area of SiC MOSFET device is evaluated respectively. Through the above-mentioned mode, the root cause of the secondary problem of SiC MOSFET device switching transient is considered, the current change rate and the voltage change rate are selected to represent the switching rate, and the voltage and current overshoot and oscillation of the switching transient are effectively evaluated, and the safety work area is evaluated combined with the temperature characteristics and degradation information, so as to effectively improve the accuracy of evaluating the high-frequency operation dynamic safety work area.

The driving circuit generates a first control signal and a second control signal and outputs the first control signal and the second control signal to respective control electrodes of the first power semiconductor element and the second power semiconductor element which are connected in parallel. The range of the safe operation area of the first power semiconductor element is larger than the range of the safe operation area of the second power semiconductor element. The driving circuit comprises a time delay circuit, a control logic circuit and a buffer. The time delay circuit compares a voltage level of the second control signal with a first reference voltage or compares a drain-source voltage of the first power semiconductor element with a second reference voltage, and generates a first voltage according to a comparison result. The first and second reference voltages are associated with temperatures of the first and second power semiconductor elements. The control logic circuit generates a logic signal according to the first voltage. The buffer generates a first or second control signal according to a logic signal. According to the invention, a relatively large range of a safe working area can be realized.

The application provides a medium-high voltage shield gate power device layout and device. By optimizing a gate contact hole connection mode, the first grooves where the gate contact hole areas are located are arranged at intervals, that is, gate polysilicon interval connection gate contact holes. The safety operating area (SOA) performance of the application can be improved by several times. The first grooves where the gate contact hole areas are located can be selected to be separated by several first grooves according to the required safety operating area (SOA) performance. In addition, a mask plate does not need to be increased, and there is a certain advantage in cost.

The invention relates to the technical field of IGBT (Insulated Gate Bipolar Translator) structures, and discloses a soft-recoverable IGBT structure, which comprises an MOS (Metal Oxide Semiconductor) gate structure positioned on the front surface of a device, a diode anode structure, an n drift layer for bearing the withstand voltage of the device, and a field stop layer positioned below the n drift layer and used for optimizing an internal electric field of the device, a gradually-doped n-type adjusting layer, an IGBT part, a diode part, a p-type collector region and an n-type cathode region are arranged between the n drift layer and the field stop layer, the IGBT part and the diode part are arranged in anti-parallel, the p-type collector region is located on the back surface of the device and serves as the IGBT part, and the n-type cathode region is located on the back surface of the device and serves as the diode part. By introducing the n-type adjusting layer, excellent soft recovery characteristic and dynamic robustness are realized, low overall loss is maintained, and the device has strong recovery capability under extreme conditions (high VCC, high forward current and high temperature). And the tradeoff and tradeoff triangular relationship limitation among the traditional total loss, reverse recovery softness and diode (FWD) recovery safety working area is broken through.

The invention discloses a laterally diffused metal oxide semiconductor device and a manufacturing method thereof, the device comprises a plurality of cells, each cell comprises a substrate, a drift region located in the substrate, N body regions, a source region, a drain region, a source region and a body contact region, the N body regions extend from the surface of the drift region into the drift region and are located in the middle region of the cell, n is a positive integer greater than or equal to 2, the first body region to the Nth body region are sequentially arranged in the direction perpendicular to the substrate, the first body region extends from the surface of the drift region, the second body region to the Nth body region are located in the drift region, the body contact region extends from the surface of the first body region into the first body region, the source region and the body contact region are in contact with each other, and the N is a positive integer greater than or equal to 2. The source regions are located at two ends of the body contact region. And the Nth body region collects holes generated by collision ionization, so that the Vbe voltage of the parasitic BJT is reduced, and the safe working region of the device is improved.

The present application provides a method for manufacturing a field-effect transistor and a field-effect transistor. The manufacturing method forms a second conductive type semiconductor body region with different doping concentrations by ion implantation, without significantly increasing the manufacturing process and cost of the field-effect transistor. Due to the difference in doping concentration of the second conductive type semiconductor body region, the turn-on time between cells is different, which avoids the concentration of current and heat, enhances the thermal stability of the field-effect transistor, and increases the safe operating area. Compared with devices with virtual cells, its on-resistance is significantly reduced.

A motor drive circuit comprising: a motor bridge, comprising a bridge arm comprising upper and lower switches for each motor phase, which may be selectively closed to modulate voltage applied to the respective phases to drive signals from a motor control circuit, at least one solid-state-phase-isolation-relay (SSPIR) provided in series in an electrical path connecting a respective phase of the motor to a respective bridge arm, the SSPIR being closed in normal operation so that current can flow in the phase and held open in a fault mode of operation to prevent current flow, a monitoring arrangement for monitoring a current waveform in the phase to identify when it is safe to open the SSPIR without causing damage to the SSPIR due to an avalanche mode, and a control circuit that applies a voltage to each SSPIR that is sufficient to hold the SSPIR closed in normal operation is only opened when the current is in a safe operational area.

The invention discloses an IGBT (Insulated Gate Bipolar Translator) driving control method based on secondary side hardware protection and active clamping, which comprises the following specific steps of: establishing an IGBT digital twin model, and updating junction temperature distribution, saturation voltage drop and theoretical boundaries of a dynamic safe working area under different working conditions in real time through model simulation; in the normal switching process of the IGBT, voltage waveforms and current change rate waveforms in the switching-on and switching-off stages of the IGBT are collected in real time, key parameters are identified, and meanwhile self-adaptive correction is carried out; according to the invention, the conversion from passive protection to active prediction can be realized, the accuracy of protection criteria is greatly improved, the voltage stress and loss of a device are remarkably reduced, false triggering and misjudgment are reduced, the self-diagnosis capability and response speed of a system are improved, the time precision and coordination of protection decisions are ensured, and the reliability of the system is improved. Thermal fatigue and breakdown risks caused by overstress are reduced, so that the service life of the device is prolonged, and the overall reliability and operation efficiency of the power module are improved.

The invention belongs to the technical field of thermal management and reliability optimization, and particularly discloses a heterogeneous hybrid switch unit thermal reliability optimization method based on a safe operation area, and the method comprises the following steps: S1, obtaining a corresponding two-dimensional safe operation area projection under a rated parameter according to the safe operation area of a heterogeneous hybrid switch unit, extracting a current maximum value Imax20 according to the regional projection; s2, acquiring a current load current IF, comparing the size of Imax20 with the size of IF, if Imax20 is greater than or equal to IF, performing S3, and if Imax20lt, performing S3; when IF, performing S4; s3, single parameter adjustment is carried out; s4, carrying out two-parameter adjustment; and S5, inputting the target optimization parameters into a PWM signal generation module, and generating SiC-based device and Si-based device driving signals corresponding to the target switching frequency and the SiC interruption proportion through cooperative work of the DSP and the FPGA, thereby expanding the safe operation area of the hybrid switch unit. The over-temperature risk of the hybrid switch unit is avoided, and the reliability of the hybrid switch unit is improved.

Systems and methods are provided for controlling power down of an overdrive low drop out regulator circuits. The system is designed with a low dropout regulator circuit configured to operate in a safe operating area range of operation with very low current. The circuit contains a regulator, a current boost, and a power down switch. The current boost is responsive to a power down signal, generally from a power distribution board. The circuit is fabricated such that the low dropout regulator circuit with the current boost operates with minimum current pull while maintaining safe operating area range of operation. The safe operating area range of operation is maintained during various design operations, normal operations, and power down. This regulator circuit may be designed without a middle level voltage or high-ground.

In a disclosed Schmitt trigger, an input stage includes a first p-channel field effect transistor (PFET) and a second PFET, which are connected in series to a VDD rail, and a first n-channel field effect transistor (NFET) and a second NFET, which are connected in series between ground and the second PFET. An output stage includes additional FETs for hysteresis. The first PFET and first NFET are different from the other FETs and have a higher voltage rating. For example, the first PFET and first NFET can be buried oxide field effect transistors (BOXFETs) and the other FETs can be laterally diffused metal oxide semiconductor field effect transistors (LDMOSFETs)). Gates of the first PFET and first NFET are connected to an input node. Gates of the second PFET and NFET are connected to receive reference voltages to prevent safe operating area (SOA) violations and control trigger voltage levels.

The invention discloses a converter transient voltage active support method based on a protection demand, and belongs to the technical field of power electronics, and the method comprises the steps: obtaining an instantaneous electric stress parameter of a converter, and obtaining a real-time thermal stress state in combination with a thermal response relation of a power semiconductor device; fusing the electric stress parameter and the thermal stress state, and combining the characteristic data of the safe working area to generate a dynamic safe working boundary; meanwhile, transient information of the power grid is detected, and an ideal transient supporting instruction is generated according to the supporting guide rule; and according to the boundary, constraining and reconstructing the instruction, and generating an adaptive transient support instruction by intelligently adjusting the amplitude or change rate of the instruction. According to the method, the electric thermal stress state of the power semiconductor device is sensed in real time to dynamically generate the safe working boundary, intelligent constraint and reconstruction are carried out on the ideal supporting instruction following the power grid guide rule according to the boundary, and the operation safety and reliability of equipment can be ensured while the transient supporting capacity of the converter can be exerted to the maximum extent.

The invention relates to the technical field of power devices, in particular to a trench-type insulated gate bipolar transistor with a wide positive bias safe working area and a preparation method, and the trench-type insulated gate bipolar transistor comprises a drift region, and a first well region and a second well region are sequentially formed above the drift region; the doping concentration of the first well region is higher than that of the second well region, so that the carrier concentration of the first well region is higher than that of the second well region. In order to solve the problem that the pinch-off voltage of a trench-type insulated gate bipolar transistor in the prior art is too small, the high-concentration doped first well region is introduced to the bottom of the well region in the scheme, so that the carrier concentration in the region is improved, the voltage drop from a collector electrode to an emitter electrode when a device works is reduced, a channel is more difficult to pinch off, and the reliability of the device is improved. The pinch-off voltage is increased, and the device enters a desaturation region later, so that the device has a larger working current and a wider positive bias safe working region.

According to the shield gate trench MOSFET device and the preparation method thereof provided by the invention, the first contact hole and the second contact hole with different densities are manufactured in the interlayer dielectric layer of the cellular region, and the distribution density of the first contact hole is low, so that the ion concentration of the channel region of the cell where the first contact hole is located is low, and the threshold voltage is also low; the distribution density of the second contact holes is high, the channel ion concentration of the cells where the second contact holes are located is high, and the threshold voltage is also high, so that when the MOS device works, the cells with low threshold voltage are firstly started to conduct electricity, the cells with high threshold voltage are then started, the later started cells can serve as heat dissipation channels through the time-sharing starting mechanism, heat is dissipated for the cells started firstly, and the heat dissipation efficiency of the MOS device is improved. According to the preparation method, only the layout design of the contact hole mask needs to be adjusted, additional process steps do not need to be added, the reliability of the MOS device is improved, and the application range of the MOS device is widened with extremely low cost.

The invention provides a single-point detection device and method for a safe working area of a power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), and relates to the technical field of semiconductor device testing. The single-point detection device comprises a pulse trigger circuit, a sampling feedback circuit, a driving amplification circuit, a capacitance energy storage circuit and a data collector. The pulse trigger circuit is used for outputting a pulse signal with a preset width according to the conduction time corresponding to the specific test point; the sampling feedback circuit is used for collecting the drain current of the power MOSFET and generating a feedback signal; the driving amplification circuit drives the power MOSFET to be switched on or switched off according to the feedback signal and the pulse signal; the capacitance energy storage circuit provides target drain-source voltage for the power MOSFET according to the drain-source voltage corresponding to the specific test point; and the data collector records the waveforms of the drain-source voltage and the drain current of the power MOSFET. The single-point detection device does not need to add extra lines, parameter matching is achieved by adjusting devices in the single-point detection device, the test efficiency is improved, and the single-point detection device has the advantages of being efficient, flexible, high in precision and the like.

The invention discloses a SiC MOSFET extended SOA measurement method considering the crosstalk influence of a half-bridge structure, and belongs to the technical field of power semiconductors. The method comprises the following steps: giving a maximum forward crosstalk current value, and testing and establishing a mapping relation between maximum allowable bus voltage and bus voltage rise time under different grid resistance conditions; giving a maximum negative crosstalk voltage value, and testing and establishing a mapping relation between the maximum allowable bus voltage and the bus voltage drop time under different grid resistance conditions; and based on the mapping relation, establishing a positive crosstalk safe working area and a negative crosstalk safe working area, and forming a comprehensive crosstalk safe working area by taking the intersection of the two. According to the invention, the coverage of the dynamic overstress risk under the cooperative work of multiple devices is realized, the application stability and reliability of the SiC MOSFET in the half-bridge circuit are improved, and the technical problem that the traditional SOA evaluation is disjointed with the actual working condition is solved.

A switch circuit has a transistor switch (305, 353, 401, 451, 501) and a first MOS transistor (T1, T3, 505), both of a first type, and a second MOS transistor (T2, T4, 517) of a second type that is complementary to the first type, wherein the first type is an NFET or a PFET. The transistor switch (305, 353, 401, 451, 501) has a source (311, 355, 515), a drain (309, 359, 516), and a gate (503), wherein the gate (503) is connected to a first control signal (307, 403, 453, 503) having at least a first voltage state for turning the transistor switch (305, 353, 401, 451, 501) on and a second voltage state for turning the transistor switch (305, 353, 401, 451, 501) off. The first MOS transistor (T1, T3, 505) has a first non-gate terminal (507) connected to receive a second control signal (405, 455, 509), a gate terminal (511) connected to a voltage source that supplies a DC bias voltage, and a second non-gate terminal (513) connected to a first terminal (309, 311, 355, 515, 516) of the transistor switch (305, 353, 401, 451, 501) that is one of the source (311, 355, 515) of the transistor switch (305, 353, 401, 451, 501) and the drain (309, 359, 516) of the transistor switch (305, 353, 401, 451, 501). The second control signal (405, 455, 509) has at least a first voltage state that is inversely related to the first voltage state of the first control signal (307, 403, 453, 503) and a second voltage state that is inversely related to the second voltage state of the first control signal (307, 403, 453, 503). The second MOS transistor (T2, T4, 517) has a first non-gate terminal (519) connected to receive the second control signal (405, 455, 509); a gate terminal (521) connected to the voltage source that supplies the DC bias voltage; and a second non-gate terminal (523) connected to the first terminal of the transistor switch (305, 353, 401, 451, 501). When the first type is the NFET, then the DC bias voltage is less than or equal to the first voltage state of the first control signal (307, 403, 453, 503) and greater than the second voltage state of the first control signal (307, 403, 453, 503); and when the first type is the PFET, then the DC bias voltage is greater than or equal to the first voltage state of the first control signal (307, 403, 453, 503) and less than the second voltage state of the first control signal (307, 403, 453, 503).

A power MOSFET device includes an active area accommodating a first body region and a second body region having a first and, respectively, a second conductivity value. The second value is higher than the first value. A first channel region is disposed in the first body region between a first source region and a drain region, and the first channel region has and having a first channel length. A second channel region is disposed in the second body region between a second source region and the drain region, and the second channel region has and having a second channel length smaller than the first channel length. A first device portion, having a first threshold voltage, includes the first channel region, and a second device portion, having a second threshold voltage higher than the first threshold voltage, includes the second channel region.