14 results about "Safe operating area" patented technology

The application belongs to the technical field of safety evaluation, and specifically discloses a kind of high-frequency operation dynamic safety work area evaluation method, device and equipment. According to the temperature characteristics and degradation information, the second current change rate and the second voltage change rate of SiC MOSFET device under the driving protection circuit are determined respectively through the application. After calculating the target current change rate combined with the first current change rate, and calculating the target voltage change rate combined with the first voltage change rate, the high-frequency operation dynamic safety work area of SiC MOSFET device is evaluated respectively. Through the above-mentioned mode, the root cause of the secondary problem of SiC MOSFET device switching transient is considered, the current change rate and the voltage change rate are selected to represent the switching rate, and the voltage and current overshoot and oscillation of the switching transient are effectively evaluated, and the safety work area is evaluated combined with the temperature characteristics and degradation information, so as to effectively improve the accuracy of evaluating the high-frequency operation dynamic safety work area.

The application provides a medium-high voltage shield gate power device layout and device. By optimizing a gate contact hole connection mode, the first grooves where the gate contact hole areas are located are arranged at intervals, that is, gate polysilicon interval connection gate contact holes. The safety operating area (SOA) performance of the application can be improved by several times. The first grooves where the gate contact hole areas are located can be selected to be separated by several first grooves according to the required safety operating area (SOA) performance. In addition, a mask plate does not need to be increased, and there is a certain advantage in cost.

A multi-parameter safe operating region constraint design method and simulation system for a dual active bridge converter is disclosed. The method includes: determining the key parameters to be designed; designing transmission power constraints to ensure that the dual active bridge converter can still meet the theoretical maximum allowable power output requirement under maximum phase shift conditions; designing current stress constraints to ensure that the high-voltage side current stress and low-voltage side current stress are within the safe operating range of the corresponding switches in the dual active bridge converter; designing steady-state thermal stress constraints to ensure that the effective value of the current of the switches under continuous operation conditions does not exceed the allowable range of the switches; constructing a multi-parameter safe operating region by finding the intersection of the transmission power constraint, current stress constraint, and steady-state thermal stress constraint in the parameter space of the series inductor and the switching frequency of the switches; and then selecting the required parameters within the multi-parameter safe operating region. This invention provides an intuitive and engineering-operable design basis for parameter selection.

Hybrid MOSFET designs in which low ON resistance RON and high transconductance Gm values can be achieved while improving the safe operating area (SOA) of the device. Embodiments accomplish these design goals by adding a sub-gate drift region substantially only under the conductive layer of the gate structure, thereby allowing the drain to be positioned in closer proximity to the source and thus reducing RON and increasing Gm. The sub-gate drift region also reduces the peak drain-side E-field by dividing the E-field into two edges. This aspect helps push out the onset of breakdown mechanisms such as band-to-band tunneling and / or impact ionizations. Another aspect is a stepped gate oxide that is thicker in the drift region, which reduces parasitic CGD and improves the breakdown voltage, BVDSS, thus enhancing device reliability. Hybrid MOSFETs are particularly useful in cascode applications such as for envelope tracking and average power tracking.

This invention provides a MOS device and its fabrication method. The MOS device includes at least one cell structure, each cell structure comprising at least one body region and at least one source region. The body region is of a second conductivity type and is located in a substrate. The source regions are located in the substrate, with one source region corresponding to one body region and positioned above the corresponding body region. The source regions are connected to their corresponding body regions and are of a first conductivity type opposite to the second conductivity type. Specifically, a portion of the source regions in all cell structures of the MOS device is a high-concentration doped region of the first conductivity type, and another portion is a low-concentration doped region of the first conductivity type. This allows for self-negative feedback adjustment of the source region potential of the MOS device, significantly improving the safe operating area of ​​the MOS device in linear operating mode with minimal sacrifice in on-resistance. The fabrication method of the MOS device can fabricate the aforementioned MOS device.

This invention discloses a crane energy recovery safety control method, comprising: acquiring instantaneous voltage values ​​of the recovery circuit and instantaneous current values ​​of the power system, and calculating instantaneous feedback power; monitoring voltage and current waveform characteristics when the power exceeds the fluctuation range, and determining the main system interference risk when a transient voltage drop or preset current distortion is detected; responding to an emergency braking command under interference risk, and generating a configuration command to improve electrical isolation based on power amplitude iteration optimization; after execution, monitoring the energy status based on power accumulation, and activating the discharge backup channel when voltage saturation or abnormal temperature rise rate is detected; generating and executing a conduction timing sequence based on the discharge current decay slope and the safe operating area boundary, and outputting a collaborative control command after monitoring the power to fall back to the safe range. This invention achieves proactive management of discharge overload while ensuring the stability of the main system through power-guided waveform diagnosis, isolation optimization, and discharge timing control.

This application discloses an energy storage thermal management method and an energy storage device. The energy storage thermal management method is applied to the energy storage device, which includes a battery module, a casing, and a thermal regulation execution unit. The method includes: acquiring the cell temperature of the battery module and the surface temperature of the casing; when the surface temperature of the casing exceeds a preset upper limit of comfortable touch temperature and the temperature margin between the cell temperature and a preset upper limit of cell safety temperature is greater than or equal to a preset safety margin threshold, entering a user touch-priority mode to control the thermal regulation execution unit to perform a first thermal management operation; or when the cell temperature reaches or exceeds a preset upper limit of cell safety temperature, or the temperature margin is less than a preset safety margin threshold, entering a cell safety-priority mode to control the thermal regulation execution unit to perform a second thermal management operation. This application effectively avoids the risk of user discomfort or burns due to high casing temperature and ensures that the battery module is always within a safe operating range.

The application relates to a shielded gate power MOSFET with low capacitance and wide SOA and a preparation method. The application comprises a substrate layer of a first doping type; an epitaxial layer of the first doping type arranged on the surface of the substrate layer; a drain arranged on the back surface of the substrate layer; a deep trench formed in the epitaxial layer and extending downward from the upper surface of the epitaxial layer; a first oxide layer arranged in the deep trench; a second source arranged in the deep trench and wrapped by the first oxide layer; a gate arranged in the upper part of the deep trench, the gate is arranged in two sections which are left-right symmetrical in a single MOS cell, and each section comprises a transverse part and a longitudinal part, and the transverse part and the longitudinal part jointly form an L-shaped structure. By additionally introducing a transverse channel length, the safe working area SOA of the device is widened, the length of the transverse part of the gate can be adjusted to realize adjustable control of the equivalent channel length, and the device design parameters have higher flexibility.

The application provides a QKD device power voltage tolerance detection method and an electronic device, including: controlling a programmable power supply to provide a power voltage for a to-be-tested quantum key distribution (QKD) device, and collecting multiple input voltages of the to-be-tested QKD device; constructing multiple groups of input variables according to the multiple input voltages, wherein each group of input variables includes at least one input voltage; performing multiple-output prediction on the multiple groups of input variables by using a preset multiple-output Gaussian process model to obtain multiple groups of output variables, each group of output variables including multiple-dimension performance prediction parameters corresponding to one input voltage; performing power voltage tolerance analysis on the to-be-tested QKD device according to the multiple input voltages and the multiple-dimension performance prediction parameters to obtain a power voltage tolerance range of the to-be-tested QKD device. The multiple input voltages and the multiple-dimension performance prediction parameters are used to accurately locate a device voltage safe working interval, and the accuracy of abnormality detection is improved.

The application provides a shield gate power MOSFET layout for optimizing SOA and a MOSFET, wherein a second well region is arranged above part of the first well region. The two well regions are formed by ion implantation, so that two different threshold voltages exist, and current mainly flows out of the channel with a low threshold voltage. In the case that other processes remain unchanged, compared with other designs, the device is in a safe working area SOA, and the overcurrent capacity of the safe working area SOA is optimized.

One embodiment provides a semiconductor device capable of preventing RBSOA (Reverse Bias Safe Operating Area). According to one embodiment, a semiconductor device includes a semiconductor component, a gate metal layer, a first gate electrode, and an emitter electrode. The gate metal layer includes a first portion and a second portion. The first gate electrode extends along a first direction, the first direction being from the first portion toward the second portion. The first gate electrode is connected to the gate metal layer in the first portion. The emitter electrode is provided on the semiconductor component. The emitter electrode includes a third portion and a fourth portion. The emitter electrode is electrically connected to the semiconductor component in the third portion and the fourth portion. The second portion is located between the third portion and the fourth portion in the first direction.

The application discloses a power MOSFET and a manufacturing method, which is suitable for different process treatments. The power MOSFET is manufactured by the following steps: exposing a plurality of grooves in a spaced manner by using a photoresist mask layer; and implanting P-type (or N-type) ions into implantation regions at different positions by using any one of ion implantation modes, such as inclined implantation, reverse doping implantation and channel implantation, so as to form a doping region; the dose of the doping region is used to control the threshold voltage of a second sub-transistor; P-type ions are implanted between the grooves to form a P-type well region, so as to control the threshold voltage of a first sub-transistor; and the different ion implantation modes are matched with the staggered arrangement element design method, so that the threshold voltage of the element can be controlled in different ranges under the premise of maintaining the element size, and a wider safe working area capability is realized.

A charge pump circuit includes a first pump unit and a second pump unit. The first pump unit generates a pump voltage from an input voltage, a first clock signal and a second clock signal. The first clock signal and the second clock signal are in phase, and the second clock signal has a higher swing than the first clock signal. The second pump unit has a similar structure to the first pump unit, and the first and second pump units alternately output the pump voltage from the input voltage. Transistors in the first pump unit and the second pump unit operate in their safe operating area (SOA) and are disposed in two wells under independent biasing.