52 results about "Snapback" patented technology

Technology is disclosed for reading memory cells having threshold switching selectors. A sense amplifier may have a set of capacitors that may be used to exchange charge with a sense node connected to the selected word line. A capacitor may be used to pull excess charge from the sense node or to provide charge to the sense node. A control circuit drives a current to the selected word line to charge up the selected word line to switch on the threshold switching selector of the selected memory cell. A capacitor may be connected to the selected word line when, or soon after, the threshold switching selector switches on. The capacitor may draw away excess charge to prevent a snapback current from flowing through the memory cell thereby preventing mis-reads. The capacitor may reduce read latency by speeding the rate of voltage change on a word line.

A storage device includes a memory cell including a variable resistance element and a switching element having snapback current-voltage characteristics. The switching element includes a first conductive layer in contact with the variable resistance element, a second conductive layer, and a switching layer provided between the first conductive layer and the second conductive layer. The switching layer includes at least one switching member and a first insulating layer having a thermal conductivity higher than 1.4 W / m / K. A cross-sectional area of the switching member at a connection surface between the switching layer and the first conductive layer and a cross-sectional area of the switching member at a connection surface between the switching layer and the second conductive layer are each smaller than a cross-sectional area at a connection surface between the first conductive layer and the variable resistance element.

Technology for reading memory cells in a cross-point memory array. Each memory cell may have a threshold switching selector in series with a programmable resistance memory element. The memory system has control circuitry adjacent to the cross-bar memory array that is used to generate and deliver currents to the cross-bar memory array. The memory system temporarily provides capacitive isolation of the selected memory cell from capacitance of the adjacent circuitry while the snapback current is present. The memory system provides a discharge path to a node between the control circuitry and the selected memory cell during a period in which the capacitive isolation is removed.

Circuit structure comprising: a resistor-capacitor circuit (RC circuit) (110) having a first node (A), a second node (B) separated from the first node (A) by a resistive element (112) and a capacitive element (114), and a third node (C) between the resistive element (112) and the capacitive element (114); a trigger transistor (122) having a pair of source / drain (S / D) terminals connected between the first node (A) and the second node (B) in parallel with the RC circuit (110) and a gate terminal coupled to the third node (C) of the RC circuit (110); a mirror transistor (126) having a pair of S / D terminals coupled between the first node (A) and the second node (B) in parallel with the RC circuit (110), and a gate terminal coupled to the gate terminal of the trigger transistor (122), wherein a current through the pair of S / D terminals of the mirror transistor (126) is smaller than a current through the pair of S / D terminals of the trigger transistor (122); and a snapback device (130) having a gate terminal (T Gate ) for controlling the current flow in the snapback device (130), the snapback device (130) comprising: a P-well (142) having a first N-doped region (146) coupled to one of the first nodes (A), an N-well (144) adjacent to the P-well (142) and having a first P-doped region (148) coupled to the second node (B), wherein a current path from the first node (A) to the second node (B) runs through the snapback device (130) in parallel with the RC circuit (110), and at least one doped region within the P-well (142) or the N-well (144) coupled to a selected one of the pair of S / D terminals of the mirror transistor (126) and the gate terminal (T Gate ) of the snapback device (130), wherein the at least one doped region has a same doping type with respect to the P-well (142) or the N-well (144).

Technology for reading memory cells in a cross-bar memory array. Each cell has a threshold switching selector in series with a programmable resistance memory element. A current diverting resistor is connected to a selected word line while a read current is driven to the selected word line. Driving the read current to the selected word line causes a voltage across the memory cell to increase until the threshold switching selector switches on. After the threshold switching selector switches on the voltage across the memory cell drops rapidly thereby resulting in a snapback current. Some of the read current is diverted to the current diverting resistor as the voltage across the memory cell increases. When the threshold switching selector switches on the resistor continues to divert current from flowing through the memory cell to prevent excessive current from inadvertently changing the state of the programmable resistance memory element.

The purpose of the present invention is to provide a semiconductor device in an RC-IGBT that can suppress a snapback phenomenon when the IGBT is switched on and hole injection from the IGBT region to a diode region when the diode is conducting, using a simple structure. The semiconductor device, which has an IGBT region 21 and a diode region 22 within the same chip, is characterized in that the gate resistance R of the IGBT near the boundary of the IGBT region 21 and the diode region 22 is larger than the gate resistance of the IGBT near the center of the IGBT region 21.

A semiconductor device comprises a switching device and a cathode pad disposed in a semiconductor die and a termination structure disposed between the switching device and the cathode pad. The switching device comprises a first conduction terminal on a top surface of the semiconductor die, and a second conduction terminal disposed on a bottom surface of the semiconductor die. A drift layer of the semiconductor die may be disposed between the first and second conduction terminals. The cathode pad is disposed on the top surface and electrically connected to the drift layer, and corresponds to a cathode terminal of a diode having the first conduction terminal as an anode terminal. The diode operates as a free-wheeling diode for the switching device when the cathode pad is electrically coupled to the second conduction terminal. Accordingly, the semiconductor device may operate as a Reverse-Conducting Insulated Gate Transistor having reduced snapback.

An ESD protection circuit includes a silicon controlled rectifier (SCR) including a first conduction path between a first node and a second node and a clamp circuit coupled to a control terminal of the SCR. The clamp circuit is part of a second conduction path between the first node and the second node. During an ESD event, the clamp circuit conduct an ESD current until a threshold IV point is reached. The clamp circuit triggers the SCR, which then acts as a snapback device to conduct the ESD current at a lower voltage.

The present invention belongs to the field of power semiconductor technology and relates to an adaptive high-voltage and low-loss power device. Compared with the traditional LIGBT structure, the present invention introduces an adaptive PMOS structure at the anode end of the LIGBT, and the gate of the PMOS structure is controlled by an integrated diode. When forward-conducting, the PMOS channel is closed, and the electron extraction path is blocked, thereby eliminating the snapback effect. During the shutdown process, as the anode voltage rises, the LIGBT anode PMOS channel is adaptively turned on, and the electrons in the drift region are converted into holes by the electrode 11, and then extracted from the P+ collector region through the PMOS channel; at the same time, the P+ collector region and the N-type buffer layer are almost short-circuited at the same potential, which inhibits the P+ collector region from injecting holes into the drift region, and the two jointly accelerate the shutdown of the device to reduce the shutdown loss. During forward blocking, the hole current in the P+ collector region is converted from the electrode 11 to the electron current and injected into the drift region through the PMOS channel, forming a MOS-like breakdown mode, which increases the breakdown voltage. Therefore, the present invention has smaller shutdown losses and higher breakdown voltages.

To provide a semiconductor device which restrains a snapback phenomenon.SOLUTION: A semiconductor device 100 includes a first semiconductor element 10 having a second semiconductor region 7 on a first semiconductor region 5, a third semiconductor region 8 on a second semiconductor region, a first trench 14 penetrating the second semiconductor region, an in-first-trench electrode 14a, a fourth semiconductor region 2 below the first semiconductor region, an upper electrode 11 connected to the third semiconductor region, and a lower electrode 1 connected to the fourth semiconductor region, a second semiconductor element 20 that is electrically connected to the upper electrode and has a fifth semiconductor region 12 on the first semiconductor region and a sixth semiconductor region 3 connected to the lower electrode, and a dummy region 30 that is provided between the first semiconductor element and the second semiconductor element and has a seventh semiconductor region 7D on the first semiconductor region, a third trench 15 penetrating the seventh semiconductor region, and an in-third-trench electrode 15a that is electrically connected to the first trench electrode in the third trench.SELECTED DRAWING: Figure 3

The present disclosure provides a semiconductor device, a preparation method thereof, and an electronic device. A low-doped N-type high-resistance region is added above a P+ collector region, thereby increasing the resistance above the P+ collector region. A P-type floating region with a partition region is provided between the N-type high-resistance region and an N-type buffer layer, thereby extending the current path above the P+ collector region. The P+ collector region is provided at the bottom of a first groove in the N-type high-resistance region, thereby increasing the longitudinal distance of the N-type high-resistance region in the collector structure, making the distance from the N+ collector region to the middle position of the P+ collector region farther. Therefore, the parasitic resistance of the device from the middle position of the P+ collector region to the N+ collector region is relatively higher, and the PN junction formed by the P+ collector region / N-type high-resistance region is easier to open, which can more effectively suppress the snapback phenomenon existing in a conventional reverse-conducting device when it is forward-conducted, and at the same time help to improve the forward conduction characteristics and reverse conduction characteristics of the device.

The present invention relates to the technical field of electrostatic discharge (ESD), and provides an ESD device based on a PNPN structure. A first junction is formed between a first P-well and an N-well, and a second junction is formed between the N-well and a second P-well; a first ion implantation region is provided in the surface region of the first P-well; a second ion implantation region is provided in the surface region of the second P-well; a first N-ion boundary implantation region is provided at a first junction formed by the intersection of the surface region of the first P-well and the surface region of the N-well; a second N-ion boundary implantation region is provided at a second junction formed by the intersection of the surface region of the N-well and the surface region of the second P-well; and a parasitic discharge circuit spans the first P-well, the N-well, and the second P-well, and is respectively connected to the first ion implantation region and the second ion implantation region. The present invention reduces snapback voltage by setting a high-concentration boundary, thereby improving ESD performance.

Provided is a semiconductor device capable of suppressing a snapback phenomenon when an IGBT is turned on and hole injection from an IGBT region to a diode region when a diode is turned on by a simple structure in an RC-IGBT. In a semiconductor device having an IGBT region (21) and a diode region (22) in the same chip, the gate resistance (R) of the IGBT near the boundary portion between the IGBT region (21) and the diode region (22) is greater than the gate resistance of the IGBT near the center portion of the IGBT region (21).

Technology for reading programmable resistance memory cells in a cross-bar memory array. Each cell has a threshold switching selector in series with a programmable resistance memory element. Each memory cell has a capacitor associated therewith. One of the electrodes of the capacitor may be formed from a conductive region of the cell in contact with the threshold switching selector. When the threshold switching selector turns on the voltage across the memory cell may rapidly drop, thereby resulting in a snapback current. The capacitor is able to absorb at least some of the snapback current to therefore reduce or even eliminate snapback current flow through the memory element.

A transient voltage suppression device includes a first transient voltage suppression diode having a first clamping characteristic, and a second bounce diode having a second clamping characteristic in series with the first transient voltage suppression diode. The first transient voltage suppression diode and the second jump-back diode are electrically connected in parallel to the load.

Technology for reading memory cells having threshold switching selectors. A sense amplifier may have a set of capacitors that may be used to exchange charge with a sense node connected to the selected word line. A capacitor may be used to pull excess charge from the sense node or to provide charge to the sense node. A control circuit drives a current to the selected word line to charge up the selected word line to switch on the threshold switching selector of the selected memory cell. A capacitor may be connected to the selected word line when, or soon after, the threshold switching selector switches on. The capacitor may draw away excess charge to prevent a snapback current from flowing through the memory cell thereby preventing mis-reads. The capacitor may reduce read latency by speeding the rate of voltage change on a word line.

A method and apparatus for simulating breakdown of an electronic component are provided. The method includes: when a terminal of an equivalent circuit model receives test charges, pulling up a voltage level of a first node of the equivalent circuit model; when the voltage level of the first node reaches a first threshold, turning on a first voltage controlled switch to pull up a voltage level of a second node of the equivalent circuit model; when the voltage level of the second mode reaches a second threshold, turning on a second voltage controlled switch to pull down a voltage level of the terminal to a holding voltage level to simulate snapback breakdown of the electronic component; and turning on a third voltage controlled switch to pull down the voltage level of the second node to turn off the second voltage controlled switch, thereby simulating second breakdown of the electronic component.

The invention designs an RC-LIGBT device integrated with double self-biased MOS transistors and capable of reducing saturation current, and belongs to the technical field of semiconductors. The invention comprises a self-biased NMOS (N-channel Metal Oxide Semiconductor) at a collector side and a self-biased PMOS (P-channel Metal Oxide Semiconductor) at an emitter During forward conduction, the substrate of the self-biased NMOS inhibits electrons from directly reaching the collector through the collector N +, the Snapback effect is eliminated, injected holes enter the source of the self-biased PMOS, the voltage of the source is increased, self-biased opening of the PMOS is achieved, and the saturation current can be reduced through the caused hole extraction effect; during reverse conduction, a reverse electron current path of the device is provided after the self-biased NMOS is started, so that reverse conduction is realized; in the turn-off process, the opening of the self-bias NOMS provides an electron extraction channel, and the opening of the self-bias PMOS provides a hole extraction channel. According to the device, the Snapback effect is eliminated under the condition that an additional control electrode is not added, and compared with a traditional LIGBT, the saturation current is reduced by 21.2% when the collector voltage is 100 V, and the turn-off loss is reduced by 31.1%.

A snapback electrostatic discharge (ESD) protection circuit includes a first well in a substrate, a drain region of a transistor, a source region of the transistor, a gate region of the transistor, and a second well embedded in the first well. The first well has a first dopant type. The drain region is in the first well, and has a second dopant type different from the first dopant type. The source region is in the first well, has the second dopant type, and is separated from the drain region in a first direction. The gate region is over the first well and the substrate. The second well is embedded in the first well, and is adjacent to a portion of the drain region. The second well has the second dopant type.

Technology for reading memory cells in a cross-bar memory array. Each cell has a threshold switching selector in series with a programmable resistance memory element. A current diverting resistor is connected to a selected word line while a read current is driven to the selected word line. Driving the read current to the selected word line causes a voltage across the memory cell to increase until the threshold switching selector switches on. After the threshold switching selector switches on the voltage across the memory cell drops rapidly thereby resulting in a snapback current. Some of the read current is diverted to the current diverting resistor as the voltage across the memory cell increases. When the threshold switching selector switches on the resistor continues to divert current from flowing through the memory cell to prevent excessive current from inadvertently changing the state of the programmable resistance memory element.

A snapback phenomenon in an RC-IGBT is suppressed. In a semiconductor device 100 comprising an IGBT region 21 and a diode region 22 on the same chip, an IGBT of IGBT region 21 has a drift layer 1 of a first conductivity type, a trench 3, a gate electrode 5 provided in the trench 3, a body layer 2 of a second conductivity type, an emitter layer 7 of the first conductivity type, a gate insulating film (insulating film 4), and a collector layer 11 of the second conductivity type. A diode of diode region 22 has the drift layer 1, a first semiconductor layer 12 of the second conductivity type, which is provided closer to a front side than the drift layer 1, and a second semiconductor layer 13 of the first conductivity type, which is provided closer to a back side than the drift layer 1.and the IGBT region 21 has a boundary column layer 8A of the second conductivity type at a boundary section with the diode region 22, which penetrates the drift layer 1 and is in contact with the body layer 2 and the collector layer 11.

An electrostatic discharge (ESD), protection device is provided. In accordance with the present disclosure, an ESD protection device is provided that includes a series connection of a first unit having strong snapback and low series capacitance and a second high-voltage unit that displays a relatively high holding / trigger voltage to ensure latch up and improper triggering of the ESD protection device while at the same time providing high-voltage operation with low capacitive loading.

A technology for reading memory cells with threshold switching selectors is disclosed. A sensing amplifier can include a set of capacitors that can be used to exchange charge with a sensing node connected to the selected word line. A capacitor can be used to drain excess charge from the sensing node or to supply charge to the sensing node. A control circuit introduces a current into the selected word line to charge it and turn on the threshold switching selector of the selected memory cell. A capacitor can be connected to the selected word line when, or shortly after, the threshold switching selector turns on. The capacitor can drain excess charge to prevent a snapback current from flowing through the memory cell, thereby preventing erroneous readouts.The capacitor can reduce read latency by accelerating the rate of voltage change across a word line.

Technology for reading memory cells in a cross-point memory array. Each memory cell has a threshold switching selector in series with a programmable resistance memory element. The memory system applies a step voltage pulse during a current force read of programmable resistance memory cells in a cross-bar memory array. In an aspect, the step voltage pulse is used to switch on the threshold switching selector. In an aspect, the step voltage pulse is applied after the threshold switching selector switches on when a snapback current may be present. In an aspect, the step voltage pulse is applied after the snapback current has dissipated.

Technology for reading memory cells in a cross-bar memory array. Each cell has a threshold switching selector in series with a programmable resistance memory element. A current diverting resistor is connected to a selected word line while a read current is driven to the selected word line. Driving the read current to the selected word line causes a voltage across the memory cell to increase until the threshold switching selector switches on. After the threshold switching selector switches on the voltage across the memory cell drops rapidly thereby resulting in a snapback current. Some of the read current is diverted to the current diverting resistor as the voltage across the memory cell increases. When the threshold switching selector switches on the resistor continues to divert current from flowing through the memory cell to prevent excessive current from inadvertently changing the state of the programmable resistance memory element.

Technology for reading programmable resistance memory cells in a cross-bar memory array. Each cell has a threshold switching selector in series with a programmable resistance memory element. Each memory cell has a capacitor associated therewith. One of the electrodes of the capacitor may be formed from a conductive region of the cell in contact with the threshold switching selector. When the threshold switching selector turns on the voltage across the memory cell may rapidly drop, thereby resulting in a snapback current. The capacitor is able to absorb at least some of the snapback current to therefore reduce or even eliminate snapback current flow through the memory element.

According to the semiconductor device, the preparation method thereof and the electronic equipment provided by the invention, the resistance above the P + collector region is increased by adding the low-doped N-type high-resistance region above the P + collector region, and the current path above the P + collector region is prolonged by arranging the P-type floating region with the partition region between the N-type high-resistance region and the N-type buffer layer, so that the current path above the P + collector region is prolonged. And the P + collector region is arranged at the bottom of the first groove of the N-type high-resistance region, so that the longitudinal distance of the N-type high-resistance region in the collector structure is increased, the distance from the N + collector region to the middle position of the P + collector region is farther, and the parasitic resistance of the device from the middle position of the P + collector region to the N + collector region is relatively higher; a PN junction formed by the P + collector region / the N-type high-resistance region is easier to open, the snapback phenomenon existing when a conventional reverse conducting device is conducted in the forward direction can be more effectively restrained, and meanwhile the forward conducting characteristic and the reverse conducting characteristic of the device can be improved.

An electrostatic discharge (ESD) protection structure that provides snapback protections to one or more high voltage circuit components. The ESD protection structure can be integrated along a peripheral region of a high voltage circuit, such as a high side gate driver of a driver circuit. The ESD protection structure includes a bipolar transistor structure interfacing with a PN junction of a high voltage device, which is configured to discharge the ESD current during an ESD event. The bipolar transistor structure has a collector region overlapping the PN junction, a base region embedded with sufficient pinch resistance to launch the snapback protection, and an emitter region for discharging the ESD current.

Technology for reading memory cells in a cross-point memory array. Each memory cell has a threshold switching selector in series with a programmable resistance memory element. The memory system applies a step voltage pulse during a current force read of programmable resistance memory cells in a cross-bar memory array. In an aspect, the step voltage pulse is used to switch on the threshold switching selector. In an aspect, the step voltage pulse is applied after the threshold switching selector switches on when a snapback current may be present. In an aspect, the step voltage pulse is applied after the snapback current has dissipated.

Provided is a semiconductor device in which a snapback phenomenon is suppressed. The semiconductor device includes a first semiconductor element, a second semiconductor element, and a dummy region. The first semiconductor element includes: a second semiconductor region above the first semiconductor region; a third semiconductor region above the second semiconductor region; a first trench penetrating the second semiconductor region; a first in-trench electrode; a fourth semiconductor region below the first semiconductor region; an upper electrode connected to the third semiconductor region; and a lower electrode connected to the fourth semiconductor region, the second semiconductor element having: a fifth semiconductor region above the first semiconductor region and electrically connected to the upper electrode; and a sixth semiconductor region connected to the lower electrode, the dummy region having, between the first semiconductor element and the second semiconductor element, a seventh semiconductor region above the first semiconductor region, a third trench penetrating the seventh semiconductor region, and a third trench inner electrode electrically connected to the first trench electrode in the third trench.