7 results about "Snapback" patented technology

Technology for reading memory cells in a cross-bar memory array. Each cell has a threshold switching selector in series with a programmable resistance memory element. A current diverting resistor is connected to a selected word line while a read current is driven to the selected word line. Driving the read current to the selected word line causes a voltage across the memory cell to increase until the threshold switching selector switches on. After the threshold switching selector switches on the voltage across the memory cell drops rapidly thereby resulting in a snapback current. Some of the read current is diverted to the current diverting resistor as the voltage across the memory cell increases. When the threshold switching selector switches on the resistor continues to divert current from flowing through the memory cell to prevent excessive current from inadvertently changing the state of the programmable resistance memory element.

The present invention relates to the technical field of electrostatic discharge (ESD), and provides an ESD device based on a PNPN structure. A first junction is formed between a first P-well and an N-well, and a second junction is formed between the N-well and a second P-well; a first ion implantation region is provided in the surface region of the first P-well; a second ion implantation region is provided in the surface region of the second P-well; a first N-ion boundary implantation region is provided at a first junction formed by the intersection of the surface region of the first P-well and the surface region of the N-well; a second N-ion boundary implantation region is provided at a second junction formed by the intersection of the surface region of the N-well and the surface region of the second P-well; and a parasitic discharge circuit spans the first P-well, the N-well, and the second P-well, and is respectively connected to the first ion implantation region and the second ion implantation region. The present invention reduces snapback voltage by setting a high-concentration boundary, thereby improving ESD performance.

The invention designs an RC-LIGBT device integrated with double self-biased MOS transistors and capable of reducing saturation current, and belongs to the technical field of semiconductors. The invention comprises a self-biased NMOS (N-channel Metal Oxide Semiconductor) at a collector side and a self-biased PMOS (P-channel Metal Oxide Semiconductor) at an emitter During forward conduction, the substrate of the self-biased NMOS inhibits electrons from directly reaching the collector through the collector N +, the Snapback effect is eliminated, injected holes enter the source of the self-biased PMOS, the voltage of the source is increased, self-biased opening of the PMOS is achieved, and the saturation current can be reduced through the caused hole extraction effect; during reverse conduction, a reverse electron current path of the device is provided after the self-biased NMOS is started, so that reverse conduction is realized; in the turn-off process, the opening of the self-bias NOMS provides an electron extraction channel, and the opening of the self-bias PMOS provides a hole extraction channel. According to the device, the Snapback effect is eliminated under the condition that an additional control electrode is not added, and compared with a traditional LIGBT, the saturation current is reduced by 21.2% when the collector voltage is 100 V, and the turn-off loss is reduced by 31.1%.

The embodiment of the invention provides an RC-IGBT device and a preparation method, the device comprises an N-drive region (1), a P + collector region (2) and an FS structure (3), and the FS structure (3) is connected below the N-drive region (1) and above the P + collector region (2); the lower structure and the upper structure are connected with the FS structure (3), the upper structure is connected to the N-drive region (1), the lower structure is connected to the P + Colletor region (2), and the phosphorus doping concentration of the lower structure is lower than that of the upper structure so as to increase the parasitic resistance above the P + Colletor region (2), that is, the short-circuit resistance of the P + Colletor region (2) at the collector side is increased, and the snapback phenomenon can be inhibited. And the width of the P + Collector region (2) is also reduced, so that the overall size of the primitive cell is reduced.

Technology for reading memory cells in a cross-point memory array. Each memory cell has a threshold switching selector in series with a programmable resistance memory element. The memory system applies a step voltage pulse during a current force read of programmable resistance memory cells in a cross-bar memory array. In an aspect, the step voltage pulse is used to switch on the threshold switching selector. In an aspect, the step voltage pulse is applied after the threshold switching selector switches on when a snapback current may be present. In an aspect, the step voltage pulse is applied after the snapback current has dissipated.

The application relates to the technical field of semiconductors, and particularly discloses an ESD protection device with a folding trigger mechanism and a preparation method thereof. The method comprises a P-type substrate; an N-type well layer and a P-type well layer formed in the substrate; at least one P-type doped layer formed on the surface of the N-type well layer; at least one N-type doped layer formed on the surface of the P-type well layer; a third groove arranged between the N-type well layer and the P-type well layer; and a suspended electric field modulation structure arranged on the third groove. The application introduces the suspended electric field modulation structure, realizes dynamic electric field regulation of the SCR trigger process without increasing the device leakage and changing the main discharge path, and makes the device have low trigger voltage, moderate holding voltage, excellent large-current discharge capacity and good static reliability.

Embodiments of the present disclosure provide a circuit structure and method of controlling electrostatic discharge (ESD) events in a resistance-capacitance (RC) circuit. The circuit structure according to the present disclosure can include a trigger transistor coupled in parallel with the RC circuit, and a gate terminal coupled to a portion of the RC circuit. A mirror transistor coupled in parallel with the RC circuit passes a current less than the current through the trigger transistor. A snapback device has a gate terminal coupled to a source or drain of the mirror transistor, and a pair of anode / cathode terminals coupled in parallel with the RC circuit. A current at the gate terminal of the snapback device derived from the current in the mirror transistor controls anode / cathode current flow in the snapback device.