72 results about "Snapback" patented technology

In the reverse-conducting IGBT according to the present invention, an n-type buffer layer surrounds a p-type collector layer. A p-type separation layer surrounds an n-type cathode layer. The n-type buffer layer separates the p-type collector layer and the p-type separation layer from each other. The p-type separation layer separates the n-type cathode layer and the n-type buffer layer from each other. Therefore, the present invention makes it possible to reduce snapback.

An electrostatic discharge (ESD) protection circuit is coupled between first and second pads to protect an internal circuit therebetween. Under a normal operating condition, a voltage on the first pad is higher than that on the second pad. The ESD protection circuit includes a substrate of a first conductivity type; first well of a second conductivity type in the substrate, wherein the first well is coupled to the first pad; a snapback device housed in the first well; and a diode string in the substrate, connected in series with the snapback device and separated from the first well, wherein the serially connected diode string and snapback device is connected between the first pad and the second pad. With the isolation from the first well, the holding voltage of the ESD protection circuit can be tuned by adjusting the number of diodes in the diode string without using a guard ring.

Snapback ESD protection circuits that include an Input/Output pad, a ground source, a first and a second NMOS transistor, and trigger circuit, pad bias circuit, and gate bias circuit. The first transistor drain connects to the pad. The second transistor drain connects to the first transistor source. The second transistor source connects to ground. The trigger circuit connects to the pad and a reference voltage to detect an ESD event at the pad. The pad bias circuit connects to the pad, the trigger circuit, ground, and the reference voltage to manage a voltage level for the reference voltage. The gate bias circuit connects to the reference voltage, a supply voltage, ground, and the gates of the first and second transistor to dynamically control the voltage of each gate of the first and a second NMOS transistor.

The invention provides an SOI transverse insulated gate bipolar transistor, which is characterized in that a first dielectric oxide layer and a floating field plate polycrystalline silicon electrode form a longitudinal floating field plate which is distributed in a whole second conduction type drift region to form a longitudinal floating field plate array; and a longitudinal field plate connectedwith the collector contact electrode is formed in the collector region by the same process, and a second conductive type well region is inserted in parallel to form an anode resistance structure. Whenthe transistor is in an on state, an accumulation layer can be formed on the surface of the longitudinal floating field plate, and the saturation current of the device is improved. The longitudinal field plate introduced into the well region of the second conductive type can accurately control the size of the anode resistance, eliminates the impact on the output characteristics of the device fromthe snapback phenomenon, and improves the stability of the device.

The present invention relates to semiconductor technology, and more particularly to a reverse conducting IGBT without a Snapback effect and a manufacturing method thereof. The main scheme of the invention is that: the collector structure at the back surface of an IGBT is improved, the reverse blocking voltage of the device is reduced as much as possible by optimizing the doping concentration and the thickness of a P++ collector region and an N++ layer, and the reverse conduction is achieved by adopting the avalanche breakdown effect and the tunnel breakdown effect in the reverse blocking mode.Compared to a conventional reverse-conducting IGBT, since there is no an N+ short-circuit region, and there is no transition from an MOSFET conduction mode to an IGBT conduction mode during forward conduction, the snapback phenomenon cannot occur when the forward conducting of the new reverse-conducting IGBT provided by the invention is performed. Since the threshold voltage of the reverse conducting of the novel reverse conducting IGBT proposed by the present invention is larger than that of the conventional reverse conducting IGBT, the reverse conducting IGBT is suitable for a case that theforward conducting time is mostly occupied such as a quasi-resonant circuit and the reverse conducting time is short. Besides, the novel reverse conducting IGBT provide in the invention has the advantages such as the small forward voltage drop and good soft recovery characteristics.

The silicon carbide MPS diode comprises a cathode ohmic contact electrode, a silicon carbide N + substrate and a silicon carbide N-epitaxial layer which are laminated from bottom to top, two P + injection regions are formed at the top of the silicon carbide N-epitaxial layer, the two P + injection regions are respectively contacted with the tops of the two P + buried layers I through the two P + buried layers II, and the widths of the P + injection regions and the P + buried layers I are greater than those of the P + buried layers II; two ohmic contact electrodes are arranged at the tops of the two P + injection regions, and a Schottky contact electrode is arranged between the two ohmic contact electrodes. The P + injection region and the P + buried layer I are connected through the narrow P + buried layer II, the proportion of PN junctions is increased in the epitaxial layer, and the snapback phenomenon during forward conduction of the MPS diode is eliminated; and meanwhile, the breakover voltage of the MPS diode from a unipolar working state to a bipolar working state is reduced, so that the diode enters the bipolar working state under a relatively low forward current, the high-current working temperature of the diode is reduced, and higher surge current resistance is achieved.

A semiconductor device includes an ESD protection device. In a N-well, two P+ doped regions form a collector and emitter of a parasitic transistor of the ESD protection device. The N-well area between the P+ doped regions, forms a base of the parasitic transistor. At some distance away from the P+ doped regions an N+ doped region is provided. The N-well in between the N+ doped region and base of the transistor forms a parasitic resistor of the ESD protection device. The N+ doped region and the emitter of the transistor are coupled to each other via an electrical connection. The ESD protection device has a limited snapback behaviour and has a well-tunable trigger voltage.

The invention discloses a snapback transient voltage suppressor, and belongs to the field of semiconductor protection devices. The suppressor comprises: an epitaxial layer formed on a substrate; a plurality of preset regions formed in the epitaxial layer and isolated by an isolation structures, wherein the first preset region and the fifth preset region comprise a first P+ region, a first N+ region and a second P+ region, the second preset region and the fourth preset region comprise a second N+ region, a third P+ region and a third N+ region, and the third preset region comprises a first P-type well region, a second P-type well region, a fourth N+ region formed in the second P-type well region, and two fourth P+ regions and two fifth N+ regions formed in the first P-type well region; a dielectric layer formed on the upper surface of the epitaxial layer, wherein the dielectric layer comprises metal holes corresponding to the P+ regions and the N+ regions; and a plurality of metal layers formed in each of the metal holes. The suppressor has the beneficial effects that the breakdown voltage and the trigger voltage are lower, the protection response is faster, the on resistance and the clamping voltage are smaller, and the protection capability for a post-stage integrated circuit is stronger.

The invention discloses a reverse conducting IGBT (Insulated Gate Bipolar Translator) capable of eliminating a voltage turn-back phenomenon, which comprises a semi-cellular structure, and the semi-cellular structure comprises a collector electrode structure, a voltage-withstanding layer structure, an emitter electrode structure and a grid electrode structure, the collector structure is located at one end of the voltage-withstanding layer structure, and the emitter structure and the gate structure are located at two sides of the other end of the voltage-withstanding layer structure; wherein the collector structure comprises a P + collector region, an N + collector region, an N-type buffer layer, a P + conductive material, collector metal, an N-type conductive material and floating metal; one side of the N-type buffer layer is connected to the voltage withstanding layer structure, one side of the P + collector region and one side of the N + collector region are connected to the other side of the N-type buffer layer, a gap is formed between the P + collector region and the N + collector region, and collector metal is arranged on the other side of the P + collector region; on the basis of a conventional reverse conducting IGBT structure, the snapback phenomenon is eliminated by optimizing and improving the collector electrode structure, and the reverse conducting current is more uniform.

The invention belonging to the technical field of microelectronics discloses a SiC MPS diode device and a preparation method thereof.The device comprises a cathode, an N + substrate, an N-epitaxial layer, P + injection regions and an anode which are sequentially arranged from bottom to top, and is characterized in that a trench structure is arranged between the two P + injection regions, N + injection regions are arranged between the two sides of the trench structure and the P + injection regions respectively, and the P + injection regions are surrounded by the N + injection regions to form awell structure. The SiC MPS diode device provided by the invention is provided with the trench structure; according to the SiC MPS diode device integrated with the trench structure, the internal potentials of the PiN structure and the Schottky structure can be promoted to be more uniform when the device is in forward conduction to be close to the potential distribution in the PiN body, so that thephenomenon of rapid return of voltage drop of the device is effectively inhibited; N + injection is additionally carried out on the original PiN diode on the basis of the trench type SiC MPS diode, and the purposes of improving the injection efficiency of the PiN transistor and improving the surge capacity of the device are achieved.

Embodiments of the present invention provide a transient voltage suppression device. The transient voltage suppression device includes a substrate, a first semiconductor layer of a first conductivitytype disposed on the substrate, a second semiconductor layer of a second conductivity type disposed on the first semiconductor layer, and a first well and a second well of the first conductivity typedisposed in the second semiconductor layer. The second well is disposed adjacent to the first well but separated from each other. The transient voltage suppression device further includes a first heavily doped region disposed between the first well and the second well and extending into the second conductivity type of the first well and the second well, a second heavily doped region of the first conductivity type disposed in the first well under the first heavily doped region, and a third heavily doped region of the first conductivity type disposed in the second well under the first heavily doped region. The transient voltage suppression device can reduce the snapback voltage of the transient voltage suppression device and further increase the secondary breakdown current.