25 results about "Snapback" patented technology

Technology for reading memory cells in a cross-point memory array. Each memory cell may have a threshold switching selector in series with a programmable resistance memory element. The memory system has control circuitry adjacent to the cross-bar memory array that is used to generate and deliver currents to the cross-bar memory array. The memory system temporarily provides capacitive isolation of the selected memory cell from capacitance of the adjacent circuitry while the snapback current is present. The memory system provides a discharge path to a node between the control circuitry and the selected memory cell during a period in which the capacitive isolation is removed.

Technology for reading memory cells in a cross-bar memory array. Each cell has a threshold switching selector in series with a programmable resistance memory element. A current diverting resistor is connected to a selected word line while a read current is driven to the selected word line. Driving the read current to the selected word line causes a voltage across the memory cell to increase until the threshold switching selector switches on. After the threshold switching selector switches on the voltage across the memory cell drops rapidly thereby resulting in a snapback current. Some of the read current is diverted to the current diverting resistor as the voltage across the memory cell increases. When the threshold switching selector switches on the resistor continues to divert current from flowing through the memory cell to prevent excessive current from inadvertently changing the state of the programmable resistance memory element.

The present invention relates to the technical field of electrostatic discharge (ESD), and provides an ESD device based on a PNPN structure. A first junction is formed between a first P-well and an N-well, and a second junction is formed between the N-well and a second P-well; a first ion implantation region is provided in the surface region of the first P-well; a second ion implantation region is provided in the surface region of the second P-well; a first N-ion boundary implantation region is provided at a first junction formed by the intersection of the surface region of the first P-well and the surface region of the N-well; a second N-ion boundary implantation region is provided at a second junction formed by the intersection of the surface region of the N-well and the surface region of the second P-well; and a parasitic discharge circuit spans the first P-well, the N-well, and the second P-well, and is respectively connected to the first ion implantation region and the second ion implantation region. The present invention reduces snapback voltage by setting a high-concentration boundary, thereby improving ESD performance.

Technology for reading programmable resistance memory cells in a cross-bar memory array. Each cell has a threshold switching selector in series with a programmable resistance memory element. Each memory cell has a capacitor associated therewith. One of the electrodes of the capacitor may be formed from a conductive region of the cell in contact with the threshold switching selector. When the threshold switching selector turns on the voltage across the memory cell may rapidly drop, thereby resulting in a snapback current. The capacitor is able to absorb at least some of the snapback current to therefore reduce or even eliminate snapback current flow through the memory element.

A transient voltage suppression device includes a first transient voltage suppression diode having a first clamping characteristic, and a second bounce diode having a second clamping characteristic in series with the first transient voltage suppression diode. The first transient voltage suppression diode and the second jump-back diode are electrically connected in parallel to the load.

Technology for reading memory cells having threshold switching selectors. A sense amplifier may have a set of capacitors that may be used to exchange charge with a sense node connected to the selected word line. A capacitor may be used to pull excess charge from the sense node or to provide charge to the sense node. A control circuit drives a current to the selected word line to charge up the selected word line to switch on the threshold switching selector of the selected memory cell. A capacitor may be connected to the selected word line when, or soon after, the threshold switching selector switches on. The capacitor may draw away excess charge to prevent a snapback current from flowing through the memory cell thereby preventing mis-reads. The capacitor may reduce read latency by speeding the rate of voltage change on a word line.

A method and apparatus for simulating breakdown of an electronic component are provided. The method includes: when a terminal of an equivalent circuit model receives test charges, pulling up a voltage level of a first node of the equivalent circuit model; when the voltage level of the first node reaches a first threshold, turning on a first voltage controlled switch to pull up a voltage level of a second node of the equivalent circuit model; when the voltage level of the second mode reaches a second threshold, turning on a second voltage controlled switch to pull down a voltage level of the terminal to a holding voltage level to simulate snapback breakdown of the electronic component; and turning on a third voltage controlled switch to pull down the voltage level of the second node to turn off the second voltage controlled switch, thereby simulating second breakdown of the electronic component.

The invention designs an RC-LIGBT device integrated with double self-biased MOS transistors and capable of reducing saturation current, and belongs to the technical field of semiconductors. The invention comprises a self-biased NMOS (N-channel Metal Oxide Semiconductor) at a collector side and a self-biased PMOS (P-channel Metal Oxide Semiconductor) at an emitter During forward conduction, the substrate of the self-biased NMOS inhibits electrons from directly reaching the collector through the collector N +, the Snapback effect is eliminated, injected holes enter the source of the self-biased PMOS, the voltage of the source is increased, self-biased opening of the PMOS is achieved, and the saturation current can be reduced through the caused hole extraction effect; during reverse conduction, a reverse electron current path of the device is provided after the self-biased NMOS is started, so that reverse conduction is realized; in the turn-off process, the opening of the self-bias NOMS provides an electron extraction channel, and the opening of the self-bias PMOS provides a hole extraction channel. According to the device, the Snapback effect is eliminated under the condition that an additional control electrode is not added, and compared with a traditional LIGBT, the saturation current is reduced by 21.2% when the collector voltage is 100 V, and the turn-off loss is reduced by 31.1%.

A snapback phenomenon in an RC-IGBT is suppressed. In a semiconductor device 100 comprising an IGBT region 21 and a diode region 22 on the same chip, an IGBT of IGBT region 21 has a drift layer 1 of a first conductivity type, a trench 3, a gate electrode 5 provided in the trench 3, a body layer 2 of a second conductivity type, an emitter layer 7 of the first conductivity type, a gate insulating film (insulating film 4), and a collector layer 11 of the second conductivity type. A diode of diode region 22 has the drift layer 1, a first semiconductor layer 12 of the second conductivity type, which is provided closer to a front side than the drift layer 1, and a second semiconductor layer 13 of the first conductivity type, which is provided closer to a back side than the drift layer 1.and the IGBT region 21 has a boundary column layer 8A of the second conductivity type at a boundary section with the diode region 22, which penetrates the drift layer 1 and is in contact with the body layer 2 and the collector layer 11.

Technology for reading memory cells in a cross-point memory array. Each memory cell has a threshold switching selector in series with a programmable resistance memory element. The memory system applies a step voltage pulse during a current force read of programmable resistance memory cells in a cross-bar memory array. In an aspect, the step voltage pulse is used to switch on the threshold switching selector. In an aspect, the step voltage pulse is applied after the threshold switching selector switches on when a snapback current may be present. In an aspect, the step voltage pulse is applied after the snapback current has dissipated.

Technology for reading programmable resistance memory cells in a cross-bar memory array. Each cell has a threshold switching selector in series with a programmable resistance memory element. Each memory cell has a capacitor associated therewith. One of the electrodes of the capacitor may be formed from a conductive region of the cell in contact with the threshold switching selector. When the threshold switching selector turns on the voltage across the memory cell may rapidly drop, thereby resulting in a snapback current. The capacitor is able to absorb at least some of the snapback current to therefore reduce or even eliminate snapback current flow through the memory element.

Technology for reading memory cells in a cross-point memory array. Each memory cell has a threshold switching selector in series with a programmable resistance memory element. The memory system applies a step voltage pulse during a current force read of programmable resistance memory cells in a cross-bar memory array. In an aspect, the step voltage pulse is used to switch on the threshold switching selector. In an aspect, the step voltage pulse is applied after the threshold switching selector switches on when a snapback current may be present. In an aspect, the step voltage pulse is applied after the snapback current has dissipated.

The embodiment of the invention provides an RC-IGBT device and a preparation method, the device comprises an N-drive region (1), a P + collector region (2) and an FS structure (3), and the FS structure (3) is connected below the N-drive region (1) and above the P + collector region (2); the lower structure and the upper structure are connected with the FS structure (3), the upper structure is connected to the N-drive region (1), the lower structure is connected to the P + Colletor region (2), and the phosphorus doping concentration of the lower structure is lower than that of the upper structure so as to increase the parasitic resistance above the P + Colletor region (2), that is, the short-circuit resistance of the P + Colletor region (2) at the collector side is increased, and the snapback phenomenon can be inhibited. And the width of the P + Collector region (2) is also reduced, so that the overall size of the primitive cell is reduced.

Technology for reading memory cells in a cross-point memory array. Each memory cell has a threshold switching selector in series with a programmable resistance memory element. The memory system applies a step voltage pulse during a current force read of programmable resistance memory cells in a cross-bar memory array. In an aspect, the step voltage pulse is used to switch on the threshold switching selector. In an aspect, the step voltage pulse is applied after the threshold switching selector switches on when a snapback current may be present. In an aspect, the step voltage pulse is applied after the snapback current has dissipated.

A silicon-on-insulator (SOI) power device with introduced fixed charges is provided. The SOI power device is a shorted-anode—lateral insulated gate bipolar transistor (SA-LIGBT) or separated shorted-anode—lateral insulated gate bipolar transistor (SSA-LIGBT) structure, and includes a semiconductor substrate, a dielectric buried layer, and a semiconductor active layer stacked in sequence, where a first charge layer is provided between the dielectric buried layer and the semiconductor active layer, and / or a second charge layer is provided between a field oxide layer and the semiconductor active layer; and the charge layer carries continuously and uniformly distributed positive charges. The snapback present in the output characteristics of the traditional SA-LIGBT or SSA-LIGBT is addressed. By inserting the fixed charges between the dielectric buried layer and the semiconductor active layer, the SOI power device reduces the voltage of the snapback effect and significantly suppresses the occurrence of the snapback phenomenon.

An ESD protection device protects a circuit from TLPs between a first terminal and a second terminal. The device includes an NPN discharge structure and a PNP triggering device. The first terminal is coupled to the p-doped emitter and the n-doped base of the PNP triggering device and also the n-doped emitter of the NPN discharge structure. The second terminal is coupled to the n-doped collector of the NPN discharge structure. The p-doped collector of the PNP triggering device is coupled to the p-doped base of the NPN discharge structure. A TLP causes base-collector junction breakdown in the PNP triggering device, which results in a current through the PNP triggering device. That current is injected into the base of the NPN discharge structure, which results in a larger discharge current through the NPN discharge structure. The device provides high holding voltage ESD protection device with snapback.

The invention provides a method for inhibiting the hysteresis effect of a trench metal oxide semiconductor field effect transistor. The method aims at solving the hysteresis problem caused by a parasitic NPN triode formed at the corner of a table top in a low-turn-on-voltage short-channel device. The method comprises the following steps of: firstly, performing source region injection in a body region of a semiconductor substrate to form a source region; then, an interlayer dielectric layer is deposited on the grid electrode and the source region to cover the grid electrode; and finally, performing expansion processing on the source region. An interlayer dielectric layer is deposited in advance before high-temperature expansion, so that a path of outward diffusion of a dopant in a grid electrode is effectively blocked, and formation of a parasitic NPN triode is inhibited from the source. According to the invention, the voltage-resistant stability of the device can be obviously improved, the hysteresis phenomenon is eliminated, and the reliability and production yield of the device are improved.

The application relates to the technical field of semiconductors, and particularly discloses an ESD protection device with a folding trigger mechanism and a preparation method thereof. The method comprises a P-type substrate; an N-type well layer and a P-type well layer formed in the substrate; at least one P-type doped layer formed on the surface of the N-type well layer; at least one N-type doped layer formed on the surface of the P-type well layer; a third groove arranged between the N-type well layer and the P-type well layer; and a suspended electric field modulation structure arranged on the third groove. The application introduces the suspended electric field modulation structure, realizes dynamic electric field regulation of the SCR trigger process without increasing the device leakage and changing the main discharge path, and makes the device have low trigger voltage, moderate holding voltage, excellent large-current discharge capacity and good static reliability.

The present disclosure relates to random value generators. The present disclosure includes systems, devices, and methods related to generating random data values. For example, a first read operation can be performed on a memory cell programmed to a first state, where the first read operation is performed using a first read voltage that is within a predetermined threshold voltage distribution corresponding to the first state. A program signal can be applied to the memory cell in response to the first read operation resulting in a snapback event, where the program signal is configured to place the memory cell in a second state. A second read operation can be performed using a second read voltage that is between the predetermined threshold voltage distribution corresponding to the first state and a second threshold voltage distribution corresponding to the second state to determine whether the memory cell is in the first state or the second state.

Technology for reading memory cells in a cross-point memory array. Each memory cell may have a threshold switching selector in series with a programmable resistance memory element. The memory system has control circuitry adjacent to the cross-bar memory array that is used to generate and deliver currents to the cross-bar memory array. The memory system temporarily provides capacitive isolation of the selected memory cell from capacitance of the adjacent circuitry while the snapback current is present. The memory system provides a discharge path to a node between the control circuitry and the selected memory cell during a period in which the capacitive isolation is removed.

The silicon carbide MPS diode disclosed by the application comprises, from bottom to top, a cathode ohmic contact electrode, a silicon carbide N+ substrate and a silicon carbide N- epitaxial layer; two P+ implantation regions are formed on the top of the silicon carbide N- epitaxial layer, the two P+ implantation regions are in contact with the top of two P+ buried layers I through two P+ buried layers II respectively, the width of the P+ implantation region and the P+ buried layer I is greater than that of the P+ buried layer II; two ohmic contact electrodes are arranged on the top of the two P+ implantation regions, and a Schottky contact electrode is arranged between the two ohmic contact electrodes. The narrow P+ buried layer II is used to connect the P+ implantation region and the P+ buried layer I, the proportion of the PN junction in the epitaxial layer is increased, and the snapback phenomenon of the MPS diode in the forward conduction is eliminated; meanwhile, the transition voltage of the MPS diode from the unipolar working state to the bipolar working state is reduced, so that the diode enters the bipolar working state under a lower forward current, the working temperature of the diode under a large current is reduced, and the diode has a higher surge current resistance.

An ESD protection device protects a circuit from TLPs between a first terminal and a second terminal. The device includes an NPN discharge structure and a PNP triggering device. The first terminal is coupled to the p-doped emitter and the n-doped base of the PNP triggering device and also the n-doped emitter of the NPN discharge structure. The second terminal is coupled to the n-doped collector of the NPN discharge structure. The p-doped collector of the PNP triggering device is coupled to the p-doped base of the NPN discharge structure. A TLP causes base-collector junction breakdown in the PNP triggering device, which results in a current through the PNP triggering device. That current is injected into the base of the NPN discharge structure, which results in a larger discharge current through the NPN discharge structure. The device provides high holding voltage ESD protection device with snapback.

Embodiments of the present disclosure provide a circuit structure and method of controlling electrostatic discharge (ESD) events in a resistance-capacitance (RC) circuit. The circuit structure according to the present disclosure can include a trigger transistor coupled in parallel with the RC circuit, and a gate terminal coupled to a portion of the RC circuit. A mirror transistor coupled in parallel with the RC circuit passes a current less than the current through the trigger transistor. A snapback device has a gate terminal coupled to a source or drain of the mirror transistor, and a pair of anode / cathode terminals coupled in parallel with the RC circuit. A current at the gate terminal of the snapback device derived from the current in the mirror transistor controls anode / cathode current flow in the snapback device.

The application discloses a reverse conducting IGBT for eliminating snapback phenomenon, comprising a half cell structure, the half cell structure comprising a collector structure, a voltage resistance layer structure, an emitter structure and a gate structure; the collector structure is located at one end of the voltage resistance layer structure, the emitter structure and the gate structure are located at two sides of the other end of the voltage resistance layer structure; wherein the collector structure comprises a P+ collector region, an N+ collector region, an N type buffer layer, a P+ conductive material, a collector metal, an N type conductive material and a floating metal; one side of the N type buffer layer is connected to the voltage resistance layer structure, one side of the P+ collector region and the N+ collector region is respectively connected to the other side of the N type buffer layer, and the P+ collector region and the N+ collector region have a gap therebetween, and the other side of the P+ collector region has the collector metal; the application eliminates the snapback phenomenon and makes the reverse conducting current more uniform by optimizing and improving the collector structure on the basis of the conventional reverse conducting IGBT structure.

And the snapback phenomenon in the RC-IGBT is inhibited. In a semiconductor device (100) having an IGBT region (21) and a diode region (22) in the same chip, an IGBT in the IGBT region (21) has a drift layer (1) of a first conductivity type, a trench (3), a gate electrode (5) provided in the trench (3), a body layer (2) of a second conductivity type, an emitter layer (7) of the first conductivity type, a gate insulating film (insulating film (4)), and a collector layer (11) of the second conductivity type. The diode in the diode region (22) has a drift layer (1), a first semiconductor layer (12) of a second conductivity type provided closer to the front surface side than the drift layer (1), and a second semiconductor layer (13) of the first conductivity type provided closer to the back surface side than the drift layer (1). The IGBT region (21) has a boundary pillar layer (8A) of the second conductivity type at a boundary with the diode region (22), the boundary pillar layer (8A) penetrating the drift layer (1) and being in contact with the body layer (2) and the collector layer (11).