230results about How to "Improve transconductance" patented technology

A semiconductor structure and a method of manufacturing a silicon on insulator (SOI) structure having a silicon germanium (SiGe) layer interposed between the silicon and the insulator. According to one manufacturing method, a first SiGe layer, a silicon layer, and a second SiGe layer are epitaxially grown in sequence over a first substrate, and then an insulating layer is formed on the second SiGe layer. Then, impurity ions are implanted into a predetermined location of the first substrate underlying the first SiGe layer to form an impurity implantation region. A second substrate is bonded to the insulating layer on the first substrate. After the first substrate is separated along the impurity implantation region and removed, the first SiGe layer remaining on the surface of the separated region is removed so that the surface of the silicon layer may be exposed.

A transistor structure optimizes current along the A-face of a silicon carbide body to form an AMOSFET that minimizes the JFET effect in the drift region during forward conduction in the on-state. The AMOSFET further shows high voltage blocking ability due to the addition of a highly doped well region that protects the gate corner region in a trench-gated device. The AMOSFET uses the A-face conduction along a trench sidewall in addition to a buried channel layer extending across portions of the semiconductor mesas defining the trench. A doped well extends from at least one of the mesas to a depth within the current spreading layer that is greater than the depth of the trench. A current spreading layer extends between the semiconductor mesas beneath the bottom of the trench to reduce junction resistance in the on-state. A buffer layer between the trench and the deep well further provides protection from field crowding at the trench corner.

A method of forming an SRAM cell device includes the following steps. Form pass gate FET transistors and form a pair of vertical pull-down FET transistors with a first common body and a first common source in a silicon layer patterned into parallel islands formed on a planar insulator. Etch down through upper diffusions between cross-coupled inverter FET transistors to form pull-down isolation spaces bisecting the upper strata of pull-up and pull-down drain regions of the pair of vertical pull-down FET transistors, with the isolation spaces reaching down to the common body strata. Form a pair of vertical pull-up FET transistors with a second common body and a second common drain. Then, connect the FET transistors to form an SRAM cell.

The invention discloses a gain increased operational transconductance amplifier which is formed in a manner that a bias constant current source is sequentially connected with differential input, a load current mirror, a cascode output stage and an adjustable auxiliary differential pair in sequence, wherein the differential input is composed of four PMOS pipes namely M1a, M2a, M1b and M2b; the load current mirror is composed of six NMOS pipes namely M3, M4, M5a, M6a, M5b and M6b; the cascode output stage is composed of six MOS pipes namely M7, M8, M9, M10, M11 and M12; the adjustable auxiliary differential pair is composed of M13, M14 and M15. Reutilization of current and the output stage increased adjustable auxiliary differential pair thoroughly solve the inherent contradiction among gain, bandwidth, power dissipation and the like in a circuit; the gain increased operational transconductance amplifier is slightly influenced by output voltage, an additional pole is not introduced, the simulation results show same static power dissipation, and multiplication is realized for gain and bandwidth; the gain increased operational transconductance amplifier further has the characteristics of fine tuning and high accuracy and is applicable to communication, electronic measurement and automatic control systems.

A method, and a resulting device, for fabricating a heterojunction bipolar transistor (HBT). HBT devices have a high transconductance typical of bipolar devices and are additionally capable of high-power operation. To achieve the aforementioned characteristics, HBT devices are generally of the npn type, preferably with a thin, heavily doped base. The thin, heavily doped base maintains a low base-spreading resistance, leading to a high maximum oscillation frequency. In order to maintain a high doping concentration while minimizing outdiffusion of the dopant material, carbon is remotely doped into the base region. Details of the carbon dopant techniques and procedures are described with respect to fabrication of an exemplary HBT device.

The embodiment of the invention discloses a low dropout linear regulator, a method for improving the stability of the low dropout linear regulator and a phase-locked loop. The low dropout linear regulator comprises a reference voltage source, an error amplifier, an adjustment circuit, a load, a first compensating circuit and a second compensating circuit. The first compensating circuit is coupled with the adjustment circuit and used for adjusting a dominant pole and a secondary dominant pole of the low dropout linear regulator to adjust the phase margin. The second compensating circuit is used for adjusting the dominant pole of the low dropout linear regulator on the basis that the dominant pole and the secondary dominant pole of the low dropout linear regulator are adjusted by the first compensating circuit, further increasing the secondary dominant pole to adjust the phase margin and adjusting the gain bandwidth product of the low dropout linear regulator. By means of the low dropout linear regulator, the value of the gain bandwidth product and the dominant pole can be remarkably reduced, the secondary dominant pole can be increased, and therefore the error amplifier has the better noise performance.

The invention discloses a radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS) component. A light dope P type buried layer and a middle dope buried layer in the light dope P type buried layer are additionally arranged under a P type channel region. The base electrode resistance of a parasitic non-protein nitrogen (NPN) pipe can be reduced, so that snapback effect is not prone to be generated. A reversed diode formed by a source electrode, the channel and the buried layer can strangulate drain-source voltage of an LDMOS and can sink extra current on a substrate. Thick gate oxide at the drain electrode end can reduce hot carrier effect, and thin gate oxide at the source electrode end can improve transconductance of the component. The invention further discloses a manufacture method of the RF LDMOS component. In process realization, the manufacture method only adds two photoetching steps in an existing process so as to be easy to implement.

An integrated optical waveguide has a first optical waveguide, a second optical waveguide, and a groove. The second optical waveguide is coupled to the first optical waveguide and has a refractive index that is different from the first optical waveguide. The groove is disposed so as to traverse an optical path of the first optical waveguide and is separated from an interface between the first optical waveguide and the second optical waveguide by a predetermined spacing. The spacing from the interface and the width of the groove are determined such that reflection at a boundary between the first optical waveguide and the second optical waveguide is weakened. A semiconductor board may be disposed at a boundary between the first optical waveguide and the second optical waveguide. In this case, the width of the groove and the thickness of the semiconductor board are determined such that light reflected off an interface between the first optical waveguide and the groove is weakened by light reflected from an interface between the groove and the semiconductor board, and by light reflected from an interface between the semiconductor board and the second optical waveguide.

The present invention relates to a depletion or enhancement mode metal transistor in which the channel region of a transistor device comprises a thin film metal or metal composite layer formed over an insulating substrate.

The present invention relates to a semiconductor power device and power integrated circuits (ICs). The lateral SOI MOSFET in the present comprises a trench gate extended to the dielectric buried layer, one or multiple dielectric trenches in the drift region, and a buried gate in said dielectric trench. The permittivity of the dielectric in said dielectric trench is lower than that of said active layer. Firstly, said dielectric trench not only greatly improves breakdown voltage, but also reduces pitch size. Secondly, the trench gate widens the effective conductive region in the vertical direction. Thirdly, dual gates of said trench gate and buried gate increase channel and current densities. Thereby, specific on-resistance and the power loss are reduced. The device of the present invention has many advantages, such as high voltage, high speed, low power loss, low cost and ease of integration. The device in the present invention is particularly suitable for power integrated circuits and RF power integrated circuits.

The present invention discloses a carborundum secondary epitaxy material structure used for carborundum preparation comprising of: a carborundum single crystal substrate, a first homoepitaxy layer on surface of substrate, a secondary epitaxy material on surface of first homoepitaxy which comprises of p-type carborundum buffer layer, n-type carborundum active layer and unintentional doped intrinsic carborundum layer. Corresponding to MESFET (metal mosfet) with common structure, the MESFET fabricated by secondary epitaxy type has merits of small source-drain resistance, large ohm interface and uniform electric field distribution of working field in MESFET, can enhance transconductance, improve working voltage and power of appliance, and at the same time, the technique of preparation is simplified and the stability of appliance is ensured.

The invention discloses a nanowire based vertical circular grating transistor and a preparation method thereof. According to the structure, a conducting channel material is an intrinsic or low doped nanowire perpendicular to a substrate; a low-resistance nanowire is connected above the intrinsic or low doped nanowire in a gapless manner; the intrinsic or low doped nanowire is surrounded by a source electrode, a gate medium and a gate electrode sequentially from bottom to top; the source electrode and the gate medium as well as the gate medium and the grate electrode are connected in the position of the side wall of the nanowire in a gapless manner; the low-resistance nanowire is surrounded by a drain electrode; and three isolation layers are arranged among the electrodes. The invention further provides the preparation method of the transistor. Both the source electrode and the gate electrode are obtained with the method that firstly, a metal film is plated and then metal above BCB (benzocyclobutene) is eroded by using BCB as a mask; and the low-resistance nanowire is obtained through heavy doping of the intrinsic or low doped nanowire or through metal alloy. According to the short-channel transistor structure and the preparation method, a device with a short channel can be prepared, the parasitic resistance and the parasitic capacitance can be effectively reduced, and the device performance is improved.

The invention belongs to the technical field of electronics and relates to the frequency compensation technology of operational amplifiers in analog integrated circuits. The split compensation two-stage operational amplifier comprises a two-stage operational amplifier. A first-stage operational amplifier is composed of N-channel metal oxide semiconductor (NMOS) tubes (M1N, M2N, M3 and M4) and P-channel metal oxide semiconductor (PMOS) tubes (M1P, M2P and M0). A second-stage operational amplifier is composed of a PMOS tube M5P and an NMOS tube M5N. A traditional Miller capacitor is divided into a Cm1 portion and a Cm2 portion to finish frequency compensation of the operational amplifier. A first frequency compensation capacitor Cm1 is connected with the position between the output end of the first operational amplifier and the output end of the whole two-stage operational amplifier. A second frequency compensation capacitor Cm2 is connected with the position between a connection point of a source of the NMOS tube M2N and a drain of the NMOS tube M4 in the first-stage operational amplifier and the output end of the whole two-stage operational amplifier. The split compensation two-stage operational amplifier has strong robustness and higher unit grain bandwidth and output slew rate due to the fact that non-dominant poles and stray parameter are not related.

The invention discloses a heterogeneous metal stacked grid strained silicon-germanium on insulator p-channel metal oxide semiconductor field effect tube (SSGOI pMOSFET) device structure, which comprises a heterogeneous metal stacked grid structure, a grid insulation layer, an intrinsic or n-doped strained Si channel layer, a strained Si1-xGex layer of which an intrinsic or n-doped component is changed gradually, an n-doped relaxation Si1-yGey layer, a stepped oxygen buried layer and an n-doped substrate part sequentially from top to bottom, wherein the n-doped substrate part consists of four parts, namely an n<+>-doped relaxation Si1-yGey layer, an n<->-doped relaxation Si1-yGey buffer layer, an n-doped relaxation SiGe gradient layer and an n<->-doped monocrystal Si(100) substrate. The device has a simple structure, can be totally compatible with the conventional Si silicon on insulator (SOI) process, is integrated with the advantages of grid engineering, strain engineering and substrate engineering, and makes a complementary metal-oxide-semiconductor structure process simply integrated.