131 results about "Slew rate" patented technology

A method of driving a transistor between switching states includes controlling a transition of a gate voltage at a gate terminal of a transistor during each of a plurality of turn-off switching events to turn off the transistor, wherein the transistor is configured to be turned off according to a desaturation time during each of the plurality of turn-off switching events; measuring a transistor parameter indicative of a voltage slew rate of the transistor for a first turn-off switching event during which the transistor is transitioned from an on state to an off state; and regulating a duration of the desaturation time for a next turn-off switching event based on the measured transistor parameter.

A display driving circuit may include a source driver that includes a decoder circuit and a buffer circuit. The decoder circuit selects a first gamma voltage and a second gamma voltage among a plurality of gamma voltages based on pixel data, and selects a third gamma voltage different from the first and second gamma voltages among the plurality of gamma voltages. The buffer circuit interpolates between the first and second gamma voltages to output a first target voltage, and steps up or steps down a source voltage formed on the source line to the first target voltage. The buffer circuit includes a fast slew circuit that compares the first source voltage with the third gamma voltage to adjust slew rate of the first source voltage.

A control circuit for generating a control parameter that defines a state sequence of a power converter may include a loop filter configured to, based on an error signal between a reference current signal and a feedback current measurement signal, correct for unmodeled errors in the feedback current measurement signal to generate the control parameter. The control circuit may also include a first feedforward block configured to generate a first offset to the control parameter based on a slew rate of the reference current signal.

The invention provides a current multiplexing type output amplifier. The current multiplexing type output amplifier comprises a current multiplexing type input stage, a first self-biased diode pair, a second self-biased diode pair, a first AB type output stage and a second AB type output stage, wherein the first self-biased diode pair and the second self-biased diode pair are connected with the current multiplexing type input stage; the first AB type output stage is connected with the first self-biased diode pair; according to the invention, two self-biased diode pairs are adopted to replace a floating voltage source in the prior art. When a large pulse signal is input, one diode in each of the two diode pairs is in a cut-off state, transient change current I only flows into or out of the output end from a certain branch, and compared with a traditional amplifier, the slew rate is multiplied under the same bias current condition. In addition, the input stage adopts a current multiplexing type architecture combining a PMOS (P-channel Metal Oxide Semiconductor) and an NMOS (N-channel Metal Oxide Semiconductor), under the same bias current, the equivalent input transconductance is the sum of the transconductance of the PMOS and the transconductance of the NMOS, and the unity gain bandwidth is also multiplied.

This invention provides an adaptive slew rate enhancement circuit for CMOS operational amplifiers, used for adaptively increasing the slew rate of a two-stage operational amplifier with rail-to-rail input and floating Class AB output. The circuit is characterized by including at least a positive slew rate enhancement circuit and a negative slew rate enhancement circuit connected to the rail-to-rail input floating Class AB operational amplifier. The positive slew rate enhancement circuit accelerates the time it takes for the output voltage VOUT to rise with the input voltage VIP, and the negative slew rate enhancement circuit accelerates the time it takes for the output voltage VOUT to fall with the input voltage VIP. A corresponding control method is also provided. Under the action of the positive and negative slew rate enhancement circuits provided by this invention, the speed at which the output voltage VOUT builds up to 99% is increased by approximately 60% and 40%, respectively, when the input voltage VIP changes. This patent proposes an enhancement circuit that is simple, low-cost, and can significantly improve the driving speed of the operational amplifier.

The application discloses a dynamic biasing circuit and method for improving the slew rate of an operational amplifier, which comprises PMOS tubes PM1-PM9, NMOS tubes NM1-NM3, resistors R11, R12, R2, R31 and R32, and detects the step jump of the operational amplifier; the greater the step jump, the greater the differential mode value, the greater the tail current, the greater the working current of the main operational amplifier, the faster the establishment, and the greater the SR; when the step jump is small or no jump, the static current is very small. The dynamic biasing circuit of the application has the advantages of simple structure, rapid response, easy integration and no influence on other performances of the operational amplifier, can efficiently detect the jump of the input signal and instantaneously provide additional driving current, so that the large signal transient response speed of the operational amplifier is fundamentally improved without sacrificing the static power consumption.

This invention provides an optimized system for improving the slew rate of a Line Driver, comprising a differential input module, a bias current module, an amplification module, an active load module, and a mirror load module. The differential input module receives the input signal and converts the voltage signal into a current signal. The bias current module provides a stable bias current to the circuit. The amplification module receives the current signal from the differential input module and achieves voltage gain. The amplification module is electrically connected to the active load module. The active load module can improve the amplification gain of the amplification module, replicate the current, and stabilize the output node. The mirror load module can replicate the signal amplification path of the amplification module to achieve symmetrical output, thereby improving the signal amplification effect and anti-interference reliability of the circuit and solving the problem of limited slew rate in traditional optimized systems for Line Drivers.

Average power tracking (APT) systems with fast transient settling are disclosed. In certain embodiments, an APT system is used to provide a power amplifier supply voltage to a power amplifier that amplifies a radio frequency (RF) signal. The APT system controls the power amplifier supply voltage to track an average power of the RF signal, and includes a DC-to-DC converter that is assisted by an error amplifier in transitioning from one power amplifier supply voltage level to another power amplifier supply voltage level. Thus, the combination of a DC-to-DC converter with a fast changing error amplifier can swing enough AC voltage with a low enough slew rate to be able to rapidly transition the power amplifier supply voltage from one APT voltage level to another APT voltage level.

A system includes a control valve with a first control port and a second control port. An actuator of the system includes a piston between an extend chamber and a retract chamber. The system also includes a shutoff valve fluidically connected between the control valve and the actuator. The shutoff valve is passively controlled by a pressure differential between the extend chamber and the retract chamber. If the pressure differential between the extend chamber and the retract chamber exceeds normal operating pressures for the actuator, the shutoff valve closes to stop pressure and flow communication between the control valve and the actuator, thereby pausing the actuator. When the pressure differential between the extend chamber and the retract chamber returns to the normal operating pressures for the actuator, the shutoff valve passively returns to an equilibrium position that allows the actuator to resume operation.

The present application discloses a low-power-consumption self-biased slew-rate-enhanced circuit and an integrator. The enhanced circuit comprises: a self-biased control circuit used for outputting a bias voltage on the basis of an output voltage of an input voltage measurement circuit; the input voltage measurement circuit connected to the self-biased control circuit and used for measuring the magnitude of a differential input voltage; and a slew rate control circuit used for providing, when the voltage of a differential input voltage end exceeds a starting voltage, a sourcing current or a sinking current for an output end of an operational amplifier, and when the voltage of the differential input voltage end does not exceed the starting voltage, not generating an additional current or not generating a slew rate enhancement effect. In the present invention, an additional bias voltage or bias current does not need to be input, a static current is not consumed when the function of the slew-rate-enhanced circuit is not enabled, and a static bias current of an operational amplifier does not need to be increased when the slew-rate-enhanced circuit is started, so that fast charging and discharging of a large capacitance load can be achieved without affecting a small signal frequency domain characteristic of the operational amplifier, and a bidirectional slew rate of the operational amplifier is enhanced, thereby meeting low-power consumption and high-speed design requirements of an integrated circuit.

The application discloses a delay circuit and a driving device. The delay circuit can include at least two branches in parallel, each of the at least two branches has different delay; the delay circuit includes at least one register for controlling one of the at least two branches to be turned on, so that the delay circuit generates the delay corresponding to the turned-on branch. Since the greater the delay of the input signal is, the smaller the slew rate is, the slew rates of the input signal through any one of the at least two branches are different. The at least one register controls one of the at least two branches to be turned on, so that the slew rate of the output signal can be adjusted, and the slew rate of the output signal can be compatible with different protocols or different modes under the same protocol.

A technique of charging a capacitive load is presented in which the load is charged by current pulses in a sequence of stages. The amplitude of the current pulses in each stage increases from one stage to the next. Transition between stages is triggered by the voltage across the load meeting a threshold requirement, until a target voltage is reached. The slew rate of a rising edge of each current pulse is lower than the sew rate of the falling edge.

This invention provides a transmitter circuit for a CAN bus, relating to the field of CAN bus communication. The circuit includes: a common-mode feedback circuit for generating first and second gate voltages; a slew rate control circuit comprising a CANH terminal circuit for receiving the first gate voltage and a CANL terminal circuit for receiving the second gate voltage, each terminal circuit including multiple sequentially connected delay units and power transistors, the delay units controlling the gate voltage of the power transistors stage by stage to alternately switch the power transistors; and a port positive and negative high-voltage protection circuit, respectively connected between the output terminals of the CANH and CANL terminal circuits and the bus port, for protecting against positive and negative high voltages on the bus and suppressing parasitic effects. The beneficial effects are: by controlling the switching of the power transistors stage by stage through the delay units, the current surge rate is reduced, and electromagnetic radiation is reduced; by stabilizing the gate voltage and balancing the output current through common-mode feedback, signal symmetry is improved and common-mode interference is suppressed.

A circuit includes a first transistor having a control terminal and includes a predriver having an input and an output. The output is coupled to the control terminal of the first transistor. A second transistor of a first polarity has a control terminal coupled to the output of the predriver. A third transistor of a second polarity has first and second terminals. The first terminal of the third transistor is coupled to the control terminal of the second transistor. A fourth transistor having the second polarity has first and second terminals. The first terminal of the fourth transistor is coupled to the second terminal of the third transistor. The second terminal of the fourth transistor is coupled to a supply terminal.

The application belongs to the technical field of amplifiers, and relates to a cyclic structure amplifier, in particular to a high-gain transconductance-enhanced cyclic structure amplifier. The cyclic structure amplifier comprises PMOS tubes P1a, P1b, P2a, P2b, P5, P6, P7, P8 and P9, and NMOS tubes N1, N2, N3, N4, N5a, N5b, N6a, N6b, N7a, N7b, N8a and N8b. The drain of the PMOS tube P1b is connected to the gate of the NMOS tube N5b. The drain of the PMOS tube P2b is connected to the gate of the NMOS tube N6b. The NMOS tube N5b and the PMOS tube P1b and the NMOS tube N6b and the PMOS tube P2b form a cross positive feedback path, which can enhance the transconductance of the PMOS tubes P1b and P2b. The high-gain transconductance-enhanced cyclic structure amplifier provided by the application has a transconductance five times that of a conventional folded cascode operational amplifier and a nine-time higher slew rate than that of the folded cascode operational amplifier.

A circuit includes a latch, a first variable resistor, a second variable resistor, a slew detector, and a conductor configured to provide a power supply voltage. The latch has a first latch input, a second latch input, a first latch output, and a second latch output. The first variable resistor has a first terminal coupled to the conductor, a second terminal coupled to the first latch input, a first control input, and a second control input coupled to the first latch output. The second variable resistor has a first terminal coupled to the conductor, a second terminal coupled to the second latch input, a third control input, and a fourth control input coupled to the second latch output. The slew detector is coupled to the conductor. The slew detector has an output coupled to the first control input and the third control input.

According to one embodiment, an electronic circuitry includes: a timing detector configured to detect a voltage generated in a parasitic inductance of a switching element, the driving of the switching element being controlled in accordance with a control signal and to detect a first timing at which the voltage becomes lower or higher than a predetermined value, and a second timing, occurring after the first timing, at which the voltage becomes higher or lower than the predetermined value; and a calculator configured to calculate a slew rate of a current flowing through the switching element based on a current flowing through the switching element at the first timing and the second timing.

The present application relates to a slew rate enhancement circuit, comprising: a comparator comparing a first differential input voltage and a second differential input voltage and generating a dynamic current; a first boost current supply terminal mirroring the generated dynamic current and supplying the dynamic current to a main source amplifier circuit section if the dynamic current is generated; and a second boost current supply terminal additionally supplying the dynamic current to the main source amplifier circuit section based on an operation of a timing controller.

The present disclosure relates to techniques for measuring slew rate in a current integrating phase interpolator. An apparatus is described that includes a current integrating phase interpolator core having a programmable bias current; an inverter circuit coupled to an output of the current integrating phase interpolator core for receiving a signal containing a periodic sawtooth waveform therefrom; a digital-to-analog (D / A) converter for setting an input common mode voltage of the inverter circuit; a duty cycle measurement (DCM) circuit for measuring a duty cycle distortion (DCD) of a clock signal output from the inverter circuit; and a circuit for calculating a difference between a first state of the DCD of the clock signal corresponding to the inverter circuit being set to a high voltage input common mode voltage and a second state of the DCD of the clock signal corresponding to the inverter circuit being set to a low voltage input common mode voltage.

A display driving circuit may include a source driver that includes a decoder circuit and a buffer circuit. The decoder circuit selects a first gamma voltage and a second gamma voltage among a plurality of gamma voltages based on pixel data, and selects a third gamma voltage different from the first and second gamma voltages among the plurality of gamma voltages. The buffer circuit interpolates between the first and second gamma voltages to output a first target voltage, and steps up or steps down a source voltage formed on the source line to the first target voltage. The buffer circuit includes a fast slew circuit that compares the first source voltage with the third gamma voltage to adjust slew rate of the first source voltage.

The invention discloses an emission driver capable of controlling the slew rate and reducing the internal pressure difference, and belongs to the technical field of signal drivers, and the emission driver comprises a level conversion circuit, a pre-driving circuit and an output circuit. The level conversion circuit generates a first data signal according to an input data signal and generates a first control signal according to an enable signal. The pre-driving circuit generates a second data signal and a second control signal according to the first data signal and the first control signal, and adjusts the level of the first output node according to the first data signal and the first control signal. The output circuit selectively pulls up the level of the second output node according to the second data signal and selectively pulls down the level of the second output node according to the second control signal so as to generate an output data signal through the second output node. The output circuit includes a switched capacitor array coupled between the first and second output nodes for adjusting a slew rate of the output data signal.

Processor load slew rate may be controlled to help avoid undesirable supply voltage effects such as overshoot or undershoot. A dynamic processor load current budget may be set during each of successive time intervals, and processor activity level may be throttled according to the dynamic processor load current budget.

The utility model relates to a sectional driving framework for detecting and adjusting the slew rate of a BOOST power tube, which comprises a logic and dead zone module for receiving a PWM (Pulse Width Modulation) signal, and a level shift module, a high-side driving circuit and a high-side power tube which are sequentially connected with the logic and dead zone module, the slope detection and dynamic adjustment module, the low-side driving circuit and the low-side power tube are sequentially connected with the logic and dead zone module, the slope detection and dynamic adjustment module is connected with a source electrode of the high-side power tube and a drain electrode of the low-side power tube, and the logic and dead zone module processes the PWM signal and then generates a switch control signal. The slope detection and dynamic adjustment module receives the switch control signal, detects the slew rate of the low-side power tube when the low-side power tube is turned off, and controls the parallel number of driving tubes in the low-side driving circuit according to a detection result, and the low-side driving circuit outputs a low-side driving signal according to the parallel number of the driving tubes; and the low-side driving signal controls the on and off of the low-side power tube.

An electronic device is provided. The electronic device includes a slew rate control circuit. The slew rate control circuit includes a first transistor, a second transistor, an input terminal, and an output terminal. The slew rate control circuit is configured to receive a scan signal switching between a first high voltage level and a first low voltage level, and output an adjusted scan signal switching between a second high voltage level and a second low voltage level. The first transistor and the second transistor are the same type of transistors, and each forms a diode or a source follower amplifier.

This application relates to methods and apparatus for controlling slew-rate of components for outputting an analogue output signal. Described is a signal processing circuit having a forward signal path for receiving an input signal and outputting an analogue output signal. The signal processing circuit has a first component located in said forward signal path for outputting the analogue output signal. A predictor is configured to predict a required slew-rate for the first component based on the input signal and a controller is configured to controllably vary an output slew-rate limit of the first component based on the prediction of required slew-rate.

A power supply device for supplying power to an electronic device. The power supply device includes a switched mode power supply (SMPS) comprising at least one switching element and configured to convert an input power input to the power supply device to the power supplied to the electronic device; and a controller configured to obtain a voltage and / or a current of the input power, determine a load of the electronic device based on the obtained voltage and / or current, and set a slew rate of the at least one switching element based on the obtained load.

A signal transmission device includes a primary side circuit that receives a primary side control signal from the external device, a secondary side circuit that drives a gate of the target transistor, and an insulation circuit that transmits a primary side control signal as a secondary side control signal to the secondary side circuit in an insulation form. The secondary side circuit is configured to control a gate voltage of the target transistor in accordance with the secondary side control signal so as to switch the target transistor between ON and OFF, and to be capable of adjusting a slew rate of change of the gate voltage of the target transistor in multiple steps. The secondary side circuit generates temperature information according to temperature of the target transistor, and compares the temperature information with reference information, so as to adjust the slew rate.

Disclosed in the present invention is a two-stage cascaded high-gain amplifier based on adaptive biasing and cascode compensation. Said amplifier uses the basic structure of a two-stage cascaded amplifier, where a first stage uses an adaptively biased cascode floating inverting amplifier structure, which significantly improves the gain by means of cross-coupled biasing while obtaining a larger current to increase the bandwidth and slew rate, and eliminates the need for an external biasing circuit and an additional common-mode feedback circuit, and a second stage uses a current-source-biased inverting amplifier structure, which achieves a higher current efficiency by means of current reuse, and obtains a larger output swing. In addition, the present invention uses a cascode compensation circuit to eliminate the need for a nulling resistor required for Miller compensation, and offers overall advantages of high gain and high speed.

The invention discloses a Class-AB operational amplifier slew rate acceleration circuit and electronic equipment, the circuit comprises a first comparator and a second comparator, the input end of the first comparator comprises a first NMOS tube, a second NMOS tube and a first resistor, the input end of the second comparator comprises a third NMOS tube, a fourth NMOS tube and a second resistor, and the input end of the second comparator comprises a third NMOS tube, a fourth NMOS tube and a second resistor. The output end of the first comparator is connected to the grid end of the PMOS tube at the output end of the Class-AB operational amplifier; the output end of the second comparator is connected to the grid end of the NMOS tube at the output end of the Class-AB operational amplifier through a fifth NMOS tube; the positive input voltage of the Class-AB operational amplifier is simultaneously connected with the grid electrodes of the second NMOS tube and the third NMOS tube, and the negative input voltage of the Class-AB operational amplifier is simultaneously connected with the grid electrodes of the first NMOS tube and the fourth NMOS tube; the source electrode of the first NMOS tube is connected with a first resistor, and the source electrode of the third NMOS tube is connected with a second resistor. According to the invention, the response capability of the Class-AB operational amplifier to the change of the rapid input signal can be obviously improved.

This invention proposes a dynamic, adjustable slew rate CMTI testing method, relating to the field of power semiconductors. The method includes: constructing a test circuit connecting a high-voltage half-bridge switching circuit to the gate driver chip of the high-voltage non-isolated half-bridge under test; connecting variable gate resistors in series with the gates of the upper and lower transistors of the high-voltage half-bridge switching circuit, and using a dual-channel signal generator to output control signals with adjustable timing and phase relationships to the high-side input of the chip under test and the high-voltage half-bridge switching circuit, thereby generating common-mode transient interference with adjustable slew rate; performing static CMTI testing; performing dynamic CMTI testing; and comprehensively evaluating the common-mode transient immunity of the chip under test based on the static and dynamic CMTI test results. This invention enables a comprehensive evaluation of the common-mode transient immunity of the chip under test under both static and dynamic operating conditions.