277 results about "Slew rate" patented technology

A variable slew rate gate drive system for powering an electric machine. The system may include a gate driver operable for controlling each of a plurality of hybrid switch power modules between opened and closed states to facilitate powering the electric machine. The gate driver may be operable for selecting slew rates and controlling ON and OFF states of first and second semiconductor switches included as part of each power module to optimize powering of the electric machine by varying the slew rates as a function of performance characteristics of the first and second semiconductor switches.

The invention discloses a slew rate enhancement circuit of an operational amplifier, which comprises a comparison module used for comparing a positive input voltage and a negative input voltage of the operational amplifier and generating a first comparison signal and a second comparison signal according to a comparison result; the slew rate enhancing module is used for enhancing the slew rate of the falling edge of the output voltage of the operational amplifier according to the first comparison signal and enhancing the slew rate of the rising edge of the output voltage of the operational amplifier according to the second comparison signal; the common-mode feedback module is used for clamping the common-mode voltage of the first comparison signal and the common-mode voltage of the second comparison signal to a reference voltage when the operational amplifier is in a steady state, so that the slew rate enhancing module is in a closed state; therefore, the slew rate of the output voltage of the operational amplifier can be quickly enhanced when the operational amplifier has large step signal output, so that the output of the operational amplifier is quickly responded and established.

A buffer circuit configured to generate an output voltage according to an input voltage includes: an input stage configured to provide first and second differential currents to a load stage or receive third and fourth differential currents from the load stage based on a difference between the input voltage and the output voltage; a load stage configured to apply gate voltages to first and second output transistors of an output stage based on the first through fourth differential currents; the output stage configured to regulate the output voltage based on the gate voltages applied to the first and the second output transistors; and a slew rate compensator configured to regulate the gate voltages of the first and second output transistors by providing a source current to the load stage or receiving a sink current from the load stage.

In one aspect of the disclosure, a variable-current gate driver includes a plurality of inputs for receiving pulse-width-modulation (PWM) control signals transmitted from a processing system. Current sources controlled based on the pulse-width modulation (PWM) signals are coupled to respective gates of at least two transistors of a hybrid switch in the power module (PM) including different semiconductor technologies. The current sources are coupled respectively to at least one other non-gate terminal of the transistors. The current sources provide the slew rate control of the PM using variable current values to compensate for differences in the at least two semiconductor technologies in real-time to reduce switching losses and maximize efficiency.

A method of driving a transistor between switching states includes controlling a transition of a gate voltage at a gate terminal of a transistor during each of a plurality of turn-off switching events to turn off the transistor, wherein the transistor is configured to be turned off according to a desaturation time during each of the plurality of turn-off switching events; measuring a transistor parameter indicative of a voltage slew rate of the transistor for a first turn-off switching event during which the transistor is transitioned from an on state to an off state; and regulating a duration of the desaturation time for a next turn-off switching event based on the measured transistor parameter.

A circuit for slew rate detection and phase control in a multi-phase converter is provided. The circuit includes a first comparator configured to trigger when an output voltage of the multi-phase converter falls to a first output voltage level threshold value. The circuit further includes a second comparator configured to trigger when the output voltage falls to a second output voltage level threshold value which is lower than the first output voltage level threshold value. The circuit further includes a timer configured to start to run for a predefined time window, when the output voltage of the multi-phase converter falls below first output voltage level threshold value. The circuit further includes phase control logic configured to distinguish the ramp rate of the output voltage of the multi-phase converter as corresponding to a slow-rate ramp, a mid-rate ramp or a fast-rate ramp based on the outputs of the first comparator, the second comparator and the timer and enable phases synchronously or asynchronously based on the distinguishing of the ramp rate of the output voltage of the multi-phase converter as corresponding to the mid-rate ramp or the fast-rate ramp.

A method includes determining a current slew rate associated with a motor of the steering column, determining a speed slew rate associated with the motor, determining a current and speed slew rate threshold for the motor, and determining whether the current slew rate or the speed slew rate indicates a pinch event based on a comparison of the current slew rate, the speed slew rate, and the current and speed slew rate threshold. The method also includes, in response to a determination that at least one of the current slew rate and the speed slew rate indicates a pinch event, selectively instructing the motor to one of stop operation and reverse operation for a calibration period and, in response to the pinch event having a magnitude that is less than a pinch event threshold, selectively instructing the motor to continue operation.

A cascode switch device includes a normally-on switch device, a normally-off switch device, and a gate driver. The normally-on switch device has a first terminal, a second terminal and a control terminal. The normally-off switch device has a first terminal, a second terminal and a control terminal. The first terminal of the normally-off switch device is coupled to the second terminal of the normally-on switch device, and the control terminal of the normally-off switch device is coupled to the control terminal of the normally-on switch device. The gate driver is configured to provide a gate driver signal to the control terminal of the normally-on switch device to control a switching slew rate of a voltage at the first terminal of the normally-on switch device. The normally-on switch device is turned on or turned off in response to the gate driver signal.

The invention relates to a sectional driving framework for detecting and adjusting the slew rate of a BOOST power tube, which comprises a logic and dead zone module for receiving a PWM (Pulse Width Modulation) signal, and a level shifting module, a high-side driving circuit and a high-side power tube which are sequentially connected with the logic and dead zone module, the slope detection and dynamic adjustment module, the low-side driving circuit and the low-side power tube are sequentially connected with the logic and dead zone module, the slope detection and dynamic adjustment module is connected with a source electrode of the high-side power tube and a drain electrode of the low-side power tube, and the logic and dead zone module processes the PWM signal and then generates a switch control signal. The slope detection and dynamic adjustment module receives the switch control signal, detects the slew rate of the low-side power tube when the low-side power tube is turned off, and controls the parallel number of driving tubes in the low-side driving circuit according to a detection result, and the low-side driving circuit outputs a low-side driving signal according to the parallel number of the driving tubes; and the low-side driving signal controls the on and off of the low-side power tube.

A display driving circuit may include a source driver that includes a decoder circuit and a buffer circuit. The decoder circuit selects a first gamma voltage and a second gamma voltage among a plurality of gamma voltages based on pixel data, and selects a third gamma voltage different from the first and second gamma voltages among the plurality of gamma voltages. The buffer circuit interpolates between the first and second gamma voltages to output a first target voltage, and steps up or steps down a source voltage formed on the source line to the first target voltage. The buffer circuit includes a fast slew circuit that compares the first source voltage with the third gamma voltage to adjust slew rate of the first source voltage.

The invention is suitable for the technical field of integrated circuits, and provides a high-voltage operational amplifier. Comprising a biasing circuit, a first current mirror circuit, a first slew rate boosting circuit, a first gain circuit, a second gain circuit, a second current mirror circuit, an input stage circuit, an output stage circuit, a chopping switch circuit, a first high-voltage protection circuit, a third current mirror circuit, a fourth current mirror circuit, a second slew rate boosting circuit and a fifth current mirror circuit. And a sixth current mirror circuit and a second high-voltage protection circuit. The precision of the operational amplifier under the 36V high voltage can be improved.

The invention discloses a dynamic comparator and a voltage calibration method thereof, relates to the field of dynamic comparators, and is used for improving the comparison precision of the dynamic comparator in a mode of not sacrificing the power consumption and the efficiency of the dynamic comparator. A kickback noise suppression circuit is connected to a tail current tube of an input geminate transistor to adjust the switching time of a clock signal, a calibration crystal geminate transistor is connected to a regeneration node of the input geminate transistor, and a reference voltage is adjusted through a resistor string DAC to calibrate an offset voltage. The kickback noise is effectively suppressed by adjusting the slew rate of the clock signal of the tail current tube, the calibration speed is increased through the two-stage resistor string DAC, the crystal pair tube is controlled and calibrated by multiplexing the adjusted clock signal, and the calibration precision is improved.

The present disclosure provides a semiconductor device, which includes a process monitor circuit, a controller, and an output buffer. The process monitor circuit is configured to measure process information of the semiconductor device. The controller is electrically connected to the process monitor circuit, and configured to generate a trimming code based on the measured process information. The output buffer is electrically connected to the controller, and configured to adjust a first bias current and a second bias current based on the trimming code.

A slew-rate control circuit, including: a proportional calculation circuit, which generates a first indicating voltage according to a plurality of adjusted first signals within a previous preset period and a plurality of first signals within a current preset period, and generates a second indicating voltage according to the plurality of adjusted first signals within the previous preset period and a plurality of second signals that are inverted from the plurality of first signals within the current preset period; a logic operation circuit, which generates an operation result according to a relationship between the first indicating voltage, and first and second reference voltages, and a relationship between the second indicating voltage, and the first and second reference voltages; and an output adjustment circuit, which determines whether to invert the multiple first signals within the current preset period according to the operation result.

A semiconductor device is provided. The semiconductor devices is connected to a power device. The semiconductor device includes a gate driver unit with a first circuit and a second circuit, a resistor unit connecting the gate of the power device and the gate driver unit, and a first control circuit connected to the gate driver unit. The first control circuit is configured to increase the resistance of the power device by issuing an instruction to reduce the slew rate of the power device to the first circuit during the turn-off of the power device.

The invention is suitable for the technical field of slew rate improvement of operational amplifiers, and provides a slew rate improvement circuit and an operational amplifier. The slew rate increasing circuit comprises a first slew rate triggering module, a first slew rate enhancing module, a second slew rate triggering module and a second slew rate enhancing module, the first slew rate triggering module is electrically connected with the first slew rate enhancing module, and the first slew rate enhancing module is used for being electrically connected with a grid electrode of an upper power tube. The second slew rate triggering module is electrically connected with the second slew rate strengthening module, and the second slew rate strengthening module is used for being electrically connected with the grid electrode of the lower power tube. The first slew rate triggering module and the second slew rate triggering module are additionally arranged, the establishment requirement of the output signal is directly judged according to the difference value between the first voltage and the second voltage, and the corresponding slew rate enhancing module is triggered in real time so as to quickly open the upper power tube or the lower power tube. The loop response delay problem does not exist in the whole process, the establishment time of the output signal can be remarkably shortened, and the output slew rate is more efficiently improved.

A power integrated circuit comprising at least one III-nitride high voltage high-electron-mobility transistor (power HEMT), the power HEMT comprising a heterojunction formed between a GaN layer and an AlGaN layer, and a slew rate protection circuit. The slew rate protection circuit comprising a clamping transistor electrically connected between a gate terminal and a source terminal of the power HEMT, and a detection circuit electrically connected between a drain terminal and the source terminal of the power HEMT, wherein an output of the detection circuit is electrically connected to a gate terminal of the clamping transistor. The detection circuit is configured to output a signal to turn-on the clamping transistor when a transient voltage greater than a threshold transient voltage is observed across the drain and the source terminals of the power HEMT.

A new inverting logic gate or a FET gate driver is disclosed. The logic gate mitigates the trade-off between power dissipation (or quiescent power) and slew rate of the typical RTL and DLL buffers by using an innovative circuit topology involving a pull-up bootstrapping transistor. The bootstrapping transistor may be an enhancement mode GaN field effect transistor (FET). This bootstrapping transistor may be driven by the complement of the input signal. Alternatively, the bootstrapping transistor may monitor the drain terminal of the pull-down transistor and conduct current accordingly. Other Boolean functions may also be achieved using this approach.

An apparatus includes a first transistor having a control input. The apparatus also includes a driver having an output coupled to the control input. The driver includes an adaptive slew rate control circuit having an input coupled to a first terminal. The adaptive slew rate control circuit is configured to control the slew rate of the first transistor based on a resistor coupled to the first terminal.

A method to enhance the functionality of a battery through the use of a pulsing apparatus. The pulsing apparatus configured to improve cell conditioning, maintain battery cells, and overall cell function through pulsing a selected current into and out of a battery. The pulsing selected to deliver a predetermined number of pulses to the battery. The pulses having a slew rate of at least 0.1 A / μs, a pulse width between 1 μs and 10 ms with a pulse rise time of at least 1 μs to alter a current of the battery. Preferably the predetermined number of pulses is between 100 pulses per second and 1 pulse per minute.

A display driver includes a plurality of gamma bus lines and a drive leg configured to receive pixel data. The drive leg includes a decoder having first and second outputs, a source amplifier having a set of inputs, and a source interpolation selector. The decoder electrically connects, based on the pixel data, the first output to a first one of the gamma bus lines and the second output to a second one of the gamma bus lines. The source amplifier provides a data voltage to a display panel based on a set of input voltages at the set of inputs. The source interpolation selector provides, based on the pixel data, electrical connections between the first and second outputs of the decoder and the set of inputs of the source amplifier, and electrically connects the first and second outputs of the decoder during a first period of a horizontal sync period.

A control circuit for generating a control parameter that defines a state sequence of a power converter may include a loop filter configured to, based on an error signal between a reference current signal and a feedback current measurement signal, correct for unmodeled errors in the feedback current measurement signal to generate the control parameter. The control circuit may also include a first feedforward block configured to generate a first offset to the control parameter based on a slew rate of the reference current signal.

A half-bridge driver drives a half-bridge circuit. The half-bridge driver includes a switch selection circuit and at least one slew rate adjustment circuit, wherein the slew rate adjustment circuit includes a pulse-width control unit, an adjustment pulling unit and a halt adjustment pulling unit. The switch selection circuit generates a source current or a sink current to correspondingly pull up or pull down the gate-source voltage of the upper switch or the lower switch, thereby turning-on or turning-off the upper switch or the lower switch. The adjustment pulling unit is for adjusting the pulling-up or pulling-down of the gate-source voltage of the upper switch or the lower switch. The stop-adjustment pulling unit is for stopping adjusting the pulling-up or pulling-down of the gate-source voltage of the upper switch or the lower switch.

The invention discloses an adjustable high-voltage output low-ripple switching power supply which comprises an input filter circuit, a VCC power supply circuit, a PWM controller, a main power circuit, a high-frequency transformer, a linear voltage regulation circuit, an output rectification filter, an output voltage regulation circuit and an output auxiliary source reference circuit. The method for realizing low-ripple high-voltage adjustable output and controlling the voltage and current slew rate of an external N-channel MOSFET switch comprises the steps of independently setting the voltage slew rate and the current slew rate, setting the voltage slew rate through an external capacitor and setting the current slew rate through an external resistor. The high-voltage adjustable output is realized, the output ripple is reduced, the voltage regulation rate is improved, the EMI (Electro-Magnetic Interference) performance is optimized, the high-frequency harmonic power is reduced, the efficiency loss is reduced, and the problem that the traditional switching power supply cannot realize high-voltage, adjustable and low-ripple output at the same time is solved.

The invention provides a current multiplexing type output amplifier. The current multiplexing type output amplifier comprises a current multiplexing type input stage, a first self-biased diode pair, a second self-biased diode pair, a first AB type output stage and a second AB type output stage, wherein the first self-biased diode pair and the second self-biased diode pair are connected with the current multiplexing type input stage; the first AB type output stage is connected with the first self-biased diode pair; according to the invention, two self-biased diode pairs are adopted to replace a floating voltage source in the prior art. When a large pulse signal is input, one diode in each of the two diode pairs is in a cut-off state, transient change current I only flows into or out of the output end from a certain branch, and compared with a traditional amplifier, the slew rate is multiplied under the same bias current condition. In addition, the input stage adopts a current multiplexing type architecture combining a PMOS (P-channel Metal Oxide Semiconductor) and an NMOS (N-channel Metal Oxide Semiconductor), under the same bias current, the equivalent input transconductance is the sum of the transconductance of the PMOS and the transconductance of the NMOS, and the unity gain bandwidth is also multiplied.

The invention relates to the technical field of semiconductor integrated circuit design, in particular to a low-power-consumption slew rate increasing circuit which is composed of two field-effect tubes J1 and J2, six transistors Q1 to Q6, two current sources I1 and I2 and two resistors R1 and R2 which are correspondingly connected to form the slew rate increasing circuit. The slew rate increasing circuit is applied to the operational amplifier and is used for solving the problems of slew rate and power consumption of the amplifier. According to the invention, the slew rate is increased by about 10 times on the premise that the direct current characteristic and the small-signal alternating current characteristic are not influenced and extra power consumption is basically not increased.

This invention provides an adaptive slew rate enhancement circuit for CMOS operational amplifiers, used for adaptively increasing the slew rate of a two-stage operational amplifier with rail-to-rail input and floating Class AB output. The circuit is characterized by including at least a positive slew rate enhancement circuit and a negative slew rate enhancement circuit connected to the rail-to-rail input floating Class AB operational amplifier. The positive slew rate enhancement circuit accelerates the time it takes for the output voltage VOUT to rise with the input voltage VIP, and the negative slew rate enhancement circuit accelerates the time it takes for the output voltage VOUT to fall with the input voltage VIP. A corresponding control method is also provided. Under the action of the positive and negative slew rate enhancement circuits provided by this invention, the speed at which the output voltage VOUT builds up to 99% is increased by approximately 60% and 40%, respectively, when the input voltage VIP changes. This patent proposes an enhancement circuit that is simple, low-cost, and can significantly improve the driving speed of the operational amplifier.

Disclosed herein is a display apparatus including a display panel including a plurality of pixels; a timing controller configured to generate current control information based on a degree of transition of image data applied to a corresponding pixel among the plurality of pixels; and a plurality of output buffers configured to output a target data voltage corresponding to the image data to a data output channel connected to the plurality of pixels, wherein each of the output buffers includes an amplifier output circuit configured to apply a pre-set rising current or falling current for outputting the target data voltage to an output node connected to one of the data output channels, and a slew rate adjustment circuit configured to selectively and further apply an additional rising current or an additional falling current to the output node based on the current control information to increase an output slew rate of the target data voltage.

The application discloses a dynamic biasing circuit and method for improving the slew rate of an operational amplifier, which comprises PMOS tubes PM1-PM9, NMOS tubes NM1-NM3, resistors R11, R12, R2, R31 and R32, and detects the step jump of the operational amplifier; the greater the step jump, the greater the differential mode value, the greater the tail current, the greater the working current of the main operational amplifier, the faster the establishment, and the greater the SR; when the step jump is small or no jump, the static current is very small. The dynamic biasing circuit of the application has the advantages of simple structure, rapid response, easy integration and no influence on other performances of the operational amplifier, can efficiently detect the jump of the input signal and instantaneously provide additional driving current, so that the large signal transient response speed of the operational amplifier is fundamentally improved without sacrificing the static power consumption.

One embodiment relates to a data driver for driving pixels of a display panel and a differential amplifier that can be applied to the data driver. Embodiments provide a technique that supplies a dynamic current to both a first transistor and a second transistor of a differential amplifier through a boost circuit, thereby improving the slew rate of the differential amplifier.