201 results about "Slew rate" patented technology

A buffer circuit configured to generate an output voltage according to an input voltage includes: an input stage configured to provide first and second differential currents to a load stage or receive third and fourth differential currents from the load stage based on a difference between the input voltage and the output voltage; a load stage configured to apply gate voltages to first and second output transistors of an output stage based on the first through fourth differential currents; the output stage configured to regulate the output voltage based on the gate voltages applied to the first and the second output transistors; and a slew rate compensator configured to regulate the gate voltages of the first and second output transistors by providing a source current to the load stage or receiving a sink current from the load stage.

In one aspect of the disclosure, a variable-current gate driver includes a plurality of inputs for receiving pulse-width-modulation (PWM) control signals transmitted from a processing system. Current sources controlled based on the pulse-width modulation (PWM) signals are coupled to respective gates of at least two transistors of a hybrid switch in the power module (PM) including different semiconductor technologies. The current sources are coupled respectively to at least one other non-gate terminal of the transistors. The current sources provide the slew rate control of the PM using variable current values to compensate for differences in the at least two semiconductor technologies in real-time to reduce switching losses and maximize efficiency.

A method of driving a transistor between switching states includes controlling a transition of a gate voltage at a gate terminal of a transistor during each of a plurality of turn-off switching events to turn off the transistor, wherein the transistor is configured to be turned off according to a desaturation time during each of the plurality of turn-off switching events; measuring a transistor parameter indicative of a voltage slew rate of the transistor for a first turn-off switching event during which the transistor is transitioned from an on state to an off state; and regulating a duration of the desaturation time for a next turn-off switching event based on the measured transistor parameter.

A display driving circuit may include a source driver that includes a decoder circuit and a buffer circuit. The decoder circuit selects a first gamma voltage and a second gamma voltage among a plurality of gamma voltages based on pixel data, and selects a third gamma voltage different from the first and second gamma voltages among the plurality of gamma voltages. The buffer circuit interpolates between the first and second gamma voltages to output a first target voltage, and steps up or steps down a source voltage formed on the source line to the first target voltage. The buffer circuit includes a fast slew circuit that compares the first source voltage with the third gamma voltage to adjust slew rate of the first source voltage.

A semiconductor device is provided. The semiconductor devices is connected to a power device. The semiconductor device includes a gate driver unit with a first circuit and a second circuit, a resistor unit connecting the gate of the power device and the gate driver unit, and a first control circuit connected to the gate driver unit. The first control circuit is configured to increase the resistance of the power device by issuing an instruction to reduce the slew rate of the power device to the first circuit during the turn-off of the power device.

The invention is suitable for the technical field of slew rate improvement of operational amplifiers, and provides a slew rate improvement circuit and an operational amplifier. The slew rate increasing circuit comprises a first slew rate triggering module, a first slew rate enhancing module, a second slew rate triggering module and a second slew rate enhancing module, the first slew rate triggering module is electrically connected with the first slew rate enhancing module, and the first slew rate enhancing module is used for being electrically connected with a grid electrode of an upper power tube. The second slew rate triggering module is electrically connected with the second slew rate strengthening module, and the second slew rate strengthening module is used for being electrically connected with the grid electrode of the lower power tube. The first slew rate triggering module and the second slew rate triggering module are additionally arranged, the establishment requirement of the output signal is directly judged according to the difference value between the first voltage and the second voltage, and the corresponding slew rate enhancing module is triggered in real time so as to quickly open the upper power tube or the lower power tube. The loop response delay problem does not exist in the whole process, the establishment time of the output signal can be remarkably shortened, and the output slew rate is more efficiently improved.

A new inverting logic gate or a FET gate driver is disclosed. The logic gate mitigates the trade-off between power dissipation (or quiescent power) and slew rate of the typical RTL and DLL buffers by using an innovative circuit topology involving a pull-up bootstrapping transistor. The bootstrapping transistor may be an enhancement mode GaN field effect transistor (FET). This bootstrapping transistor may be driven by the complement of the input signal. Alternatively, the bootstrapping transistor may monitor the drain terminal of the pull-down transistor and conduct current accordingly. Other Boolean functions may also be achieved using this approach.

An apparatus includes a first transistor having a control input. The apparatus also includes a driver having an output coupled to the control input. The driver includes an adaptive slew rate control circuit having an input coupled to a first terminal. The adaptive slew rate control circuit is configured to control the slew rate of the first transistor based on a resistor coupled to the first terminal.

A method to enhance the functionality of a battery through the use of a pulsing apparatus. The pulsing apparatus configured to improve cell conditioning, maintain battery cells, and overall cell function through pulsing a selected current into and out of a battery. The pulsing selected to deliver a predetermined number of pulses to the battery. The pulses having a slew rate of at least 0.1 A / μs, a pulse width between 1 μs and 10 ms with a pulse rise time of at least 1 μs to alter a current of the battery. Preferably the predetermined number of pulses is between 100 pulses per second and 1 pulse per minute.

A control circuit for generating a control parameter that defines a state sequence of a power converter may include a loop filter configured to, based on an error signal between a reference current signal and a feedback current measurement signal, correct for unmodeled errors in the feedback current measurement signal to generate the control parameter. The control circuit may also include a first feedforward block configured to generate a first offset to the control parameter based on a slew rate of the reference current signal.

A half-bridge driver drives a half-bridge circuit. The half-bridge driver includes a switch selection circuit and at least one slew rate adjustment circuit, wherein the slew rate adjustment circuit includes a pulse-width control unit, an adjustment pulling unit and a halt adjustment pulling unit. The switch selection circuit generates a source current or a sink current to correspondingly pull up or pull down the gate-source voltage of the upper switch or the lower switch, thereby turning-on or turning-off the upper switch or the lower switch. The adjustment pulling unit is for adjusting the pulling-up or pulling-down of the gate-source voltage of the upper switch or the lower switch. The stop-adjustment pulling unit is for stopping adjusting the pulling-up or pulling-down of the gate-source voltage of the upper switch or the lower switch.

The invention discloses an adjustable high-voltage output low-ripple switching power supply which comprises an input filter circuit, a VCC power supply circuit, a PWM controller, a main power circuit, a high-frequency transformer, a linear voltage regulation circuit, an output rectification filter, an output voltage regulation circuit and an output auxiliary source reference circuit. The method for realizing low-ripple high-voltage adjustable output and controlling the voltage and current slew rate of an external N-channel MOSFET switch comprises the steps of independently setting the voltage slew rate and the current slew rate, setting the voltage slew rate through an external capacitor and setting the current slew rate through an external resistor. The high-voltage adjustable output is realized, the output ripple is reduced, the voltage regulation rate is improved, the EMI (Electro-Magnetic Interference) performance is optimized, the high-frequency harmonic power is reduced, the efficiency loss is reduced, and the problem that the traditional switching power supply cannot realize high-voltage, adjustable and low-ripple output at the same time is solved.

The invention provides a current multiplexing type output amplifier. The current multiplexing type output amplifier comprises a current multiplexing type input stage, a first self-biased diode pair, a second self-biased diode pair, a first AB type output stage and a second AB type output stage, wherein the first self-biased diode pair and the second self-biased diode pair are connected with the current multiplexing type input stage; the first AB type output stage is connected with the first self-biased diode pair; according to the invention, two self-biased diode pairs are adopted to replace a floating voltage source in the prior art. When a large pulse signal is input, one diode in each of the two diode pairs is in a cut-off state, transient change current I only flows into or out of the output end from a certain branch, and compared with a traditional amplifier, the slew rate is multiplied under the same bias current condition. In addition, the input stage adopts a current multiplexing type architecture combining a PMOS (P-channel Metal Oxide Semiconductor) and an NMOS (N-channel Metal Oxide Semiconductor), under the same bias current, the equivalent input transconductance is the sum of the transconductance of the PMOS and the transconductance of the NMOS, and the unity gain bandwidth is also multiplied.

This invention provides an adaptive slew rate enhancement circuit for CMOS operational amplifiers, used for adaptively increasing the slew rate of a two-stage operational amplifier with rail-to-rail input and floating Class AB output. The circuit is characterized by including at least a positive slew rate enhancement circuit and a negative slew rate enhancement circuit connected to the rail-to-rail input floating Class AB operational amplifier. The positive slew rate enhancement circuit accelerates the time it takes for the output voltage VOUT to rise with the input voltage VIP, and the negative slew rate enhancement circuit accelerates the time it takes for the output voltage VOUT to fall with the input voltage VIP. A corresponding control method is also provided. Under the action of the positive and negative slew rate enhancement circuits provided by this invention, the speed at which the output voltage VOUT builds up to 99% is increased by approximately 60% and 40%, respectively, when the input voltage VIP changes. This patent proposes an enhancement circuit that is simple, low-cost, and can significantly improve the driving speed of the operational amplifier.

Disclosed herein is a display apparatus including a display panel including a plurality of pixels; a timing controller configured to generate current control information based on a degree of transition of image data applied to a corresponding pixel among the plurality of pixels; and a plurality of output buffers configured to output a target data voltage corresponding to the image data to a data output channel connected to the plurality of pixels, wherein each of the output buffers includes an amplifier output circuit configured to apply a pre-set rising current or falling current for outputting the target data voltage to an output node connected to one of the data output channels, and a slew rate adjustment circuit configured to selectively and further apply an additional rising current or an additional falling current to the output node based on the current control information to increase an output slew rate of the target data voltage.

The application discloses a dynamic biasing circuit and method for improving the slew rate of an operational amplifier, which comprises PMOS tubes PM1-PM9, NMOS tubes NM1-NM3, resistors R11, R12, R2, R31 and R32, and detects the step jump of the operational amplifier; the greater the step jump, the greater the differential mode value, the greater the tail current, the greater the working current of the main operational amplifier, the faster the establishment, and the greater the SR; when the step jump is small or no jump, the static current is very small. The dynamic biasing circuit of the application has the advantages of simple structure, rapid response, easy integration and no influence on other performances of the operational amplifier, can efficiently detect the jump of the input signal and instantaneously provide additional driving current, so that the large signal transient response speed of the operational amplifier is fundamentally improved without sacrificing the static power consumption.

This invention provides an optimized system for improving the slew rate of a Line Driver, comprising a differential input module, a bias current module, an amplification module, an active load module, and a mirror load module. The differential input module receives the input signal and converts the voltage signal into a current signal. The bias current module provides a stable bias current to the circuit. The amplification module receives the current signal from the differential input module and achieves voltage gain. The amplification module is electrically connected to the active load module. The active load module can improve the amplification gain of the amplification module, replicate the current, and stabilize the output node. The mirror load module can replicate the signal amplification path of the amplification module to achieve symmetrical output, thereby improving the signal amplification effect and anti-interference reliability of the circuit and solving the problem of limited slew rate in traditional optimized systems for Line Drivers.

An external chip driving system includes a decision circuit, multiple first adjustable enhancement circuits, multiple second adjustable enhancement circuits, a pull-up circuit, and a pull-down circuit. The decision circuit outputs first and second decision signals based on a frequency signal and an input signal. In response to the first and second decision signals and one of the first selection signals, each of the first adjustable enhancement circuits generates a first control signal. In response to the first and second decision signals and one of the second selection signals, each of the second adjustable enhancement circuits generates a second control signal. Because the signal amplitude attenuates and becomes distorted during high-speed data transmission, in this disclosure, the first driver in the pull-up circuit is activated in response to the corresponding first control signal, and the second driver in the pull-down circuit is activated in response to the corresponding second control signal, thereby increasing the slew rate of the output signal and reducing the distortion of the output data.

Average power tracking (APT) systems with fast transient settling are disclosed. In certain embodiments, an APT system is used to provide a power amplifier supply voltage to a power amplifier that amplifies a radio frequency (RF) signal. The APT system controls the power amplifier supply voltage to track an average power of the RF signal, and includes a DC-to-DC converter that is assisted by an error amplifier in transitioning from one power amplifier supply voltage level to another power amplifier supply voltage level. Thus, the combination of a DC-to-DC converter with a fast changing error amplifier can swing enough AC voltage with a low enough slew rate to be able to rapidly transition the power amplifier supply voltage from one APT voltage level to another APT voltage level.

The invention provides a low-distortion pulse generator which comprises a transistor MP1, an S pole of the transistor MP1 is used for connecting a high-voltage power supply end, and a D pole of the transistor MP1 is used for connecting a transducer; the first level translator is used for driving the G pole of the transistor MP1 so as to apply a voltage pulse with a rising edge to the transducer; s poles of the transistor MN1 and the transistor MP1 are grounded, and D poles of the transistor MN1 and the transistor MP1 are connected with a transducer; the second level shifter is used for driving the G pole of the transistor MP2 so as to apply a voltage pulse with a falling edge to the transducer; and the level shifter is used for adjusting the voltage difference VGS between the grid electrode and the source electrode of the transistor so as to realize the time adjustment of the rising edge or the falling edge of the voltage pulse. According to the invention, the voltage difference VGS between the grid electrode and the source electrode of the transistor is adjusted through the level translator to realize the time adjustment of the rising edge or the falling edge of the voltage pulse, so that the slew rates of different edges are adjusted, and the waveform distortion is reduced.

A system includes a control valve with a first control port and a second control port. An actuator of the system includes a piston between an extend chamber and a retract chamber. The system also includes a shutoff valve fluidically connected between the control valve and the actuator. The shutoff valve is passively controlled by a pressure differential between the extend chamber and the retract chamber. If the pressure differential between the extend chamber and the retract chamber exceeds normal operating pressures for the actuator, the shutoff valve closes to stop pressure and flow communication between the control valve and the actuator, thereby pausing the actuator. When the pressure differential between the extend chamber and the retract chamber returns to the normal operating pressures for the actuator, the shutoff valve passively returns to an equilibrium position that allows the actuator to resume operation.

The present application discloses a low-power-consumption self-biased slew-rate-enhanced circuit and an integrator. The enhanced circuit comprises: a self-biased control circuit used for outputting a bias voltage on the basis of an output voltage of an input voltage measurement circuit; the input voltage measurement circuit connected to the self-biased control circuit and used for measuring the magnitude of a differential input voltage; and a slew rate control circuit used for providing, when the voltage of a differential input voltage end exceeds a starting voltage, a sourcing current or a sinking current for an output end of an operational amplifier, and when the voltage of the differential input voltage end does not exceed the starting voltage, not generating an additional current or not generating a slew rate enhancement effect. In the present invention, an additional bias voltage or bias current does not need to be input, a static current is not consumed when the function of the slew-rate-enhanced circuit is not enabled, and a static bias current of an operational amplifier does not need to be increased when the slew-rate-enhanced circuit is started, so that fast charging and discharging of a large capacitance load can be achieved without affecting a small signal frequency domain characteristic of the operational amplifier, and a bidirectional slew rate of the operational amplifier is enhanced, thereby meeting low-power consumption and high-speed design requirements of an integrated circuit.

The application discloses a delay circuit and a driving device. The delay circuit can include at least two branches in parallel, each of the at least two branches has different delay; the delay circuit includes at least one register for controlling one of the at least two branches to be turned on, so that the delay circuit generates the delay corresponding to the turned-on branch. Since the greater the delay of the input signal is, the smaller the slew rate is, the slew rates of the input signal through any one of the at least two branches are different. The at least one register controls one of the at least two branches to be turned on, so that the slew rate of the output signal can be adjusted, and the slew rate of the output signal can be compatible with different protocols or different modes under the same protocol.

A technique of charging a capacitive load is presented in which the load is charged by current pulses in a sequence of stages. The amplitude of the current pulses in each stage increases from one stage to the next. Transition between stages is triggered by the voltage across the load meeting a threshold requirement, until a target voltage is reached. The slew rate of a rising edge of each current pulse is lower than the sew rate of the falling edge.

This invention provides a transmitter circuit for a CAN bus, relating to the field of CAN bus communication. The circuit includes: a common-mode feedback circuit for generating first and second gate voltages; a slew rate control circuit comprising a CANH terminal circuit for receiving the first gate voltage and a CANL terminal circuit for receiving the second gate voltage, each terminal circuit including multiple sequentially connected delay units and power transistors, the delay units controlling the gate voltage of the power transistors stage by stage to alternately switch the power transistors; and a port positive and negative high-voltage protection circuit, respectively connected between the output terminals of the CANH and CANL terminal circuits and the bus port, for protecting against positive and negative high voltages on the bus and suppressing parasitic effects. The beneficial effects are: by controlling the switching of the power transistors stage by stage through the delay units, the current surge rate is reduced, and electromagnetic radiation is reduced; by stabilizing the gate voltage and balancing the output current through common-mode feedback, signal symmetry is improved and common-mode interference is suppressed.

A circuit includes a first transistor having a control terminal and includes a predriver having an input and an output. The output is coupled to the control terminal of the first transistor. A second transistor of a first polarity has a control terminal coupled to the output of the predriver. A third transistor of a second polarity has first and second terminals. The first terminal of the third transistor is coupled to the control terminal of the second transistor. A fourth transistor having the second polarity has first and second terminals. The first terminal of the fourth transistor is coupled to the second terminal of the third transistor. The second terminal of the fourth transistor is coupled to a supply terminal.

The application belongs to the technical field of amplifiers, and relates to a cyclic structure amplifier, in particular to a high-gain transconductance-enhanced cyclic structure amplifier. The cyclic structure amplifier comprises PMOS tubes P1a, P1b, P2a, P2b, P5, P6, P7, P8 and P9, and NMOS tubes N1, N2, N3, N4, N5a, N5b, N6a, N6b, N7a, N7b, N8a and N8b. The drain of the PMOS tube P1b is connected to the gate of the NMOS tube N5b. The drain of the PMOS tube P2b is connected to the gate of the NMOS tube N6b. The NMOS tube N5b and the PMOS tube P1b and the NMOS tube N6b and the PMOS tube P2b form a cross positive feedback path, which can enhance the transconductance of the PMOS tubes P1b and P2b. The high-gain transconductance-enhanced cyclic structure amplifier provided by the application has a transconductance five times that of a conventional folded cascode operational amplifier and a nine-time higher slew rate than that of the folded cascode operational amplifier.

A power driving circuit includes a power conversion module, a plurality of gate drivers, a waveform processing unit, a control unit, a weight unit and a comparator. Each gate driver includes a driving resistance setting value. The waveform processing unit outputs an absolute value waveform of current of alternating current power. The weight unit generates a trigger voltage. When the comparator judges that the absolute value waveform of current is greater than the trigger voltage, a slew rate control signal is output to each gate driver. When each gate driver receives the slew rate control signal, the driving resistance setting value of each gate driver is respectively adjusted. The present invention also relates to a control method for a power driving circuit.

A circuit includes a latch, a first variable resistor, a second variable resistor, a slew detector, and a conductor configured to provide a power supply voltage. The latch has a first latch input, a second latch input, a first latch output, and a second latch output. The first variable resistor has a first terminal coupled to the conductor, a second terminal coupled to the first latch input, a first control input, and a second control input coupled to the first latch output. The second variable resistor has a first terminal coupled to the conductor, a second terminal coupled to the second latch input, a third control input, and a fourth control input coupled to the second latch output. The slew detector is coupled to the conductor. The slew detector has an output coupled to the first control input and the third control input.

According to one embodiment, an electronic circuitry includes: a timing detector configured to detect a voltage generated in a parasitic inductance of a switching element, the driving of the switching element being controlled in accordance with a control signal and to detect a first timing at which the voltage becomes lower or higher than a predetermined value, and a second timing, occurring after the first timing, at which the voltage becomes higher or lower than the predetermined value; and a calculator configured to calculate a slew rate of a current flowing through the switching element based on a current flowing through the switching element at the first timing and the second timing.