130results about "Analog signal digital control" patented technology

A programmable gain amplifier (PGA) architecture provides for robust operation over a bandwidth and for a multitude of gain settings. For instance, the PGA architecture may include multiple switches to implement different current paths by bypassing resistors in a resistor ladder. The different current paths may result in different gain settings. In some implementations, the switches may be used to hold a value of RA constant while a value of RB may be varied over the different gain settings, where gain may be inferred from the equation Vout=Vin*(1+RB / RA).

Variable gain amplifiers (VGAs) with fine attenuation step control and flat signal-to-noise ratio (SNR) versus attenuation are provided. In certain embodiments, a VGA includes an input that receives a radio frequency (RF) input signal, a segmented amplification circuit including multiple amplification cells that operate in parallel to amplify the RF input signal to generate multiple amplified RF signals, an impedance ladder including multiple taps each connected to a different node of the impedance ladder, and switches that control routing of the amplified RF signals to one or more selected taps of the impedance ladder. Accordingly, the VGA uses the switches to connect the outputs of the segmented amplification circuit to the selected tap(s) of the impedance ladder. By changing the tap selection, the attenuation step of the VGA is controlled.

An apparatus includes a plurality of gain stages connected in parallel between a first bias voltage and ground, where each gain stage includes an amplification portion and a current control portion including a first selectable signal path connected between an output of the amplification portion and a signal output, and a second selectable signal path connected between an output of the amplification portion and a signal output. And a second selectable signal path connected between the output of the amplification section and ground by a shunt device.

An analog front-end chip and an oscilloscope are provided. The analog front-end chip is integrated with an input buffer module, a variable gain amplification module, and at least two output branches. An input end of the input buffer module is configured as an input end of the analog front-end chip, and an output end of the input buffer module is electrically connected to an input end of the variable gain amplification module. An input end of each of the output branches is electrically connected to an output end of the variable gain amplification module, and an output end of each of the output branches is configured as an output end of the analog front-end chip, wherein each of the output branches includes an output buffer module.

A buzzer driving system includes a filter circuit and a driving circuit. The filter circuit is configured to filter an audio playback signal and output an analog playback signal. The driving circuit is electrically connected to the filter circuit and configured to output a driving voltage to the buzzer based on the analog playback signal. The driving system generates the driving voltage in an analog form to enhance the output audio quality of the buzzer.

An audio processing apparatus having an echo canceling mechanism is provided. An audio transmission circuit receives an input digital audio signal from an external device. A DAC circuit performs conversion according to the input digital audio signal to generate an output analog audio signal to an external display device for power amplification and playback. An ADC circuit performs analog-to-digital conversion on an amplified signal generated by a power amplification circuit and a received audio signal generated by an audio receiving device to generate an amplified digital signal and a received digital audio signal. A processor implements an echo canceling algorithm to perform echo cancellation according to the amplified digital signal and the received digital audio signal to generate an output digital audio signal to be transmitted to the external device through the audio transmission circuit.

Analog front-end chip, characterized in that the analog front-end chip (1) is integrated with an input buffer module (11), an amplification module (12) with variable gain and at least two output branches (13), wherein the input end of the input buffer module (11) serves as the input end of the analog front-end chip (1), wherein the output end of the input buffer module (11) is electrically connected to the input end of the variable gain amplifier module (12), wherein the input end of each output branch (13) is electrically connected to the output end of the variable gain amplifier module (12), wherein the output end of each output branch (13) serves as the output end of the analog front-end chip (1), and wherein each output branch (13) comprises an output buffer module (131).

An attenuator circuit for testing electronic devices includes a first circuit having a first input, a first output, a first resistor coupled between the first input and the first output, and a second resistor coupled between the first output and a reference node, a second circuit having a second input, a second output, and a first amplifier circuit, the second input coupled to the first output, and the first amplifier circuit coupled between the second input and the second output, and a third circuit having a third input, a third output, a second amplifier circuit, and a gain control circuit, the third input coupled to the second output, the second amplifier circuit coupled between the third input and the third output, and the gain control circuit configured to adjust a gain of the second amplifier circuit.

A measurement system includes a gain chain configured to amplify an analog input signal; a range selector configured to select a gain between the analog input signal and a plurality of analog-to-digital converter (ADC) outputs from a plurality of ADCs, wherein each ADC output has a path, and a gain of each output path is made up of a plurality of gain stages in the gain chain; and a mixer configured to combine the plurality of ADC outputs into a single mixed output.

The present application relates to a device and method for multiplying signals. A multiplication circuit (100) has a first time-coded modulator (103a) and a second time-coded modulator (103b), wherein the first time-coded modulator (103a) and the second time-coded modulator (103b) are configured to receive a first combined signal (S C1 ) and the second combined signal (S C2 ) and generate respective first PWM signals (S) each having a cycle frequency that substantially depends on the square of the value of the input combined signal PWM1 ) and the second PWM signal (S PWM2 ). The first combined signal (S C1 ) corresponds to the sum of the first input signal (S1) and the second input signal (S2), and the second combined signal (S C2 ) corresponds to the difference between the first input signal (S1) and the second input signal (S2). The first time decoding converter (104a) and the second time decoding converter (104b) receive the first PWM signal and the second PWM signal and provide a corresponding first count value (D1) and a second count value (D2) based on a parameter related to the frequency of the corresponding first PWM signal or the second PWM signal. The subtractor (105) determines the difference between the first count value (D1) and the second count value (D2) and provides an output signal (D1) based on the difference. OUT ).

A method of avoiding clipping in audio signals is disclosed (figure 2). Sound signals are amplified in a pre-amplifier that successively uses a plurality of analogue gain values to generate a pluralit

An amplifying apparatus includes: clip processor circuitry configured to perform clip processing, on a basis of the power of a first signal, so as to multiply the power of the first signal by a clip correction value such that the power of the first signal falls within a specified range; gain processor circuitry configured to perform gain processing so as to multiply the power of the first signal subjected to the clip processing by a gain correction value, and further configured to input to analog converter (DAC) the signal after the gain processing; and a gain adjuster configured to restore the power of the first signal output from the DAC to the power before the gain processing and the clip processing, and further configured to input the signal to a carrier amplifier.

The present disclosure relates to a voltage gain amplifier for automotive radar. Disclosed herein is a voltage gain amplifier for use in an automotive radar receiver chain. The voltage gain amplifier utilizes pole-to-zero cancellation to yield a desired transfer function without gain peaking at a bandwidth where peaking is desired, and utilizes a low pass filter that is effectively formed by a feedback loop that includes a high pass filter and a differential amplifier to ensure a desired level of attenuation at the desired bandwidth. In some instances, a chopper can be utilized in the feedback loop before the high pass filter and after the differential amplifier in order to reduce the bandwidth of the differential amplifier in the feedback loop.

An integrated circuit (IC), comprising: a first gain stage configured to apply a first gain to a first signal to generate a first gain adjusted signal; a first converter configured to convert the first gain adjusted signal to a first converted signal; a second gain stage configured to apply a second gain to the first converted signal to generate a second gain adjusted signal; and a controller configured to coordinate changes in a first gain of the first gain stage and a second gain of the second gain stage to prevent transients in the second gain adjusted signal.

An integrated circuit device includes a variable gain amplifier with multiple gain circuits coupled in parallel, where one or more of the multiple gain circuits comprises a first differential pair of transistors, and a complementarily switched second differential pair of transistors cross-connected to the first differential pair of transistors with a sign inversion relative to the first differential pair of transistors. Other examples are disclosed and claimed.

An apparatus for controlling the gain and phase of an input signal input to a power amplifier comprises a gain control loop configured to control the gain of the input signal based on power levels of the input signal and an amplified signal output by the power amplifier, to obtain a predetermined gain of the amplified signal, and a phase control loop configured to obtain an error signal related to a phase difference between a first signal derived from the input and a second signal derived from the amplified signal, and control the phase based on the error signal, to obtain a predetermined phase of the amplified signal. The phase control loop is arranged to delay the first signal before obtaining the error signal, such that the delayed first signal and the second signal used to obtain the error signal correspond to the same part of the input signal. The gain control loop may compare a power of a third signal derived from the input signal and a power of a fourth signal derived from the amplified signal. The third and fourth signals may be output by first and second couplers, which may have coupling factors that are selected such that the third and fourth signals have the same power level when the amplified signal has the predetermined gain. The current gain and phase of the amplified signal may be dependent on an operational history of the power amplifier, which may be a GaN power amplifier, and the apparatus and power amplifier may be included in a satellite. In another embodiment, a satellite includes a power amplifier control system that uses a feed-forward control loop to control both the gain and phase of a signal input to the power amplifier.

A circuit includes an operational amplifier and a resistor network coupled to an output of the operational amplifier. The resistor network includes a first set of resistors coupled between the output of the operational amplifier and a first node of the resistor network, wherein the resistors of the first set are electrically connected in series with each other, a second set of resistors coupled between the first node and a second node of the resistor network, wherein the resistors of the second set are electrically connected in series with each other and include a first number of resistors, a third set of resistors coupled between the second node and a third node of the resistor network, wherein the third node is coupled to a first voltage, and wherein the resistors of the third set are electrically connected in parallel with each other and include a second number of resistors, and a resistor coupled between the first node and the second node and arranged in parallel with the second set of resistors.

An amplifier circuit that includes a capacitor voltage divider that is selectively enabled with a switch. The circuit includes two capacitor banks where the banks are electrically coupled to opposing side terminals of the switch. When the capacitor voltage divider is not enabled, one bank is adjusted to control the gain of the amplifier. When the capacitor voltage divider is enabled, both banks are used to control the gain of the amplifier.

Systems, methods, apparatus, and articles of manufacture to control audio playback devices are disclosed. An example method includes receiving (1302) first audio information from a first audio information source; generating (1304) audio signals based on the received first audio information from the first audio information source; receiving (1306) a source command from a user input device to change to a second audio information source; and in response to the source command: changing (1308) a signal source to the second audio information source and sending (1310) a volume message to the first audio information source to change a volume setting of the first audio information source.

There is provided a method of amplifying a signal. The method comprises: applying analogue gain to a signal, an analogue gain amount being applied at an offset amount below a set gain amount; applying digital gain to the signal, a digital gain amount applied being an amount up to the offset amount; and converting the signal between digital and analogue between the steps of applying gain. The digital gain amount is adjustable based on an amplitude of the signal. An amplifier is also provided with an analogue gain module, a digital gain module and a converter connected between the modules.

A digitally controlled variable gain amplifier (1) or digitally controlled VGA (1) for generating amplification output levels (10), comprising: - a positive amplification stage (100) comprising at least two positive amplifiers (101;102); - a corresponding negative amplification stage (200) coupled to said positive amplification stage (100), wherein said corresponding negative amplification stage (200) comprises at least two negative amplifiers (201; 202); wherein said positive amplification stage (100) and said corresponding negative amplification stage (200) are digitally controlled by one or more digital codes (240); and wherein: - said corresponding negative amplification stage (200) is coupled in parallel with said positive amplification stage (100) and is equally weighted as said positive amplification stage (100); and - both said positive amplification stage (100) and said corresponding negative amplification stage (200) selectively contribute to the generation of said amplification output levels (10) for said digitally controlled VGA (1).

An amplifier circuit that includes a capacitor voltage divider that is selectively enabled with a switch. The circuit includes two capacitor banks where the banks are electrically coupled to opposing side terminals of the switch. When the capacitor voltage divider is not enabled, one bank is adjusted to control the gain of the amplifier. When the capacitor voltage divider is enabled, both banks are used to control the gain of the amplifier.

There is provided an amplifier for amplifying audio signals. The amplifier comprises a plurality of stages. At least two of the stages of the plurality of stages are connected in series and each of the at least two stages is a gain stage each provided by a preamplifier stage. The at least two stages are arranged, in use, to apply gain to an input signal provided to the amplifier.

A variable gain amplifier includes first and second stage common-source (CS) amplifiers and a first transformer. The second stage CS amplifier includes a differential circuit and a current steering circuit. The differential circuit and the current steering circuit are coupled to a common connecting node, and the current steering circuit draws at least part of a current flowing through the differential circuit from the common connecting node. The first transformer includes primary and secondary sides. A first terminal of the primary side is coupled to an output terminal of the first stage CS amplifier, and a second terminal of the primary side is coupled to the common connecting node. A first terminal of the secondary side is coupled to a first differential input terminal of the differential circuit, and a second terminal of the secondary side is coupled to a second differential input terminal of the differential circuit.

Novel tools and techniques are provided for implementing a novel integrated programmable gain amplifier "PGA" and protection circuit. In various embodiments, a circuit is provided that includes a PGA, an analog-to-digital converter "ADC", and a protection circuit, all disposed on the same semiconductor chip. The PGA is configured to receive a wireless signal received from an antenna as input, and to output an amplified wireless signal at its output based on amplifying the wireless signal by a programmable gain amount. The protection circuit is configured to, in response to detecting a spike in gain at the output of the PGA that exceeds a threshold magnitude, control a reduction in the programmable gain amount to bring the resulting signal at the output of the PGA below the threshold magnitude. A normally open switch can also be added at the differential output of the PGA to further clamp the PGA output.

A network transceiver device is provided, including at least two variable gain amplifiers (VGAs), and at least two sets of analog digital converters (ADCs), each set including ADCs coupled to an output of one of the VGAs, the sets being arranged in VGA-specific channels. The device includes a plurality of feed-forward equalizers (FFEs), each FFE being coupled to receive an output of one of the ADCs in one of the VGA-specific channels. Each FFE is configured to adaptively equalize the output received from the ADCs utilizing a first equalization coefficient subset with coefficient values that are common to all FFEs, and a second equalization coefficient subset that is channel specific and that has a first set of coefficient values for a first VGA-specific channel and a second set of coefficient values for a second VGA-specific channel, the sets of coefficient values being computed independently.

Signal processing to compensate for gain control output spikes caused by steps in a digital step attenuator. A method includes receiving a changing power input signal at a receiver. The method includes determining that a change in power of the input signal will cause a step attenuator to change its attenuation in a step of a predetermined amount. The method further includes based on determining that the change in power of the input signal will cause a digital step attenuator to change its attenuation in a step of a predetermined amount, causing a variable attenuator to change its attenuation by an amount related to the predetermined amount at a time coinciding with a time when the step attenuator changes its attenuation by the predetermined amount. The method further includes outputting a gain-controlled output signal resulting from applying the step attenuator and the variable attenuator to the changing power input signal.

A method of amplifying a signal is provided. The method includes: applying an analog gain to a signal, wherein an analog gain amount is applied with an offset lower than a set gain amount; applying a digital gain to the signal, wherein the amount of the applied digital gain is up to the offset; and converting the signal between digital and analog between the steps of applying the gain. The digital gain amount is adjustable based on the amplitude of the signal. The amplifier is further provided with an analog gain module, a digital gain module and a converter connected between the modules.

An aspect includes a filtering method including operating a first filter to filter a first input signal to generate a first output signal; operating a second filter to filter a second input signal to generate a second output signal; and selectively coupling at least a portion of the second filter with the first filter to filter a third input signal to generate a third output signal. Another aspect includes a filtering method including operating switching devices to configure a filter with a first set of pole(s); filtering a first input signal to generate a first output signal with the filter configured with the first set of pole(s); operating the switching devices to configure the filter with a second set of poles; and filtering a second input signal to generate a second output signal with the filter configured with the second set of poles.