71results about "Analog signal digital control" patented technology

A programmable gain amplifier (PGA) architecture provides for robust operation over a bandwidth and for a multitude of gain settings. For instance, the PGA architecture may include multiple switches to implement different current paths by bypassing resistors in a resistor ladder. The different current paths may result in different gain settings. In some implementations, the switches may be used to hold a value of RA constant while a value of RB may be varied over the different gain settings, where gain may be inferred from the equation Vout=Vin*(1+RB / RA).

A buzzer driving system includes a filter circuit and a driving circuit. The filter circuit is configured to filter an audio playback signal and output an analog playback signal. The driving circuit is electrically connected to the filter circuit and configured to output a driving voltage to the buzzer based on the analog playback signal. The driving system generates the driving voltage in an analog form to enhance the output audio quality of the buzzer.

An attenuator circuit for testing electronic devices includes a first circuit having a first input, a first output, a first resistor coupled between the first input and the first output, and a second resistor coupled between the first output and a reference node, a second circuit having a second input, a second output, and a first amplifier circuit, the second input coupled to the first output, and the first amplifier circuit coupled between the second input and the second output, and a third circuit having a third input, a third output, a second amplifier circuit, and a gain control circuit, the third input coupled to the second output, the second amplifier circuit coupled between the third input and the third output, and the gain control circuit configured to adjust a gain of the second amplifier circuit.

A measurement system includes a gain chain configured to amplify an analog input signal; a range selector configured to select a gain between the analog input signal and a plurality of analog-to-digital converter (ADC) outputs from a plurality of ADCs, wherein each ADC output has a path, and a gain of each output path is made up of a plurality of gain stages in the gain chain; and a mixer configured to combine the plurality of ADC outputs into a single mixed output.

A method of avoiding clipping in audio signals is disclosed (figure 2). Sound signals are amplified in a pre-amplifier that successively uses a plurality of analogue gain values to generate a pluralit

An amplifying apparatus includes: clip processor circuitry configured to perform clip processing, on a basis of the power of a first signal, so as to multiply the power of the first signal by a clip correction value such that the power of the first signal falls within a specified range; gain processor circuitry configured to perform gain processing so as to multiply the power of the first signal subjected to the clip processing by a gain correction value, and further configured to input to analog converter (DAC) the signal after the gain processing; and a gain adjuster configured to restore the power of the first signal output from the DAC to the power before the gain processing and the clip processing, and further configured to input the signal to a carrier amplifier.

The present disclosure relates to a voltage gain amplifier for automotive radar. Disclosed herein is a voltage gain amplifier for use in an automotive radar receiver chain. The voltage gain amplifier utilizes pole-to-zero cancellation to yield a desired transfer function without gain peaking at a bandwidth where peaking is desired, and utilizes a low pass filter that is effectively formed by a feedback loop that includes a high pass filter and a differential amplifier to ensure a desired level of attenuation at the desired bandwidth. In some instances, a chopper can be utilized in the feedback loop before the high pass filter and after the differential amplifier in order to reduce the bandwidth of the differential amplifier in the feedback loop.

An integrated circuit (IC), comprising: a first gain stage configured to apply a first gain to a first signal to generate a first gain adjusted signal; a first converter configured to convert the first gain adjusted signal to a first converted signal; a second gain stage configured to apply a second gain to the first converted signal to generate a second gain adjusted signal; and a controller configured to coordinate changes in a first gain of the first gain stage and a second gain of the second gain stage to prevent transients in the second gain adjusted signal.

An apparatus for controlling the gain and phase of an input signal input to a power amplifier comprises a gain control loop configured to control the gain of the input signal based on power levels of the input signal and an amplified signal output by the power amplifier, to obtain a predetermined gain of the amplified signal, and a phase control loop configured to obtain an error signal related to a phase difference between a first signal derived from the input and a second signal derived from the amplified signal, and control the phase based on the error signal, to obtain a predetermined phase of the amplified signal. The phase control loop is arranged to delay the first signal before obtaining the error signal, such that the delayed first signal and the second signal used to obtain the error signal correspond to the same part of the input signal. The gain control loop may compare a power of a third signal derived from the input signal and a power of a fourth signal derived from the amplified signal. The third and fourth signals may be output by first and second couplers, which may have coupling factors that are selected such that the third and fourth signals have the same power level when the amplified signal has the predetermined gain. The current gain and phase of the amplified signal may be dependent on an operational history of the power amplifier, which may be a GaN power amplifier, and the apparatus and power amplifier may be included in a satellite. In another embodiment, a satellite includes a power amplifier control system that uses a feed-forward control loop to control both the gain and phase of a signal input to the power amplifier.

An amplifier circuit that includes a capacitor voltage divider that is selectively enabled with a switch. The circuit includes two capacitor banks where the banks are electrically coupled to opposing side terminals of the switch. When the capacitor voltage divider is not enabled, one bank is adjusted to control the gain of the amplifier. When the capacitor voltage divider is enabled, both banks are used to control the gain of the amplifier.

Systems, methods, apparatus, and articles of manufacture to control audio playback devices are disclosed. An example method includes receiving (1302) first audio information from a first audio information source; generating (1304) audio signals based on the received first audio information from the first audio information source; receiving (1306) a source command from a user input device to change to a second audio information source; and in response to the source command: changing (1308) a signal source to the second audio information source and sending (1310) a volume message to the first audio information source to change a volume setting of the first audio information source.

A digitally controlled variable gain amplifier (1) or digitally controlled VGA (1) for generating amplification output levels (10), comprising: - a positive amplification stage (100) comprising at least two positive amplifiers (101;102); - a corresponding negative amplification stage (200) coupled to said positive amplification stage (100), wherein said corresponding negative amplification stage (200) comprises at least two negative amplifiers (201; 202); wherein said positive amplification stage (100) and said corresponding negative amplification stage (200) are digitally controlled by one or more digital codes (240); and wherein: - said corresponding negative amplification stage (200) is coupled in parallel with said positive amplification stage (100) and is equally weighted as said positive amplification stage (100); and - both said positive amplification stage (100) and said corresponding negative amplification stage (200) selectively contribute to the generation of said amplification output levels (10) for said digitally controlled VGA (1).

A variable gain amplifier includes first and second stage common-source (CS) amplifiers and a first transformer. The second stage CS amplifier includes a differential circuit and a current steering circuit. The differential circuit and the current steering circuit are coupled to a common connecting node, and the current steering circuit draws at least part of a current flowing through the differential circuit from the common connecting node. The first transformer includes primary and secondary sides. A first terminal of the primary side is coupled to an output terminal of the first stage CS amplifier, and a second terminal of the primary side is coupled to the common connecting node. A first terminal of the secondary side is coupled to a first differential input terminal of the differential circuit, and a second terminal of the secondary side is coupled to a second differential input terminal of the differential circuit.

Novel tools and techniques are provided for implementing a novel integrated programmable gain amplifier "PGA" and protection circuit. In various embodiments, a circuit is provided that includes a PGA, an analog-to-digital converter "ADC", and a protection circuit, all disposed on the same semiconductor chip. The PGA is configured to receive a wireless signal received from an antenna as input, and to output an amplified wireless signal at its output based on amplifying the wireless signal by a programmable gain amount. The protection circuit is configured to, in response to detecting a spike in gain at the output of the PGA that exceeds a threshold magnitude, control a reduction in the programmable gain amount to bring the resulting signal at the output of the PGA below the threshold magnitude. A normally open switch can also be added at the differential output of the PGA to further clamp the PGA output.

A network transceiver device is provided, including at least two variable gain amplifiers (VGAs), and at least two sets of analog digital converters (ADCs), each set including ADCs coupled to an output of one of the VGAs, the sets being arranged in VGA-specific channels. The device includes a plurality of feed-forward equalizers (FFEs), each FFE being coupled to receive an output of one of the ADCs in one of the VGA-specific channels. Each FFE is configured to adaptively equalize the output received from the ADCs utilizing a first equalization coefficient subset with coefficient values that are common to all FFEs, and a second equalization coefficient subset that is channel specific and that has a first set of coefficient values for a first VGA-specific channel and a second set of coefficient values for a second VGA-specific channel, the sets of coefficient values being computed independently.

Signal processing to compensate for gain control output spikes caused by steps in a digital step attenuator. A method includes receiving a changing power input signal at a receiver. The method includes determining that a change in power of the input signal will cause a step attenuator to change its attenuation in a step of a predetermined amount. The method further includes based on determining that the change in power of the input signal will cause a digital step attenuator to change its attenuation in a step of a predetermined amount, causing a variable attenuator to change its attenuation by an amount related to the predetermined amount at a time coinciding with a time when the step attenuator changes its attenuation by the predetermined amount. The method further includes outputting a gain-controlled output signal resulting from applying the step attenuator and the variable attenuator to the changing power input signal.

A method of amplifying a signal is provided. The method includes: applying an analog gain to a signal, wherein an analog gain amount is applied with an offset lower than a set gain amount; applying a digital gain to the signal, wherein the amount of the applied digital gain is up to the offset; and converting the signal between digital and analog between the steps of applying the gain. The digital gain amount is adjustable based on the amplitude of the signal. The amplifier is further provided with an analog gain module, a digital gain module and a converter connected between the modules.

An aspect includes a filtering method including operating a first filter to filter a first input signal to generate a first output signal; operating a second filter to filter a second input signal to generate a second output signal; and selectively coupling at least a portion of the second filter with the first filter to filter a third input signal to generate a third output signal. Another aspect includes a filtering method including operating switching devices to configure a filter with a first set of pole(s); filtering a first input signal to generate a first output signal with the filter configured with the first set of pole(s); operating the switching devices to configure the filter with a second set of poles; and filtering a second input signal to generate a second output signal with the filter configured with the second set of poles.

An example apparatus includes: variable gain amplifier (VGA) circuitry having: an input terminal, an output terminal, and a control terminal; and peak detector circuitry having: an input terminal coupled to the output terminal of the VGA circuitry; an output terminal coupled to the control terminal of the VGA circuitry; the peak detector circuitry configured to: compare a voltage on the output of the VGA circuitry to an offset voltage; and adjust, responsive to the comparison, a gain of the VGA circuitry.

An integrated circuit (IC), comprising: a first input pin for receiving a first input signal; a first converter configured to convert the first input signal to a first output signal; a first gain stage configured to apply a first gain to the first output signal; gain update circuitry configured to: output a first external gain control signal to a first output pin of the IC; and subsequently output a first internal gain control signal to the first gain stage to update the first gain of the first gain stage, wherein output of the first internal gain control signal is delayed relative to output of the first external gain control signal by a first predetermined delay, the first predetermined delay to compensate for signal chain delay between the first input pin and the first gain stage.

To provide a signal amplifier for a wireless communication device that provides impedance scaling with gain mode conversion.SOLUTION: A signal amplifier 10 having an input impedance Zin that varies over different bias currents includes a gain stage including a plurality of switchable amplifier branches and a scalable impedance block 104 having a plurality of switchable inductive elements Zs1 to Zs4, and one or more of the amplifier branches when activated provides a targeted adjustment to the input impedance.SELECTED DRAWING: Figure 12

A transimpedance amplifier circuit includes an amplifier circuit configured to convert a current signal into a voltage signal with a gain being varied based on a control signal and a gain control circuit configured to generate the control signal based on an amplitude of the voltage signal, an amplitude detection signal in accordance with the amplitude of the voltage signal, an amplitude reference signal, a differential voltage signal obtained by offsetting a voltage difference between the amplitude detection signal and the amplitude reference signal based on an amplitude setting signal, and a differential current signal based on the differential voltage signal. The gain control circuit includes a variable capacitance being varied based on the amplitude setting signal, and is configured to be charged / discharged by the differential current signal and output a charging voltage. The control signal is generated based on the charging voltage.

A circuit (100) includes a programmable gain amplifier (PGA 102) having a PGA output. The circuit (100) further includes a delta-sigma modulator (104) having an input coupled to the PGA output. The circuit (100) also includes a digital filter (114) and a dynamic range enhancer (DRE) circuit (110). The digital filter (114) is coupled to the delta-sigma modulator output and to the PGA (102). The DRE circuit (110) is configured to monitor a signal level of the delta-sigma modulator output. In response to the signal level being less than a DRE threshold, the DRE circuit (110) is configured to program the PGA to a gain level greater than unity gain and to cause the digital filter to implement an attenuation of the same magnitude as the gain level to be programmed into the PGA (102).

A variable gain amplifier (100) includes first (110) and second (120) stage common-source (CS) amplifiers and a first transformer (130). The second stage CS amplifier (120) includes a differential circuit (121) and a current steering circuit (122). The differential circuit and the current steering circuit are coupled to a common connecting node (P), and the current steering circuit draws at least part of a current flowing through the differential circuit from the common connecting node (P). The first transformer (130) includes primary (130) and secondary (132) sides. A first terminal of the primary side (131) is coupled to an output terminal of the first stage CS amplifier, and a second terminal of the primary side is coupled to the common connecting node. A first terminal of the secondary side (132) is coupled to a first differential input terminal, and a second terminal is coupled to a second differential input terminal.

A circuit includes an analog-to-digital converter (ADC). The circuit also includes an analog front end (AFE, 310) having an AFE input and an AFE output. The AFE output is coupled to an input of the ADC. The AFE includes a programmable gain amplifier (PGA, 115) having a first PGA input and a second PGA input. The PGA (115) includes a first operational amplifier (OP AMP, OP1) having first and second OP AMP inputs. The AFE (310) also includes a programmable resistance circuit (320) having a first programmable resistance circuit input and first and second programmable resistance circuit outputs. The first programmable resistance circuit input is coupled to the first and second PGA inputs. The programmable resistance circuit (320) includes a resistor network having first and second balancing resistances. The first balancing resistance is coupled to the first and second OP AMP inputs, and the second balancing resistance is coupled to the first and second OP AMP inputs.

Disclosed is a low noise amplifier system. Included is a main amplifier having a main input coupled to a RF input and a main output connected to an RF output and an impedance amplifier having an impedance input coupled to the RF input and an impedance output coupled to the RF output, wherein the impedance amplifier is configured to provide input impedance matching to the main amplifier. The impedance amplifier also provides a first noise path that passes through the impedance amplifier such that the noise generated by the impedance amplifier is substantially out of phase with the noise that passes through a second noise path that passes through the main amplifier.

A receiver circuit, comprising: an receiver-input-terminal configured to receive input-signalling; an receiver-output-terminal configured to provide output-signalling; a plurality of sub-receivers, each configured to compare the received input-signalling with a different effective threshold value in order to provide a digital sub-receiver-output-signal, wherein the different effective threshold values have weighted values in a sequence between a least significant value and a most significant value; a controller configured to, in response to detecting calibration-signalling at the receiver-input-terminal: process the digital sub-receiver-output-signals in order to identify the sub-receiver with the most significant effective threshold value that is triggered by the calibration-signalling as a triggered-sub-receiver; identify a preceding-sub-receiver as the sub-receiver that has an effective threshold value that is before that of the triggered-sub-receiver in the sequence of weighted effective threshold values; and configure the receiver circuit such that, for subsequent signal processing, the sub-receiver-output-signal from the preceding-sub-receiver is provided to the receiver-output-terminal.

The present invention relates to a conversion device, or commonly called transimpedance amplifier, able to convert an input electric current (Id) from a current source such as a photonic sensor (D) into an output voltage (Vo) and comprising an integrated electronic circuit comprising, inter alia, a resistive component (Rf) of adjustable value and a capacitive component (Cf) of adjustable value. The invention also relates to a method for determining the values of the resistive component and of the capacitive component.

To suppress deterioration in radio characteristics.SOLUTION: Amplifying power of a first signal input via two or more amplifiers and a digital-to-analog converter (DAC) that performs output to each of the amplifiers; A clipping processing unit configured to perform, for a part of the amplifiers, clipping processing of multiplying power of the first signal by a clipping correction value in accordance with the power of the first signal so that the power of the first signal falls within a predetermined range, and a gain processing of multiplying the power of the first signal subjected to the clipping processing by a gain correction value; The gain processing unit returns the power of the first signal output from the DAC to the power before the gain processing and the clip processing are performed, and inputs the power to the amplifier.SELECTED DRAWING: Figure 3

Disclosed is a low noise amplifier system. Included is a main amplifier having a main input coupled to an RF input and a main output connected to an RF output and an impedance amplifier having an impedance input coupled to the RF input and an impedance output coupled to the RF output, wherein the impedance amplifier is configured to provide input impedance matching to the main amplifier. The impedance amplifier also provides a first noise path that passes through the impedance amplifier such that the noise generated by the impedance amplifier is substantially out of phase with the noise that passes through a second noise path that passes through the main amplifier.