624 results about "Programmable-gain amplifier" patented technology

A noise reduction circuit for reducing the effects of low frequency noise such as wind noise in communications applications is described. In one embodiment, the noise reduction circuit features a high pass filter formed by exploiting the existing off-chip AC coupling capacitances in making the connection to the source of audio signals. The filter may be adaptive to environmental low frequency noise level through programming the shunt resistances. A low-noise wide dynamic range programmable gain amplifier is also described. Adaptive equalization of the audio signal is also described through the utilization of programmable front-end resistors and a back-end audio equalizer.

A novel apparatus and method of reduced power consumption for battery backup operation of a communication device such as a cable modem. When the cable modem senses a failure of the external power source it requests from the cable head-end to switch from multi-channel DOCSIS 3.0 operation to single-channel DOCSIS 2.0 operation. In response to approval by the cable head-end, the cable modem shuts down multi-channel circuits in the PHY such as the wideband analog to digital converter (ADC) which is normally used during multi-channel operation. In its place, it activates narrowband circuitry such as a narrowband ADC which consumes far less power. Tuner filter circuits are also swapped to match the reduced bandwidth requirements of battery backup operation. To further reduce power, the narrower bandwidth requirements during battery backup operation permit the linearity of a programmable gain amplifier (PGA) in the upstream path to be reduced.

In a variable gain amplifier controlling a gain by using differential amplifiers with a gain control signal, a gain switchover differential amplifier or a bias circuit which composes a current mirror with the gain switchover differential amplifier is connected between a high and a low gain differential amplifier for the same bias current which are mutually connected to share load resistances for the same output polarity and a bias current source common to both of the differential amplifiers, to perform switchover operations of the high and the low differential amplifier by a gain control signal, and a current source which flows a fixed offset current through at least the low one of the high and the low differential amplifier is provided.

An automatic gain control method and system for use in signal processing of OFDM symbols at a receiver. Two stages of coarse and fine automatic gain control are implemented that adjust different gains in an analog RF processing stage of the receiver. Gain of a low noise amplifier and a mixer are adjusted during a first and coarse automatic gain control stage based on feedback from a digital baseband stage. During a subsequent fine gain control period, the gain of a programmable gain amplifier is adjusted separately for each frequency band used by the OFDM symbols based on a histogram bin that counts the number of output samples of an analog to digital converter whose magnitude falls within certain ranges. Coarse and fine gains are updated after each OFDM symbol.

A black clamp circuit for an image sensor utilizes a differential programmable gain amplifier and a feed-back loop to adjust a black level based on comparison to a reference black level. The gain (and therefore step size and range) of the feed-back loop constant for all programmable gain amplifier gain settings. The gain of the fee-back loop is kept constant by adjusting the values of programmable capacitors in the circuit.

ADC circuitry has a first programmable gain amplifier to amplify an analog input, a first analog to digital converter coupled to an output of the first amplifier, a second programmable gain amplifier, to amplify the analog input, a second analog to digital converter coupled to an output of the second amplifier, and a digital circuit for deriving a digital output from the outputs of the first and second converters and a controller for controlling the gains of the first and second amplifiers, according to the outputs of the first and second converters. Such programmable gain pre amplifiers help enable effective dynamic range to be extended without unduly increasing the number of quantisation bits, or the number of components or the power dissipation. It can be used in applications sensitive to size and power, such as DSP based acoustic devices including hearing aids.

The invention discloses a radio frequency automatic gain control amplifier. The radio frequency automatic gain control amplifier comprises a radio frequency receiving unit, a radio frequency amplifier control unit and an intermediate frequency amplifier, wherein the radio frequency receiving unit is composed of an adjustable low noise amplifier (LNA), a programmable gain amplifier (PGA), a down-conversion frequency mixer and a low-pass filter; the radio frequency amplifier control unit comprises a signal strength detector, a DAC (digital-to-analog converter), a comparator and a decoder; the signal strength detector is used for detecting the strength of an intermediate frequency signal; a comparator circuit is used for comparing an output signal of the signal strength detector with a fixed comparing level output from the DAC so as to output a comparison result; the decoder is used for inputting the comparison result into a gain control digital module and outputting a digital control signal so as to carry out the feedback control to the signal at the front end of the radio frequency, so that the gains of the LNA and the PGA are controlled, the signal to noise ratio of a receiving system is increased, and the requirements on dynamic ranges and high linearity of an input signal are met. The automatic gain control amplifier can be used in various radio frequency receiving chips flexibly, and particularly is applicable to radio frequency front-end circuit which has a wider input range of a radio frequency signal.

In receiver systems for cellular phones using the W-CDMA method, the change in DC voltage occurring when the gain of a programmable gain amplifier (PGA circuit) is switched to adjust the gain for a received signal, can be suppressed. A sample-and-hold circuit is installed containing a “sample” mode for directly outputting a signal from the PGA section and also containing a “hold” mode for outputting the electric charge of a specified voltage stored in a capacitor. This sample-and-hold circuit normally operates in “sample” mode so the output signal from the PGA section is directly output, but is operated in “hold” mode at the gain switching timing of the PGA circuit, so that the electric charge of the specified voltage stored in the capacitor is output for a specified length of time (equal to the time required for the DC voltage change to converge to a stable level).

The present invention relates to a system for measuring the impedance of a skin/electrode interface and selectively modifying the system gain of the monitoring circuit to compensate for errors introduced by variations in the skin/electrode impedance. More particularly, a simplified, low-cost method for measuring and compensating for skin/electrode impedance variations is provided. The skin/electrode impedance measuring circuit and determines a system gain correction factor which may be applied to the measured signal using a software algorithm, thereby eliminating the need to change the circuit topology with a programmable gain amplifier or programmable resistor network.

To reduce circuit area and power consumption and suppress transient response occurring at switching in PGA of a programmable gain amplifier is provided a wireless communication receiver comprising PGAs for adjusting the gain of a received signal down-converted by mixers and sending it to base-band block. Within PGAs are provided HPFATT circuits formed of capacitors arranged in series, and ladder resistors arranged in parallel, with signal lines, and a plurality of switches. HPFATT is a circuit serving as a high-pass filter and an attenuator for gain switching, wherein switches are controlled by control signal sg from a controller. Amplifiers connected to the rear stage of the HPFATT circuit are formed of MOS transistors.

A black clamp stabilization circuit for an image sensor utilizes a mixed-signal SoC block comprising sub-blocks to dynamically and precisely adjust the black level based on comparison to a reference black level. The black level adjustments include a first level regulation using digital control of an analog signal in a feedback loop that includes a programmable gain amplifier and high-resolution A/D converter. By applying the black clamping in the analog domain, dynamic range is extended. Additional black level regulation is subsequently performed in the digital domain to differentially eliminate line noise and column noise generated within the imaging System-on-Chip. By providing information between the sub-blocks, the algorithms can converge more quickly. The technique enables multiple signal paths to separately handle individual colors and to increase imaging data throughput.

Embodiments of the present invention provide a radio frequency identification (RFID) based electricity metering system enabled to meter energy consumption of individual devices. Specifically, embodiments of this invention provide a set (a least one) of RFID sensor units, each RFID sensor unit comprising: an inductor affixed to the power line of an electronic device configured to produce an induced current using the power line of the electronic device through inductive coupling; a programmable gain amplifier (PGA) coupled to the inductor configured to provide gain or attenuation control on the induced current so that the induced current is properly scaled; an analog-to-digital converter (ADC) configured to convert the amplitude of the induced current to a digital value representing the energy consumption of the electronic device; a central processing unit (CPU) coupled to the ADC configured to receive the digital value from the ADC; a memory unit configured to store the digital value from the CPU; an antenna coupled to the CPU configured to transmit the digital value within a frequency band; and an RFID reader configured to receive the digital value transmitted by the RFID sensor unit.

The invention discloses a multi-path data acquiring system based on FPGA, which mainly solves the problems of small signal acquiring range and poor acquiring precision of the prior multi-path acquiring system. The multi-path data acquiring system comprises a multi-path selector, a programmable-gain amplifier, an AD converter and an FPGA data processing module, wherein the FPGA data processing module sends an address signal to the multi-path selector and also sends a magnification signal to the programmable-gain amplifier; the multi-path selector selects an external analog signal according to the address signal to enter the programmable-gain amplifier; after amplifying the input analog signal, the programmable-gain amplifier outputs the analog signal to the AD converter; the AD converter samples the input analog signal, quantifies the analog signal to form a digital signal and transmits the digital signal to the FPGA data processing module; and the FPGA data processing module transmits the input data to a host computer after sequencing, wave filtering and table searching. The invention has the advantages of wide signal acquisition range, high precision can convenient acquisition path expansion, thereby being suitable for the signal acquisition of an industrial monitoring and sensing network.

The invention discloses a signal processing circuit of a fluxgate sensor. The signal processing circuit of the fluxgate sensor comprises a DSP (digital signal processor) and a signal feedback unit; an environment voltage signal collected by a fluxgate probe is linked with a digital signal processor through a bridging circuit and a programmable gain amplifier; the signal feedback unit feeds the processing signal of the digital signal processor back to the front end of the bridging circuit; the DSP comprises an analogue-digital converter, a digital frequency selector, a phase sensitive detector and a magnetic field calibrating module; the signal feedback unit comprises an interpolation calculation module, the analogue-digital converter and the programmable gain amplifier; the DSP receives the signal of the fluxgate probe, and outputs the size of the tested environment magnetic field by means of analogue-digital conversion, digital frequency selecting filtering, phase-sensitive rectifying and magnetic field calibration orderly; the measurement precision and the product performance of the fluxgate sensor are improved by digital treatment of the environment signal, so that adjustment and upgrade of the system are more convenient.

A system comprising an integrated multi-axis MEMS inertial sensor architecture. The system can include a MEMS gyroscope having a MEMS resonator and a MEMS accelerometer overlying a CMOS IC substrate. The CMOS IC substrate can include low noise Charge Sense amplifiers to process the sensed signals, programmable gain amplifiers, a demodulator, mixer, an AGC loop circuit coupled to the MEMS gyroscope to drive MEMS resonator. The CMOS IC also includes programmable Quadrature cancellation, Analog and digital phase shifters are implemented in the architecture to ensure quadrature cancellation and demodulation to achieve optimal performance. The AGC loop acts in a way such that generated desired signal amplitude out of the drive signal maintains MEMS resonator velocity at a desired frequency and amplitude while consuming low power. The MEMS gyroscope and accelerometer can be coupled to an input multiplexer configured to operate in a time-multiplexed manner.

An integrated circuit for controlling a DC motor is disclosed. The integrated circuit includes at least one digital position and speed circuit (DPS) for providing measurements of speed, position, and direction of the motor, the DPS being in signal communication with the motor for receiving a pair of signals having a quadrature relationship; and at least one programmable gain amplifier (PGA) electrically coupled to the motor, the PGA being configured to receive a feedback signal indicative of current flowing through the motor and to apply a second signal to the motor for adjusting the speed of the motor; and at least two analog-to-digital converters (A/D), one A/D being used to quantize the output of the PGA for an off-chip processor; and another A/D to provide motor reference position from an analog sensor, such as a potentiometer; and at least two digital-to-analog converters (D/A), one D/A used to set the motor voltage; and another D/A used to set the motor current limit. The integrated circuit can be incorporated into a larger motor control loop which further includes a summing amplifier for providing the feedback signal to the motor that is indicative of current flowing through the motor; a buffer amplifier electrically for sensing the output current of the motor, and a processor for providing control signals to the system monolithic module and for receiving the measurements of speed, position, and direction of the motor.

The invention discloses a system used for eliminating the Fixed Pattern Noise (FPN). The system includes a pixel array, a reading circuit used for reading the pixel value of each pixel unit, a programmable gain amplifier (PGA) algorithm unit, an A/D conversion unit and an FPN elimination unit; the system adopts the dummy pixel values of the current row and the current column for compensation; the invention also discloses an implementation method for eliminating the FPN, including that the pixel array is read; the read result is inputted to the PGA algorithm unit; a pixel offset is added to each pixel unit; the operation result is processed with A/D conversion; the dummy pixel values of the current row and the current column are used for compensation. Based on the system and the method for eliminating the FPN, each pixel in the pixel array not only can use the dummy pixel of the current row to eliminate the column FPN, but also can use the dummy pixel of the current column to eliminate the row FPN; besides, because the data of the dummy pixels in the pixel array are acquired real-timely, the dummy pixel data have certain compensation effect on the FPN caused by the power disturbance.

An image processing apparatus (200) for a charge coupled device including analog front end circuitry having optical black and offset correction, whereby the offset and optical black correction circuit is programmable. The present invention includes a first circuit (202, 204, 206, 208, 210) to sample the incoming optical black signal output from a CCD. This first circuit includes a correlated double sampler (202) coupled to a first programmable gain amplifier (204). An adder (206) connects between the first programmable gain amplifier (204) and a second gain amplifier (208) for adding in the optical black offset to the optical black signal input from the CCD. A second circuit (212, 214) includes a reverse programmable gain amplifier (212) connected to the output of the second programmable gain amplifier (208) to amplify the optical black level inversely proportional to the gain from the second programmable gain amplifier (208). The second circuit (212, 214) also includes an integrator (214) coupled to the reverse programmable gain amplifier (212) to integrate the difference between the incoming signal and the desired optical black value. The second circuit (212, 214) couples to the adder (206) to add the positive and negative difference to the optical black signal. An analog-to-digital converter (210) converts the sampled signal for further processing at the output of the image processing apparatus (200).

The invention discloses a signal conditioning circuit, a conditioning method thereof and a double sampling retaining circuit. The signal conditioning circuit comprises a first chopping switch, a programmable gain amplifier, a second chopping switch, a double sampling retaining circuit, an analog-to-digital converter, and a digital reduction sampling filter which are connected in sequence. The double sampling retaining circuit samples outputs of the programmable gain amplifier in two-phase positions of a chopping clock, and the results of two samplings are added. and an added output voltage is transmitted to and processed by the analog-to-digital converter, and the digital reduction sampling filter. Since the double sampling retaining circuit is added, the invention avoids the residual and off-tune problem in a chopping amplifier. Meanwhile, the invention facilitates the integration of a single chip, without the need of external filtering capacitor. Furthermore, a novel sequential control reduces the consumption of a digital signal conditioning circuit based on a chopping amplifier.