33 results about "Buffer amplifier" patented technology

A self-calibration digital-to-analog converter (DAC) and a calibration method for DAC are provided. The circuit includes a resistor circuit, a buffer amplifier, a fine-tuning circuit, and a correction switching circuit. In normal operation mode, the resistor circuit receives the common voltage for conversion. In correction mode, the circuit performs self-correction in a sampling time and a comparison time. During the sampling time, the resistor circuit receives the reference voltage and first correction data, and the buffer amplifier input samples the voltage. During the comparison time, the resistor circuit receives the common connection voltage and second correction data, and the fine-tuning circuit adjusts the correction data until the buffer amplifier output voltage flips and records the correction value corresponding to the second correction data. With this self-correction mechanism, the circuit can output theoretically correct digital-to-analog conversion results under the reference voltage and common connection voltage.

A kind of two-port driven isolation coupling device, including first buffer amplifier, isolation coupler and second buffer amplifier, the isolation coupler includes isolation coupling transmitting unit and isolation coupling receiving unit, the isolation coupling transmitting unit is electrically connected to the first buffer amplifier and the second buffer amplifier.The first buffer amplifier is configured to be controlled by first control signal to output first voltage to one end of the isolation coupling transmitting unit;The second buffer amplifier is configured to be controlled by second control signal to output second voltage to the other end of the isolation coupling transmitting unit;The isolation coupling transmitting unit is configured to be driven by the first voltage and the second voltage to be isolated to the isolation coupling receiving unit.

The invention discloses a multi-stage feedback broadband low-noise amplifier which comprises a first-stage amplifier, a second-stage amplifier and an output-stage buffer amplifier. The first-stage amplifier is composed of a cascode structure and a current multiplexing structure; the second-stage amplification electric appliance is composed of a complementary common-source structure and a current multiplexing structure. The output stage buffer amplification circuit is composed of a common source buffer structure and a current multiplexing structure. According to the invention, the cascade structure and the complementary common-source structure are connected in parallel, and inter-stage capacitance offset, source inductance and current multiplexing are adopted. By means of the mode, the use efficiency of current in the circuit is improved, the circuit gain and noise performance and the like are improved, on the other hand, the Miller effect is effectively restrained, a dominant pole is pushed to high frequency, and therefore the circuit bandwidth is greatly expanded.

A display device and a driving method thereof are disclosed. A display device according to an embodiment of the present application for solving the technical problem includes a display portion including a plurality of pixels connected with a data line and a sensing line, a data driving portion including a plurality of buffer amplifiers supplying a first sensing voltage to the data line during a first sensing period and a sensing portion receiving a first sensing signal from the pixels through the sensing line during the first sensing period, and a GIA amplifier providing a second sensing voltage to the data line during a second sensing period different from the first sensing period. The sensing portion receives a second sensing signal corresponding to the second sensing voltage from the pixels through the sensing line during the second sensing period and generates compensation data based on a difference between the first sensing signal and the second sensing signal.

A radio frequency (RF) front-end module (FEM) includes an amplifier and an integrated circuit coupled to the amplifier. The integrated circuit includes a buffer amplifier coupled to the amplifier, a variable attenuator coupled to the buffer amplifier, a phase shifter or time delayer coupled to the buffer amplifier, and a memory configured to store a gain calibration value and a phase calibration value. The gain calibration value controls an attenuation of the variable attenuator and the phase calibration value controls a phase shift of the phase shifter or a time delay of the first time delayer. The RF FEM also includes an interface configured to store the gain calibration value and the phase calibration value in the memory, an RF connection to a transceiver, and an RF connection to an antenna.

The embodiment of the invention provides a terahertz dual-band radar transceiver and a radar system, and belongs to the technical field of communication. The transceiver comprises a terahertz voltage-controlled oscillator (VCO), a buffer amplifier, a double-harmonic generator and a terahertz double-frequency on-chip antenna which are connected in sequence. The method is characterized in that a single radio frequency link and an antenna are adopted to realize dual-band operation: in a transmitting mode, after a high-frequency signal generated by a VCO is amplified, a dual-harmonic generator generates a dual-band signal containing a fundamental frequency and a second harmonic, and the dual-band signal is radiated through the antenna; in the receiving mode, the double-harmonic generator is multiplexed as a frequency mixer, and echo signals received by the antenna are down-converted into intermediate-frequency signals to be output. According to the invention, the amplitude of the dual-frequency signal is balanced through the controllable asymmetric bias design, and the modulation bandwidth is equivalently expanded through the digital domain synthesis intermediate frequency signal. The problems that a traditional dual-frequency system is large in chip area and high in cost and a single-frequency system is low in resolution are solved, and the system has the advantages of being high in integration level, low in cost and high in resolution.

The application relates to the field of feedback type automatic gain control circuits, and discloses a full-differential peak detection AGC circuit, which comprises a multi-stage variable gain amplifier, a buffer amplifier group, a first comparator EA1, a full-differential peak detection unit and an external port; the external port comprises a power supply end VDD, a ground end GND, a negative signal input end INN, a positive signal input end INP, a positive signal output end VON, a negative signal output end VOP, a plurality of bias ports and a reference voltage end VREF; the application adopts a full-differential structure design, can effectively suppress common-mode noise and external interference, and realizes continuous discharge adjustment of the capacitor C11 through the alternate discharge of the first NMOS tube NM1 and the second NMOS tube NM2 on the capacitor C11, avoids the problem of capacitor discharge interruption in traditional peak detection, improves the loop response speed and the gain adjustment precision, and even if one of the differential signals is temporarily missing, the other signal can still drive the peak detection unit and the feedback loop to work, thereby improving the reliability.

Disclosed embodiments provide a self-contained topology that enables a significant noise reduction of capacitive sensor readout interfaces. For example, various embodiments can provide low noise capacitive sensor readout interfaces or analog front ends having a main buffer amplifier in a bootstrap configuration, wherein a bootstrap loop configuration comprises a negative capacitance coupled to an input of the main buffer amplifier with a negative impedance converter.

The application discloses a kind of multi-core voltage-controlled oscillator local oscillator signal power synthesis extraction devices, including power synthesis network, the power synthesis network is coupled with multi-core voltage-controlled oscillator, and the local oscillator signal of each core of multi-core voltage-controlled oscillator is power synthesized, the port of the power synthesis network is used to extract high-power local oscillator signal after power synthesis.The application can realize the output power promotion of local oscillator signal on the basis of reducing the phase noise of local oscillator signal of multi-core voltage-controlled oscillator by introducing power synthesis network, improve the direct current-radio frequency conversion efficiency of multi-core voltage-controlled oscillator, so as to save the direct current power consumption of subsequent output buffer amplifier.

This disclosure provides methods, devices, and systems for generating clock signals. The present implementations more specifically relate to generating multiple clock signals having different frequencies using a single piezoelectric resonator. In some aspects, a clock generator, including a piezoelectric resonator coupled to a voltage amplifier in a feedback network, may be operable in a high-performance mode and a low-power mode. When operating in the high-performance mode, the clock generator may produce a high frequency clock signal and a low frequency clock signal using the same piezoelectric resonator. In some implementations, the high frequency clock signal may be produced by a buffer amplifier coupled to an output of the voltage amplifier and the low frequency clock signal may be produced by a frequency divider coupled to the output of the voltage amplifier. When operating in the low-power mode, the clock generator produces only the low-frequency clock signal via the frequency divider.

The utility model provides a novel digital composite signal generator, specifically related to data composite signal technical field, including single-chip microcomputer and digital synthesis circuit, single-chip microcomputer inside integrated DAC, and DAC generates fundamental wave sinusoidal signal, and digital synthesis circuit includes operational amplifier module and low pass filter module, and the fundamental wave sinusoidal signal of DAC generation, through operational amplifier module promotes fundamental wave amplitude, and low pass filter restrains high -frequency noise, ensures the output smooth pure sinusoidal wave. Buffer amplifier enhances signal drive ability and adapts 100 omega load, and adjustable gain module realizes output amplitude accurate control. The on -chip VDD monitor real -time monitoring power supply anomaly, watchdog timer prevents program failure, and JTAG debugging circuit supports non -invasive full -speed in system debugging. The scheme fuses signal processing, voltage monitoring and fault protection function, realizes the novel digital composite signal generator of frequency and amplitude programmable control, guarantees output stable and reliable in industrial environment and long -term unattended operation.

Examples include a column readout amplifier and an image sensor including the same. In one example, the column readout amplifier includes a signal amplifier having an amplifier output and first and second amplifier inputs, a filter capacitor having first and second terminals, the second terminal connected to a ground terminal, a buffer amplifier having a buffer amplifier input and a buffer amplifier output, a switching network configured to switchably connect the amplifier output to the buffer amplifier input and the buffer amplifier output to the first terminal of the filter capacitor during a first period and to switchably connect the amplifier output directly to the first terminal of the filter capacitor during a second period, and a low pass filter connected in a feedback path of the signal amplifier between the amplifier output and the first amplifier input, the low pass filter including a series resistor and a capacitor.

The invention relates to compensation for low dropout voltage regulators. In one form, a low dropout voltage regulator configured to provide a drive signal to adjust an output voltage in response thereto includes an error amplifier, an intermediate amplifier, a buffer amplifier, and a compensation network. The error amplifier has a first input to receive a reference voltage, a second input to receive a feedback signal representative of the output voltage, a first output, and a second output. The intermediate amplifier has a first input coupled to the first output of the error amplifier, a second input coupled to the second output of the error amplifier, and an output. The buffer amplifier has a first input coupled to the output of the intermediate amplifier and an output to provide the drive signal. The compensation network has a first terminal coupled to the first input of the intermediate amplifier and a second terminal coupled to the output of the intermediate amplifier.

This invention provides a waveform digitization analog front-end circuit suitable for low power supply voltages. Its unit circuit includes a switched capacitor circuit, a buffer amplifier, and a comparator. The buffer amplifier consists of an amplifying transistor Mnt and a current source Ib. The input voltage signal Vin is connected to the gate of the sampling capacitor Cs via a sampling switch SW, and simultaneously connected to the gate of the amplifying transistor Mnt in the buffer amplifier. The other end of the sampling capacitor Cs is connected to signal ground. The drain of the buffer amplifier is connected to the power supply voltage VDD, and the source of the buffer amplifier is connected to the current source Ib and the negative input terminal of the comparator. The positive input terminal of the comparator is connected to the ramp voltage VRamp. This invention solves the problem of obtaining a large input dynamic range under low power supply voltage conditions, effectively alleviating the contradictions between power supply voltage, input dynamic range, linearity, accuracy, noise, and area.

The invention discloses a voltage and current integrated sensor and a three-phase measurement system and method, and relates to the technical field of electric power measurement, and the system comprises a current measurement module which comprises a magnetic core used for generating magnetic flux after a primary current passes through a primary side conductor, and a secondary side winding used for collecting a magnetic core induction signal, the compensation winding is used for carrying out fixed transformation ratio output on the magnetic core induction signal according to the selected measuring range; the voltage measuring module comprises a puncture unit used for collecting voltage in a puncture needle sampling mode, a voltage dividing network used for selecting the voltage dividing ratio according to the voltage amplitude and outputting the voltage after voltage dividing, and a buffer amplifier used for amplifying the voltage after voltage dividing. And the signal conditioning module is used for carrying out standardized conditioning output on the current and the voltage output by the current measurement module and the voltage measurement module so as to carry out power load identification. High-quality analog signals can be provided for rear-end digital equipment, and the requirements of power load identification and electric energy quality analysis are met.

The invention provides a driving circuit, a display device and a driving method of a display panel. The driving circuit comprises a time schedule controller, a data driving circuit and a power management chip. The data driving circuit comprises a digital-to-analog converter and a buffer amplifier, the digital-to-analog converter is electrically connected with the time schedule controller and the buffer amplifier, and the buffer amplifier is electrically connected with the display panel; the power management chip is electrically connected with the timing controller and the positive power end of the buffer amplifier; the time schedule controller controls the power management chip to output a first positive power supply voltage to the positive power supply end of the buffer amplifier when determining that a picture to be displayed is a crosstalk picture based on original image data; and when the to-be-displayed picture is determined to be a non-crosstalk picture based on the original image data, the power management chip is controlled to output a positive power supply voltage of which the voltage value is greater than the first positive power supply voltage to the positive power supply end of the buffer amplifier. The driving circuit can improve the crosstalk problem of the display panel.

This invention relates to a dual-reference synthesized voltage generation circuit, comprising: a first reference source circuit and a second reference source circuit; a PWM circuit, including an analog switch and an isolation chip, wherein the analog switch is connected to the output terminal of the second reference source circuit and the isolation chip respectively; a digital control circuit, connected to the isolation chip via the digital control chip; a filter circuit, connected to the analog switch; an integral feedback circuit, connected to the filter module; a buffer amplifier circuit, connected to the output terminals of the second reference source circuit and the integral feedback circuit; and a protection circuit, with its input terminal connected to the first reference source circuit and the buffer amplifier circuit, and its output terminal connected to the integral feedback circuit. This invention employs a dual-reference voltage synthesis approach, reducing dependence on precision resistors and temperature, minimizing changes in the reference chip output caused by temperature variations, and simultaneously reducing high-frequency noise introduced by PWM modulation.

The invention relates to a leakage compensation circuit and a method for leakage compensation, and an integrated circuit having the leakage compensation circuit. In one form, the leakage compensation circuit comprises a buffer amplifier, a link coupling element and a leakage compensation element. The buffer amplifier has an output and an input coupled to a sense node. The link coupling element has an output and an input coupled to the output of the buffer amplifier, wherein the link coupling element is unidirectional in a direction from the input to its output. The leakage compensation element has a first current terminal coupled to the sense node, a control terminal coupled to the output of the link coupling element, and a second current terminal coupled to a reference voltage terminal.

An exemplary receive antenna having a conductive surface. The conductive surface includes an aperture configured to operate as a slot antenna, and one or more amplifiers or buffer amplifiers is electrically connected across the aperture. At least one feed is connected between the one or more amplifiers and the aperture. An input impedance ZB of each of the one or more amplifiers at the at least one feed location is lower than 0.5× an impedance of the aperture ZA at a first resonance frequency.

A radio antenna comprises a folded monopole radiator, a high-impedance buffer amplifier, and a ground wire. The amplifier includes an input side, an output side, a two-pole filter, and a voltage regulator. The input side is electrically connected to the folded monopole radiator and maintains a constant impedance level, while the output side is electrically connected to a power source and also maintains a constant impedance level. The two-pole filter attenuates frequencies, and the voltage regulator is configured to supply the buffer amplifier with a fixed DC bias when power is received from the power source. The flexible ground wire is directly wired to the amplifier, has a metallic mounting end, and is positioned to maintain a constant impedance level across the folded monopole radiator.

The invention discloses a W-band fully differential active phase shifter with high linearity and low temperature fluctuation. The W-band fully differential active phase shifter comprises a spiral differential quadratic coupler, an I-path high-linearity buffer amplifier, a Q-path high-linearity buffer amplifier, an I-path vector modulation circuit, a Q-path vector modulation circuit, a vector synthesis output circuit, a bias current array and a current source in quadratic correlation with temperature, wherein the spiral differential orthogonal coupler adopts two completely symmetrical spiral coupling line structures to reduce the area and generate differential orthogonal signals with high precision and low insertion loss; on the basis that the I-path high-linearity buffer amplifier and the Q-path high-linearity buffer amplifier isolate post-stage impedance fluctuation to the spiral differential quadrature coupler, the linearity of a circuit is improved through a source feedback resistor, and deterioration of the linearity of the whole phase shifter is avoided; the I-path vector modulation circuit and the Q-path vector modulation circuit both adopt a variable gain amplifier structure capable of realizing phase inversion, and have a larger gain control range and better linearity while realizing phase inversion; a common-base triode with a self-biased resistor is used as an output buffer stage to realize a vector synthesis function, and the structure can ensure relatively constant output impedance in different phase shift states so as to realize good output matching in all phase shift states; a current source in secondary correlation with the temperature is used for biasing, and the change of the gain of the whole circuit along with the temperature is compensated so as to reduce the temperature fluctuation.

A self-calibrated buffered-voltage DAC includes a DAC configured to receive an input digital signal and output a first analog voltage signal, a buffer amplifier configured to receive the first voltage signal from the DAC and provide a buffered second analog voltage signal, a voltage to frequency converter configured to selectively receive the first and second voltage signals and provide first and second output signals at respective first and second frequencies, a counter configured to receive the output signals from the voltage to frequency converter and provide respective first and second digital output signals corresponding to the respective first and second frequencies, a comparator configured to receive the first and second digital output signals and provide a digital calibration offset, and a DAC error code module configured to receive a digital input code and the digital calibration offset and to provide an offset corrected input digital signal to the DAC.

Example embodiments include an apparatus with a buffer amplifier having an output node. A first switchable unidirectional current path is provided between the output node and a capacitor, the first path allowing current flow from the capacitor to the output node. A second switchable unidirectional current path is provided between the output node and the capacitor, the second path allowing current flow from the output node to the capacitor. Comparator circuitry is provided that operates to open the first path if the capacitor voltage is above an upper threshold and to open the second path if the capacitor voltage is below a lower threshold. The capacitor voltage may be read by an analog-to-digital converter.

The invention provides a digital-to-analog conversion circuit capable of self-correction and a correction method of a digital-to-analog converter. The circuit comprises a resistance circuit, a buffer amplifier, a fine tuning circuit and a correction switching circuit. In the normal operation mode, the resistance circuit receives the common voltage for conversion. In the correction mode, the circuit carries out self-correction in two steps: sampling time and comparison time. In sampling time, the resistance circuit receives a reference voltage and a first correction digital value, and the input end of the buffer amplifier samples the voltage. And at the comparison time, the resistance circuit receives the common voltage and the second correction digital value, the fine tuning circuit adjusts the correction data until the output voltage of the buffer amplifier is overturned, and the correction value is recorded to correspond to the second correction digital value. By means of the self-correction mechanism, the circuit can output theoretically correct digital-analog conversion results under the reference voltage and the common voltage.

The invention provides a power ramp circuit configured to generate a combined output signal, the power ramp circuit comprising: a plurality of ramp slice circuits, each ramp slice circuit configured to provide an output voltage upon activation, wherein the power ramping circuit is configured to combine the output voltages of the ramp slice circuits so as to provide the combined output signal, and wherein each ramp slice circuit comprises: a buffer circuit comprising a buffer amplifier; and a smoothing circuit configured to selectively operate in a current limiting mode and a non-current limiting mode, and an RF power amplifier configured to amplify an input signal, and wherein the amplification applied by the RF power amplifier is controlled by the buffer circuit.

A steering control device (7) is provided with a charge removal circuit (39) that, when an input to a buffer amplifier (37), which generates an excitation signal to be supplied to a rotation sensor (28), is switched from a first excitation pulse to a second excitation pulse, removes the charge charged in an excitation capacitor (38) before the switching.

The invention discloses a system and method for polarization-resistant voltage of a bio-electricity signal acquisition front end, the system comprises an electrode, an analog front-end chip U1, a buffer amplifier, a right leg driving module and a compensation module, the buffer amplifier is arranged between the electrode and the analog front-end chip U1 and is used for improving the input impedance of a bio-electricity signal; and the right leg driving module is used for improving the mode rejection ratio, performing compensation processing on the bio-electricity signal output by the analog front-end chip U1, and recovering the attenuated effective signal in real time. Therefore, on the premise that the signal-to-noise ratio and the input impedance of the system are not sacrificed, the common-mode input voltage range is obviously expanded. The problem of saturation distortion or performance reduction of the amplifier caused by overlarge polarization voltage generated by an electrode-skin interface in a dry electrode scene or a long-time monitoring scene is effectively solved.

This invention provides a current integral value measuring device that suppresses the discharge rate under long-term storage conditions while using small-capacity capacitors, leading to accurate evaluation of insulation performance. [Solution] The current integral value measuring device (20) is a measuring circuit (23) having a measuring input terminal (21) and a ground terminal (22), and comprises a charge storage capacitor (24) connected in series with an insulating sample (S), a surge absorber (27) connected in parallel with the charge storage capacitor, a buffer amplifier (25) connected from the connection point of the surge absorber towards the measuring input terminal, and a surge current protection resistor (26) connected before the buffer amplifier. The charge storage capacitor, the surge absorber, and the surge current protection resistor are potted, and the charge storage capacitor, the surge absorber, the surge current protection resistor, and the buffer amplifier are connected to the measuring circuit by point-to-point wiring.

A buffer amplifier device includes a first-side buffer amplifier and a first-side current mirror circuit; the first-side current mirror circuit is electrically connected to the first-side buffer amplifier. The first-side buffer amplifier is configured to output a first-side current; the first-side current mirror circuit is configured to output a first-side replicated current associated with the first-side current; the first-side buffer amplifier is configured to receive a first-side input voltage and output a first-side output voltage; the first-side output voltage is equal to the first-side input voltage, or the first-side output voltage is a fixed multiple of the first-side input voltage.

The present disclosure provides a power ramping circuit configured to generate a combined output signal comprising: a plurality of ramp slice circuits each configured to, upon activation, provide an output voltage, wherein the power ramping circuit is configured to combine the output voltages of the ramp slice circuits in order to provide the combined output signal, and wherein each ramp slice circuit comprises: a buffer circuit comprising a buffer amplifier; and a smoothing circuit configured to selectively operate in a current-limiting mode and a non-current-limiting mode and an RF power amplifier which is configured to amplify an input signal and wherein the amplification applied by the RF power amplifier is controlled by the buffer circuit.