188 results about "Clock buffer" patented technology

The invention relates to an ultra-low power consumption multichannel high-speed signal synchronous acquisition and emission system suitable for satellite communication. The system comprises an acquisition and emission board card which mainly comprises a plurality of radio frequency transceivers, an optical module, a clock unit, an FPGA (Field Programmable Gate Array) 1 processor and the like; the clock unit comprises a clock chip, a clock Buffer and the like; the optical module is used for receiving data, sending the data to an FPGA (Field Programmable Gate Array) 1 for processing, then sending the data to a transmitting channel of the radio frequency transceiver through a JESD204B interface for interpolation filtering, QEC (Quadrature Error Correction) calibration and refreshing, and then performing up-conversion to output an I / Q analog modulation signal; a receiving channel of the radio frequency transceiver receives an I / Q analog signal, the I / Q analog signal is sampled after low-pass filtering, the sampled data is sent to the FPGA1 for processing through the JESD204B interface after QEC calibration, and then the data is forwarded through the optical module. The system can realize ultra-low power consumption and reduce the weight of the whole machine.

The invention provides a clock input buffer and electronic equipment. The clock input buffer comprises a multi-protocol input circuit, a level conversion circuit, a step-down circuit and a clock buffer circuit. The multi-protocol input circuit is adjusted to different working modes through a control signal transmitted by the control unit so as to be compatible with various input protocols, the multi-protocol input circuit processes an input signal based on a target working mode, and the level conversion circuit performs level shifting on an output signal of the multi-protocol input circuit so as to realize multi-protocol conversion. The voltage reduction circuit is used for converting the output signal into a low-voltage domain signal so as to meet the working voltage requirement of the clock buffer circuit, and meanwhile, the voltage reduction circuit is used for reducing the power supply voltage so as to provide low-voltage power supply voltage for the clock buffer circuit; therefore, the clock buffer circuit can buffer high-speed signals in different input protocols and voltage ranges by using a low-voltage domain device, and the application scenarios of the clock input buffer are greatly expanded.

The invention discloses an LVDS (Low Voltage Differential Signaling) receiving circuit and an LVDS transmitting circuit for cross-BANK transmission. The LVDS receiving circuit for cross-BANK transmission comprises a clock channel and a plurality of data channels, the clock channel and the data channels are distributed in at least two BANKs, and the clock channel and at least one of the data channels are located in the same BANK; the programmable phase-locked loop is used for receiving a single-ended clock signal generated by the clock channel, and the first global clock buffer and the second global clock buffer are respectively used for buffering a first clock and a second clock and then outputting the first clock and the second clock; each of the clock channel and the data channel comprises a differential-to-single-ended module, a delay module and a serial-to-parallel conversion module. The programmable phase-locked loop and the global clock buffer are introduced, the clock channels and the data channels are distributed in the at least two BANKs, it is guaranteed that part of the data channels and the clock channels are located in the same BANK, and a flexible and efficient LVDS transmission architecture for cross-BANK transmission is achieved.

The invention belongs to the technical field of hardware circuit board design, and discloses a PCIe Switch board downlink port compatible uplink port structure, which comprises a CPU (Central Processing Unit), a PCIe Switch chip, a PCIe port, PCIe equipment, a downlink port Root end and a Clock Buffer, the PCIe expansion system constructs a tree topology through a PCIe Switch chip, a single PCIe channel of a CPU is branched into a plurality of independent channels, and parallel access of multiple devices is achieved. The Switch chip comprises an uplink port and a plurality of downlink ports, and the uplink port is directly connected with the PCIe controller of the CPU through a special connector and bears a data signal and a key clock signal; clock signals are transmitted by adopting high-speed differential pairs. According to the PCIe Switch board, high-efficiency expansion is achieved through the design that a downlink port of the PCIe Switch board is compatible with an uplink port and multi-dimensional technological innovation, the core of the PCIe Switch board adopts a CPLD dynamic configuration technology, a BPTYPE level and a 2W-CLK mode are switched in real time through an onboard dial switch, the same physical port can be flexibly configured to be an I2C master equipment clock source or a data channel, and the switching delay is smaller than 50 ns.

The invention discloses a hard disk backboard and a server, and relates to the technical field of servers. The power supply control interface of the backboard controller is connected with the hard disk connector, the power supply control function of the hard disk is fully utilized to control the work of the hard disk, the situation that the occupied area of the backboard is additionally increased in an electronic fuse mode is avoided, and connection is achieved only in an interface mode; meanwhile, a clock buffer is added and integrated with a power supply control function of the hard disk to realize a power-on time sequence which is strictly required by a high-speed signal of a specific hard disk, so that the hard disk identification error problem caused by a time sequence error risk is reduced, the hard disk identification accuracy is improved, and the adaptation compatibility between the hard disk and a mainboard is correspondingly improved. Besides, the backboard controller and the hard disk connector are connected through the first communication interface, the situation that key information is leaked due to the fact that conventional hard disk information acquisition occupies a polling communication protocol for a long time is avoided, and the safety of hard disk information acquisition is improved.

The invention discloses a multi-channel clock buffer test system and method, and relates to the technical field of electronic testing, and the method comprises the steps: collecting an original waveform data set, synchronizing a unified reference baseline, and generating a clock output data stream; performing frequency domain transformation on the clock output data stream, extracting dominant frequency drift, harmonic intensity change and phase fluctuation, and generating a spectrum disturbance feature vector sequence; performing recursive estimation on the spectrum disturbance feature vector sequence by using a Kalman filter, correcting state distribution in combination with a Bayesian probability updating method, and generating a health score drift trend vector; and performing multi-scale comparison on the health score drift trend vector, and identifying a channel entering a sub-health area by using an abnormal drift acceleration factor to generate an abnormal channel feature data set. According to the method, complex association between historical failure modes and features is mastered through the training time sequence prediction network, potential health score changes and failure time in the future are effectively predicted, and early warning is achieved.

The embodiment of the invention discloses a memory device, an operation method and a memory system. The memory device includes: a bias generation circuit configured to: generate a target bias signal according to a data transmission rate of the memory device; the target bias signal changes along with the change of a preset data transmission rate range; and the clock buffer circuit is coupled with the bias generation circuit and is configured to perform conversion processing on an input clock signal matched with the data transmission rate based on the target bias signal to obtain a target clock signal used by the memory device.

The invention relates to a radio frequency transceiving multichannel amplitude-phase calibration system, which comprises a radio frequency receiver, a radio frequency transmitter, a data converter, an FPGA (Field Programmable Gate Array) processor and a clock network, wherein the radio frequency receiver adopts a zero intermediate frequency architecture and is used for receiving a multichannel radio frequency signal and down-converting the multichannel radio frequency signal into an analog baseband signal; the radio frequency transmitter adopts a zero intermediate frequency architecture and is used for up-converting the analog baseband signal into a radio frequency signal and transmitting the radio frequency signal; the data converter is connected with the radio frequency receiver and the radio frequency transmitter and is used for realizing conversion between an analog signal and a digital signal; the FPGA processor is connected with the data converter through a JESD204B interface and is used for aligning the data of each receiving and transmitting channel; and the clock network consists of a clock chip with JESD204B characteristics and a clock Buffer, and is used for providing a synchronous clock and an SYSREF signal for the whole system and supporting an SYNC synchronous trigger signal. By adopting the method, the problem of multi-channel amplitude-phase consistency can be solved.

A quadrature clock generator that takes advantage of the inherently low delay of a shunt-series inductively peaked clock buffer to generate quadrature clocks with the high jitter performance using just one additional stage in Q path compared to I path. The generator includes a delay cell that uses shunt-series peaking and uses a resistive DAC in series with the shunt inductor to provide a large delay range with good jitter characteristics. The resistive DAC can be placed near a real or a virtual ground to minimize capacitive loading on the signal path. This delay cell can provide greater than 2× delay tuning range and is suitable for clocks at high frequencies. This delay cell can also be used as a ring oscillator with large frequency tuning range. A low voltage differential signaling termination switch control that uses feed forward mechanism to control termination impedance of device in a receiver.

A clock buffer has a clock-in port that inputs a reference clock and an enable port that inputs a video-clock-enable signal from a video receiver. The clock buffer generates a video pixel clock signal that has pulses of the reference signal as enabled by the video-clock-enable signal. The video receiver includes a link symbol extractor, a link-to-pixel mapper, and a timing generator that work to mirror the actual pixel data rate from the active period in a blanking period and thereby recover the actual video pixel clock.

The embodiment of the utility model provides a mainboard, a daughter card and electronic equipment. The first mainboard comprises a selection switch, a phase-locked loop and at least one first clock buffer, the output end of the selection switch is connected with the input end of the phase-locked loop, and the selection switch is used for gating one of the input ends of the selection switch and the output end of the selection switch; a plurality of input ends of the selection switch are respectively used for inputting a first clock source signal and a second clock source signal, the first clock source signal is generated by a clock source of the first mainboard, and the second clock source signal is generated by a clock source of the daughter card; the output end of the phase-locked loop is connected with the input end of the first clock buffer, and the phase-locked loop is used for outputting a first output clock signal to the first clock buffer; the first clock buffers are used for buffering first output clock signals and outputting second output clock signals to the daughter cards, and one first clock buffer corresponds to one daughter card.

A phase-locked loop or delay locked loop provides a coarse alignment between an input clock and an output clock. A latch receiver circuit provides an indicator of a delay error between the input clock and the output clock. The delay error is used by a control circuit or state machine to adjust a fine delay that affects the output clock signal timing relative to the input clock signal. The fine delay is adjusted to minimize the timing difference between the output clock signal and the input clock signal.

The invention relates to the technical field of clock source sharing, and particularly discloses a system and a method for sharing a clock source by a platform, which are used for sampling LVPECL clock signals distributed to a Feiteng processor and a 10-gigabit network card by a clock buffer so as to obtain a first LVPECL clock sampling signal and a second LVPECL clock sampling signal; and a signal processing algorithm based on artificial intelligence and deep learning is introduced at a rear end to analyze LVPECL clock sampling signals of the two, so that fine-grained optimal matching interaction characteristics of the LVPECL clock sampling signals of the two are learned and captured, and signal waveform semantic joint representation and clock buffer performance monitoring are carried out. Therefore, the monitoring result of whether the working state of the clock buffer is abnormal or not is obtained. Therefore, the quality of the clock signal can be continuously checked and monitored in an intelligent automatic monitoring mode, and the working condition of the clock buffer can be fed back in time.

The invention provides an extensible server architecture system suitable for various processors, which comprises a main board carrying a processor; the backboard is integrated with a multi-protocol interface control chip, a programmable clock buffer, a plurality of impedance adjusting circuits, a plurality of expansion slots and a plurality of groups of differential high-speed signal channels, the backboard is connected with the mainboard and the expansion slots through internal wiring, and the expansion slots are used for connecting pluggable expansion modules; the plurality of switching chips are arranged on a connecting path of the back plate and the mainboard and are used for topological connection of the processor and the expansion slot; the switching chip supports automatic negotiation of a PCIe / CXL protocol; according to the invention, the bus protocol difference between the processor and the pluggable expansion module is automatically adapted through the multi-protocol interface control chip and the switching chip, so that the universality of the system is improved; through the impedance adjusting circuit and the programmable clock buffer, the difference of different pluggable expansion modules in electrical characteristics and time sequences is solved, and the compatibility stability of different devices is guaranteed.

The invention discloses a multichannel clock buffer test system and method, and relates to the technical field of semiconductor testing, and the method comprises the steps: calibrating the delay of an optical clock signal of each time-to-digital converter node to a preset precision threshold value; a standard clock signal is injected into the clock buffer input channel, and the clock buffer is driven to enter a working state; triggering a time-to-digital converter array by using the calibrated optical clock signal, collecting timestamp data of each output channel of a clock buffer, and generating an original time data set; inputting the original time data set into a double-mixing processor, and outputting a multi-channel skew parameter and a three-dimensional cloud picture; the multi-channel skew parameter is converted to a life indicator value for each output channel of the clock buffer based on the multi-channel skew parameter invoking a material model. According to the invention, the original time data set is subjected to two times of frequency mixing processing through the double frequency mixing processors, and phase detection and spectrum analysis are combined, so that high-precision extraction of the time deviation value of each output channel of the clock buffer is realized.

The invention provides a time-delay phase-locked loop circuit and a system device.According to the time-delay phase-locked loop circuit, the first time-delay circuit to the (2a + 1) th time-delay circuit and the second time-delay circuit to the (2a + 1) th phase discriminator are additionally arranged on the basis of an original DLL circuit framework (including a first phase discriminator), the first time-delay circuit is arranged between a controllable time-delay chain and a clock buffer circuit, and the second time-delay circuit is arranged between a controllable time-delay chain and a clock buffer circuit; the second to (2a + 1) th delay circuits are cascaded and further delay feedback clock signals output by the copy clock buffer circuit, so that the second to (2a + 1) th delay circuits and the copy clock buffer circuit generate (2a + 1) feedback clock signals, and the first to (2a + 1) th phase discriminators detect the phase relation between the feedback clock signals and external clock signals. The control circuit can quickly judge the moment when the phase difference between the output clock signal and the external clock signal is less than 1C (the 1C is the coarse adjustment unit length of the controllable delay chain) or is less than 2C and 1C respectively according to the detection results of the phase discriminators, so that the locking steps are reduced, the locking time is shortened, and the locking of the DLL circuit is accelerated.

A semiconductor device includes: a cell region including active regions where components of transistors are formed; the cell region are arranged to function as a D flip-flop that includes a primary latch (having a first sleepy inverter and a first non-sleepy (NS) inverter), a secondary latch (having a second sleepy inverter and a second NS inverter), and a clock buffer (having third and fourth NS inverters). The transistors are grouped: a first group has a standard threshold voltage (Vt_std); a second group has a low threshold voltage (Vt_low); and an optional third group has a high threshold voltage (Vt_high). The transistors which comprise the first or second NS inverter have Vt_low. Alternatively, the transistors of the cell region are further arranged to function as a scan-insertion type of D flip-flop (SDFQ) that further includes a multiplexer; and the transistors of the multiplexer have Vt_low.

A clock tree 900 comprises a first clock buffer 906 electrically connected to a second clock buffer 910. The first clock buffer comprises a first transistor 972, a second transistor 974, a first resis

Disclosed are techniques for reducing voltage drooping in a microelectronic chip, including separating a scan data launch clock from a capture clock with a variable time delay depending on a delay of a succeeding scan path of the latches, where the scan data launch clock and the capture clock are based on a base clock signal. The techniques further include analyzing and categorizing the latches against the time delay into dedicated buffer group categories. The techniques further include assigning the at least two local clock buffers to the latches within the dedicated buffer group categories.

The present invention discloses a trigger merging method, system, medium and product based on K-means clustering. The method of the present invention comprises obtaining all triggers in the same clock domain in the layout completed design and putting them into a list; taking a trigger from the list as the current cluster center, calculating the distance from other triggers to the trigger; if the distance is less than T1, adding the trigger to the class corresponding to the current cluster center; if the distance is less than T2, deleting the trigger from the list; repeating the above steps to finally obtain K Cluster centers are assigned to triggers according to the cost value. K The present invention aims to reduce the number of clock tree leaf nodes and thus reduce the line length of the clock network and the number of clock buffers required on the clock network, thereby reducing the area and power consumption of the clock network and better controlling the clock deviation by automatically selecting and determining the number and position of the initial cluster centers and merging the clustered triggers.

The application belongs to the technical field of automatic test program, and particularly relates to a LabVIEW test method of a multi-channel programmable output clock buffer. The method comprises the following steps: initializing the clock buffer after power-on; resetting the FSWP spectrum analyzer and clearing the previous interface settings; switching the radio frequency switch to channel 1 and opening the channel 1 output; setting the signal source input frequency; setting the signal source input amplitude; starting the signal source input, and outputting the set frequency and amplitude to the input end of the clock buffer; starting the register configuration module, and transmitting the 174 24-bit register values to the SPI in sequence through the serial port, and then transmitting the SPI to the clock buffer; reading the data on the FSWP spectrum analyzer; and the method automatically measures the key indicators of the 14-channel clock buffer, saves the data and judges the advantages and disadvantages. The method reduces the burden of the test personnel, reduces the test time cost, and avoids causing data errors.

A clock architecture, including one or more clock module layers; each clock module layer including one or more clock modules, each clock module including a local clock generator, a selection switch circuit and a plurality of clock buffer circuits; wherein the local clock generator is configured to generate an independent local clock signal; a first input terminal of the selection switch circuit receives the local clock signal, a second input terminal of the selection switch circuit receives an external clock signal, a plurality of output terminals of the selection switch circuit are respectively connected to input terminals of the plurality of clock buffer circuits, and an enable terminal of the selection switch circuit is configured to receive an enable signal; and the selection switch circuit is configured to enable, all the output terminals to output the local clock signal or enable all the output terminals to output the external clock signal, according to the enable signal.

A DC coupled buffer is provided with two switching transistors controlled by a delayed version of an output signal for the DC coupled buffer. A first of the switching transistors functions to cut off a current discharged into ground that would otherwise flow when an input signal for the DC coupled buffer is discharged. A remaining second of the switching transistors functions to increase the operating speed of the DC coupled buffer.

Methods, systems, and products for power reduction by removal of redundancy in clock pathways of VLSI circuits includes: calculating, based on a circuit design data file, a timing budget for an LCB (local clock buffer) and an associated group of latches receiving a clock signal from the LCB, where the circuit design data file includes a structural representation of a circuit design and timing data, identifying, based on the timing budget, a delay element to remove, the delay element included within a delay element chain associated with the LCB, and removing the delay element from the circuit design.

An inverter circuit, usable in a clock buffer circuit, includes a main inverter stage having a first transistor of a first conductivity type coupled in series with a second transistor of a second conductivity type, wherein control electrodes of the first and second transistors are coupled to an input node and first current electrodes of the first and second transistors are coupled at an output node. The inverter circuit also includes a first set of additional transistors of the first conductivity type, a second set of additional transistors of the second conductivity type, and a set of switches configured to connect a first transistor of the first set of additional transistors in series with the first transistor for a first time period while connecting a first transistor of the second set of additional transistors in parallel with the second transistor during the first time period.

A memory device is provided. The memory device includes: a clock buffer for receiving a master clock signal and providing an internal master clock signal; a data clock buffer for receiving a data clock signal; and a delay control circuit configured to generate delay information based on the data clock signal and provide the delay information to a data input / output circuit. The delay control circuit includes: a frequency divider configured to generate a divided-by-two clock signal based on the data clock signal; a frequency divider configured to generate a divided-by-four clock signal based on a first group of divided-by-two clock signals; a first synchronization detector configured to output a divided-by-two alignment signal indicating whether the second group of divided-by-two clock signals is synchronized with the data clock signal; and a delay selector configured to detect a phase of the divided-by-four clock signal based on the divided-by-two alignment signal and adjust the delay of the master clock signal based on the phase.

Provided is a memory device including a chip select (CS) buffer that is configured to output a first internal chip selection signal, a command clock (CK) buffer that is configured to output an internal clock signal, a command / address (CA) buffer that that is configured to output a first internal command / address signal, a CA buffer controller configured to control on / off of the CA buffer based on the first internal chip selection signal, synchronize the first internal chip selection signal and the first internal command / address signal to the internal clock signal, and delay the phase of a second internal chip selection signal synchronized to the internal clock signal, and a command decoder configured to decode any one of the second internal chip selection signal, a phase-delayed third internal chip selection signal, and / or a second internal command / address signal synchronized with the internal clock signal.

The application discloses a kind of high-precision time interval measuring instrument based on GNSS and TDC-GPX2, including thermostatic crystal oscillator, level conversion module, clock buffer module, GNSS receiver module, time interval measurement module, main control module and digital-analog conversion module.The application combines the technology of taming thermostatic crystal oscillator, uses the 1PPS signal of GNSS receiver output to tame thermostatic crystal oscillator, designs the outlier algorithm module based on Allan variance to improve stability in taming process, according to the Kalman filter state equation of thermostatic crystal oscillator output frequency established, reasonable filter parameters can be obtained, so that Kalman filter algorithm module can effectively reduce the measurement error caused by 1PPS signal jitter, thermostatic crystal oscillator can output high-precision clock signal under long-term taming, and the high-precision frequency signal output by thermostatic crystal oscillator is used as reference clock signal by time interval measurement module, so as to improve measurement accuracy.The time interval measuring instrument of the application has the characteristics of simplicity, low cost and high precision.

Embodiments of this disclosure provide an apparatus and method for generating a circuit clock signal. The apparatus includes: a clock buffer configured to buffer an original clock signal to obtain a buffered clock signal; a clock delay unit configured to delay the original clock signal to obtain a plurality of delayed clock signals, the plurality of delayed clock signals being delayed by different amounts of time relative to the original clock signal; a broadened clock generator configured to generate a broadened clock signal based on the original clock signal and the plurality of delayed clock signals, the frequency of the broadened clock signal being lower than the frequency of the original clock signal; and a clock selector configured to select one of the buffered clock signal and the broadened clock signal as the circuit clock signal based on the selection signal.

Examples of the present application disclose a memory device, an operation method, and a memory system. The memory device includes: a bias generation circuit configured to generate a target bias signal according to a data transfer rate of the memory device, wherein the target bias signal varies with a preset data transfer rate range; and a clock buffer circuit coupled with the bias generation circuit and configured to perform, based on the target bias signal, conversion processing on an input clock signal matched with the data transfer rate to obtain a target clock signal used by the memory device.