76 results about "Clock buffer" patented technology

The invention discloses a multi-channel clock buffer test system and method, and relates to the technical field of electronic testing, and the method comprises the steps: collecting an original waveform data set, synchronizing a unified reference baseline, and generating a clock output data stream; performing frequency domain transformation on the clock output data stream, extracting dominant frequency drift, harmonic intensity change and phase fluctuation, and generating a spectrum disturbance feature vector sequence; performing recursive estimation on the spectrum disturbance feature vector sequence by using a Kalman filter, correcting state distribution in combination with a Bayesian probability updating method, and generating a health score drift trend vector; and performing multi-scale comparison on the health score drift trend vector, and identifying a channel entering a sub-health area by using an abnormal drift acceleration factor to generate an abnormal channel feature data set. According to the method, complex association between historical failure modes and features is mastered through the training time sequence prediction network, potential health score changes and failure time in the future are effectively predicted, and early warning is achieved.

The invention relates to a radio frequency transceiving multichannel amplitude-phase calibration system, which comprises a radio frequency receiver, a radio frequency transmitter, a data converter, an FPGA (Field Programmable Gate Array) processor and a clock network, wherein the radio frequency receiver adopts a zero intermediate frequency architecture and is used for receiving a multichannel radio frequency signal and down-converting the multichannel radio frequency signal into an analog baseband signal; the radio frequency transmitter adopts a zero intermediate frequency architecture and is used for up-converting the analog baseband signal into a radio frequency signal and transmitting the radio frequency signal; the data converter is connected with the radio frequency receiver and the radio frequency transmitter and is used for realizing conversion between an analog signal and a digital signal; the FPGA processor is connected with the data converter through a JESD204B interface and is used for aligning the data of each receiving and transmitting channel; and the clock network consists of a clock chip with JESD204B characteristics and a clock Buffer, and is used for providing a synchronous clock and an SYSREF signal for the whole system and supporting an SYNC synchronous trigger signal. By adopting the method, the problem of multi-channel amplitude-phase consistency can be solved.

The invention provides an extensible server architecture system suitable for various processors, which comprises a main board carrying a processor; the backboard is integrated with a multi-protocol interface control chip, a programmable clock buffer, a plurality of impedance adjusting circuits, a plurality of expansion slots and a plurality of groups of differential high-speed signal channels, the backboard is connected with the mainboard and the expansion slots through internal wiring, and the expansion slots are used for connecting pluggable expansion modules; the plurality of switching chips are arranged on a connecting path of the back plate and the mainboard and are used for topological connection of the processor and the expansion slot; the switching chip supports automatic negotiation of a PCIe / CXL protocol; according to the invention, the bus protocol difference between the processor and the pluggable expansion module is automatically adapted through the multi-protocol interface control chip and the switching chip, so that the universality of the system is improved; through the impedance adjusting circuit and the programmable clock buffer, the difference of different pluggable expansion modules in electrical characteristics and time sequences is solved, and the compatibility stability of different devices is guaranteed.

The invention discloses a multichannel clock buffer test system and method, and relates to the technical field of semiconductor testing, and the method comprises the steps: calibrating the delay of an optical clock signal of each time-to-digital converter node to a preset precision threshold value; a standard clock signal is injected into the clock buffer input channel, and the clock buffer is driven to enter a working state; triggering a time-to-digital converter array by using the calibrated optical clock signal, collecting timestamp data of each output channel of a clock buffer, and generating an original time data set; inputting the original time data set into a double-mixing processor, and outputting a multi-channel skew parameter and a three-dimensional cloud picture; the multi-channel skew parameter is converted to a life indicator value for each output channel of the clock buffer based on the multi-channel skew parameter invoking a material model. According to the invention, the original time data set is subjected to two times of frequency mixing processing through the double frequency mixing processors, and phase detection and spectrum analysis are combined, so that high-precision extraction of the time deviation value of each output channel of the clock buffer is realized.

A clock tree 900 comprises a first clock buffer 906 electrically connected to a second clock buffer 910. The first clock buffer comprises a first transistor 972, a second transistor 974, a first resis

Disclosed are techniques for reducing voltage drooping in a microelectronic chip, including separating a scan data launch clock from a capture clock with a variable time delay depending on a delay of a succeeding scan path of the latches, where the scan data launch clock and the capture clock are based on a base clock signal. The techniques further include analyzing and categorizing the latches against the time delay into dedicated buffer group categories. The techniques further include assigning the at least two local clock buffers to the latches within the dedicated buffer group categories.

The application belongs to the technical field of automatic test program, and particularly relates to a LabVIEW test method of a multi-channel programmable output clock buffer. The method comprises the following steps: initializing the clock buffer after power-on; resetting the FSWP spectrum analyzer and clearing the previous interface settings; switching the radio frequency switch to channel 1 and opening the channel 1 output; setting the signal source input frequency; setting the signal source input amplitude; starting the signal source input, and outputting the set frequency and amplitude to the input end of the clock buffer; starting the register configuration module, and transmitting the 174 24-bit register values to the SPI in sequence through the serial port, and then transmitting the SPI to the clock buffer; reading the data on the FSWP spectrum analyzer; and the method automatically measures the key indicators of the 14-channel clock buffer, saves the data and judges the advantages and disadvantages. The method reduces the burden of the test personnel, reduces the test time cost, and avoids causing data errors.

An inverter circuit, usable in a clock buffer circuit, includes a main inverter stage having a first transistor of a first conductivity type coupled in series with a second transistor of a second conductivity type, wherein control electrodes of the first and second transistors are coupled to an input node and first current electrodes of the first and second transistors are coupled at an output node. The inverter circuit also includes a first set of additional transistors of the first conductivity type, a second set of additional transistors of the second conductivity type, and a set of switches configured to connect a first transistor of the first set of additional transistors in series with the first transistor for a first time period while connecting a first transistor of the second set of additional transistors in parallel with the second transistor during the first time period.

The application discloses a kind of high-precision time interval measuring instrument based on GNSS and TDC-GPX2, including thermostatic crystal oscillator, level conversion module, clock buffer module, GNSS receiver module, time interval measurement module, main control module and digital-analog conversion module.The application combines the technology of taming thermostatic crystal oscillator, uses the 1PPS signal of GNSS receiver output to tame thermostatic crystal oscillator, designs the outlier algorithm module based on Allan variance to improve stability in taming process, according to the Kalman filter state equation of thermostatic crystal oscillator output frequency established, reasonable filter parameters can be obtained, so that Kalman filter algorithm module can effectively reduce the measurement error caused by 1PPS signal jitter, thermostatic crystal oscillator can output high-precision clock signal under long-term taming, and the high-precision frequency signal output by thermostatic crystal oscillator is used as reference clock signal by time interval measurement module, so as to improve measurement accuracy.The time interval measuring instrument of the application has the characteristics of simplicity, low cost and high precision.

Embodiments of this disclosure provide an apparatus and method for generating a circuit clock signal. The apparatus includes: a clock buffer configured to buffer an original clock signal to obtain a buffered clock signal; a clock delay unit configured to delay the original clock signal to obtain a plurality of delayed clock signals, the plurality of delayed clock signals being delayed by different amounts of time relative to the original clock signal; a broadened clock generator configured to generate a broadened clock signal based on the original clock signal and the plurality of delayed clock signals, the frequency of the broadened clock signal being lower than the frequency of the original clock signal; and a clock selector configured to select one of the buffered clock signal and the broadened clock signal as the circuit clock signal based on the selection signal.

Examples of the present application disclose a memory device, an operation method, and a memory system. The memory device includes: a bias generation circuit configured to generate a target bias signal according to a data transfer rate of the memory device, wherein the target bias signal varies with a preset data transfer rate range; and a clock buffer circuit coupled with the bias generation circuit and configured to perform, based on the target bias signal, conversion processing on an input clock signal matched with the data transfer rate to obtain a target clock signal used by the memory device.

This utility model discloses a signal hub board and a grid screen control system for a mesh screen. The signal hub board includes an input interface, multiple output interfaces, and a signal distribution circuit. The input interface receives a drive signal from a receiving card, which includes a master clock signal and multiple parallel data signals. The signal distribution circuit includes a clock buffer module and a data buffer module. The clock buffer module receives the master clock signal and, through buffering and copying, generates multiple output clock signals that are the same number as the number of output interfaces and synchronized with the phase. The data buffer module buffers the multiple parallel data signals one-to-one to generate multiple output data signals. Each output clock signal is paired with its corresponding output data signal and sent to a single mesh screen module through the corresponding output interface. The signal hub board and control system of this application improve signal quality by centrally synchronizing and shaping the drive signals, thereby ensuring that the mesh screen can achieve smooth, clear, and high-quality video playback.

The utility model discloses E1 interface equipment for connecting PCM (Pulse Code Modulation) equipment and signaling conversion equipment, which belongs to the technical field of telecommunication and comprises an E1 interface A, an E1 interface B, an E1 interface C, an E1 interface D, an E1 transceiver A, an E1 transceiver B, an E1 transceiver C, an E1 transceiver D, an FPGA (Field Programmable Gate Array) controller A, an FPGA controller B, a DPS chip A, a DPS chip B, a clock synchronization circuit, a 232 communication module, a communication interface, a power supply circuit and a 12V power supply interface. By adopting the FPGA / DSP cooperative low-jitter clock buffer and isolation protection circuit, precise clock synchronization of multiple paths of E1 signals is realized, the technical problems of clock drifting and hardware processing capability bottleneck in a traditional system are effectively solved, task separation and efficient cooperation can be realized, a consistent and low-jitter reference clock is provided, and the reliability of the system is improved. The method has obvious advantages in clock synchronization, data processing and module division.

This utility model discloses a computer processing module and a computer, relating to the field of computer technology. It includes an onboard CPU, a first PCIe x8 interface and an information interface connected to a bridge chip, a power interface of the bridge chip connected to a power module, and the bridge chip further configured to connect a second memory chip, a second Flash chip, and a first crystal oscillator; the bridge chip; the onboard CPU further configured to connect the first memory chip, the first Flash chip, and an RTC clock chip; an FMC connector, the FMC connector including multiple first expansion interface groups connected to the onboard CPU, and multiple second expansion interface groups and functional interface groups connected to the bridge chip; and a second crystal oscillator, the second crystal oscillator providing clock to the onboard CPU, the bridge chip, and the FMC connector through a clock buffer. This achieves miniaturization and interface expansion.

The application relates to a clock calibration device, a method and a tire pressure monitoring system. The clock calibration device is applied to a tire pressure sensing device. A temperature reading module reads the working temperature of the tire pressure sensing device when the tire pressure sensing device is in a wake-up reset state. Then, a query module queries clock buffer data corresponding to the working temperature. A correction determination module determines whether the clock buffer data is consistent with initial data and generates a determination result. A correction module obtains clock correction data according to the determination result. Finally, a clock calibration module modulates the clock signal of the tire pressure sensing device according to the clock correction data, so that the frequency of the modulated clock signal reaches a target frequency. In this way, the working period offset of the tire pressure sensing device caused by temperature change can be dynamically corrected during the working process, thereby prolonging the service life of the tire pressure sensing device and finally improving the reliability of the monitoring system.

The application provides a high-speed serial communication interface, a chip and a clock distribution method. The high-speed serial communication interface comprises an internal-external interconnection module, at least one internal reference clock buffer module and an external reference clock buffer module. The external reference clock buffer module is connected with the internal-external interconnection module, and the internal-external interconnection module is connected with the at least one internal reference clock buffer module. The external reference clock buffer module is used for receiving a clock signal of an external clock source and outputting the clock signal to the internal-external interconnection module. The at least one internal reference clock buffer module is used for receiving a clock signal from other high-speed serial communication interfaces and outputting the clock signal to the internal-external interconnection module, or outputting a clock signal received from the internal-external interconnection module to other high-speed serial communication interfaces. The internal-external interconnection module is used for taking the clock signal received from the external reference clock buffer module or the clock signal received from the at least one internal reference clock buffer module as a reference clock of the high-speed serial communication interface.

Semiconductor device (100B) comprising: a cell region (102B) containing active regions extending in a first direction and comprising transistor components formed therein; wherein the transistors of the cell region (102B) are arranged to function as a D flip-flop (234, 434), DFF, comprising a primary latch (236, 336), a secondary latch (238, 338), and a clock buffer (246, 346); the primary latch (236, 336) comprising a first sleepy inverter (250, 350) and a first non-sleepy inverter (248, 348), NS inverter; the secondary latch (238, 338) comprising a second sleepy inverter (250, 350) and a second NS inverter (248, 348) includes; and the clock buffer (246, 346) includes the third and fourth NS inverters (248, 348); a first group of some, but not all, of the transistor elements has elements configured with a standard threshold voltage, these being referred to as Vt_std elements;a second group of some, but not all, of the transistor elements that have a low threshold voltage configured lower than the standard threshold voltage, these being referred to as Vt_low elements; and those of the transistors that comprise the third NS inverter (248, 348) and / or the fourth NS inverter (248, 348) are Vt_low elements of the second group, wherein: a third group of some, but not all, of the transistor elements that have a high threshold voltage configured higher than the standard threshold voltage, these being referred to as Vt_high elements; and those of the transistors that comprise the first sleepy inverter (250, 350) of the primary latch (236, 336) and the second sleepy inverter (250, 350) of the secondary latch (238, 338) are Vt_high elements of the third group.

The application provides a relay adjusting circuit of an endoscope and the endoscope. The relay adjusting circuit is provided with an input interface, a clock buffer, an input impedance adjusting module, an output matching adjusting module and an output interface. The input end of the clock buffer is electrically connected with the input interface. The input impedance adjusting module is connected with the input end and the grounding end of the clock buffer in parallel. The output matching adjusting module is electrically connected with the output end of the clock buffer. The output interface is electrically connected with the output matching adjusting module. The clock buffer is used for receiving a first clock driving signal adjusted by the input impedance adjusting module, enhancing the driving capacity of the adjusted first clock driving signal, obtaining a second clock driving signal and outputting the second clock driving signal. The output matching adjusting module is used for adjusting the signal peak value of the second clock driving signal, outputting a third clock driving signal with identifiable high and low level properties, and then compensating the signal attenuation formed by long-distance transmission and improving the accuracy of image acquisition.

This application provides a synthesis method, storage medium, and program product for H-type clock trees, relating to the field of chip design. The method classifies each clock unit in the clock structure according to the number of flip-flops it covers; determines the number of H-type clock trees and their generation order based on different types of clock units and clock source types; uses a weighted clustering algorithm to determine the starting point and mounting point position of each H-type clock tree according to the number of H-type clock trees and their generation order; and constructs the corresponding H-type clock tree according to the starting point and mounting point position of each H-type clock tree. The H-type clock tree structure design of this application can effectively reduce unnecessary clock buffers and wiring capacitors, controlling power consumption at its source. It is applicable to clock structures with multiple clock sources and complex clock logic, and is suitable for large-scale high-performance integrated circuit design, providing a more efficient and reliable clock design solution for related design work.

The present application relates to the field of servers, and discloses a server clock architecture and a configuration method therefor, a device, a product, and a medium, used for solving the problem that a clock transmission link of a server clock architecture cannot satisfy the clock constraint of a common clock architecture. The server clock architecture comprises a main control assembly, a chipset, a crystal oscillator circuit, and a first-stage clock buffer that are arranged on a server main board, and further comprises a second-stage clock buffer arranged on an external card. The main control assembly is used for adjusting the working mode of the first-stage clock buffer and / or the working mode of the second-stage clock buffer when the current transmission delay time of a clock transmission link does not satisfy a clock constraint corresponding to the server clock architecture, so that the current transmission delay time of the clock transmission link satisfies the clock constraint. The present application enables the clock transmission link of the server clock architecture to satisfy the clock constraint, and allows for peripheral compatibility due to an adaptable peripheral slot.

This invention discloses a layout structure, design method, and system-on-a-chip for a clock buffer module. The layout structure of the clock buffer module includes: a standard buffer unit; multiple functional element units, including at least one pre-embedded coupling capacitor unit and at least one pre-embedded charge discharge unit; multiple functional element units are integrated in the layout in a manner surrounding the standard buffer unit; signal pins and power pins are located on different preset high-layer metal layers, and the signal connection terminals and power connection terminals of the standard buffer unit are electrically connected to the signal pins and power pins respectively through internal connection holes. The technical solution provided by this invention improves upon the uncontrollable problems such as wiring, voltage drop, and antenna effects caused by directly using high-drive-force devices provided in the process library, while also avoiding the dependence on customized high-drive-force devices for high-speed, long-distance, low-latency applications.

The invention discloses a high-speed multi-channel low-jitter USB device capable of being used for infrared circuit clock configuration, the device comprises a shell, a USB socket is fixedly assembled on one side of the shell, a frequency adjusting and distributing unit is arranged in the shell, a programmable clock in the frequency adjusting and distributing unit is electrically connected with a microcontroller, and the microcontroller is electrically connected with the USB socket. The clock buffer is electrically connected with the programmable clock, the clock buffer is used for receiving a clock signal of the programmable clock and distributing the clock signal into six pairs of differential clocks, through the programmable clock chip and a precision algorithm, the 1Hz precision linear continuous adjustment of the output frequency within the range of 10 MHz to 810 MHz is realized, and meanwhile, the output frequency of the programmable clock chip is greatly improved. The integrated clock buffer can synchronously distribute one path of high-quality clock into six pairs of differential signals to ensure that the multi-channel infrared imaging system obtains synchronous low-jitter clock input.

To provide a circuit configuration that reduces hold violation of scan data, and that is advantageous for preventing an increase in circuit scale and an increase in power consumption.SOLUTION: A plurality of logical circuits include n data holding circuits each holding data, a scan chain transferring scan data, and a clock line including a plurality of clock buffers for delaying clock signals. The clock signals in the clock line are supplied to the n data holding circuits, and clock signals are supplied to the n data holding circuits, such that the amount of delay of the clock signal is increased from the first data holding circuit toward the n-th data holding circuit that is on the most downstream side in a forward direction. The scan chain is used to transfer the scan data in a reverse direction directed from the n-th data holding circuit toward the first data holding circuit. The scan data is transferred between the logical circuits via a delay adjustment unit.SELECTED DRAWING: Figure 2

A source drive integrated circuit (IC) with a length in a first direction and a width in a second direction perpendicular to the first direction, includes: one or more digital circuit parts configured to receive a digital signal and arranged along the first direction; a plurality of signal wires connected to the digital circuit parts and configured to transmit the digital signal to the digital circuit parts and configured to transmit the digital signal to the one or more digital circuit parts; a plurality of signal buffers configured to be connected in series to each of the plurality of signal wires; a clock wire configured to be arranged along the first direction to be connected to the one or more digital circuit parts, and configured to transmit a clock to the digital circuit parts; and a plurality of clock buffers connected in series to the clock wire.

Disclosed are techniques for reducing voltage drooping in a microelectronic chip, including separating a scan data launch clock from a capture clock with a variable time delay depending on a delay of a succeeding scan path of the latches, where the scan data launch clock and the capture clock are based on a base clock signal. The techniques further include analyzing and categorizing the latches against the time delay into dedicated buffer group categories. The techniques further include assigning the at least two local clock buffers to the latches within the dedicated buffer group categories.

The application discloses a clock data recovery circuit for half-rate data re-timing, comprising a switched capacitor module, a filter capacitor, a two-stage differential ring oscillator, a clock buffer, a four same OR gate module and a re-timer module, wherein the switched capacitor module controls a sampling period and a sampling frequency by using input binary random data, samples a clock signal and outputs a sampling voltage signal; the filter capacitor filters the sampling voltage signal and outputs a control voltage; the two-stage differential ring oscillator generates four clock signals according to the control voltage; the clock buffer obtains the four square wave clock signals; the four same OR gate module outputs a double frequency clock signal and feeds back to the switched capacitor module; and the re-timer module samples binary random data according to two square wave clock signals. The application can significantly reduce power consumption, reduce area, save cost, and has good jitter performance of recovered clock and jitter tolerance performance of recovered data.

A local clock buffer for improving energy efficiency using a power saving clock buffer for clock grid-based scanning includes a grid node that receives a global clock signal from a global clock grid; a clock enable latch configured to latch a clock enable signal, wherein the clock enable latch is clocked based on the global clock signal; a clock gate configured to output a functional clock signal in dependence upon a latched value of the clock enable signal; a scan clock enable latch configured to latch a scan enable signal, wherein the scan enable latch is a non-clocked latch; and a scan clock gate coupled to the output of the functional clock gate and configured to output a scan clock signal in dependence upon a latched value of the scan enable signal.

This invention belongs to the field of clock synchronization technology, and relates to a telemetry expansion method and an inter-board synchronization acquisition circuit. The inter-board synchronization acquisition circuit includes: a first circuit board and at least one set of second circuit boards; the first circuit board includes a first analog-to-digital converter (ADC), a controller chip, a clock chip, and a first clock buffer; the second circuit board includes a second ADC and a second clock buffer; the controller chip's first serial communication interface operates in master mode to configure and read data from the registers of the first ADC and configure the registers of the second ADC; the controller chip's second serial communication interface operates in slave mode to read data from the second ADC. This invention achieves synchronization of the clock feedback path between telemetry expansion and the expanded circuit board, avoiding data reading errors caused by asynchronous clock signals and data input signals on the SPI bus due to signal delays in the transmission path.

A semiconductor device is provided. The semiconductor device includes a plurality of power lines extending in a first direction, first transistors each formed in a first region and having a first threshold voltage, and second transistors each formed in a second region and having a second threshold voltage higher than the first threshold voltage. One of the plurality of power lines is interposed between the first region and the second region, the first transistors implement a first portion of a multiplexer, a clock buffer, and a first latch, the first portion of the multiplexer, the clock buffer, and the first latch are disposed on a data path, the second transistors implement a second portion of a multiplexer circuit and a second latch, the second portion of the multiplexer circuit and the second latch are disposed on a feedback path, and the first portion of the multiplexer circuit and the second portion of the multiplexer circuit are disposed at a common location along the first direction.

A method for clock distribution network control includes determining, at a first clock node of a plurality of clock nodes within a clock distribution network, a downstream clock request status. A clock request signal is transmitted by the first clock node to an upstream parent node based on the downstream clock request status. A clock buffer of the first clock node is toggled based at least in part on the clock request signal to the parent node. If the first clock node receives an asserted clock request signal from one or more downstream child nodes and clock acknowledgment signal from the parent node, a clock enable signal is asserted to the clock buffer to output a clock signal to the one or more downstream child nodes.