138 results about "Clock buffer" patented technology

The invention relates to an ultra-low power consumption multichannel high-speed signal synchronous acquisition and emission system suitable for satellite communication. The system comprises an acquisition and emission board card which mainly comprises a plurality of radio frequency transceivers, an optical module, a clock unit, an FPGA (Field Programmable Gate Array) 1 processor and the like; the clock unit comprises a clock chip, a clock Buffer and the like; the optical module is used for receiving data, sending the data to an FPGA (Field Programmable Gate Array) 1 for processing, then sending the data to a transmitting channel of the radio frequency transceiver through a JESD204B interface for interpolation filtering, QEC (Quadrature Error Correction) calibration and refreshing, and then performing up-conversion to output an I / Q analog modulation signal; a receiving channel of the radio frequency transceiver receives an I / Q analog signal, the I / Q analog signal is sampled after low-pass filtering, the sampled data is sent to the FPGA1 for processing through the JESD204B interface after QEC calibration, and then the data is forwarded through the optical module. The system can realize ultra-low power consumption and reduce the weight of the whole machine.

The invention provides a clock input buffer and electronic equipment. The clock input buffer comprises a multi-protocol input circuit, a level conversion circuit, a step-down circuit and a clock buffer circuit. The multi-protocol input circuit is adjusted to different working modes through a control signal transmitted by the control unit so as to be compatible with various input protocols, the multi-protocol input circuit processes an input signal based on a target working mode, and the level conversion circuit performs level shifting on an output signal of the multi-protocol input circuit so as to realize multi-protocol conversion. The voltage reduction circuit is used for converting the output signal into a low-voltage domain signal so as to meet the working voltage requirement of the clock buffer circuit, and meanwhile, the voltage reduction circuit is used for reducing the power supply voltage so as to provide low-voltage power supply voltage for the clock buffer circuit; therefore, the clock buffer circuit can buffer high-speed signals in different input protocols and voltage ranges by using a low-voltage domain device, and the application scenarios of the clock input buffer are greatly expanded.

The invention discloses an LVDS (Low Voltage Differential Signaling) receiving circuit and an LVDS transmitting circuit for cross-BANK transmission. The LVDS receiving circuit for cross-BANK transmission comprises a clock channel and a plurality of data channels, the clock channel and the data channels are distributed in at least two BANKs, and the clock channel and at least one of the data channels are located in the same BANK; the programmable phase-locked loop is used for receiving a single-ended clock signal generated by the clock channel, and the first global clock buffer and the second global clock buffer are respectively used for buffering a first clock and a second clock and then outputting the first clock and the second clock; each of the clock channel and the data channel comprises a differential-to-single-ended module, a delay module and a serial-to-parallel conversion module. The programmable phase-locked loop and the global clock buffer are introduced, the clock channels and the data channels are distributed in the at least two BANKs, it is guaranteed that part of the data channels and the clock channels are located in the same BANK, and a flexible and efficient LVDS transmission architecture for cross-BANK transmission is achieved.

The invention belongs to the technical field of hardware circuit board design, and discloses a PCIe Switch board downlink port compatible uplink port structure, which comprises a CPU (Central Processing Unit), a PCIe Switch chip, a PCIe port, PCIe equipment, a downlink port Root end and a Clock Buffer, the PCIe expansion system constructs a tree topology through a PCIe Switch chip, a single PCIe channel of a CPU is branched into a plurality of independent channels, and parallel access of multiple devices is achieved. The Switch chip comprises an uplink port and a plurality of downlink ports, and the uplink port is directly connected with the PCIe controller of the CPU through a special connector and bears a data signal and a key clock signal; clock signals are transmitted by adopting high-speed differential pairs. According to the PCIe Switch board, high-efficiency expansion is achieved through the design that a downlink port of the PCIe Switch board is compatible with an uplink port and multi-dimensional technological innovation, the core of the PCIe Switch board adopts a CPLD dynamic configuration technology, a BPTYPE level and a 2W-CLK mode are switched in real time through an onboard dial switch, the same physical port can be flexibly configured to be an I2C master equipment clock source or a data channel, and the switching delay is smaller than 50 ns.

The invention discloses a multi-channel clock buffer test system and method, and relates to the technical field of electronic testing, and the method comprises the steps: collecting an original waveform data set, synchronizing a unified reference baseline, and generating a clock output data stream; performing frequency domain transformation on the clock output data stream, extracting dominant frequency drift, harmonic intensity change and phase fluctuation, and generating a spectrum disturbance feature vector sequence; performing recursive estimation on the spectrum disturbance feature vector sequence by using a Kalman filter, correcting state distribution in combination with a Bayesian probability updating method, and generating a health score drift trend vector; and performing multi-scale comparison on the health score drift trend vector, and identifying a channel entering a sub-health area by using an abnormal drift acceleration factor to generate an abnormal channel feature data set. According to the method, complex association between historical failure modes and features is mastered through the training time sequence prediction network, potential health score changes and failure time in the future are effectively predicted, and early warning is achieved.

The embodiment of the invention discloses a memory device, an operation method and a memory system. The memory device includes: a bias generation circuit configured to: generate a target bias signal according to a data transmission rate of the memory device; the target bias signal changes along with the change of a preset data transmission rate range; and the clock buffer circuit is coupled with the bias generation circuit and is configured to perform conversion processing on an input clock signal matched with the data transmission rate based on the target bias signal to obtain a target clock signal used by the memory device.

The invention relates to a radio frequency transceiving multichannel amplitude-phase calibration system, which comprises a radio frequency receiver, a radio frequency transmitter, a data converter, an FPGA (Field Programmable Gate Array) processor and a clock network, wherein the radio frequency receiver adopts a zero intermediate frequency architecture and is used for receiving a multichannel radio frequency signal and down-converting the multichannel radio frequency signal into an analog baseband signal; the radio frequency transmitter adopts a zero intermediate frequency architecture and is used for up-converting the analog baseband signal into a radio frequency signal and transmitting the radio frequency signal; the data converter is connected with the radio frequency receiver and the radio frequency transmitter and is used for realizing conversion between an analog signal and a digital signal; the FPGA processor is connected with the data converter through a JESD204B interface and is used for aligning the data of each receiving and transmitting channel; and the clock network consists of a clock chip with JESD204B characteristics and a clock Buffer, and is used for providing a synchronous clock and an SYSREF signal for the whole system and supporting an SYNC synchronous trigger signal. By adopting the method, the problem of multi-channel amplitude-phase consistency can be solved.

The embodiment of the utility model provides a mainboard, a daughter card and electronic equipment. The first mainboard comprises a selection switch, a phase-locked loop and at least one first clock buffer, the output end of the selection switch is connected with the input end of the phase-locked loop, and the selection switch is used for gating one of the input ends of the selection switch and the output end of the selection switch; a plurality of input ends of the selection switch are respectively used for inputting a first clock source signal and a second clock source signal, the first clock source signal is generated by a clock source of the first mainboard, and the second clock source signal is generated by a clock source of the daughter card; the output end of the phase-locked loop is connected with the input end of the first clock buffer, and the phase-locked loop is used for outputting a first output clock signal to the first clock buffer; the first clock buffers are used for buffering first output clock signals and outputting second output clock signals to the daughter cards, and one first clock buffer corresponds to one daughter card.

A phase-locked loop or delay locked loop provides a coarse alignment between an input clock and an output clock. A latch receiver circuit provides an indicator of a delay error between the input clock and the output clock. The delay error is used by a control circuit or state machine to adjust a fine delay that affects the output clock signal timing relative to the input clock signal. The fine delay is adjusted to minimize the timing difference between the output clock signal and the input clock signal.

The invention provides an extensible server architecture system suitable for various processors, which comprises a main board carrying a processor; the backboard is integrated with a multi-protocol interface control chip, a programmable clock buffer, a plurality of impedance adjusting circuits, a plurality of expansion slots and a plurality of groups of differential high-speed signal channels, the backboard is connected with the mainboard and the expansion slots through internal wiring, and the expansion slots are used for connecting pluggable expansion modules; the plurality of switching chips are arranged on a connecting path of the back plate and the mainboard and are used for topological connection of the processor and the expansion slot; the switching chip supports automatic negotiation of a PCIe / CXL protocol; according to the invention, the bus protocol difference between the processor and the pluggable expansion module is automatically adapted through the multi-protocol interface control chip and the switching chip, so that the universality of the system is improved; through the impedance adjusting circuit and the programmable clock buffer, the difference of different pluggable expansion modules in electrical characteristics and time sequences is solved, and the compatibility stability of different devices is guaranteed.

The invention discloses a multichannel clock buffer test system and method, and relates to the technical field of semiconductor testing, and the method comprises the steps: calibrating the delay of an optical clock signal of each time-to-digital converter node to a preset precision threshold value; a standard clock signal is injected into the clock buffer input channel, and the clock buffer is driven to enter a working state; triggering a time-to-digital converter array by using the calibrated optical clock signal, collecting timestamp data of each output channel of a clock buffer, and generating an original time data set; inputting the original time data set into a double-mixing processor, and outputting a multi-channel skew parameter and a three-dimensional cloud picture; the multi-channel skew parameter is converted to a life indicator value for each output channel of the clock buffer based on the multi-channel skew parameter invoking a material model. According to the invention, the original time data set is subjected to two times of frequency mixing processing through the double frequency mixing processors, and phase detection and spectrum analysis are combined, so that high-precision extraction of the time deviation value of each output channel of the clock buffer is realized.

A clock tree 900 comprises a first clock buffer 906 electrically connected to a second clock buffer 910. The first clock buffer comprises a first transistor 972, a second transistor 974, a first resis

Disclosed are techniques for reducing voltage drooping in a microelectronic chip, including separating a scan data launch clock from a capture clock with a variable time delay depending on a delay of a succeeding scan path of the latches, where the scan data launch clock and the capture clock are based on a base clock signal. The techniques further include analyzing and categorizing the latches against the time delay into dedicated buffer group categories. The techniques further include assigning the at least two local clock buffers to the latches within the dedicated buffer group categories.

The application belongs to the technical field of automatic test program, and particularly relates to a LabVIEW test method of a multi-channel programmable output clock buffer. The method comprises the following steps: initializing the clock buffer after power-on; resetting the FSWP spectrum analyzer and clearing the previous interface settings; switching the radio frequency switch to channel 1 and opening the channel 1 output; setting the signal source input frequency; setting the signal source input amplitude; starting the signal source input, and outputting the set frequency and amplitude to the input end of the clock buffer; starting the register configuration module, and transmitting the 174 24-bit register values to the SPI in sequence through the serial port, and then transmitting the SPI to the clock buffer; reading the data on the FSWP spectrum analyzer; and the method automatically measures the key indicators of the 14-channel clock buffer, saves the data and judges the advantages and disadvantages. The method reduces the burden of the test personnel, reduces the test time cost, and avoids causing data errors.

A clock architecture, including one or more clock module layers; each clock module layer including one or more clock modules, each clock module including a local clock generator, a selection switch circuit and a plurality of clock buffer circuits; wherein the local clock generator is configured to generate an independent local clock signal; a first input terminal of the selection switch circuit receives the local clock signal, a second input terminal of the selection switch circuit receives an external clock signal, a plurality of output terminals of the selection switch circuit are respectively connected to input terminals of the plurality of clock buffer circuits, and an enable terminal of the selection switch circuit is configured to receive an enable signal; and the selection switch circuit is configured to enable, all the output terminals to output the local clock signal or enable all the output terminals to output the external clock signal, according to the enable signal.

An inverter circuit, usable in a clock buffer circuit, includes a main inverter stage having a first transistor of a first conductivity type coupled in series with a second transistor of a second conductivity type, wherein control electrodes of the first and second transistors are coupled to an input node and first current electrodes of the first and second transistors are coupled at an output node. The inverter circuit also includes a first set of additional transistors of the first conductivity type, a second set of additional transistors of the second conductivity type, and a set of switches configured to connect a first transistor of the first set of additional transistors in series with the first transistor for a first time period while connecting a first transistor of the second set of additional transistors in parallel with the second transistor during the first time period.

Provided is a memory device including a chip select (CS) buffer that is configured to output a first internal chip selection signal, a command clock (CK) buffer that is configured to output an internal clock signal, a command / address (CA) buffer that that is configured to output a first internal command / address signal, a CA buffer controller configured to control on / off of the CA buffer based on the first internal chip selection signal, synchronize the first internal chip selection signal and the first internal command / address signal to the internal clock signal, and delay the phase of a second internal chip selection signal synchronized to the internal clock signal, and a command decoder configured to decode any one of the second internal chip selection signal, a phase-delayed third internal chip selection signal, and / or a second internal command / address signal synchronized with the internal clock signal.

The application discloses a kind of high-precision time interval measuring instrument based on GNSS and TDC-GPX2, including thermostatic crystal oscillator, level conversion module, clock buffer module, GNSS receiver module, time interval measurement module, main control module and digital-analog conversion module.The application combines the technology of taming thermostatic crystal oscillator, uses the 1PPS signal of GNSS receiver output to tame thermostatic crystal oscillator, designs the outlier algorithm module based on Allan variance to improve stability in taming process, according to the Kalman filter state equation of thermostatic crystal oscillator output frequency established, reasonable filter parameters can be obtained, so that Kalman filter algorithm module can effectively reduce the measurement error caused by 1PPS signal jitter, thermostatic crystal oscillator can output high-precision clock signal under long-term taming, and the high-precision frequency signal output by thermostatic crystal oscillator is used as reference clock signal by time interval measurement module, so as to improve measurement accuracy.The time interval measuring instrument of the application has the characteristics of simplicity, low cost and high precision.

Embodiments of this disclosure provide an apparatus and method for generating a circuit clock signal. The apparatus includes: a clock buffer configured to buffer an original clock signal to obtain a buffered clock signal; a clock delay unit configured to delay the original clock signal to obtain a plurality of delayed clock signals, the plurality of delayed clock signals being delayed by different amounts of time relative to the original clock signal; a broadened clock generator configured to generate a broadened clock signal based on the original clock signal and the plurality of delayed clock signals, the frequency of the broadened clock signal being lower than the frequency of the original clock signal; and a clock selector configured to select one of the buffered clock signal and the broadened clock signal as the circuit clock signal based on the selection signal.

Examples of the present application disclose a memory device, an operation method, and a memory system. The memory device includes: a bias generation circuit configured to generate a target bias signal according to a data transfer rate of the memory device, wherein the target bias signal varies with a preset data transfer rate range; and a clock buffer circuit coupled with the bias generation circuit and configured to perform, based on the target bias signal, conversion processing on an input clock signal matched with the data transfer rate to obtain a target clock signal used by the memory device.

The invention discloses a clock buffer and a clock module, and relates to the technical field of clock circuits. The clock buffer comprises a first capacitor, a first transistor, a second transistor, a current mirror and a hysteresis comparator, dC of externally input clock signals is removed through DC blocking of a first capacitor, the clock signals are biased to DC voltage provided by a first branch of the current mirror through a first transistor, and the clock signals are biased to DC voltage provided by a second branch of the current mirror through a reference voltage follower circuit formed by a second transistor and the second branch of the current mirror. The DC bias voltage in the composite signal input to the hysteresis comparator is maintained to be equal to the reference voltage under different operation conditions, and the clock buffer can ensure that the duty ratio of the output signal of the hysteresis comparator is kept to be 50%.

This utility model discloses a signal hub board and a grid screen control system for a mesh screen. The signal hub board includes an input interface, multiple output interfaces, and a signal distribution circuit. The input interface receives a drive signal from a receiving card, which includes a master clock signal and multiple parallel data signals. The signal distribution circuit includes a clock buffer module and a data buffer module. The clock buffer module receives the master clock signal and, through buffering and copying, generates multiple output clock signals that are the same number as the number of output interfaces and synchronized with the phase. The data buffer module buffers the multiple parallel data signals one-to-one to generate multiple output data signals. Each output clock signal is paired with its corresponding output data signal and sent to a single mesh screen module through the corresponding output interface. The signal hub board and control system of this application improve signal quality by centrally synchronizing and shaping the drive signals, thereby ensuring that the mesh screen can achieve smooth, clear, and high-quality video playback.

A source driver chip and a display device are disclosed. The source driver chip includes an OR logic arithmetic unit, a clock buffer, a shift register, and an AND logic arithmetic unit. An OR logic operation is performed on a line latch signal and a first output data delay control enabling signal to obtain a second output data delay control enabling signal, and an AND logic operation is performed on an initial line latch sub-signals and the second output data delay control enabling signal, such that electrostatic interference of the line latch signal can be reduced.

The utility model discloses E1 interface equipment for connecting PCM (Pulse Code Modulation) equipment and signaling conversion equipment, which belongs to the technical field of telecommunication and comprises an E1 interface A, an E1 interface B, an E1 interface C, an E1 interface D, an E1 transceiver A, an E1 transceiver B, an E1 transceiver C, an E1 transceiver D, an FPGA (Field Programmable Gate Array) controller A, an FPGA controller B, a DPS chip A, a DPS chip B, a clock synchronization circuit, a 232 communication module, a communication interface, a power supply circuit and a 12V power supply interface. By adopting the FPGA / DSP cooperative low-jitter clock buffer and isolation protection circuit, precise clock synchronization of multiple paths of E1 signals is realized, the technical problems of clock drifting and hardware processing capability bottleneck in a traditional system are effectively solved, task separation and efficient cooperation can be realized, a consistent and low-jitter reference clock is provided, and the reliability of the system is improved. The method has obvious advantages in clock synchronization, data processing and module division.

This utility model discloses a computer processing module and a computer, relating to the field of computer technology. It includes an onboard CPU, a first PCIe x8 interface and an information interface connected to a bridge chip, a power interface of the bridge chip connected to a power module, and the bridge chip further configured to connect a second memory chip, a second Flash chip, and a first crystal oscillator; the bridge chip; the onboard CPU further configured to connect the first memory chip, the first Flash chip, and an RTC clock chip; an FMC connector, the FMC connector including multiple first expansion interface groups connected to the onboard CPU, and multiple second expansion interface groups and functional interface groups connected to the bridge chip; and a second crystal oscillator, the second crystal oscillator providing clock to the onboard CPU, the bridge chip, and the FMC connector through a clock buffer. This achieves miniaturization and interface expansion.

The application relates to a clock calibration device, a method and a tire pressure monitoring system. The clock calibration device is applied to a tire pressure sensing device. A temperature reading module reads the working temperature of the tire pressure sensing device when the tire pressure sensing device is in a wake-up reset state. Then, a query module queries clock buffer data corresponding to the working temperature. A correction determination module determines whether the clock buffer data is consistent with initial data and generates a determination result. A correction module obtains clock correction data according to the determination result. Finally, a clock calibration module modulates the clock signal of the tire pressure sensing device according to the clock correction data, so that the frequency of the modulated clock signal reaches a target frequency. In this way, the working period offset of the tire pressure sensing device caused by temperature change can be dynamically corrected during the working process, thereby prolonging the service life of the tire pressure sensing device and finally improving the reliability of the monitoring system.

The application provides a high-speed serial communication interface, a chip and a clock distribution method. The high-speed serial communication interface comprises an internal-external interconnection module, at least one internal reference clock buffer module and an external reference clock buffer module. The external reference clock buffer module is connected with the internal-external interconnection module, and the internal-external interconnection module is connected with the at least one internal reference clock buffer module. The external reference clock buffer module is used for receiving a clock signal of an external clock source and outputting the clock signal to the internal-external interconnection module. The at least one internal reference clock buffer module is used for receiving a clock signal from other high-speed serial communication interfaces and outputting the clock signal to the internal-external interconnection module, or outputting a clock signal received from the internal-external interconnection module to other high-speed serial communication interfaces. The internal-external interconnection module is used for taking the clock signal received from the external reference clock buffer module or the clock signal received from the at least one internal reference clock buffer module as a reference clock of the high-speed serial communication interface.

An inverter circuit, usable in a clock buffer circuit, includes a main inverter stage having a first transistor of a first conductivity type coupled in series with a second transistor of a second conductivity type, wherein control electrodes of the first and second transistors are coupled to an input node and first current electrodes of the first and second transistors are coupled at an output node. The inverter circuit also includes a first set of additional transistors of the first conductivity type, a second set of additional transistors of the second conductivity type, and a set of switches configured to connect a first transistor of the first set of additional transistors in series with the first transistor for a first time period while connecting a first transistor of the second set of additional transistors in parallel with the second transistor during the first time period.

Semiconductor device (100B) comprising: a cell region (102B) containing active regions extending in a first direction and comprising transistor components formed therein; wherein the transistors of the cell region (102B) are arranged to function as a D flip-flop (234, 434), DFF, comprising a primary latch (236, 336), a secondary latch (238, 338), and a clock buffer (246, 346); the primary latch (236, 336) comprising a first sleepy inverter (250, 350) and a first non-sleepy inverter (248, 348), NS inverter; the secondary latch (238, 338) comprising a second sleepy inverter (250, 350) and a second NS inverter (248, 348) includes; and the clock buffer (246, 346) includes the third and fourth NS inverters (248, 348); a first group of some, but not all, of the transistor elements has elements configured with a standard threshold voltage, these being referred to as Vt_std elements;a second group of some, but not all, of the transistor elements that have a low threshold voltage configured lower than the standard threshold voltage, these being referred to as Vt_low elements; and those of the transistors that comprise the third NS inverter (248, 348) and / or the fourth NS inverter (248, 348) are Vt_low elements of the second group, wherein: a third group of some, but not all, of the transistor elements that have a high threshold voltage configured higher than the standard threshold voltage, these being referred to as Vt_high elements; and those of the transistors that comprise the first sleepy inverter (250, 350) of the primary latch (236, 336) and the second sleepy inverter (250, 350) of the secondary latch (238, 338) are Vt_high elements of the third group.

The application provides a relay adjusting circuit of an endoscope and the endoscope. The relay adjusting circuit is provided with an input interface, a clock buffer, an input impedance adjusting module, an output matching adjusting module and an output interface. The input end of the clock buffer is electrically connected with the input interface. The input impedance adjusting module is connected with the input end and the grounding end of the clock buffer in parallel. The output matching adjusting module is electrically connected with the output end of the clock buffer. The output interface is electrically connected with the output matching adjusting module. The clock buffer is used for receiving a first clock driving signal adjusted by the input impedance adjusting module, enhancing the driving capacity of the adjusted first clock driving signal, obtaining a second clock driving signal and outputting the second clock driving signal. The output matching adjusting module is used for adjusting the signal peak value of the second clock driving signal, outputting a third clock driving signal with identifiable high and low level properties, and then compensating the signal attenuation formed by long-distance transmission and improving the accuracy of image acquisition.