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430results about How to "Accurate recovery" patented technology

Apparatus and method for optimized self-synchronizing serializer/deserializer/framer

InactiveUS6459393B1Negatively impact design timeNegatively integrated circuit clock loadingParallel/series conversionViruses/bacteriophagesSerial transferTelecommunications link
An apparatus and method for improving the communication capabilities of computer systems is disclosed. The most preferred embodiments of the present invention use a series of data buffers and data registers to process an incoming high speed data signal. By using the buffers and registers, the incoming signal can be reformatted and manipulated at a much lower frequency than the original transmission frequency. The deserializer of the present invention also samples a greater portion of the incoming data signal than usual to further increase reliability. These various features of the invention provide for a more stable and reliable communication link and will also provide a less expensive solution for serialization/deserialization. The present invention includes a serializer that receives parallel data input from a computer and serializes the data for transmission over a high-speed serial communication link. On the receiving end, the present invention provides a deserializer that can quickly and efficiently transform the serial data back into parallel form for use within the computer system on the receiving end. By utilizing two related clock signals, one clock signal being an integer multiple of the other, a self-synchronizing serializer/deserializer can be created. In addition, by increasing the size of the data sample on the receiving end, the comparisons necessary to retrieve a parallel signal from a serial transmission can occur at a much lower frequency than the frequency of the serial transmission. In the most preferred embodiment, the invention is provided as a integrated solution manufactured on a Peripheral Component Interconnect (PCI) card, thereby allowing the present invention to be easy installed into existing computer systems.
Owner:MEDIATEK INC

Satellite communication timing synchronization error detection method based on full-digital receiving

Disclosed is a satellite communication timing synchronization error detection method based on full-digital receiving. In view of wide application of a Gardner algorithm in a timing synchronization loop and the limitation of the Gardner algorithm to band-limited signals, when polarity jump happens to two adjacent symbols, after two adjacent code elements are utilized for cosine roll-off forming filtering, the relation between samples of two best sampling points and the sample of a middle point of the two best sampling points is utilized, the effect of different adjacent symbols to the middle value is firstly taken into consideration and the effect value is calculated according to the minimum mean-square error criterion, and is then eliminated; when polarity jump does not happen to the adjacent symbols, how to reduce self noise generated by the situation that timing information can not be acquired is taken into consideration. A sign function sign (.) in an E-Gardner algorithm is utilized to solve the problem. Under the satellite channel environment, the enhancing algorithm is simple in structure, under the condition of a small roll-off coefficient, the performance of QPSK modulating signal clock capturing and error detection is improved, and the satellite communication timing synchronization error detection method based on full-digital receiving can effectively eliminate self-noise and reduce system resource consumption.
Owner:CHONGQING UNIV OF POSTS & TELECOMM

Selective scrambler for use in a communication system and method to minimize bit error at the receiver

A communication system for transmitting and receiving a sequence of bits, and the methodology for transferring that sequence of bits are provided. The communication system includes a transmitting circuit and a receiving circuit. Within the transmitting circuit is a scrambler that comprises a shift register, an enable circuit, and an output circuit. The shift register temporarily stores n bits within the sequence of bits, and the enable circuit enables the shift register to store bits that arise only within the payload section of a frame. The output circuit includes a feedback, and several taps within the n stages to scramble logic values within the sequence of n bits output from the shift registers thus effectively preventing in most instances the sequence of bits from exceeding n number of the same logic value. Within the receiving circuit is a descrambler also having a shift register, an enable circuit, and an output circuit. The descrambler recompiles the scrambled data back to its original form. The scrambler is preferably placed before an encoder in the transmission path to minimize data dependent, low frequency jitter. The encoder is used to place a coding violation into the frame to signal the beginning of each frame, and to encode the parity with an offset against any DC accumulation of the coding violation and the scrambled payload to eliminate all DC accumulation (baseline wander) within each frame.
Owner:MICROCHIP TECH INC

Washing machine, power failure memory control method thereof and power failure memory control device of washing machine

The invention provides a washing machine, a power failure memory control method thereof and a power failure memory control device of the washing machine. The power failure memory control method comprises the following steps of (S1) acquiring step marks corresponding to current running steps of the washing machine and preset parameters by using a controller; (S2) writing the step marks and the preset parameters into a preset storage unit by using the controller; (S3) acquiring the step marks and the preset parameters in the preset storage unit by using the controller after the washing machine is restarted; and (S4) acquiring running steps corresponding to the step marks according to the step marks and starting the washing machine according to the running steps and the preset parameters. By a step-by-step memorizing method, relevant information of the current running steps of the washing machine is stored in real time, the working state of the washing machine can be accurately recovered to a working state before power failure when the washing machine is restarted, and a power failure memory function is fulfilled; and circuits are simple in structure, the cost of the circuits is reduced, and the power failure memory control method is easy to implement.
Owner:WUXI LITTLE SWAN ELECTRIC CO LTD

Wavelength calibration method of optical spectrum instruments

A wavelength calibration method of spectral instrumentation mainly relating to wave length calibration method adopting spectral instrumentation of array detector pertains to the filed of wave length calibration technology of spectral instrumentation. The spectral instrumentation of the method adopts array detectors and lighting source of linear spectra, spatial locations of every spectrum peak of the lighting source are acquired from the spectrogram output from the instrumentation, and the 'spatial location - wave-length relationship' on the power spectrum is fitted by according these spectrum peak wavelength and the corresponding spatial locations thereof, thus corresponding wavelength of every pixel of the detector is confirmed, the spatial locations of every spectrum peak of the lighting source is acquired through processes as following: sub-pixel detecting; sub-pixel reestablishing; spectrum peak spatial locations acquiring. The sub-pixel detecting of the invention increases sampling ratio of spectrogram, spectrogram with improved resolution in acquired; the comprehensive applications of sub-pixel detecting, sub-pixel reestablishing and spectrum contour fitting further increases the wavelength accuracy of spectral instrumentation with array detectors step by step. The invention has prominent effect.
Owner:TSINGHUA UNIV
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