284 results about "Source-synchronous" patented technology

In a network system, clock signals of a server device and a client device are synchronized with each other without having any influence of a change and a delay of the transmission time of data. Therefore, in the network system in which the client device receives and reproduces information transmitted from the server device, the server device counts the number of clock pulses of a server clock signal used to compress and encode information on the basis of a power source synchronous pulse signal synchronized with a power source frequency. The server device outputs information showing the counted clock pulse number and the compressed and encoded information to the client device. The client device counts the number of clock pulses of a client clock signal used to decode and decompress the compressed and encoded information on the basis of the power source synchronous pulse signal synchronized with the power source frequency. The client device conforms the frequency of the client clock signal to the frequency of the server clock signal on the basis of the clock difference between the clock pulse number received from the server device and the counted clock pulse number.

A memory system having a memory element chip (DRAM) and a memory controller chips having a plurality of drivers and receivers and latches for transferred data. For writes clocks, write data and write for CRC (cyclic redundancy checks) is transferred to the DRAM from the memory controller and latched for error checking. The reads are clocked and the read data is received and transferred to a read data latch with also receives a clocked read strobe for verification of data integrity from DRAM. Each chip has a bi-functional pin that acts as a shared CRC pin during write and acts as a shared strobe pin during READ. Data transfers with the CRC signal and DQS signal are transferred across two paths CRC0 / DQS and CRC1 / DQS1. One could also transfer the CRC signal across one path with only the CRC0 / DQS signal. Read operations have no CRC, and have no need for CRC because transfer errors during read can be detected by memory error correction coding (ECC). Write data provides source synchronous I / O data to said memory element chip needed for modem high speed memory communications.

In an embodiment, a memory device comprises a clock generating unit being configured to generate a read clock signal, the clock generating unit being connected to a first clock signal contact configured to send the read clock signal, and the clock generating unit being connected to data signal contacts being configured to send data signals, the memory device being configured to send the data signals in a phase and frequency accurate (source synchronous) manner with regard to the read clock signal.