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FPGA-based SFI4.1 device

A technology of SFI4.1 and ASIC chips, which is applied in the field of OTN, can solve the problems affecting the correct reception and transmission of data, and the difficulty of implementing 10G signal interface, so as to achieve the effect of enhancing flexibility

Active Publication Date: 2011-01-19
FENGHUO COMM SCI & TECH CO LTD
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  • Abstract
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Problems solved by technology

The 10G signal interface transmitted by SFI4.1 needs to realize the reception and transmission of 16 channels of parallel high-speed source synchronous data. Due to the differences in the wiring delays of each channel of data and clocks inside the FPGA, it affects the correct reception and transmission of data, making the use of SFI4 .1 There are difficulties in implementing the 10G signal interface for transmission on FPGA

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Embodiment Construction

[0034] The present invention will be described in further detail below in conjunction with the accompanying drawings.

[0035]The present invention is applied in the OTN system equipment, and part of the line cards in the OTN system equipment internally process the ODU2 signal transmitted by the SFI4.1 interface. The present invention realizes the SF4.1 interface in the FPGA and completes the transmission by the SFI4.1 interface. The ODU2 signal is correctly received in the FPGA and sent after processing. The SFI4.1 interface uses 16 pairs of differential data lines and a pair of differential clocks to simultaneously transmit data signals, which is a high-speed source synchronous interface. The single-channel data rate of the SFI4.1 interface in the actual OTN system equipment is 627.33Mb / s. At the receiving end, the input high-speed parallel source synchronous signal satisfies the SFI4.1 interface clock-data relationship proposed by OIF. Since the internal clock signal and d...

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Abstract

The invention relates to an FPGA-based SFI4.1 device, an FPGA is used in the device for realizing an SFI4.1 interface, the device is respectively connected with an FPGA device and an ASIC chip in an OTN system through the SFI4.1 interface, the ASIC chip and the FPGA device share a reference clock REFCLK, a transmitter clock in the data transmission direction further directly adopts the reference clock REFCLK, and a receiver clock in the receiving direction directly adopts a channel-associated clock for processing. The device can realize correct receiving and sending of high-speed source synchronous data in the FPGA device, realize resources adopting the FPGA device of the parallel interface (SFI4.1) between a serial-parallel converter and a framer disclosed by an OIF, facilitate the processing of signals of a 10G source synchronous parallel bus transmitted by adopting the SFI4.1 in the FPGA device, enhance the flexibility of processing ODU2 signals of the system in the practical use, further meet the actual requirements of the device and simultaneously provide technological accumulation for designing source synchronous interfaces in the future.

Description

technical field [0001] The invention relates to the technical field of OTN (Optical Transport Network), in particular to an FPGA (Field Programmable Gate Array)-based SFI4.1 (parallel interface between a serial-to-parallel converter and a framer) device. In particular, it refers to a device that adopts the SFI4.1 standard proposed by OIF (Optical Internet Forum) to realize 10G signal reception and transmission inside FPGA. Background technique [0002] SFI4.1 proposed by the Optical Internet Forum (OIF) is mainly used in SONET (Synchronous Optical Communication Network), SDH (Synchronous Digital Hierarchy), OTN (Optical Transport Network) and other systems to realize STS-192 (Synchronous Transmission Signal), Connection between STM-64 (Synchronous Transfer Mode), OTU2 (Optical Channel Transport Unit), ODU2 (Optical Channel Data Unit) and other signals. What is transmitted in SONET / SDH is 9953.28Mb / s STS-192 and STM-64 signals, which are transmitted through 16 pairs of 622.0...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L7/04H04B10/12H04B10/25
Inventor 钟永波陈飞月
Owner FENGHUO COMM SCI & TECH CO LTD
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