4814 results about "Clock signal" patented technology

The invention discloses a clock optimization method, device and equipment and a computer readable storage medium, which are applied to the field of integrated circuits, and comprise the following steps: reading a netlist of each fragment, and traversing each netlist to generate an instance tree corresponding to each fragment; performing reverse tracing and forward tracing on each clock signal based on each instance tree to obtain a clock network path corresponding to each clock signal; determining a redundant clock according to each clock network path, and performing corresponding processing on the redundant clock; the redundant clock comprises an isolated redundant clock and an equivalent redundant clock. According to the method, the instance tree is generated by traversing the netlist, and the complete clock network path is obtained by combining reverse tracing and forward tracing, so that isolated redundant clocks and equivalent redundant clocks can be comprehensively captured, and automatic tracking of the clock network path and accurate identification of the redundant clocks are realized; the redundant clock is correspondingly processed, so that unnecessary clock generation logic and wiring resource occupation can be reduced, the chip power consumption and the area overhead are reduced, and the resource utilization rate is improved.

The invention provides a signal decoding method based on a PSI5 interface, and relates to the technical field of signal decoding, and the decoding method comprises the following steps: processing and adjusting a received PSI5 signal to obtain an accurate identification signal; and extracting a clock signal from the PSI5 signal, designing a clock compensation algorithm according to the quantum neural network, and dynamically adjusting the clock signal to obtain clock synchronization data. And determining a data frame boundary, and decoding the accurate identification signal to obtain original data. And performing comparative analysis on the original data and the PSI5 signal to obtain comparative difference data, judging whether the comparative difference data accords with a preset error type or not, and performing corresponding processing. According to the invention, fractional calculus processing is carried out on the received signal, then signal distortion is corrected by using a channel equalization method, and the quantum neural network is constructed to dynamically adjust the clock signal, so that clock synchronization is realized, a reliable time reference is provided for accurate processing of the signal, and the accuracy of signal decoding is improved.

The invention provides an ultrasonic fingerprint chip and an integral clock generation method and device of the ultrasonic fingerprint chip. Appropriate fingerprint pixel units can be selected from a plurality of fingerprint pixel units to serve as first-class pixel units and second-class pixel units, and the first-class pixel units and the second-class pixel units are respectively connected with a first-class detection circuit and a second-class detection circuit. Wherein a first integrator in the first type of detection circuit is sequentially connected with a first comparator, a time delay regulator, a clock dominant frequency duplicator and a frequency dividing circuit; the frequency dividing circuit is connected with the second type detection circuit; a second integrator in the second type detection circuit is connected with an amplification structure; the amplification structure is also connected with a second comparator; and the second comparator is connected with the time delay regulator in the first-class detection circuit. The circuit can automatically generate and obtain the integral clock signal which is matched with the ultrasonic fingerprint echo signal and is high in precision and good in effect, so that the received ultrasonic fingerprint echo signal is precisely processed, and a target signal with high quality is obtained.

The invention relates to a self-diagnosis method for a state terminal of a substation measurement system, which comprises the following steps of: comparing signal values at different sampling nodes of signals from the same physical source in each measurement channel through the state terminal, and judging that the channels have physical chain degradation or poor contact; performing perturbation modulation on a measurement sampling process based on a clock signal controlled by a crystal oscillator in the state terminal, and if response deviation abnormity is detected, judging that a sampling time base has drift, time sequence disorder or cache backlog so as to identify a time base health state of a sampling chain in the terminal; in the operation process of the transformer substation, response differences generated by the excitation in different measurement channels are collected, and if response delay, amplitude distortion or jitter starting point deviation is found, it is judged that the anti-interference capacity of the corresponding channel is degraded; and according to the electric energy change rhythm sensed by the terminal in real time, adaptively adjusting the sensitivity threshold value of the jump response, and if frequent misjudgment or slow response of the jump response is detected, marking that the behavior sensitivity of the terminal sampling system is abnormal.

The invention relates to the field of intelligent power grids, and discloses a fault classification and traceability method based on an electric energy meter event log, which comprises the following steps: performing millisecond-level dynamic acquisition on power failure, recovery and abnormal voltage data of a user electric meter and an adjacent electric meter, and performing second-level time alignment based on a transformer area reference clock signal; executing multi-table cross-time sequence correlation analysis on the event priority sequence, and constructing a power grid event multi-dimensional feature tensor; for the multi-dimensional feature tensor of the power grid event, carrying out abnormal aggregation on local modes in the tensor by adopting a hierarchical causal reasoning model; on the basis of the candidate fault propagation path, a time sequence dependence attention mechanism is introduced, and contribution degrees of different electric meter events to potential faults are dynamically evaluated; dividing electric meter nodes and affected branches corresponding to the candidate power failure reason set into fault sensitive areas, and outputting a traceability result; the method has the advantages of judging the power failure reason in real time and automatically generating the solution.

The invention provides a multi-source clock synchronization method and device based on a long short-term memory network, and the method comprises the steps: collecting multi-source clock signals outputted by a plurality of clock sources, and carrying out the timestamp alignment of the multi-source clock signals; the multi-source clock signals subjected to timestamp alignment are preprocessed; performing feature extraction based on the preprocessed multi-source clock signal to obtain a multi-source clock feature; inputting the multi-source clock characteristics into a double-layer LSTM network obtained by pre-training, and outputting a predicted time deviation result; and performing judgment based on the predicted time deviation result, and performing time compensation on a local clock according to a judgment result. The method can effectively improve the synchronization precision, is more suitable for non-stationary error characteristics in a complex electromagnetic environment, and improves the reliability of clock synchronization.

The invention provides a UCIe-based data transmission method, a storage medium and an artificial intelligence chip. The data transmission method comprises the following steps: communicating with a second core particle through a first core particle; receiving a bypass receive data signal and a bypass receive clock signal from the transmit module of the first core particle through the receive module of the second core particle; the serial-to-parallel conversion module is used for transmitting the bypass receiving data signal and the bypass receiving clock signal to the second core particle through the receiving module; counting the bypass receiving clock signal through a serial-to-parallel conversion module to obtain a bypass receiving frame count value, and sampling a bypass receiving data signal according to the bypass receiving frame count value; a serial-to-parallel conversion module decides to count a bypass burr removal count value according to a bypass burr removal counter starting signal; and when the bypass glitch removal count value is equal to the bypass glitch removal counter threshold value, resetting the bypass receiving frame count value through the serial-to-parallel conversion module. According to the invention, good data transmission quality among the core particles can be realized.

A control unit for operating a power converter in a buck-boost mode is provided. The control unit is configured to, within a switching cycle, operate the power converter in an IN state starting from the beginning of the switching cycle until a timer signal of a timer occurs. The control unit is further configured to subsequently operate the power converter in a THROUGH state stating from the timer signal until a peak current event occurs. The control unit is further configured to subsequently operate the power converter in an OUT state starting from the peak current event until a clock signal occurs, which indicates an end of the switching cycle.

The invention provides a display device which is characterized in that two cascaded gate drive circuits are spaced by X gate drive circuits, and the phase difference of first clock signals corresponding to the two cascaded gate drive circuits is (X + 1) H, the effective level of a first gate control signal corresponding to the compensation transistor and the effective level of a second gate control signal corresponding to the data transistor are at least partially overlapped; the effective level of a second gate control signal corresponding to the data transistor is located between two first effective levels of a first clock signal applied by a gate drive circuit corresponding to the compensation transistor, and the phase difference between the effective level of the second gate control signal corresponding to the data transistor and one of the two first effective levels is larger than 0 and smaller than (X + 1) H, therefore, in the same sub-pixel, the effective level of the second gate control signal corresponding to the data transistor does not coincide with the moment when the voltage drop of the first gate control signal corresponding to the compensation transistor occurs, and the problem of uneven display is solved.

The invention discloses a power frequency phase adaptive acquisition device, and relates to the technical field of electric power signal measurement, the device acquires electric field data at a gap through an electric field sensor integrated on an edge shell, calculates electric field intensity fluctuation, and generates interference diagnosis information in combination with a preset interference determination threshold value; when the interference diagnosis information shows that effective interference exists, the electric field intensity variable quantity is calculated, a mapping model is established based on a proportionality coefficient obtained through an experiment so as to obtain zero crossing point offset, and the sampling trigger moment of a zero crossing point detection module is corrected; the clock synchronization module calculates a phase difference by taking the corrected trigger moment as a reference, dynamically adjusts a calibration frequency by combining a phase difference threshold value, and outputs a synchronized system clock signal; and the control system takes the synchronized system clock signal as a trigger signal, collects power frequency phase data according to a power frequency period, and stores the power frequency phase data to a database through a transmission unit, thereby realizing high-precision power frequency phase collection.

The embodiment of the invention provides a delay measurement circuit and a memory. The delay measurement circuit is applied to the delay phase-locked loop and comprises a loop mark generation circuit which is electrically connected with a loop of the delay phase-locked loop and is configured to generate a loop mark signal and input the loop mark signal to the loop of the delay phase-locked loop when loop delay measurement is carried out on the delay phase-locked loop; after the loop mark signal circulates M times in the loop of the delay phase-locked loop, a measurement ending signal is generated, a target pulse signal is generated, and the effective pulse width of the target pulse signal is equal to M times of the loop delay; wherein M is an even number greater than 1; the counting circuit is electrically connected with the loop mark generation circuit and is configured to receive a frequency division clock signal, and the effective pulse width of the target pulse signal is timed by using the frequency division clock signal to obtain a timing result; and carrying out preset processing on the timing result to obtain a loop delay measurement result of the delay-locked loop. The embodiment of the invention is at least beneficial to increasing the margin value of the delay measurement circuit and improving the accuracy of loop delay measurement.

The invention discloses a data sampling timing error evaluation method based on an evaluation model, relates to the technical field of timing error evaluation, and solves the problem that timing error evaluation is not accurate enough. Wherein the sampling module realizes undistorted receiving and clock signal frequency output of a clock signal through a CMOS clock input circuit, a third-order digital phase-locked loop circuit and a DSP digital signal processing chip, and a Fourier phase difference algorithm removes harmonic interference to solve a phase difference between the clock signal and an ideal clock signal; the clock signal feature recognition unit adopts a convolutional neural network to carry out iterative training on a training set of the timing error evaluation module to obtain an error evaluation module, the error evaluation module and the time migration algorithm module realize accurate calculation of a timing error value, and the timing error value calculation accuracy is greatly improved.

A DC / DC converter includes a converter stage to receive an input voltage and to provide an output voltage from the input voltage in accordance with a modulated drive signal. The converter stage further provides a feedback voltage representing the output voltage. A controller circuit includes an error amplifier to receive the feedback voltage and a reference voltage and to provide an error signal based on the feedback voltage and the reference voltage. A PWM modulator receives a clock signal and the error signal and generates a modulated signal based on the clock signal and the error signal, and a logic circuit receives the modulated signal and generates the drive signal for the converter stage based on the modulated signal so that the drive signal has the same duty cycle as the modulated signal, when the duty cycle of the modulated signal is not smaller than a minimum duty cycle value.

An apparatus that includes a shift register unit, a gate driving circuit, and a display apparatus. The shift register unit includes: an input circuit, a reset circuit, a node control circuit, a cascade output circuit and a drive output circuit, where the drive output circuit is configured to provide the signal of the clock signal end to a drive output end in response to the signals of the first node.

Disclosed is a test aid unit that is installed between automatic test equipment (ATE) and a device under test (DUT), generates a test data signal according to a data processing and transmission / reception rate of the DUT in response to a control signal transmitted from the ATE, transmits the test data signal to the DUT, self-tests a test result signal transmitted from the DUT, and transmits the test result to the ATE. The test aid unit includes a clock signal divider, an integrated digital logic unit, a transmitter, and a receiver.

This disclosure is generally directed to a full-duplex transceiver including a primary circuit and a secondary circuit communicating using a clock signal of the primary circuit (e.g., a single clock signal). The primary circuit may include circuitry to generate and / or forward the clock signal to the secondary circuit. The secondary circuit may sample received data using the clock signal. Moreover, the secondary circuit may generate data, perform data processing operations, and / or transmit data using the clock signal of the primary circuit.

A method is for measuring a time lapse between a trigger and a pulse of a clock of a time-to-digital converter (TDC) device. The method includes the steps of: a) providing a delay line signal to a delay line of a TDC device; b) subsequently, at a measurement clock pulse: obtaining a measurement delay line state representing states of the delay cells; c) subsequently and within half a clock period of the measurement clock pulse: basing the delay line signal on a clock signal and providing the delay line signal based on the clock signal to the delay line; d) subsequently, at a calibration clock pulse: obtaining a calibration delay line state representing states of the delay cells, and e) computing the time lapse between the trigger and the measurement clock pulse based on the measurement amount of delay cells and the calibration amount of delay cells.

The invention provides an ultrasonic fingerprint pixel array circuit and an ultrasonic fingerprint data processing method. Based on the ultrasonic fingerprint pixel array circuit, a corresponding fingerprint pixel unit can be determined in a first position area of the ultrasonic fingerprint pixel array circuit and transformed into a first detection unit capable of locally generating an integral clock signal; meanwhile, a corresponding fingerprint pixel unit determined in a second position area of the ultrasonic fingerprint pixel array circuit is transformed into a second detection unit which can be matched with the first detection unit to carry out self-adaptive feedback adjustment on the generated integral clock signal. Therefore, the improved ultrasonic fingerprint pixel array circuit capable of automatically generating the integral clock signal matched with the ultrasonic fingerprint echo signal can be constructed by fully utilizing the original circuit structure of the ultrasonic fingerprint pixel array circuit at relatively low cost. Therefore, the ultrasonic fingerprint pixel array circuit can be utilized to efficiently and locally generate an integral clock signal with a better effect to process an ultrasonic fingerprint echo signal.

The invention belongs to the technical field of hardware circuit board design, and discloses a PCIe Switch board downlink port compatible uplink port structure, which comprises a CPU (Central Processing Unit), a PCIe Switch chip, a PCIe port, PCIe equipment, a downlink port Root end and a Clock Buffer, the PCIe expansion system constructs a tree topology through a PCIe Switch chip, a single PCIe channel of a CPU is branched into a plurality of independent channels, and parallel access of multiple devices is achieved. The Switch chip comprises an uplink port and a plurality of downlink ports, and the uplink port is directly connected with the PCIe controller of the CPU through a special connector and bears a data signal and a key clock signal; clock signals are transmitted by adopting high-speed differential pairs. According to the PCIe Switch board, high-efficiency expansion is achieved through the design that a downlink port of the PCIe Switch board is compatible with an uplink port and multi-dimensional technological innovation, the core of the PCIe Switch board adopts a CPLD dynamic configuration technology, a BPTYPE level and a 2W-CLK mode are switched in real time through an onboard dial switch, the same physical port can be flexibly configured to be an I2C master equipment clock source or a data channel, and the switching delay is smaller than 50 ns.

The invention discloses a transmitter based on a high-speed low-power-consumption data serialization and driving circuit, and the transmitter comprises a low-speed serialization module which is used for serializing 32 paths of input parallel low-speed data into 4 paths under the control of a multi-phase clock signal; the FFE 4-tap generation module is used for performing delay operation on the four paths of data under the control of a clock signal to obtain four groups of tap data; and the high-speed 4: 1 MUX hybrid SST driving module is provided with 2N first slices, the N first slices comprise K slices of PRE taps, L slices of MAIN taps, J slices of POST1 taps and H slices of POST2 taps, and the driving module is used for generating full-rate differential data according to the four groups of tap data and switching signals provided externally and realizing impedance matching of an output end. According to the invention, the number of used triggers can be reduced, full-rate nodes in the circuit are eliminated, the power consumption is reduced, the complexity of simulating the FFE is relatively low, and different channel losses can be compensated.

The invention discloses a real-time wave number space resampling method and system for SS-OCT, and relates to the technical field of signal processing, and the method comprises the steps: synchronously collecting a K clock signal and an OCT interference signal, and carrying out the filtering preprocessing of the signals; carrying out Hilbert transformation on the preprocessed K clock signal, constructing an analysis signal, extracting an instantaneous phase, and forming an instantaneous phase sequence; using a preset ideal equal wave number interval phase sequence as a target phase sequence, matching the target phase sequence with the instantaneous phase sequence, calculating a corresponding position index of each target phase in the instantaneous phase sequence, and obtaining a remapping sampling point index; and processing the preprocessed OCT interference signal by using an SINC interpolation method according to the remapping sampling point index to obtain an OCT signal which is subjected to resampling and has equal wave number intervals. According to the invention, the SINC interpolation algorithm is utilized to complete resampling in real time and with high precision in the data acquisition stage, and the requirement of high-speed real-time imaging is met.

The invention provides a display device, a gate drive circuit of the display device comprises N levels of cascaded gate drive units, the ith level of gate drive unit comprises a first transistor, a first frequency division signal line, a second frequency division signal line and a frequency division control module, a gate of the first transistor is electrically connected to a second node, and a gate of the second transistor is electrically connected to a third node. The source electrode and the drain electrode are electrically connected to the first clock signal line and the gate driving signal output end respectively, and the frequency division control module is electrically connected with the first node, the second node, the first frequency division signal line and the second frequency division signal line. The first frequency division signal line and the second frequency division signal line are located between the first transistor and the frequency division control module. Through the layout mode, the metal overline distance is reduced, the layout space of the gate driving unit is saved, meanwhile, different areas of the display panel are refreshed by adopting different refresh frequencies, and the power consumption of the display device is reduced.

An illustrative retimer includes: an upstream interface having an upstream receiver configured to convert a downlink signal into a downlink symbol stream; a downstream interface having a downstream transmitter configured to provide a transmit signal representing the downlink symbol stream; core circuitry having a downstream path and a downstream bypass path; and a controller. The downstream path is configured to convey the downlink symbol stream from the upstream receiver to the downstream transmitter via a receive clock domain component, a core clock domain component, and a transmit clock domain component. The downstream bypass path is configurable to convey the downlink symbol stream from the upstream receiver to the downstream transmitter without any core clock domain components. The controller is configured to disable a clock signal for the transmit clock domain component of the downstream path when the downstream bypass path is enabled.

Generation of a clock signal in a semiconductor integrated circuit (IC) is controlled using a Noise Modulation Agent (NMA), configured to measure the clock signal and output a parameter indicative of an effective cycle time of the clock signal. An Adaptive Frequency Scaling (AFS) circuit selectively adjusts a frequency of the clock signal, based on the output of the NMA indicating a change in a power supply voltage of the semiconductor IC.

An emission driver is disclosed. The emission driver includes a Q node controller configured to control a voltage at a Q node by applying a start signal, a carry signal, or a high-potential driving voltage to the Q node responsive to a first clock signal, a QB node controller configured to control a voltage at a QB node by applying the high-potential driving voltage or a low-potential driving voltage to the QB node responsive to the first clock signal, an output buffer configured to output the high-potential driving voltage or the low-potential driving voltage to the corresponding emission line responsive to the voltages at the Q node and the QB node, and a pump controller configured to change the voltage at the Q node according to a second clock signal while the emission signal is output at a turn-on level responsive to the start signal or the carry signal.

The invention relates to the technical field of Ethernet communication and digital information transmission, and discloses an Ethernet-based time synchronization acquisition method, device and equipment and a medium, and the method comprises the steps: obtaining initial network time based on a network time protocol and a precise time protocol; recovering the synchronous clock signal from the Ethernet physical layer signal and generating a trigger pulse signal aligned with a second boundary to generate second-level reference time; the trigger pulse signal and the synchronous clock signal are used for executing high-frequency counting accumulation to generate nanosecond-level fine time; performing frequency division processing on the synchronous clock signal based on the sampling rate configuration parameter to obtain a sampling driving clock; the analog-to-digital conversion unit is triggered at the effective jump edge of the sampling driving clock to sample and latch nanosecond-level fine time to generate a sampling timestamp, and the sampling timestamp is output in combination with sampling data. According to the method, time recovery, time refinement and sampling time locking are realized through a unified time base, so that sampling action and time counting are accurately aligned, and the data synchronization precision and consistency of distributed acquisition nodes are improved.

The invention relates to the technical field of chip delay error dynamic compensation scheme design, in particular to a chip delay error dynamic compensation method and system based on TDC. The method comprises the following steps: measuring the transmission delay of a critical path in real time by using a time-to-digital converter core integrated in a chip; dynamically predicting a future delay error through an embedded algorithm based on the delay measurement value; and according to the predicted delay error, dynamic compensation is carried out on the chip timing sequence, and the compensation comprises adjustment of a clock signal or modification of path delay. A corresponding system includes a TDC core for real-time measurement, an embedded processing unit for running a predictive algorithm, and a dynamic compensation unit for performing compensation. Closed-loop control is formed through real-time monitoring, prediction and compensation, the influence of process, voltage and temperature changes on the time sequence of the chip can be effectively resisted, the time sequence precision, working stability and reliability of the chip are remarkably improved, and the method is particularly suitable for high-frequency and precise measurement chips.

The invention belongs to the technical field of clock chips, and discloses an intelligent calibration multi-channel clock chip system and a control method, the system comprises a coprocessor, an initial phase-locked loop, a selector and a plurality of clock output branches; the clock output branch comprises a numerical control circuit and a frequency divider which are connected with each other; the initial phase-locked loop is used for receiving an input clock signal, performing frequency multiplication on the input clock signal to obtain a reference clock signal, and sending the reference clock signal to the numerical control circuit of the at least one clock output branch through the selector; and the numerical control circuit is used for eliminating the distributed transmission delay difference in the reference clock signal by adopting a digital compensation algorithm, generating a target clock signal according to the reference clock signal after the delay difference is eliminated, and sending the target clock signal to the corresponding frequency divider. According to the invention, the absolute synchronization error of each clock output branch can be reduced, and the application scene diversity and flexibility of the clock chip are improved.

The invention relates to the technical field of distributed control, and particularly discloses a distributed LED screen cooperative control system based on a wireless synchronization protocol, and the system comprises a division module which obtains the transmission bandwidth and the mean value of each LED display screen, records the LED display screen with the maximum mean value as a main screen, and records the rest as sub-screens; the detection module is used for sending a synchronizing signal, recording the moment when the synchronizing signal is received, sending a timestamp to the sub-screen, converting the direction and resending; and the adjusting module is used for generating limit value conditions, calculating network delay and clock skew, adjusting clocks of the sub-screens based on the clock skew, screening out fluctuating sub-screens, calculating a delay predicted value based on the network delay, sending frame data in advance, obtaining a picture difference between the main screen and the fluctuating sub-screens, and adjusting the delay predicted value. Through the clock signal synchronization and advanced transmission method, the problem of high delay in high-dynamic display content is solved, and the delay is reduced.

A shift register comprises: an input circuit (1) configured to write a signal provided by a signal input terminal (INPUT) to a third node (N3) in response to a signal provided by a first clock signal terminal (CK); a first control circuit (2) configured to write a voltage provided by a first power supply terminal to a first node (N1) in response to a signal provided by a preset control signal terminal (CS) and a signal provided by a preset clock signal terminal; a second control circuit (3) configured to write a voltage provided by a second power supply terminal to the first node (N1) in response to a signal provided by the signal input terminal (INPUT); and an output circuit (4) configured to write the voltage provided by the second power supply terminal to a signal output terminal (OUT) in response to a voltage at the first node (N1) and write the voltage provided by the first power supply terminal to the signal output terminal (OUT) in response to a voltage at a fourth node (N4), the third node (N3) being coupled to the fourth node (N4). The disclosure also provides a gate drive circuit (DC) and a display device.