7122 results about "Clock signal" patented technology

The invention provides an image acquisition card multi-mode identification method and system based on intelligent security and protection. The method comprises the following steps: acquiring a multi-mode original data stream according to a global clock signal of an image acquisition card; performing space-time calibration on the multi-modal original data stream to generate a synchronous multi-modal data queue; extracting a multi-modal feature tensor of the synchronous multi-modal data queue through data preprocessing; performing hierarchical attention fusion on the multi-modal feature tensor to generate a fusion feature matrix; performing channel pruning on the fusion feature matrix through a lightweight convolutional neural network, and constructing a target detection model; and determining a detection result corresponding to the multi-modal original data stream according to the target detection model. Through the synergistic effect of a global clock signal and a dynamic space-time calibration algorithm, a time synchronization and space alignment compensation mechanism is constructed in a multi-modal data stream, and the problem of multi-modal information complementary advantage attenuation caused by space-time mismatch is effectively solved.

The invention relates to a network real-time synchronization communication system, and relates to the technical field of computer network communication. The system comprises four core modules: a hardware optical IO synchronization module which integrates a multi-wavelength optical transceiver array and an anti-jitter circuit and provides a nanosecond global clock signal, and the synchronization precision is less than or equal to 15ns; the time sequence arrangement module is used for dividing a fixed time window and a dynamic buffer window based on a time sensitive network, supporting a priority preemption mechanism of the SRIO bus and realizing deterministic data transmission; the distributed RTDATA nodes replace a traditional single-board computer, a heterogeneous computing unit and an intelligent storage controller are integrated, and protocol stack processing delay is reduced through the zero copy technology; according to the dynamic multicast routing system, a safely isolated multicast tree is constructed as required, and link load distribution is optimized in combination with machine learning. Through collaborative design of hardware optical synchronization and dynamic data arrangement, the problem of real-time performance reduction caused by multi-node communication concurrence is solved.

The invention relates to the technical field of control and regulation systems, in particular to a photovoltaic module anomaly recognition method based on laser detection, which comprises the following steps: generating a clock signal synchronous with a laser scanning time sequence through a hardware synchronous trigger, and driving a temperature and humidity sensor, a salt mist sensor and an illumination intensity sensor to collect environmental parameters; and constructing a multi-source data set containing the salt crystallization trend and the environmental interference level. And based on a temperature and humidity segmented compensation reflectivity base line, a salt mist mode switching optimization dust retention judgment threshold value, and illumination correlation sensitivity adjustment hot spot detection parameters, dynamic model correction is realized. And a fault database is matched to trigger a grading alarm mechanism, and a decision tree classifier is combined to verify time continuity to generate a diagnosis report. A dynamic detection path is constructed through spiral path planning, a multi-machine contract network protocol and wind disturbance trajectory correction, data feedback is executed to form closed-loop control logic, and the problems of misjudgment and missing detection in high salt mist, temperature change and illumination fluctuation environments are effectively solved.

The invention discloses a clock tree synthesis method and related equipment, and the method comprises the steps: dividing a plurality of time sequence units which need to receive clock signals from a clock source into clustering clusters of different levels, and enabling the load capacitance of each clustering cluster of the same level to be balanced; according to a hierarchical sequence of clusters starting from the clock source, taking each cluster as a node of a clock tree, recursively constructing the clock tree, and inserting a target buffer at the position of each node for driving the corresponding node; analyzing the delay and offset of the constructed clock tree to obtain an analysis result; and if the analysis result indicates that the delay and offset of the clock tree do not meet the preset constraint condition, adjusting the clock tree until the adjusted delay and offset of the clock tree meet the preset constraint condition. According to the technical scheme, power consumption and offset can be effectively reduced, calculation efficiency and design reliability are improved, and the method is suitable for high-performance chip design under the advanced technology.

The invention belongs to the technical field of radars, and discloses a vehicle-mounted multi-source radar converged communication system based on a FlexRay bus and a synchronization method of the vehicle-mounted multi-source radar converged communication system based on the FlexRay bus. The FlexRay communication bus supports a static and dynamic dual-channel structure and has a deterministic communication capability, and the maximum bandwidth can reach 10Mbps; the distributed radar controller is connected with each radar node and used for collecting local radar data, packaging timestamps and uploading the data through FlexRay; the time synchronization controller is used for realizing nanosecond synchronization through a FlexRay global clock mechanism and broadcasting clock signals to all radar nodes; the fusion processing unit is used for intensively receiving all radar data and carrying out target detection and data fusion based on a unified time sequence; and the main control coordination module is used for upwards communicating with the automatic driving domain controller and downwards uniformly coordinating the behaviors of the subsystems. The system has the capabilities of accurate time sequence, multi-source data fusion, fault-tolerant control and the like, and is a high-reliability communication platform supporting intelligent driving decision making.

The invention discloses a clock tree synthesis method and system based on clustering, and the method comprises the steps: carrying out the preliminary grouping of registers through employing a K-means clustering method, generating the position of a first-stage buffer under the condition that the maximum fan-out number limitation constraint, the maximum RC constraint and the position overlapping constraint are satisfied, and generating a second-stage buffer based on the position, and then constructing a subsequent clock tree by adopting a DME algorithm. The problem of clock signal distribution in large-scale integrated circuit design is solved, clock delay, clock skew and the number of buffers can be reduced, and the comprehensive quality of the clock tree is improved.

Implementing asymmetric processor cores to enable higher operating frequencies in processor-based devices is disclosed herein. In some aspects, a processor-based device provides a core cluster that comprises a plurality of processor cores and a corresponding phase-locked loop (PLL). Each processor core is based on a common instruction set architecture (ISA) and is configured to operate synchronously based on a same clock signal from the PLL of the core cluster. A first subset of processor cores within the core cluster is implemented with a different physical characteristic relative to a second subset of processor cores within the core cluster, wherein the different physical characteristic enables each processor core of the first subset of processor cores to operate at a higher operating frequency than each processor core of the second subset of processor cores.

The embodiment of the invention provides a signal processing circuit, a chip and electronic equipment. The signal processing circuit comprises an analog-to-digital conversion module and a signal amplification module, the first chopping switch module is used for modulating the differential input signal to high frequency under the control of a preset clock signal and inputting the signal to the signal amplification module; the second chopping switch module is used for modulating the differential output signal output by the signal amplification module to a low frequency under the control of a preset control signal and inputting the low frequency to the analog-to-digital conversion module; and the second chopping switch module also enables the analog-to-digital conversion module to establish sampling under the control of a preset control signal. According to the application, the second chopping switch module is multiplexed as a sampling switch of the analog-to-digital conversion module, so that the problem that on-resistance is increased due to the fact that a chopping demodulation switch and the sampling switch are arranged at the same time can be avoided.

The invention provides an optical-electric hybrid ultra-low time delay communication method and system, and relates to the technical field of communication, and the method comprises the steps: outputting a global synchronous clock signal with clock jitter less than 1ppm, dynamically dividing micro time slot resources in an orthogonal frequency division multiplexing symbol period, and generating a dynamically adjusted micro time slot resource distribution result; calculating an optimal phase offset matrix of the metasurface intelligent reflecting surface through a depth deterministic strategy gradient algorithm to obtain an optimized electromagnetic wave propagation path; generating a global optimization check matrix by aggregating the locally trained lightweight error correction model gradient of each node to obtain a compensated data stream; and constructing a causal graph model dynamic pruning high-entropy path to minimize causal entropy, through multi-agent reinforcement learning, taking time delay-energy efficiency as a game target to decide an optimal modulation order and a subcarrier switching strategy, and obtaining an optimized stable communication link. According to the invention, high-reliability and low-delay communication basic support is provided for high-precision intelligent manufacturing.

The invention relates to a high-precision temperature sensor based on complementary dynamic element matching and a zoom analog-to-digital converter and a working method, and belongs to the technical field of sensor improvement, and the sensor comprises an analog front end, an analog-to-digital converter, a digital rear end and a control logic. An improved chopping technology is adopted, and one clock signal is adopted to control two sub operational amplifiers, so that the output stability and precision of the analog front end are improved. A complementary dynamic element matching technology is utilized, errors caused by voltage drop at the two ends of a switch are reduced, the influence of channel charge injection is counteracted, a scaling type analog-to-digital converter design is provided for an analog-to-digital conversion part, and balance among power consumption, speed and precision is achieved. According to the method, a 10-bit successive approximation register analog-to-digital converter is used for measuring a numerical value and a change trend, and the numerical value and the change trend are analyzed, so that the expression effects of a current mirror structure, a transistor, a filter and the like are evaluated, the aging of the transistor is found in advance, and a clear direction is provided for future design improvement.

The invention provides a clock signal generating circuit, a wired communication transceiver and electronic equipment, and the circuit outputs a first DC voltage comprising phase difference information and frequency difference information of a reference clock signal and a feedback clock signal through a phase frequency detection module. The pulse generator generates a narrow pulse signal based on the DC voltage and a reference clock signal, the oscillation frequency of each secondary ring oscillator in the cross-coupled ring oscillator is controlled by the first DC voltage, and the cross-coupled loop performs synchronous coupling and phase sequence adjustment processing on each secondary ring oscillator. One output node in the cross coupling ring oscillator receives the narrow pulse signal, frequency and phase locking is completed in an injection locking mode, and the frequency divider is used for conducting frequency division processing on any high-frequency clock signal and outputting a feedback clock signal. Therefore, a high-frequency multi-phase clock signal with low phase noise and high phase precision can be generated by using the low-frequency reference clock signal.

The invention relates to the technical field of smelter equipment control, in particular to a smelter feeding multi-equipment cooperative control method, system and equipment, and the method comprises the steps: constructing a real-time communication network between smelter feeding equipment, synchronizing the clock signals of the smelter feeding equipment, and scheduling the transmission time sequence of control instructions according to the priority; continuously collecting operation state data of each smelting furnace feeding device according to a real-time communication network, and generating a device operation index according to a preset abnormality judgment rule; when the device operation index indicates that the first device is in an abnormal state, dynamically allocating a control task of the first device to at least one second device based on a current topological structure of the real-time communication network, and adjusting a link connection relationship of the real-time communication network; and according to the instruction interface type of the target equipment, converting the cooperative control instruction into an instruction format adaptive to the target equipment. According to the invention, the problems of multi-device communication delay, high abnormal detection misjudgment rate and low protocol conversion efficiency in a complex environment are effectively solved.

A modular multiport converter system includes a plurality of distributed controllers, associated with different ports of the system that are able to synchronize to ensure that power drawn from the system is equal to power supplied to the system with precise timing. The distributed controllers are able to receive a clock signal from a leader controller, or from a vice leader controller in the event that leader controller is unable to function.

The invention discloses a clock optimization method, device and equipment and a computer readable storage medium, which are applied to the field of integrated circuits, and comprise the following steps: reading a netlist of each fragment, and traversing each netlist to generate an instance tree corresponding to each fragment; performing reverse tracing and forward tracing on each clock signal based on each instance tree to obtain a clock network path corresponding to each clock signal; determining a redundant clock according to each clock network path, and performing corresponding processing on the redundant clock; the redundant clock comprises an isolated redundant clock and an equivalent redundant clock. According to the method, the instance tree is generated by traversing the netlist, and the complete clock network path is obtained by combining reverse tracing and forward tracing, so that isolated redundant clocks and equivalent redundant clocks can be comprehensively captured, and automatic tracking of the clock network path and accurate identification of the redundant clocks are realized; the redundant clock is correspondingly processed, so that unnecessary clock generation logic and wiring resource occupation can be reduced, the chip power consumption and the area overhead are reduced, and the resource utilization rate is improved.

The invention provides a repair circuit, a display panel and display equipment. The repairing circuit comprises a dedelay unit, an input end of which is connected with a grid electrode to-be-repaired signal and an output end of which is electrically connected with a first node; the input end of the shaping unit is electrically connected to the first node, and the output end is electrically connected to the second node; the input end of the inverting unit is electrically connected to the second node, and the output end is electrically connected to the third node. The de-delay unit is used for processing the grid signal to be repaired according to the clock signal and outputting a de-delay signal, so that the falling edge of the de-delay signal is consistent with the falling edge of the clock signal; the shaping unit is used for processing the rising edge waveform of the dedelayed signal and outputting a square wave signal opposite to the dedelayed signal in phase; and the inverting unit is used for performing inverting processing on the square wave signal and outputting a grid electrode repairing signal. The repairing circuit can effectively repair abnormal grid signals in the display panel, and the product yield is improved.

The invention provides a cross-platform content compatibility method and system based on a virtual shooting LED display screen. The method comprises the following steps: processing an irrelevant data content stream of a content stream of a heterogeneous content source to generate an intermediate data stream; constructing a virtual logic display space according to the resolution parameter of the intermediate data stream and the curvature data of the physical screen database; performing dynamic resource allocation based on the control point grid of the virtual logic display space, and generating a rendering task queue; loading a three-dimensional lookup table to perform forward color gamut conversion according to the rendering task queue and a physical screen color configuration file, and adjusting HSL offset according to collected real-time chroma data to generate frame cache data; and determining a delay compensation value based on the frame buffer data and the PTP clock signal, and inserting a corresponding time offset in an output queue through the delay compensation value to generate a multi-screen output signal. According to the scheme, the rendering accuracy, the color consistency and the display stability in the virtual shooting scene can be remarkably improved.

A control system for an AC-DC converter includes a mixed-signal power controller and first and second gate drivers. The controller has a digital module and an analog module. The analog module has a current sensor generating a current sense voltage based on a sensed switch current. The digital module has a DC voltage sensor generating a DC sense voltage based on a DC bus voltage, and an AC voltage sensor generating an AC sense voltage and a binary polarity signal based on the AC voltage. The digital module induces the first gate driver to output first and second control signals for controlling a high-side switch and a low-side switch of a current shaping half-bridge based on first and second clock signals and the comparator voltage, such that an inductor current flowing through an inductor is proportional to a current command value.

The invention discloses a multi-channel analog-to-digital converter for multi-channel frequency division multiplexing and a conversion circuit and method thereof, and the frequency division multiplexing multi-channel analog-to-digital conversion circuit comprises an analog frequency conversion module which is used for receiving N paths of modulation clock signals, and generating N paths of modulation clock signals according to the modulation clock signals, n paths of input signals are modulated to preset frequencies of the input signals respectively, and N paths of modulation signals are obtained; wherein N is greater than or equal to 2, and N is a positive integer; the frequency bands where the N paths of modulation signals are located are not overlapped; the analog adder is used for combining the N paths of modulation signals to obtain one path of analog signal; the input end of the analog-digital conversion module is connected with the analog-digital conversion module; the digital logic control module is used for receiving the N paths of modulation clock signals and separating the digital signals into N paths of digital signals which are output in parallel. Multi-channel analog-to-digital conversion can be realized by adopting one analog-to-digital converter, the hardware volume, cost and power consumption can be reduced, and the analog-to-digital conversion rate and precision can be improved.

A phase interpolator circuit that generates an output clock signal having a phase according to a PI code based on input clock signals, the phase interpolator circuit includes: a first generation circuit configured to generate a first intermediate current based on a first input clock signal according to the PI code; a second generation circuit configured to generate a second intermediate current based on a second input clock signal having a first phase difference from the first input clock signal according to the PI code; a synthesis circuit configured to synthesize the first and second intermediate currents to generate the output clock signal; and a correction circuit configured to correct a current amount of at least one of the intermediate currents based on a correction current according to a correction code set according to at least an amount of shift of the first phase difference from a certain value.

The invention provides a signal decoding method based on a PSI5 interface, and relates to the technical field of signal decoding, and the decoding method comprises the following steps: processing and adjusting a received PSI5 signal to obtain an accurate identification signal; and extracting a clock signal from the PSI5 signal, designing a clock compensation algorithm according to the quantum neural network, and dynamically adjusting the clock signal to obtain clock synchronization data. And determining a data frame boundary, and decoding the accurate identification signal to obtain original data. And performing comparative analysis on the original data and the PSI5 signal to obtain comparative difference data, judging whether the comparative difference data accords with a preset error type or not, and performing corresponding processing. According to the invention, fractional calculus processing is carried out on the received signal, then signal distortion is corrected by using a channel equalization method, and the quantum neural network is constructed to dynamically adjust the clock signal, so that clock synchronization is realized, a reliable time reference is provided for accurate processing of the signal, and the accuracy of signal decoding is improved.

A control circuit for a switching converter includes a compensation circuit, a ramp generation circuit, a comparison circuit and a logic circuit. The compensation circuit is configured to generate a compensation signal in response to a feedback signal and a reference signal. The ramp generation circuit is configured to generate a ramp signal. The comparison circuit is configured to provide a comparison signal in response to the compensation signal and the ramp signal. The logic circuit is configured to provide the PWM control signal to the switching converter. The PWM control signal is at a first voltage level when a value of the ramp signal reaches a value of the compensation signal. The PWM control signal is at a second voltage level in response to the clock signal.

The invention provides an ultrasonic fingerprint chip and an integral clock generation method and device of the ultrasonic fingerprint chip. Appropriate fingerprint pixel units can be selected from a plurality of fingerprint pixel units to serve as first-class pixel units and second-class pixel units, and the first-class pixel units and the second-class pixel units are respectively connected with a first-class detection circuit and a second-class detection circuit. Wherein a first integrator in the first type of detection circuit is sequentially connected with a first comparator, a time delay regulator, a clock dominant frequency duplicator and a frequency dividing circuit; the frequency dividing circuit is connected with the second type detection circuit; a second integrator in the second type detection circuit is connected with an amplification structure; the amplification structure is also connected with a second comparator; and the second comparator is connected with the time delay regulator in the first-class detection circuit. The circuit can automatically generate and obtain the integral clock signal which is matched with the ultrasonic fingerprint echo signal and is high in precision and good in effect, so that the received ultrasonic fingerprint echo signal is precisely processed, and a target signal with high quality is obtained.

The invention relates to a self-diagnosis method for a state terminal of a substation measurement system, which comprises the following steps of: comparing signal values at different sampling nodes of signals from the same physical source in each measurement channel through the state terminal, and judging that the channels have physical chain degradation or poor contact; performing perturbation modulation on a measurement sampling process based on a clock signal controlled by a crystal oscillator in the state terminal, and if response deviation abnormity is detected, judging that a sampling time base has drift, time sequence disorder or cache backlog so as to identify a time base health state of a sampling chain in the terminal; in the operation process of the transformer substation, response differences generated by the excitation in different measurement channels are collected, and if response delay, amplitude distortion or jitter starting point deviation is found, it is judged that the anti-interference capacity of the corresponding channel is degraded; and according to the electric energy change rhythm sensed by the terminal in real time, adaptively adjusting the sensitivity threshold value of the jump response, and if frequent misjudgment or slow response of the jump response is detected, marking that the behavior sensitivity of the terminal sampling system is abnormal.

The invention belongs to the field of electronic circuits, and provides a zero-cross detection circuit with an anti-crash function, a switching power supply and electronic equipment. The circuit comprises a current output module, a capacitor module, a switch module, a comparison module and a logic module, the capacitor module is connected with the current output module, the switch module and the comparison module, the current output module is connected with the switch module and a power module, and the logic module is connected with the switch module and the comparison module. And the current output module, the capacitor module and the switch module are also grounded. The logic module determines the working state of the circuit through the zero-crossing signal output by the comparison module, when the zero-crossing detection circuit enters a dead halt state, the reset signal is output according to the clock signal and the zero-crossing signal, and the switch module is controlled to be switched on periodically, so that the capacitor module is discharged periodically, the zero-crossing detection threshold value is reduced slowly, and the zero-crossing detection efficiency is improved. Finally, the zero-cross detection circuit can normally trigger zero-cross detection, and the reliability and efficiency of the switching power supply are improved.

The invention belongs to the technical field of display driving, and particularly relates to a gate driving circuit and a display panel, the gate driving circuit comprises N cascaded GOA circuit units, and the nth GOA circuit unit comprises a control voltage maintaining module used for maintaining the control voltage of the n + 1th GOA circuit unit under the action of the pre-charging voltage on the control voltage end of the (n + 1) th GOA circuit unit, maintaining the control voltage end of the nth GOA circuit unit at a first target voltage; the output module is used for outputting a gate driving signal under the action of a first target voltage on a control voltage end and a clock signal output by a clock signal end; the stage transmission module is used for outputting a stage transmission signal for pre-charging the control voltage end of the (n + i) th stage GOA circuit unit under the action of a target voltage on the control voltage end and a clock signal output by the clock signal end; the problem that the potential of the Q point is unstable due to leakage current is solved, the falling edge time of the gate driving signal can be greatly shortened, and the display effect of a picture is improved.

The invention relates to the field of intelligent power grids, and discloses a fault classification and traceability method based on an electric energy meter event log, which comprises the following steps: performing millisecond-level dynamic acquisition on power failure, recovery and abnormal voltage data of a user electric meter and an adjacent electric meter, and performing second-level time alignment based on a transformer area reference clock signal; executing multi-table cross-time sequence correlation analysis on the event priority sequence, and constructing a power grid event multi-dimensional feature tensor; for the multi-dimensional feature tensor of the power grid event, carrying out abnormal aggregation on local modes in the tensor by adopting a hierarchical causal reasoning model; on the basis of the candidate fault propagation path, a time sequence dependence attention mechanism is introduced, and contribution degrees of different electric meter events to potential faults are dynamically evaluated; dividing electric meter nodes and affected branches corresponding to the candidate power failure reason set into fault sensitive areas, and outputting a traceability result; the method has the advantages of judging the power failure reason in real time and automatically generating the solution.

The utility model discloses a digital auxiliary simulation LDO circuit without an off-chip capacitor. A simulation main loop of the circuit comprises an error amplifier, a buffer stage circuit, a simulation power stage circuit and a VG voltage detection circuit. The digital auxiliary loop includes a digital control logic circuit, a ring oscillator circuit, and a digital power stage circuit. By introducing the digital power adjusting tube, the parasitic capacitance of the grid electrode of the analog power tube is reduced, the pole of the grid electrode is located at high frequency, and on the basis, the super source follower is added to push the pole to higher frequency, so that the circuit has better loop stability. In a steady state, the digital auxiliary loop is forbidden, and the analog main loop can ensure strict adjustment, low quiescent current and no switching noise at the output end; when a load current suddenly changes, a ring oscillator in the digital auxiliary loop is called to generate a clock signal, and the number of conducted digital power tubes is changed, so that response time is not limited by a clock period, dependence on an external clock is avoided, meanwhile, voltage precision and rapid transient response are guaranteed, and static power consumption of the circuit is reduced.

The invention provides an electric energy meter clock error calibration system and calibration method. The method comprises the steps of presetting a control time table of a high and low temperature box and at least two automatic trimming schemes; the upper computer adjusts the temperature of the high-low temperature box according to the control time table; switching the connected meter numbers through a clock signal relay, obtaining a daily timing error message of each meter number in each round of test, and analyzing to obtain PPM and S / D data; carrying out mean value calculation on all PPM and all S / D data obtained by each meter number in each round of test, and obtaining a clock error value comprising a PPM mean value and an S / D mean value; after each round of test is finished, according to a clock error value corresponding to the meter number, assembling to obtain an RTC trimming frame according to the selected automatic trimming scheme, and sending the RTC trimming frame; and verifying an RTC trimming result. According to the invention, full-automatic test trimming can be realized, and the efficiency and precision of test and calibration are significantly improved.

A circuit is provided. The circuit can include sensing circuits configured to sense differences between first and second currents on selected bit lines of an array of memory cells and produce outputs for the bit lines as a function of the difference, and a global programmable non-regular counter configured to continuously provide a count value to each of the sensing circuits in dependence on a clock signal, wherein each sensing circuit, of the sensing circuits, includes (i) a local detector circuit configured to detect a voltage (Vc) generated according to the difference and (ii) a reference voltage selector configured to receive reference voltages from a source and to select a single reference voltage (Vref), and wherein each sensing circuit produces an output according to (i) a difference between Vc and Vref and (ii) a stored count value received from the counter.

The invention belongs to the technical field of display driving, and particularly relates to a gate driving circuit and a display panel, the gate driving circuit comprises a plurality of clock signal lines and cascaded N driving units, and the nth-level driving unit further comprises a pre-charging module used for pre-charging the nth-level driving unit under the action of a level transmission signal of the (n-i) th-level driving unit, the driving control node is charged through a first driving signal of the (n-i) th-stage driving unit; the output module is used for outputting a first driving signal through the first driving output end and outputting a second driving signal through the second driving output end under the action of the control voltage on the driving control node; according to the gate driving circuit, the number of the driving units can be reduced by half on the premise that the number of the output signals is the same through the mode that the first-stage driving unit outputs the two driving signals, so that the number of transistors in the gate driving circuit is greatly reduced, a narrow-frame product can be achieved, meanwhile, the cost of a panel is reduced, and the stability of the panel is improved.