3248 results about "Clock signal" patented technology

The invention provides an ultrasonic fingerprint chip and an integral clock generation method and device of the ultrasonic fingerprint chip. Appropriate fingerprint pixel units can be selected from a plurality of fingerprint pixel units to serve as first-class pixel units and second-class pixel units, and the first-class pixel units and the second-class pixel units are respectively connected with a first-class detection circuit and a second-class detection circuit. Wherein a first integrator in the first type of detection circuit is sequentially connected with a first comparator, a time delay regulator, a clock dominant frequency duplicator and a frequency dividing circuit; the frequency dividing circuit is connected with the second type detection circuit; a second integrator in the second type detection circuit is connected with an amplification structure; the amplification structure is also connected with a second comparator; and the second comparator is connected with the time delay regulator in the first-class detection circuit. The circuit can automatically generate and obtain the integral clock signal which is matched with the ultrasonic fingerprint echo signal and is high in precision and good in effect, so that the received ultrasonic fingerprint echo signal is precisely processed, and a target signal with high quality is obtained.

The invention discloses a power frequency phase adaptive acquisition device, and relates to the technical field of electric power signal measurement, the device acquires electric field data at a gap through an electric field sensor integrated on an edge shell, calculates electric field intensity fluctuation, and generates interference diagnosis information in combination with a preset interference determination threshold value; when the interference diagnosis information shows that effective interference exists, the electric field intensity variable quantity is calculated, a mapping model is established based on a proportionality coefficient obtained through an experiment so as to obtain zero crossing point offset, and the sampling trigger moment of a zero crossing point detection module is corrected; the clock synchronization module calculates a phase difference by taking the corrected trigger moment as a reference, dynamically adjusts a calibration frequency by combining a phase difference threshold value, and outputs a synchronized system clock signal; and the control system takes the synchronized system clock signal as a trigger signal, collects power frequency phase data according to a power frequency period, and stores the power frequency phase data to a database through a transmission unit, thereby realizing high-precision power frequency phase collection.

The embodiment of the invention provides a delay measurement circuit and a memory. The delay measurement circuit is applied to the delay phase-locked loop and comprises a loop mark generation circuit which is electrically connected with a loop of the delay phase-locked loop and is configured to generate a loop mark signal and input the loop mark signal to the loop of the delay phase-locked loop when loop delay measurement is carried out on the delay phase-locked loop; after the loop mark signal circulates M times in the loop of the delay phase-locked loop, a measurement ending signal is generated, a target pulse signal is generated, and the effective pulse width of the target pulse signal is equal to M times of the loop delay; wherein M is an even number greater than 1; the counting circuit is electrically connected with the loop mark generation circuit and is configured to receive a frequency division clock signal, and the effective pulse width of the target pulse signal is timed by using the frequency division clock signal to obtain a timing result; and carrying out preset processing on the timing result to obtain a loop delay measurement result of the delay-locked loop. The embodiment of the invention is at least beneficial to increasing the margin value of the delay measurement circuit and improving the accuracy of loop delay measurement.

The invention provides an ultrasonic fingerprint pixel array circuit and an ultrasonic fingerprint data processing method. Based on the ultrasonic fingerprint pixel array circuit, a corresponding fingerprint pixel unit can be determined in a first position area of the ultrasonic fingerprint pixel array circuit and transformed into a first detection unit capable of locally generating an integral clock signal; meanwhile, a corresponding fingerprint pixel unit determined in a second position area of the ultrasonic fingerprint pixel array circuit is transformed into a second detection unit which can be matched with the first detection unit to carry out self-adaptive feedback adjustment on the generated integral clock signal. Therefore, the improved ultrasonic fingerprint pixel array circuit capable of automatically generating the integral clock signal matched with the ultrasonic fingerprint echo signal can be constructed by fully utilizing the original circuit structure of the ultrasonic fingerprint pixel array circuit at relatively low cost. Therefore, the ultrasonic fingerprint pixel array circuit can be utilized to efficiently and locally generate an integral clock signal with a better effect to process an ultrasonic fingerprint echo signal.

The invention discloses a real-time wave number space resampling method and system for SS-OCT, and relates to the technical field of signal processing, and the method comprises the steps: synchronously collecting a K clock signal and an OCT interference signal, and carrying out the filtering preprocessing of the signals; carrying out Hilbert transformation on the preprocessed K clock signal, constructing an analysis signal, extracting an instantaneous phase, and forming an instantaneous phase sequence; using a preset ideal equal wave number interval phase sequence as a target phase sequence, matching the target phase sequence with the instantaneous phase sequence, calculating a corresponding position index of each target phase in the instantaneous phase sequence, and obtaining a remapping sampling point index; and processing the preprocessed OCT interference signal by using an SINC interpolation method according to the remapping sampling point index to obtain an OCT signal which is subjected to resampling and has equal wave number intervals. According to the invention, the SINC interpolation algorithm is utilized to complete resampling in real time and with high precision in the data acquisition stage, and the requirement of high-speed real-time imaging is met.

The invention provides a display device, a gate drive circuit of the display device comprises N levels of cascaded gate drive units, the ith level of gate drive unit comprises a first transistor, a first frequency division signal line, a second frequency division signal line and a frequency division control module, a gate of the first transistor is electrically connected to a second node, and a gate of the second transistor is electrically connected to a third node. The source electrode and the drain electrode are electrically connected to the first clock signal line and the gate driving signal output end respectively, and the frequency division control module is electrically connected with the first node, the second node, the first frequency division signal line and the second frequency division signal line. The first frequency division signal line and the second frequency division signal line are located between the first transistor and the frequency division control module. Through the layout mode, the metal overline distance is reduced, the layout space of the gate driving unit is saved, meanwhile, different areas of the display panel are refreshed by adopting different refresh frequencies, and the power consumption of the display device is reduced.

The invention relates to the technical field of Ethernet communication and digital information transmission, and discloses an Ethernet-based time synchronization acquisition method, device and equipment and a medium, and the method comprises the steps: obtaining initial network time based on a network time protocol and a precise time protocol; recovering the synchronous clock signal from the Ethernet physical layer signal and generating a trigger pulse signal aligned with a second boundary to generate second-level reference time; the trigger pulse signal and the synchronous clock signal are used for executing high-frequency counting accumulation to generate nanosecond-level fine time; performing frequency division processing on the synchronous clock signal based on the sampling rate configuration parameter to obtain a sampling driving clock; the analog-to-digital conversion unit is triggered at the effective jump edge of the sampling driving clock to sample and latch nanosecond-level fine time to generate a sampling timestamp, and the sampling timestamp is output in combination with sampling data. According to the method, time recovery, time refinement and sampling time locking are realized through a unified time base, so that sampling action and time counting are accurately aligned, and the data synchronization precision and consistency of distributed acquisition nodes are improved.

The invention relates to the technical field of chip delay error dynamic compensation scheme design, in particular to a chip delay error dynamic compensation method and system based on TDC. The method comprises the following steps: measuring the transmission delay of a critical path in real time by using a time-to-digital converter core integrated in a chip; dynamically predicting a future delay error through an embedded algorithm based on the delay measurement value; and according to the predicted delay error, dynamic compensation is carried out on the chip timing sequence, and the compensation comprises adjustment of a clock signal or modification of path delay. A corresponding system includes a TDC core for real-time measurement, an embedded processing unit for running a predictive algorithm, and a dynamic compensation unit for performing compensation. Closed-loop control is formed through real-time monitoring, prediction and compensation, the influence of process, voltage and temperature changes on the time sequence of the chip can be effectively resisted, the time sequence precision, working stability and reliability of the chip are remarkably improved, and the method is particularly suitable for high-frequency and precise measurement chips.

The invention provides a clock transmission circuit, a phase calibration method and a memory. The clock transmission circuit comprises a first clock distribution network and a second clock distribution network which respectively receive a first input clock signal and a second input clock signal, transmit the first input clock signal and the second input clock signal to an output port area and output a first target clock signal and a second target clock signal; in the normal working mode, the phase difference between the second input clock signal and the first input clock signal is a preset value; in the calibration mode, the second input clock signal and the first input clock signal are in the same phase; the phase calibration module is used for receiving the first target clock signal and the second target clock signal in a calibration mode, and outputting a first phase calibration code according to the phase difference between the first target clock signal and the second target clock signal for adjusting the delay of the second clock distribution network; when calibration is completed, the phase difference between the first target clock signal and the second target clock signal is smaller than a preset threshold value. The invention is at least beneficial to improving the phase difference among the multi-phase clocks and shortening the test time.

The invention discloses an ultra-wideband circulator based on a periodic modulation topology circuit, and belongs to the technical field of microwave and radio frequency nonreciprocal circuits. The working bandwidth range of the circulator is widened, and non-reciprocal transmission is achieved through non-magnetic materials. A time sequence control unit is respectively connected with a Floquet topology circuit layer, a clock signal driving module, a reset signal driving module and a start signal driving module; the Floquet topology circuit layer is respectively connected with a first coupling port, a second coupling port and a third coupling port; the other ends of the first coupling port, the second coupling port, the third coupling port, the clock signal driving module, the reset signal driving module and the starting signal driving module are respectively grounded; the Floquet topology circuit layer adopts a six-layer parallel network structure, and each layer of network structure comprises a coupling capacitor and three N-type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) switches. The advantages of the switched capacitor structure are utilized, and the signal processing capacity which is high in integration level, small in size and capable of breaking through delay-bandwidth limitation is achieved.

Provided is a display device including a pixel array including a plurality of pixels arranged in a matrix. Each pixel includes a pulse width modulation (PWM) circuit and an emission device; a data driver configured to provide pixel data to pixels arranged in a row of the pixel array; and a row driver configured to generate control signals and clock signals for driving the pixel array. The PWM circuit is configured to generate the PWM signal based on the control signals and the clock signals, the PWM signal including a plurality of bit fields respectively corresponding to a plurality of bits of the pixel data. The PWM circuit is further configured to, in a PWM period in which the PWM signal is output, distribute a first bit field of the PWM signal corresponding to a most significant bit (MSB) of the pixel data, among the plurality of bit fields.

A high linearity phase interpolator (PI) is disclosed. A phase value parameter indicative of a desired phase difference between an output signal and an input clock signal edge may be provided by control logic. A first capacitor may be charged for a first period of time with a first current that is proportional to the phase value parameter to produce a first voltage on the capacitor that is proportional to the phase value parameter. The first capacitor may be further charged for a second period of time with a second current that has a constant value to form a voltage ramp offset by the first voltage. A reference voltage may be compared to the voltage ramp during the second period of time. The output signal may be asserted at a time when the voltage ramp equals the reference voltage.

The invention belongs to the technical field of time synchronization, and provides a multi-sensor time synchronization method and system and application, and the method comprises the steps: carrying out the calibration of a local clock of each sensor based on a reference clock signal provided by a dual-mode reference clock, so as to correct the time deviation; measuring the original transmission delay of data transmission of each sensor in real time, and generating a dynamic compensation coefficient based on a delay fluctuation model; based on the calibrated local clock and the dynamic compensation coefficient, performing correction and alignment verification on the timestamps of the sensor data, and calculating an alignment error; and if the alignment error exceeds a preset threshold value, reversely adjusting the dynamic compensation coefficient and / or the reference clock signal to form closed-loop control. According to the method, the problems of low synchronization precision, poor flexibility and insufficient real-time performance of the existing multi-sensor time synchronization method under complex working conditions can be solved, and the space-time matching reliability of a multi-sensor fusion system is improved.

The invention provides a design method and system of a high-speed RC clock system. The system comprises a high-speed RC oscillator, a reference clock module, a clock calibration module, a trigger module and a state machine module. The method comprises the following steps of: controlling a calibration process through a state machine module, counting a high-frequency clock signal by taking a theoretical count value as a reference after a clock calibration module is triggered, judging whether the frequency has deviation or not and the direction of the deviation according to a counting result, performing stepping adjustment on a calibration value, and performing frequency adjustment on a high-speed RC oscillator. And circularly executing the calibration step until the counting result falls into an allowable error range. A phase-locked loop circuit does not need to be additionally arranged, high and low temperature calibration in the production stage does not need to be introduced, the chip design complexity, the manufacturing cost and the production test cost can be effectively reduced, meanwhile, high precision and stability of clock signals are ensured, and output of a low-cost, high-frequency and high-precision RC clock is achieved.

Methods, systems, and devices for distributed temperature sensors in a die of a memory device are described. For example, the distributed temperature sensors may enable a memory system controller to detect hotspots or uneven temperature distributions across the memory system. The memory system controller may perform health monitoring reporting based on the detected hotspots or uneven temperature distributions. In some examples, the memory system controller may activate, or deactivate, one or more components of regions associated with the hotspots to reduce the temperature of the region or die. Additionally, or alternatively, the memory system controller may adjust or retrain a clock signal to compensate for the detected hotspots or uneven temperature distributions.

The invention belongs to the technical field of time sequence calibration, and relates to a core particle parallel interface time sequence calibration method, which comprises the following steps of: introducing a phase interpolator with 180-degree phase deviation in a clock path of a receiving end, and positioning a sampling clock at the center of a data eye diagram; in a data path of a receiving end, a coarse adjustment delay calibration unit is firstly adopted to carry out periodic delay compensation, and the coarse adjustment delay calibration unit adopts a numerical control delay line structure to carry out delay adjustment; and then, a fine adjustment delay calibration unit is adopted to further realize sub-period-level delay adjustment, the fine adjustment delay calibration unit adopts a phase interpolator structure and a dynamic fine adjustment calibration mechanism, and finally, the delayed data signal and the clock signal are aligned at a receiving end. According to the invention, the binary search method is introduced, the positioning speed of the optimal delay configuration is obviously improved, delay drift is fully considered, a dynamic calibration mechanism is added, a sampling window is constructed based on a phase interpolator, and a high-precision and dynamic calibration effect is realized.

There is disclosed herein methods for synchronizing clocks in power grid devices. A method performed by a clock-leader unit comprises receiving an indication of a new clock signal for a plurality of clock-follower units to follow, for use in synchronizing clocks of the plurality of clock-follower units, and sending an instruction to the plurality of clock-follower units to calibrate based on the new clock signal. The method then comprises obtaining a confirmation that the plurality of clock-follower units has completed calibration and, in response to obtaining the confirmation, sending an instruction to the clock-follower units to follow the new clock signal. By co-ordinating the transition of clock-follower units to following the new clock signal, a synchronization of time operations between the clock-follower units can be better maintained.

The invention discloses a high-precision clock taming and signal shaping method and device for a satellite timing system. The method comprises the following steps of: counting and measuring a reference pulse per second received in real time by using a local high-frequency clock signal output by a local voltage-controlled crystal oscillator to obtain a phase counting deviation sequence of the local high-frequency clock signal relative to the reference pulse per second; inputting the phase counting deviation sequence into the frequency control closed-loop model, analyzing the historical state characteristics of the phase counting deviation sequence, and calculating a frequency adjustment instruction for the local voltage-controlled crystal oscillator; the frequency adjusting instruction is converted into an analog voltage signal, a local voltage-controlled crystal oscillator is driven to adjust the output frequency, and a tamed local high-frequency clock signal is obtained; the tamed local high frequency clock signal is utilized to drive phase warping logic to generate a local pulse per second synchronized with the reference pulse per second. According to the invention, through adaptive closed-loop control and phase regulation, precise taming of crystal oscillator frequency and high-precision shaping of output signals are realized.

An analog-to-digital converter, ADC, is provided. The ADC comprises multiple time-interleaved sub-ADCs, a detection circuit, and a calibration circuit. The sub-ADCs are configured to, when the ADC is in a calibration mode, generate a first signal by sampling a calibration signal based on a first clock signal and at least a second clock signal. The first clock signal comprises a phase shift relative to the second clock signal. The calibration circuit is configured to determine a first mismatch between the phase shift and a phase shift threshold based on the first signal. The detection circuit is configured to, when the ADC is in an operation mode, generate a second signal by sampling one of a biased signal to be received by the sub-ADCs or a second calibration signal based on at least one of the first clock signal and the second clock signal. The calibration circuit is configured to determine a second mismatch between the phase shift and the phase shift threshold based on the second signal and calibrate the ADC based on the first and the second mismatch.

The invention discloses a power equipment multi-band signal comprehensive detection method, which comprises the following steps: deploying a multi-band sensor, and synchronously coupling and collecting an original composite signal; distributing a unified clock signal to each monitoring point based on an optical fiber synchronous network, and controlling an acquisition channel to synchronously acquire an original composite signal; preprocessing and performing frequency band separation on the original composite signal, and outputting a plurality of sub-frequency bands; and extracting signal features from the sub-bands, outputting a multi-dimensional feature vector to a pre-trained deep learning diagnosis model, outputting a combined diagnosis result, and calculating spatial position coordinates of the discharge source. Electrician frequency, overvoltage and partial discharge signals are integrally acquired through the multi-frequency-band sensor, high-precision time alignment acquisition of multi-parameter signals is realized in combination with a subnanosecond optical fiber synchronization technology, intelligent analysis is performed by adopting a double-branch deep neural network for parallel processing of time domain and frequency domain characteristics, and the accuracy and the reliability of the system are improved. And the combined diagnosis precision and the early warning capability of complex insulation defects and overvoltage events are obviously improved.

A semiconductor memory device includes a physical region, a direct access region and a power manager. The direct access region interfaces with an external test device directly. The power manager generates an internal power supply voltage based on one of a first power supply voltage, a second power supply voltage and a power supply voltage, and provides the internal power supply voltage to the direct access region. The power manager provides the second power supply voltage to the physical region. The direct access region includes a test interface circuit and the test interface circuit, in a direct access mode, generates an internal clock signal based on an external clock signal, generates an internal test clock signal by latching a test control signal received from the external test device based on the internal clock signal and provides the internal test control signal to the physical region.

The invention belongs to the technical field of industrial measurement and control, and discloses a multi-case cascade vibration noise data acquisition clock synchronization method. A clock drift prediction model based on deep learning is constructed by acquiring local clock signals and environment parameters of all cases in real time, and accurate prediction of clock behaviors is achieved. A multi-mode communication strategy combining optical fibers and wireless radio frequency is innovatively adopted, reliable transmission mechanisms which are redundant to each other are formed, and the anti-interference capability is remarkably enhanced. A dynamic compensation mechanism based on the fuzzy logic controller can intelligently adjust compensation parameters according to clock states and environment changes, and accurate correction is achieved. A multi-level verification mechanism including local self-inspection, mutual inspection between cases and global optimization is established, a graph neural network technology is introduced to carry out system-level optimization, and the system has self-learning and self-optimization capabilities. According to the method, the time consistency of the vibration noise data is remarkably improved.

The invention relates to the technical field of analog and digital-analog hybrid integrated circuits, and discloses a bootstrap sampling switch circuit with a pre-charging function and an analog-to-digital converter. The circuit comprises a sampling switch module and a time sequence control module. The sampling switch module sequentially works at a holding phase, a pre-charging phase and a tracking phase under the control of a multi-phase clock signal generated by the time sequence control module, the pre-charging phase is added before the tracking phase, the grid voltage of a sampling switch is pre-boosted, and the pre-charging time is dynamically controlled by using an adjustable clock circuit, so that the pre-charging time of the sampling switch is dynamically controlled. Therefore, the charge sharing effect caused by the gate parasitic capacitance is effectively suppressed. The analog-to-digital converter comprises the sampling switch circuit. The linearity and the conduction characteristic of the sampling switch are remarkably improved, and the sampling switch has excellent time sequence configurability and is suitable for a high-speed and high-precision analog-to-digital conversion system.

A pixel includes a first transistor including a first terminal configured to receive a driving voltage, a second terminal connected to a light-emitting diode, and a gate terminal connected to a node, a second transistor including a first terminal configured to receive a data voltage, a second terminal connected to the node, and a gate terminal configured to receive a scan signal, a third transistor including a first terminal configured to receive an initialization voltage, a second terminal connected to the light-emitting diode, and a gate terminal configured to receive a sensing signal, and a fourth transistor including a first terminal configured to receive a scan clock signal, a second terminal connected to the gate terminal of the second transistor, and a gate terminal configured to receive a voltage of a Q node.

A flip-flop circuit includes a first memory circuit and a second memory circuit. The flip-flop circuit can be configured to store a first value of the data signal in the first storage circuit in response to a rising edge of the clock signal and a second value of the data signal in the second storage circuit in response to a falling edge of the clock signal during a double edge trigger mode. The flip-flop circuit can be configured to store a third value of the data signal in the first storage circuit and output the third value from the first storage circuit in response to the clock signal during the single-edge trigger mode.

Disclosed are an automotive Ethernet circuit board and communications system, and a vehicle. The automotive Ethernet circuit board includes: a component placement layer, configured to carry a PHY chip and a control chip of the PHY chip; a plurality of signal wiring layers, configured to carry signal wiring between components in the component placement layer; and a signal shielding layer, located between the plurality of signal wiring layers and configured to prevent interference of a clock signal in the signal wiring. In the embodiments of the present application, a plurality of signal wiring layers are used for signal wiring between components, and a plurality of complete signal shielding layers are used to prevent interference of a clock signal in the wiring. The embodiments help reduce signal crosstalk between PCBs, prevent interference of a clock signal in signal wiring, and improve stability and consistency of a data communications system.

A scan driving circuit includes: a switching circuit configured to deliver a third voltage to a first node in response to a carry signal and a first clock signal and to deliver the third voltage to a second node in response to the first clock signal; a first output transistor connected between a first voltage terminal and an output terminal, and configured to operate in response to a second signal of the second node, wherein the first voltage terminal receives a first voltage; and a second output transistor connected between the output terminal and a second clock terminal, and configured to operate in response to a first signal of the first node.

A ramp driver includes a ramp generator for generating a reference ramp signal, and a ramp delayer for sequentially outputting ramp signals based on the reference ramp signal, and including delay blocks including k output terminals, k being an integer greater than or equal to 2, wherein the delay blocks include k delay circuits sequentially connected to each other, respectively connected to the output terminals, and configured to receive an input ramp signal from a previous one of the delay circuits, receive an input gate clock signal from a previous delay circuit, output an output ramp signal by delaying the input ramp signal, and output an output gate clock signal by inverting the input gate clock signal.

The invention discloses a grid driving circuit, a driving circuit, a display panel and a display device, and a level transmission module is used for controlling a signal of a first node, a signal of a second node and a signal of a third node according to a starting signal and a clock signal, and outputting a level transmission control signal. The output module is used for outputting a grid control signal according to the signal of the fourth node and the signal of the fifth node. And the output frequency division module is used for controlling signal transmission between the first node and the third node and controlling signal transmission between the second node and the fifth node and between the third node and the fifth node according to the node control signal, the first frequency division control signal and the signal of the third node. When the current path between the first node and the fourth node and the current path between the second power supply end and the stage transmission output end are disconnected, the output frequency division module disconnects the current paths between the second node and the third node and the fifth node; and the output module is connected with a current path between the fourth power supply end and the signal output end according to the signal of the fifth node.

The invention relates to a clock management structure, a system on chip and electronic equipment, and the clock management structure comprises a phase-locked loop and an arbitration frequency division module connected with the phase-locked loop. The phase-locked loop is deployed in the PHY; the phase-locked loop is used for generating a phase-locked loop clock of X channels according to an externally input clock signal; the arbitration frequency division module is used for processing the phase-locked loop clocks of the X channels to generate an MAC interface clock, and synchronizing the MAC interface clock to an MAC interface and a port corresponding to each channel; wherein X represents the total number of channels corresponding to a plurality of ports between the PHY and the MAC. According to the clock management structure, the cross-clock domain design in the SoC design is greatly reduced, and the clock structure in the SoC is simplified, so that the area of the SoC chip is reduced.