9241 results about "Clock signal" patented technology

The invention provides an image acquisition card multi-mode identification method and system based on intelligent security and protection. The method comprises the following steps: acquiring a multi-mode original data stream according to a global clock signal of an image acquisition card; performing space-time calibration on the multi-modal original data stream to generate a synchronous multi-modal data queue; extracting a multi-modal feature tensor of the synchronous multi-modal data queue through data preprocessing; performing hierarchical attention fusion on the multi-modal feature tensor to generate a fusion feature matrix; performing channel pruning on the fusion feature matrix through a lightweight convolutional neural network, and constructing a target detection model; and determining a detection result corresponding to the multi-modal original data stream according to the target detection model. Through the synergistic effect of a global clock signal and a dynamic space-time calibration algorithm, a time synchronization and space alignment compensation mechanism is constructed in a multi-modal data stream, and the problem of multi-modal information complementary advantage attenuation caused by space-time mismatch is effectively solved.

The invention relates to a network real-time synchronization communication system, and relates to the technical field of computer network communication. The system comprises four core modules: a hardware optical IO synchronization module which integrates a multi-wavelength optical transceiver array and an anti-jitter circuit and provides a nanosecond global clock signal, and the synchronization precision is less than or equal to 15ns; the time sequence arrangement module is used for dividing a fixed time window and a dynamic buffer window based on a time sensitive network, supporting a priority preemption mechanism of the SRIO bus and realizing deterministic data transmission; the distributed RTDATA nodes replace a traditional single-board computer, a heterogeneous computing unit and an intelligent storage controller are integrated, and protocol stack processing delay is reduced through the zero copy technology; according to the dynamic multicast routing system, a safely isolated multicast tree is constructed as required, and link load distribution is optimized in combination with machine learning. Through collaborative design of hardware optical synchronization and dynamic data arrangement, the problem of real-time performance reduction caused by multi-node communication concurrence is solved.

The invention relates to the technical field of control and regulation systems, in particular to a photovoltaic module anomaly recognition method based on laser detection, which comprises the following steps: generating a clock signal synchronous with a laser scanning time sequence through a hardware synchronous trigger, and driving a temperature and humidity sensor, a salt mist sensor and an illumination intensity sensor to collect environmental parameters; and constructing a multi-source data set containing the salt crystallization trend and the environmental interference level. And based on a temperature and humidity segmented compensation reflectivity base line, a salt mist mode switching optimization dust retention judgment threshold value, and illumination correlation sensitivity adjustment hot spot detection parameters, dynamic model correction is realized. And a fault database is matched to trigger a grading alarm mechanism, and a decision tree classifier is combined to verify time continuity to generate a diagnosis report. A dynamic detection path is constructed through spiral path planning, a multi-machine contract network protocol and wind disturbance trajectory correction, data feedback is executed to form closed-loop control logic, and the problems of misjudgment and missing detection in high salt mist, temperature change and illumination fluctuation environments are effectively solved.

The invention provides an autonomous navigation method and related equipment based on laser and vision fusion, and the method comprises the following steps: carrying out multi-sensor space-time joint synchronization processing on laser point cloud data, binocular image data and a clock signal, and generating a space-time aligned multi-modal data stream; the multi-modal data stream is processed through cross-modal feature pyramid and attention guidance fusion, and dense environment characterization and a dynamic object space-time mask are generated; determining a multi-layer semantic map corresponding to the dense environment representation through layered factor graph optimization; fusing the multilayer semantic map with the neural radiation field to generate a mixed map of an explicit semantic map and an implicit radiation field; and determining a motion track of the target equipment through space-time joint constraint on the mixed map and the space-time mask of the dynamic object. Through the implementation of the scheme of the invention, the real-time distinguishing between the dynamic obstacle and the static structure can be realized in a dynamic complex environment, so that the obstacle avoidance robustness of the motion trail is remarkably improved.

The invention discloses a clock tree synthesis method and related equipment, and the method comprises the steps: dividing a plurality of time sequence units which need to receive clock signals from a clock source into clustering clusters of different levels, and enabling the load capacitance of each clustering cluster of the same level to be balanced; according to a hierarchical sequence of clusters starting from the clock source, taking each cluster as a node of a clock tree, recursively constructing the clock tree, and inserting a target buffer at the position of each node for driving the corresponding node; analyzing the delay and offset of the constructed clock tree to obtain an analysis result; and if the analysis result indicates that the delay and offset of the clock tree do not meet the preset constraint condition, adjusting the clock tree until the adjusted delay and offset of the clock tree meet the preset constraint condition. According to the technical scheme, power consumption and offset can be effectively reduced, calculation efficiency and design reliability are improved, and the method is suitable for high-performance chip design under the advanced technology.

The invention belongs to the technical field of radars, and discloses a vehicle-mounted multi-source radar converged communication system based on a FlexRay bus and a synchronization method of the vehicle-mounted multi-source radar converged communication system based on the FlexRay bus. The FlexRay communication bus supports a static and dynamic dual-channel structure and has a deterministic communication capability, and the maximum bandwidth can reach 10Mbps; the distributed radar controller is connected with each radar node and used for collecting local radar data, packaging timestamps and uploading the data through FlexRay; the time synchronization controller is used for realizing nanosecond synchronization through a FlexRay global clock mechanism and broadcasting clock signals to all radar nodes; the fusion processing unit is used for intensively receiving all radar data and carrying out target detection and data fusion based on a unified time sequence; and the main control coordination module is used for upwards communicating with the automatic driving domain controller and downwards uniformly coordinating the behaviors of the subsystems. The system has the capabilities of accurate time sequence, multi-source data fusion, fault-tolerant control and the like, and is a high-reliability communication platform supporting intelligent driving decision making.

The present disclosure provides a multiphase switching converter and control circuit thereof. The multiphase switching converter includes a plurality of control circuits forming a daisy chain architecture, and to generate a preparatory output signal and a switching control signal for controlling a corresponding switching circuit when receiving a clock signal from a communication bus in the preparatory state, the control circuit is configured to operate in a preparatory state when receiving a preparatory input signal. Only preparatory signals are transmitted between the plurality of control circuits, and a signal for controlling circuit being on is participated by the clock signal generated by a host controller, so that the host controller does not need to track a position of a current unit in real time during a control process of all units, thus greatly simplifying a design of the host controller and reducing a circuit cost.

The invention discloses a transmitter equalization driving circuit and a method for processing a signal to be transmitted. The circuit comprises a serialization and retiming module used for generating multiple paths of parallel data based on a signal to be transmitted; the data selector module is connected with the serialization and retiming module and used for receiving the clock signal corresponding to each path of parallel data and generating process data including front tap data, main tap data, first rear tap data and second rear tap data based on the parallel data and the clock signal; the pulse generation module is connected with the data selector module and is used for receiving the process data to generate a front tap equalization pulse and a first rear tap equalization pulse; and the hybrid equalization driving module is connected with the pulse generation module and the data selector module, and is used for receiving the front tap data, the front tap equalization pulse, the main tap data, the first rear tap equalization pulse and the second rear tap data to generate an output signal of the signal to be transmitted. The circuit can improve the signal quality of the output signal.

The invention discloses a clock tree synthesis method and system based on clustering, and the method comprises the steps: carrying out the preliminary grouping of registers through employing a K-means clustering method, generating the position of a first-stage buffer under the condition that the maximum fan-out number limitation constraint, the maximum RC constraint and the position overlapping constraint are satisfied, and generating a second-stage buffer based on the position, and then constructing a subsequent clock tree by adopting a DME algorithm. The problem of clock signal distribution in large-scale integrated circuit design is solved, clock delay, clock skew and the number of buffers can be reduced, and the comprehensive quality of the clock tree is improved.

The invention relates to the field of magnetic field generation, and discloses a multi-mode array magnetic field generation system and method. The single excitation source matrix excitation comprises an FPGA main control chip and a DDS signal generation module, a DDS chip reads a signal waveform stored in an ROM, a keying module is combined with a PLL clock signal module and an amplification circuit, signals with adjustable amplitude, frequency, phase and duty ratio are achieved, excitation is applied to an array coil through bipolar D / A conversion to generate magnetic fields of different modes, and the magnetic fields of different modes are generated. The Hall magneto-dependent sensor is combined to adjust the angle and direction of the generated magnetic field in real time, and the focusing angle of the magnetic field is dynamically changed. The array coil is excited by generating a plurality of current signals with different amplitudes, frequencies, phases, duty ratios and directions, and the Hall magneto-dependent sensor above the coil is combined, so that the energy and direction of an array magnetic field are controllable, the magnetic field generation efficiency is improved, and the detection target is enhanced.

Implementing asymmetric processor cores to enable higher operating frequencies in processor-based devices is disclosed herein. In some aspects, a processor-based device provides a core cluster that comprises a plurality of processor cores and a corresponding phase-locked loop (PLL). Each processor core is based on a common instruction set architecture (ISA) and is configured to operate synchronously based on a same clock signal from the PLL of the core cluster. A first subset of processor cores within the core cluster is implemented with a different physical characteristic relative to a second subset of processor cores within the core cluster, wherein the different physical characteristic enables each processor core of the first subset of processor cores to operate at a higher operating frequency than each processor core of the second subset of processor cores.

Aspects of this technical solution can include a plurality of SAR TC stages configured to convert an input time signal to a digital code including a plurality of output signals each corresponding to a SAR TDC stage among the plurality of SAR TDC stages connected to an input of a following SAR TDC stage among the plurality of SAR TDC stages, where the SAR stage is controlled by a clock signal based on a delayed clock signal from a previous SAR TDC stage among the plurality of SAR TDC stages.

The embodiment of the invention provides a signal processing circuit, a chip and electronic equipment. The signal processing circuit comprises an analog-to-digital conversion module and a signal amplification module, the first chopping switch module is used for modulating the differential input signal to high frequency under the control of a preset clock signal and inputting the signal to the signal amplification module; the second chopping switch module is used for modulating the differential output signal output by the signal amplification module to a low frequency under the control of a preset control signal and inputting the low frequency to the analog-to-digital conversion module; and the second chopping switch module also enables the analog-to-digital conversion module to establish sampling under the control of a preset control signal. According to the application, the second chopping switch module is multiplexed as a sampling switch of the analog-to-digital conversion module, so that the problem that on-resistance is increased due to the fact that a chopping demodulation switch and the sampling switch are arranged at the same time can be avoided.

An apparatus for correcting an error of a clock signal may include a phase adjuster that corrects an error of half-rate clock signals based on an error correction signal to output an error-corrected clock signal, a phase splitter that outputs quadrature clock signals from the error-corrected clock signal, an error detector that outputs an internal clock signal based on one of the quadrature clock signals, selects two quadrature clock signals among the quadrature clock signals based on a clock selection signal, and detects errors of the two quadrature clock signals based on an error check signal to output a correction request signal, and a controller that outputs a mode selection signal and the clock selection signal based on the internal clock signal and that outputs the error correction signal and the error check signal based on the mode selection signal, the clock selection signal, and the correction request signal.

The invention provides an optical-electric hybrid ultra-low time delay communication method and system, and relates to the technical field of communication, and the method comprises the steps: outputting a global synchronous clock signal with clock jitter less than 1ppm, dynamically dividing micro time slot resources in an orthogonal frequency division multiplexing symbol period, and generating a dynamically adjusted micro time slot resource distribution result; calculating an optimal phase offset matrix of the metasurface intelligent reflecting surface through a depth deterministic strategy gradient algorithm to obtain an optimized electromagnetic wave propagation path; generating a global optimization check matrix by aggregating the locally trained lightweight error correction model gradient of each node to obtain a compensated data stream; and constructing a causal graph model dynamic pruning high-entropy path to minimize causal entropy, through multi-agent reinforcement learning, taking time delay-energy efficiency as a game target to decide an optimal modulation order and a subcarrier switching strategy, and obtaining an optimized stable communication link. According to the invention, high-reliability and low-delay communication basic support is provided for high-precision intelligent manufacturing.

The embodiment of the invention discloses a phase adjustment circuit and method and a memory. The phase adjustment circuit includes: a multi-phase clock signal generator configured to generate an initial multi-phase clock signal, a phase error detector configured to detect a phase error of the initial multi-phase clock signal, and a phase error canceller configured to cancel a phase error of the initial multi-phase clock signal; the phase error detector is connected with the multi-phase clock signal generator and is configured to perform phase error detection on the initial multi-phase clock signals to obtain error signals used for representing phase difference information among the initial multi-phase clock signals; the phase error eliminator is connected with the phase error detector and is configured to detect the error signal to obtain an error elimination code; and the multi-phase clock signal generator is also connected with the phase error eliminator and is configured to receive the error elimination code and perform phase adjustment on the initial multi-phase clock signal based on the error elimination code to obtain a target multi-phase clock signal.

The invention discloses a method for realizing data acquisition clock synchronization through Beidou time service and an FPGA phase-locked loop, and the method comprises the steps: obtaining a short message service signal of a Beidou satellite navigation system, and carrying out the analysis to obtain time service information; controlling a digital phase-locked loop to calibrate a local clock signal according to the time service information; monitoring the deviation between the time service information and the local clock signal, and adjusting the frequency and phase of the local clock signal through feedback control of the digital phase-locked loop; monitoring a clock synchronization state, setting a clock deviation threshold value, judging the synchronization state of the time service information and the local clock signal, if the deviation exceeds a threshold value range, triggering an alarm signal, and taking a recovery measure according to an abnormity type and duration time; a hardware timestamp function is integrated, clock synchronization with other acquisition nodes is carried out through a precise time protocol, and the acquisition time of seismic data is recorded.

The invention relates to a high-precision temperature sensor based on complementary dynamic element matching and a zoom analog-to-digital converter and a working method, and belongs to the technical field of sensor improvement, and the sensor comprises an analog front end, an analog-to-digital converter, a digital rear end and a control logic. An improved chopping technology is adopted, and one clock signal is adopted to control two sub operational amplifiers, so that the output stability and precision of the analog front end are improved. A complementary dynamic element matching technology is utilized, errors caused by voltage drop at the two ends of a switch are reduced, the influence of channel charge injection is counteracted, a scaling type analog-to-digital converter design is provided for an analog-to-digital conversion part, and balance among power consumption, speed and precision is achieved. According to the method, a 10-bit successive approximation register analog-to-digital converter is used for measuring a numerical value and a change trend, and the numerical value and the change trend are analyzed, so that the expression effects of a current mirror structure, a transistor, a filter and the like are evaluated, the aging of the transistor is found in advance, and a clear direction is provided for future design improvement.

The invention provides a clock signal generating circuit, a wired communication transceiver and electronic equipment, and the circuit outputs a first DC voltage comprising phase difference information and frequency difference information of a reference clock signal and a feedback clock signal through a phase frequency detection module. The pulse generator generates a narrow pulse signal based on the DC voltage and a reference clock signal, the oscillation frequency of each secondary ring oscillator in the cross-coupled ring oscillator is controlled by the first DC voltage, and the cross-coupled loop performs synchronous coupling and phase sequence adjustment processing on each secondary ring oscillator. One output node in the cross coupling ring oscillator receives the narrow pulse signal, frequency and phase locking is completed in an injection locking mode, and the frequency divider is used for conducting frequency division processing on any high-frequency clock signal and outputting a feedback clock signal. Therefore, a high-frequency multi-phase clock signal with low phase noise and high phase precision can be generated by using the low-frequency reference clock signal.

The invention relates to the technical field of smelter equipment control, in particular to a smelter feeding multi-equipment cooperative control method, system and equipment, and the method comprises the steps: constructing a real-time communication network between smelter feeding equipment, synchronizing the clock signals of the smelter feeding equipment, and scheduling the transmission time sequence of control instructions according to the priority; continuously collecting operation state data of each smelting furnace feeding device according to a real-time communication network, and generating a device operation index according to a preset abnormality judgment rule; when the device operation index indicates that the first device is in an abnormal state, dynamically allocating a control task of the first device to at least one second device based on a current topological structure of the real-time communication network, and adjusting a link connection relationship of the real-time communication network; and according to the instruction interface type of the target equipment, converting the cooperative control instruction into an instruction format adaptive to the target equipment. According to the invention, the problems of multi-device communication delay, high abnormal detection misjudgment rate and low protocol conversion efficiency in a complex environment are effectively solved.

A modular multiport converter system includes a plurality of distributed controllers, associated with different ports of the system that are able to synchronize to ensure that power drawn from the system is equal to power supplied to the system with precise timing. The distributed controllers are able to receive a clock signal from a leader controller, or from a vice leader controller in the event that leader controller is unable to function.

A clock generation apparatus includes a counter configured to count transitions in a locally generated clock signal when a data signal is received from a 1-wire serial bus, a latch configured to capture an output of the counter and to provide a latched output representative of the transitions counted in the locally generated clock signal while a synchronization pattern is received in the data signal, a flipflop and a comparator configured to drive a decision signal to a first signaling state when the output of the counter matches the latched output and to drive the decision signal to a second signaling state when the output of the counter does not match the latched output. The flipflop has an output that changes signaling state in response to an edge in the decision signal. The counter is reset when the decision signal is driven to the first signaling state.

A system to perform high speed passive serial configuration of an FPGA is disclosed. The system includes an MCU that includes an interface, an FPGA coupled to the MCU over the interface, and a flash memory coupled to the MCU and to the FPGA over the interface. The flash memory includes MCU firmware for the MCU and FPGA configuration data for the FPGA. To perform passive serial configuration of the FPGA, the MCU is operable to at least: configure the flash memory to an input / output (IO) mode, place the FPGA in a configuration mode, send a read command over the interface to the flash memory for the FPGA configuration data, and continuously provide a clock signal over the interface to the flash memory until the FPGA configuration data is entirely read.

The invention discloses a clock optimization method, device and equipment and a computer readable storage medium, which are applied to the field of integrated circuits, and comprise the following steps: reading a netlist of each fragment, and traversing each netlist to generate an instance tree corresponding to each fragment; performing reverse tracing and forward tracing on each clock signal based on each instance tree to obtain a clock network path corresponding to each clock signal; determining a redundant clock according to each clock network path, and performing corresponding processing on the redundant clock; the redundant clock comprises an isolated redundant clock and an equivalent redundant clock. According to the method, the instance tree is generated by traversing the netlist, and the complete clock network path is obtained by combining reverse tracing and forward tracing, so that isolated redundant clocks and equivalent redundant clocks can be comprehensively captured, and automatic tracking of the clock network path and accurate identification of the redundant clocks are realized; the redundant clock is correspondingly processed, so that unnecessary clock generation logic and wiring resource occupation can be reduced, the chip power consumption and the area overhead are reduced, and the resource utilization rate is improved.

A charge pump, a phase-locked loop, a radar sensor, and an electronic device. The charge pump is applicable to the phase-locked loop. The charge pump comprises a discharging circuit and a charging circuit, both of which are connected to an output end of the charge pump. The discharging circuit reduces a current of the output terminal under control of a first control signal, the charging circuit increases it under control of a second control signal, the first control signal and the second control signal being corresponding to error signals between the two clock signals. The charge pump further comprises a voltage control circuit connected to a first node in the discharging circuit and / or a second node in the charging circuit to maintain the locked state of the phase-locked loop by controlling voltages of corresponding nodes, the first node and the second node being both connected to the output end.

The invention discloses a clock signal control soft PUF (Physical Unclonable Function) based on a coding circuit and an application method thereof, the clock signal control soft PUF comprises the coding circuit, a clock signal generator and a register module, the coding circuit can access externally input image information data, and the image information data is simultaneously used as an input excitation signal of the clock signal control soft PUF; the clock signal generator is used for generating three groups of clock signals of which the frequencies are sequentially increased, the clock cycles of the three groups of clock signals are all smaller than the critical path of the coding circuit, and each group of clock signals is an overclocking clock signal which can enable the coding circuit to be in an abnormal working state; if the external input image information data is accessed, the internal data transmission is abnormal, and at the moment, the coding circuit generates an output signal irrelevant to the input image information data and outputs the output signal to the register module for storage; the method has the advantages of being high in safety and low in resource consumption.

The present disclosure provides a digital low-dropout regulator (DLDO) and an electronic device using the same. The DLDO includes a voltage comparator circuit, a switch control circuit, a power switch module, and an asynchronous clock generation circuit. The voltage comparator circuit compares a reference voltage with the output voltage to output a comparison result signal. The switch control circuit generates a switch control signal based on the comparison result signal. The power switch module is controlled by the switch control signal to switch between the on state and the off state, thereby adjusting the output voltage. The asynchronous clock generation circuit generates a reference clock signal that is asynchronous with the system clock signal used in the load circuit and has a higher clock frequency. This allows the switch control circuit to update the switch control signal based on the reference clock signal.

The invention provides a repair circuit, a display panel and display equipment. The repairing circuit comprises a dedelay unit, an input end of which is connected with a grid electrode to-be-repaired signal and an output end of which is electrically connected with a first node; the input end of the shaping unit is electrically connected to the first node, and the output end is electrically connected to the second node; the input end of the inverting unit is electrically connected to the second node, and the output end is electrically connected to the third node. The de-delay unit is used for processing the grid signal to be repaired according to the clock signal and outputting a de-delay signal, so that the falling edge of the de-delay signal is consistent with the falling edge of the clock signal; the shaping unit is used for processing the rising edge waveform of the dedelayed signal and outputting a square wave signal opposite to the dedelayed signal in phase; and the inverting unit is used for performing inverting processing on the square wave signal and outputting a grid electrode repairing signal. The repairing circuit can effectively repair abnormal grid signals in the display panel, and the product yield is improved.

The invention provides a cross-platform content compatibility method and system based on a virtual shooting LED display screen. The method comprises the following steps: processing an irrelevant data content stream of a content stream of a heterogeneous content source to generate an intermediate data stream; constructing a virtual logic display space according to the resolution parameter of the intermediate data stream and the curvature data of the physical screen database; performing dynamic resource allocation based on the control point grid of the virtual logic display space, and generating a rendering task queue; loading a three-dimensional lookup table to perform forward color gamut conversion according to the rendering task queue and a physical screen color configuration file, and adjusting HSL offset according to collected real-time chroma data to generate frame cache data; and determining a delay compensation value based on the frame buffer data and the PTP clock signal, and inserting a corresponding time offset in an output queue through the delay compensation value to generate a multi-screen output signal. According to the scheme, the rendering accuracy, the color consistency and the display stability in the virtual shooting scene can be remarkably improved.