24results about "Power reduction by control/clock signal" patented technology

A semiconductor device includes a first regulator electrically connected to a first power supply line, a second regulator electrically connected to a second power supply line, a control circuit configured to control the first and second regulators, and at least two functional circuit modules electrically connectable to the first power supply line and the second power supply line. When all the functional circuit modules are set to a power-on state (active mode), the control circuit controls the first regulator to output a voltage to the first power supply line and the second regulator to output a voltage to the second power supply line, and when some functional circuit modules are set to a power-off state (standby mode), the control circuit controls the first regulator to output a voltage to the first power supply line and the second regulator not to output a voltage to the second power supply line.

The present subject matter relates to an electronic system comprising gated circuitry, a first regulator circuit directly coupled to the gated circuitry, always-on circuitry, a second regulator circuit directly coupled to the always-on circuitry, and a switch circuit coupled between an output of the first regulator circuit and an output of the second regulator circuit. The always-on circuitry includes control logic configured to activate the second regulator circuit and deactivate the first regulator circuit and the switch circuit in a sleep mode and activate the first regulator circuit and the switch circuit in an active mode.

A semiconductor device includes a retention circuit configured to retain a data value during a power gating operation, a non-retention circuit configured not to retain a data value during the power gating operation, a clock management unit (CMU) configured to provide a first operation clock to the retention circuit and provide a second operation clock to the non-retention circuit, and a power management unit (PMU) configured to provide a reference clock used to generate the first and second operation clocks to the CMU, generate a first isolation signal to permit a first signal to be output from the CMU, and generate a second isolation signal to permit a second signal to be output from the retention circuit and to permit a third signal to be output from the non-retention circuit.

The present disclosure relates to a power domain management circuit and a system on chip. The power domain management circuit includes: an enable unit, configured to generate an enable signal with a first preset level in a case of receiving an isolation set signal, or to generate an enable signal with a second preset level in a case of receiving a reset indication signal; and a clamping unit, electrically connected to the enable unit, and configured to clamp an initial signal transmitted from a first power domain to a second power domain to generate a target signal with a third preset level in a case of receiving the enable signal with the first preset level, or to skip clamping the initial signal to generate a target signal with a level that varies with a level of the initial signal in a case of receiving the enable signal with the second preset level.

An apparatus, including: a clock gating circuit, CGC, including: a clock gating device (920) configured to selectively gate / pass a selected clock signal based on an enable signal to generate an output clock signal; and a clock selection circuit (930) configured to select a non- complementary clock signal or a complementary clock signal to generate the selected clock signal based on the output clock signal and the non-complementary clock signal or the complementary clock signal.

In one implementation, a circuit for power-switching includes: power gating circuitry and a first back metal, where a single output of the power gating circuitry is configured to provide at least one of power and ground supply by way of the first back metal to a word line driver circuitry. A method for power-switching includes: providing a power gating circuitry and one or more back metals; and providing, by the power gating circuitry, at least one of power and ground supply through the one or more back metals to a word line driver circuitry. A method of fabrication includes: fabricating a memory macro unit; forming one or more back metals; and coupling power gating circuitry and word line driver circuitry of the memory macro unit by way of the one or more back metals.

At least one integrated power management unit (702) of the IC (700) includes a first unit (700) that is a 4-high unit, the first unit including a first contiguous n-well (704), a first power interconnect (792) coupled to a first voltage source (Vdd1) associated with a first voltage domain and the first contiguous n-well (704), a second contiguous n-well (706), a second power interconnect (796) coupled to a second voltage source (Vdd2) associated with a second voltage domain and the second contiguous n-well (706), a first subset (710a) of first voltage level shifters (710) associated with the first voltage domain and coupled to the first power interconnect, and a second subset (710b) of first voltage level shifters (710) associated with the second voltage domain and coupled to the second power interconnect.

A first block (11) is operated by receiving a first power supply voltage (VDD1) and a reference voltage (VSS). A second block (12) is operated by receiving a second power supply voltage (VDD2) and the reference voltage. When starting a semiconductor device (1a), the timing for changing the voltage of a first power supply line (PL1) from the reference voltage (VSS) to the first power supply voltage (VDD1) is earlier than the timing for changing the voltage of a second power supply line (PL2) from the reference voltage (VSS) to the second power supply voltage (VDD2). A first switch (SW1) is connected between a node (Ni) that transfers signals processed by the first block (11) or the second block (12), and the second power supply line (PL2). The first switch (SW1) turns ON when the voltage of the second power supply line (PL2) is the reference voltage (VSS), and turns OFF in response to the voltage of the second power supply line (PL2) approaching the second power supply voltage (VDD2).

Circuit, showing: a latch (120) configured to generate a gating control signal (Q) in response to a latch enable signal (EB) and an input clock signal (CP), wherein the latch (120) has a pair of logic gates (210, 220) each configured to perform a complex logic function at multiple levels; and a logic circuit (130) configured to receive the gating control signal (Q) and the input clock signal (CP) and to generate an output clock signal (CPQ) in response to the gating control signal (Q) and the input clock signal (CP), where the logic gates (210, 220) are: at least one header switch (M1) and at least one footer switch (M3), each configured to be controlled by the input clock signal (CP); a first (M5), a second (M13) and a third switch (M7) which are coupled in series with at least one header switch (M1); a fourth (M6), a fifth (M14) and a sixth switch (M8) coupled in series with at least one header switch (M1); and a pair of cross-coupled inverters (310, 320) coupled to at least one footer switch (M3), wherein the second (M13) and fifth switches (M14) are configured to be controlled by outputs of the inverters (310, 320); wherein the first (M5) and third switches (M7) are configured to be controlled by the latch release signal (EB), and the fourth (M6) and sixth switches (M8) are configured to be controlled by a logical complement of the latch release signal (EB).

Aspects of the subject disclosure address the traditional trade-off between performance and area, in relation to circuit and system design, together with power as an additional factor of consideration. Circuits and systems of this disclosure may realize a datapath of data in respect of memory state elements (e.g., registers, flops, etc.) that is dependent on multiple qualifiers. Aspects of this disclosure enhance (e.g., optimize) area and reduce leakage power associated with circuits and systems. Furthermore, aspects of this disclosure enable and enhance an insertion of clock-gating circuits or mechanisms to reduce dynamic-power consumption depending on states of the qualifiers.

Techniques and mechanisms for an integrated clock gate (ICG) to selectively output a clock signal, and to provide frequency division functionality. In an embodiment, an ICG circuit comprises first circuitry which is coupled to receive a first clock signal, and second circuitry which is coupled to receive a control signal. The first circuitry provides a single edge triggered flip-flop functionality, and is coupled to communicate a feedback signal which the first circuitry is further coupled to receive. Based on the control signal and the feedback signal, the second circuitry performs an exclusive OR (XOR) operation to selectively enable the first circuitry to generate a second clock signal based on the first clock signal. In another embodiment, a frequency of the second clock signal is substantially equal to one half of a frequency of the first clock signal.

A multi-bit level shifter that has a plurality of level shifters, each of which is configured to receive an input signal in a first voltage domain and provide a corresponding output signal in a second voltage domain. The level shifters each have an enable node. An enable circuit includes an output terminal connected to the enable node of each of the plurality of level shifters, and each of the plurality of level shifters is configured to output the corresponding output signals in response an enable signal received by the enable circuit.

A memory system in an embodiment includes: a nonvolatile memory; a memory controller configured to control the memory; and a power supply circuit configured to supply a voltage of power of at least one of the memory and the memory controller, wherein the power supply circuit is configured to: store first information having a value of the voltage to be supplied; output an output voltage based on the value of the voltage specified by the stored first information; detect an output current at an output end of the output voltage; compare a value of the detected output current with a threshold value; and update the stored first information to second information based on a result of the comparison, the second information having an updated value of the voltage to be supplied.

Technologies and implementations for a wake-up circuit. The wake-up circuit may be configured to reduce a peak value of current draw during waking up of an electronic device. The reduction of the peak value of current draw facilitates a reduction of electrical burden on various components of related circuit. Managing wake-up of circuits may include managing wake up of memory.

A cell region of a semiconductor device includes: substrates, each of which including: substantially uniformly sized clock gate blocks each of which including a clock gate; and substantially uniformly sized decap blocks each of which including a decoupling capacitor. For each substrate, at least one of a condition (A) or a condition (B) is true. The condition (A) includes each row has a first odd-even or a first even-odd intra-row arrangement of the clock gate blocks and the decap blocks, the rows are interleaved with respect to the first odd-even and even-odd intra-row arrangements; and row-wise arrangements of the substrates are different. The condition (B) includes each column has a second odd-even or a second even-odd intra-column arrangement of the clock gate blocks or the decap blocks, the columns are interleaved with respect to the second odd-even and even-odd intra-column arrangements; and column-wise arrangements of the substrates are different.

A semiconductor device includes a first transistor, a second transistor and a multiplexer. The first transistor is controlled by a first control signal. The second transistor is coupled in series with the first transistor, and is controlled by a first voltage signal. The multiplexer is configured to generate the first voltage signal according to the first control signal.

This disclosure relates to level shifting circuits and methods. One circuit includes a bias circuit and a level shifter. The bias circuit includes a first input terminal and a second input terminal configured to receive a first power supply voltage and a second power supply voltage, and the bias circuit is configured to generate a bias voltage having the greater of a first voltage level of the first power supply voltage or a second voltage level of the second power supply voltage. The level shifter includes a first PMOS transistor configured to receive the first power supply voltage and a second PMOS transistor configured to receive the second power supply voltage, and each of the first and second PMOS transistors includes a body terminal configured to receive the bias voltage.

The domain control circuit includes a power regulator for supplying power on the power rail to a first domain, a sequencing circuit for controlling the power regulator, and a clock gate signal for activating the domain. The sequencing circuit receives a domain control signal to control the activation and deactivation of the domain. The domain control circuit controls the power regulator to supply power on the power rail to the domain, and then deactivates the clock gate signal for the domain. In this way, the voltage droop of the supply voltage on the power rail is reduced. In some examples, the clock gate signal for the domain is deactivated after the voltage increases on the power rail. In some examples, the power regulator includes a plurality of parallel regulator circuits and a regulator control circuit for determining the number of parallel regulator circuits activated to supply power to the domain.

A macro cell includes one or more vertical die interconnects that vertically span the macro cell to transmit a data signal. The macro cell also includes one or more isolation features configured to manage a power of the macro cell by controlling a transmission of the data signal. Additionally, the macro cell includes one or more flip-flops configured to control a timing of the transmission of the data signal through the one or more vertical die interconnects. Various other apparatuses and systems are also disclosed.

Integrated circuits are described that utilize internal state machine-driven logic elements (e.g., flops) within input and / or output wrapper chains that are used to test internal core logic of the integrate circuit. One or more individual logic elements of the wrapper chains within the integrated circuit is implemented as a multi-flop state machine rather than a single digital flip-flop. As multi-flop state machines, each enhanced logic element of a wrapper chain is individually configurable to output preselected values so as to disassociate the state machine-driven flops from signal transmission delays that may occur in the input or output wrapper chains of the integrated circuit.

A signal isolation circuit for transferring multiple signals is disclosed. The signal isolation circuit for transferring multiple signals from a first domain to a second domain includes a multi-signal encoder configured to encode first to third signals of the first domain into a single fourth signal, a transceiver configured to transfer the fourth signal from the first domain to the second domain; and a multi-signal decoder configured to decode the first to third signals from the fourth signal in the second domain.

Embodiments disclosed herein relate to clock gating. An example integrated circuit includes an oscillator that outputs a clock signal to a clock gating system that generates and provides a gated clock signal to a data storage circuit. The clock gating system includes a first digital logic circuit having an input coupled to the oscillator to receive the clock signal, an active-low latch that includes an input coupled to an output of the first digital logic circuit and an input coupled to receive an enable signal, a second digital logic circuit that includes an input coupled to the oscillator and an input coupled to the output of the active-low latch, and an active-high latch that includes an input coupled to the output of the second digital logic circuit, an input coupled to receive the enable signal, and an output configured to provide a gated clock signal to the data storage circuit.