292results about "Power reduction by control/clock signal" patented technology

A system includes a comparator having a first input, a second input, and an output. The system also includes a first voltage divider having an input and an output, wherein the input of the first voltage divider is coupled to a first power rail, and the output of the first voltage divider is coupled to the first input of the comparator. The system also includes a second voltage divider having an input and an output, wherein the input of the second voltage divider is coupled to a second power rail, and the output of the second voltage divider is coupled to the second input of the comparator. The system further includes a power multiplexer coupled to the first power rail, the second power rail, and a first circuit, and a control circuit coupled to the output of the comparator and the power multiplexer.

A disclosed circuit structure includes a voltage level shifter connected to a variable voltage generator for receiving a low supply voltage and to a programmable voltage generator for receiving a high supply voltage that is higher than the low supply voltage. The high supply voltage is programmable to one of multiple different voltage levels. The variable voltage generator tracks the voltage level of the high supply voltage and outputs the low supply voltage based thereon. The high supply voltage is tracked either directly or using the trim bit signal employed by the programmable voltage generator to program the high supply voltage. The low supply voltage is high when the high supply voltage is high to ensure operation within the safe operating area and is low when the high supply voltage drops below some threshold level to ensure operability and, optionally, improve operating speed.

A circuit includes a power management circuit configured to receive at least a first or a second control signal, and to supply at least a first, second or a third supply voltage. The first control signal has a first voltage swing. The second control signal has a second voltage swing. The power management circuit includes a first level shifter circuit configured to generate a first level shifted signal in response to the first control signal, and a first header circuit coupled to at least the first level shifter circuit, a first voltage supply and a second voltage supply. The first header circuit is configured to supply the first supply voltage of the first voltage supply to the first node in response to the first control signal, and to supply the second supply voltage of the second voltage supply to the second node in response to the first level shifted signal.

Some embodiments include apparatuses and methods using a supply node to receive a die voltage; a delay line to stretch and squish a first clock signal in response to changes in the die voltage to generate a second clock signal; a frequency clamp circuit to receive the second clock signal and generate a third clock signal that is clamped below a frequency; and a squash controller to squash the third clock signal when the die voltage crosses at least one of a first threshold and a second threshold.

According to one embodiment, a semiconductor integrated circuit includes: a first buffer including an input end to which a first signal is configured to be supplied; a first switching element including a first end coupled to an output end of the first buffer and a second end coupled to a first node; a first capacitor including a first end coupled to the first node and a grounded second end; a second switching element including a first end coupled to the first node and a second end coupled to a second node; a second buffer including an input end coupled to the second node; and a first converter configured to determine a first bit string from a first output from the second buffer. The first and second switching elements being configured to switch between states based on a first clock signal.

A system includes a comparator having a first input, a second input, and an output. The system also includes a first voltage divider having an input and an output, wherein the input of the first voltage divider is coupled to a first power rail, and the output of the first voltage divider is coupled to the first input of the comparator. The system also includes a second voltage divider having an input and an output, wherein the input of the second voltage divider is coupled to a second power rail, and the output of the second voltage divider is coupled to the second input of the comparator. The system further includes a power multiplexer coupled to the first power rail, the second power rail, and a first circuit, and a control circuit coupled to the output of the comparator and the power multiplexer.

A multichip package includes: a chip package comprising a first IC chip, a polymer layer in a space beyond and extending from a sidewall of the first IC chip, a through package via in the polymer layer, an interconnection scheme under the first IC chip, polymer layer and through package via, and a metal bump under the interconnection scheme and at a bottom of the chip package, wherein the first IC chip comprises memory cells for storing data therein associated with resulting values for a look-up table (LUT) and a selection circuit comprising a first input data set for a logic operation and a second input data set associated with the data stored in the memory cells, wherein the selection circuit selects, in accordance with the first input data set, data from the second input data set as an output data for the logic operation; and a second IC chip over the chip package, wherein the second IC chip couples to the first IC chip through, in sequence, the through package via and interconnection scheme, wherein the second IC chip comprises a hard macro having an input data associated with the output data for the logic operation.

Various example embodiments for supporting power optimizations for electronic circuits are presented. Various example embodiments for supporting power optimizations for electronic circuits may be configured to support power optimizations for a block of an electronic circuit. Various example embodiments for supporting power optimizations for a block of an electronic circuit may be configured to support a reduction in power consumption by a clock distribution tree of the block of the electronic circuit. Various example embodiments for supporting a reduction in power consumption by a clock distribution tree of a block of an electronic circuit may be configured to reduce power consumption by the clock distribution tree of the block of the electronic circuit by supporting root clock throttling for the block of the electronic circuit, based on a workload on the block of the electronic circuit, to reduce power consumption by the clock distribution tree of the block of the electronic circuit.

A pipeline circuit and a pipeline operating method are provided. The pipeline circuit includes a gating circuit that is configured to receive an input signal at an input end and selectively output the input signal as an output signal at an output end. In a first mode, the gating circuit receives the input signal that has been gated to output as the output signal. In a second mode, the gating circuit receives the input signal to output as the output signal.

A semiconductor device includes a retention circuit configured to retain a data value during a power gating operation, a non-retention circuit configured not to retain a data value during the power gating operation, a clock management unit (CMU) configured to provide a first operation clock to the retention circuit and provide a second operation clock to the non-retention circuit, and a power management unit (PMU) configured to provide a reference clock used to generate the first and second operation clocks to the CMU, generate a first isolation signal to permit a first signal to be output from the CMU, and generate a second isolation signal to permit a second signal to be output from the retention circuit and to permit a third signal to be output from the non-retention circuit.

An apparatus, including: a clock gating circuit (CGC), including: a clock gating device configured to selectively gate / pass a selected clock signal based on an enable signal to generate an output clock signal; and a clock selection circuit configured to select a non-complementary clock signal or a complementary clock signal to generate the selected clock signal based on the output clock signal and the non-complementary clock signal or the complementary clock signal.

An apparatus, including: a clock gating circuit (CGC), including: a clock gating device configured to selectively gate / pass a selected clock signal based on an enable signal to generate an output clock signal; and a clock selection circuit configured to select a non-complementary clock signal or a complementary clock signal to generate the selected clock signal based on the output clock signal and the non-complementary clock signal or the complementary clock signal.

Certain aspects of the present disclosure are directed towards techniques for power management. The techniques provide an optimal staggering delay time between transmission of enable signals to power switches coupled (e.g., electrically coupled) to logic circuits and a power source. The optimal staggering delay time may allow enabling or turning on of the power switches in a staggered, sequential fashion while reducing power up latency of the logic circuits.

A system includes a first sense amplifier having a first data input, a second data input, a clock input configured to receive a first clock signal, a first output, and a second output. The system also includes a second sense amplifier having a first data input, a second data input, a clock input configured to receive a second clock signal, a first output, and a second output. The first data input of the second sense amplifier is coupled to the first data input of the first sense amplifier, and the second data input of the second sense amplifier is coupled to the second data input of the first sense amplifier. The system also includes a set-reset (S-R) latch coupled to the first output and the second output of the first sense amplifier, and coupled to the first output and the second output of the second sense amplifier.

Technologies and implementations for a wake-up circuit. The wake-up circuit may be configured to reduce a peak value of current draw during waking up of an electronic device. The reduction of the peak value of current draw facilitates a reduction of electrical burden on various components of related circuit. Managing wake-up of circuits may include managing wake up of memory.

A system includes a first sense amplifier having a first data input, a second data input, a clock input configured to receive a first clock signal, a first output, and a second output. The system also includes a second sense amplifier having a first data input, a second data input, a clock input configured to receive a second clock signal, a first output, and a second output. The first data input of the second sense amplifier is coupled to the first data input of the first sense amplifier, and the second data input of the second sense amplifier is coupled to the second data input of the first sense amplifier. The system also includes a set-reset (S-R) latch coupled to the first output and the second output of the first sense amplifier, and coupled to the first output and the second output of the second sense amplifier.

A flip-flop with clock gating based on data comparison is disclosed. The flip-flop unit includes an edge-triggered flip-flop and a clock gating circuit. The clock gating circuit enables or disables a first clock signal to generate a second clock signal according to a data comparison result of input data and output data. The second clock signal provides a triggering edge of the edge-triggered flip-flop. The clock gating circuit copies the first clock signal as the second clock signal in a clock cycle during which the input data is flipped, and maintains the second clock signal at a predetermined level in clock cycles during which the input data remains unchanged. The flip-flop unit enables the clock flip of the edge-triggered flip-flop only in a clock cycle during which the input data is flipped, thereby improving the circuit performance and reducing the power consumption.

A compute-in-memory (CIM) system includes a first leader-follower (L / F) flip-flop (FF), a suspender unit and a multiplication unit. The first L / F FF is configured to receive a data signal. The first L / F FF includes: a first leader FF configured to receive the data signal and a first follower FF configured to generate a signal first_Q_follow that represents a output signal of the first L / F FF. The multiplication unit is configured to receive a weight signal W and the signal first_Q_follow and generate a first product signal. The suspender unit is configured, during a given cycle of the first clock signal, detect that a first scenario is true in which all bits b(k) of the data signal equal logical zero and accordingly suppress latching from being performed by the first L / F FF, and control the multiplication unit to generate the first product signal as being equal to logical zero.

Trap circuits for use with superconducting integrated circuits having differential capacitively-coupled resonant clock networks are described. An example superconducting integrated circuit (IC) includes a first superconducting circuit comprising: (1) a first Josephson junction (JJ) coupled via a first capacitor to a first clock line, where the first capacitor is configured to receive a first clock signal having a first phase via the first clock line and couple a first bias current to the first JJ, and (2) a second JJ coupled via a second capacitor to a second clock line, where the second capacitor is configured to receive a second clock signal having a second phase via the second clock line and couple a second bias current to the second JJ. The superconducting IC further includes a first trap circuit for the first superconducting circuit and a second trap circuit for a second superconducting circuit having additional JJs.

The present disclosure relates to a circuit unit, a logic circuit, a processor, and a computing apparatus. A circuit unit is provided, including: an output terminal (OUT); an output stage (105), configured to provide an output signal to the output terminal; a first node (A), to which an input of the output stage is connected; and a feedback stage (107) that receives the output signal at the output terminal and selectively provides feedback to the node. A logic circuit is further provided, including an input stage that receives a signal input, and the circuit unit. The first node receives a signal based on an output of the input stage.

A system includes a measuring device, a processing device and a signal generating device. The measuring device is configured to measure a voltage difference between a first node and a second node. The processing device is coupled between the first node and the second node. The signal generating device is configured to provide a first clock signal to the processing device to adjust the voltage difference, configured to generate the first clock signal according to a first enable signal and a second clock signal, and configured to align an edge of the first enable signal with an edge of the second clock signal. A method and a device are also disclosed herein.

A level shift circuit (1) includes first to fourth P-type transistors, first and second N-type transistors, and a pull-up circuit (30). The first N-type transistor and the first P-type transistor are disposed between the input node and the output node, and the second P-type transistor is disposed between the first power supply and the output node. The second N-type transistor and the third P-type transistor are arranged between the inverted input node and the inverted output node, and the fourth P-type transistor is arranged between the first power supply and the inverted output node. The pull-up circuit (30) is configured to pull up the second node to the third power supply when the first node is converted from the high level to the low level, and pull up the first node to the third power supply when the second node is converted from the high level to the low level.

The invention discloses a circuit which comprises a logic circuit and a power switch module, and the power switch module comprises a plurality of switches, a voltage detection circuit and a control circuit. Each switch of the plurality of switches comprises a control end, a first end and a second end, the first end is coupled to a supply voltage, and the second end is coupled to the logic circuit; and the plurality of switches comprise a first switch and a plurality of second switches, and the control end of the first switch receives a power supply enabling signal. The voltage detection circuit is used for detecting whether a voltage of the second end of the first switch is higher than a reference voltage so as to generate a detection result. The control circuit is used for generating an output power enable signal to the plurality of second switches according to the detection result.

A semiconductor device includes a first regulator electrically connected to a first power supply line, a second regulator electrically connected to a second power supply line, a control circuit configured to control the first and second regulators, and at least two functional circuit modules electrically connectable to the first power supply line and the second power supply line. When all the functional circuit modules are set to a power-on state (active mode), the control circuit controls the first regulator to output a voltage to the first power supply line and the second regulator to output a voltage to the second power supply line, and when some functional circuit modules are set to a power-off state (standby mode), the control circuit controls the first regulator to output a voltage to the first power supply line and the second regulator not to output a voltage to the second power supply line.

A circuit includes a power management circuit configured to receive a first or second control signal, and to supply a first, second or third supply voltage. The power management circuit includes a first level shifter circuit, a first header circuit and a latch circuit. The first level shifter circuit is configured to generate a fourth control signal in response to a fifth control signal. The fourth control signal is a level shifted version of the fifth control signal. The first header circuit is configured to supply a first supply voltage of a first voltage supply to a first node in response to the first control signal, or a second supply voltage of a second voltage supply to a second node in response to a first level shifted signal. The latch circuit is configured to generate a first output control signal in response to the first and the fourth control signal.

To suppress the decrease in power supply capability even when a free area is necessary in a power supply switch circuit.SOLUTION: A semiconductor device includes a first power supply line, a second power supply line, an end cap, and a first power supply switch circuit including a first transistor and a second transistor. The first transistor is connected to the first power supply line and the second power supply line. The second transistor is connected to the first power supply line and the second power supply line. The first transistor includes a first number of first fins extending in a first direction in a plan view and arranged in a second direction, which is different from the first direction, in the plan view. The second transistor includes a second number of second fins extending in the first direction in the plan view and arranged in the second direction in the plan view. The first number is greater than the second number. The second transistor is disposed between the first transistor and the end cap in the plan view.SELECTED DRAWING: Figure 3

An apparatus, including: a clock gating circuit, CGC, including: a clock gating device (920) configured to selectively gate / pass a selected clock signal based on an enable signal to generate an output clock signal; and a clock selection circuit (930) configured to select a non- complementary clock signal or a complementary clock signal to generate the selected clock signal based on the output clock signal and the non-complementary clock signal or the complementary clock signal.

The present invention discloses a chip structure and a chip function control method, wherein the chip structure includes a programmable register circuit, a latch circuit, a core circuit, and a multiplexer circuit. The programmable register circuit and the latch circuit are located in a first power domain. When the first power domain is activated, the latch circuit is driven to read a set value to generate a latch signal. The core circuit and the multiplexer circuit are located in a second power domain. The activation timing of the first power domain is earlier than the activation timing of the second power domain. When the second power domain is activated, the multiplexer circuit receives the latch signal and outputs a function signal to the core circuit from the output end. The present invention can improve the efficiency and convenience of chip development, enhance the flexibility of chip function design, reduce the power consumption of the battery power supply, and increase the service life of the chip.

A semiconductor device includes a voltage supply circuit including a first pad to which a first source voltage that is generated from an external power source is applied and a second pad to which a second source voltage that is generated from the external power source is applied and configured to generate an internal voltage based on at least one of the first source voltage and the second source voltage and an internal voltage supply circuit configured to generate the internal voltage by supplying less than all of the second source voltage to the first source voltage when a level of the second source voltage is a set voltage level or higher, when generating the internal voltage based on the first source voltage.

A system includes a measuring device, a processing device and a signal generating device. The measuring device is configured to measure a voltage difference between a first node and a second node. The processing device is coupled between the first node and the second node. The signal generating device is configured to provide a first clock signal to the processing device to adjust the voltage difference, configured to generate the first clock signal according to a first enable signal and a second clock signal, and configured to align an edge of the first enable signal with an edge of the second clock signal. A method and a device are also disclosed herein.