1147results about "Power reduction by control/clock signal" patented technology

A semiconductor circuit or a MOS-DRAM wherein converting means is provided that converts substrate potential or body bias potential between two values for MOS-FETs in a logic circuit, memory cells, and operating circuit of the MOS-DRAM, thereby raising the threshold voltage of the MOS-FETs when in the standby state and lowering it when in active state. The converting means includes a level shift circuit and a switch circuit. The substrate potential or body bias potential is controlled only of the MOS-FETs which are nonconducting in the standby state; this configuration achieves a reduction in power consumption associated with the potential switching. Furthermore, in a structure where MOS-FETs of the same conductivity type are formed adjacent to each other, MOS-FETs of SOI structure are preferable for better results.

In a semiconductor integrated circuit, a control transistor 4 and a potential clamp circuit 9 are arranged between a power supply line 2 and a virtual power supply line 3. Even in a sleeve mode where the control transistor 4 is turned off, the potential clamp circuit 9-1 clamps the virtual power supply line 3 at a certain potential to hold a potential state (high level or low level) of each node of a logical circuit. At this time, each FET forming the logical circuit is applied with a back bias so that a threshold voltage Vt becomes higher than that in an active mode. Therefore, a leakage current can be decreased. In the semiconductor integrated circuit, the threshold voltage Vt of the control transistor 4 can be selected to be equal to that of one FET of the complementary FET forming the logical circuit. Therefore, the layout area and the number of manufacturing steps can be reduced.

A logic gate is constructed of an insulated gate field effect transistor (MIS transistor) having a thin gate insulation film. An operation power supply line to the logic gate is provided with an MIS transistor having a thick gate insulation film for switching the supply and stop of an operation power source voltage. A voltage of the gate of the power source switching transistor is made changing in an amplitude greater than an amplitude of an input and an output signal to the logic gate. Current consumption in a semiconductor device configured of MIS transistor of a thin gate insulation film can be reduced and an power source voltage thereof can be stabilized.

In a logic circuit where clock gating is performed, the standby power is reduced or malfunction is suppressed. The logic circuit includes a transistor which is in an off state where a potential difference exists between a source terminal and a drain terminal over a period during which a clock signal is not supplied. A channel formation region of the transistor is formed using an oxide semiconductor in which the hydrogen concentration is reduced. Specifically, the hydrogen concentration of the oxide semiconductor is 5x10¹⁹ (atoms/cm³) or lower. Thus, leakage current of the transistor can be reduced. As a result, in the logic circuit, reduction in standby power and suppression of malfunction can be achieved.

A method extends a clock-gating technique to provide a sleep signal for controlling switch circuits that reduce active leakage power. Using this extension of the clock-gating technique, fine-grained power-gating is achieved. The method automatically identifies, at an RTL or a gate level, the logic circuits that can be power-gated. The method of the present invention derives a sleep signal for fine-grained power-gating that may be applicable to both time-critical and non-time-critical designs.

Integrated circuit standby power consumption may be reduced using a reverse-bias transistor control arrangement that reduces transistor leakage current. Integrated circuit transistors may be turned off using a reverse bias voltage rather than a ground voltage. A charge pump circuit on the integrated circuit may be used to generate the reverse bias voltage. The reverse bias voltage may also be provided from an external source. The integrated circuit may be a programmable logic device in which logic is configured by providing programming data to configuration cells. The configuration cells may be used to apply either a positive power supply voltage to a given transistor to turn that transistor on or to provide the reverse bias voltage to that transistor to turn that transistor off.

An object of the present invention is to provide a technique of reducing the leakage current of a drive circuit for driving a circuit that must retain a potential (or information) when in its standby state. A semiconductor integrated circuit device of the present invention includes a drive circuit for driving a circuit block. This drive circuit is made up of a double gate transistor with gates having different gate oxide film thicknesses. When the circuit block is in its standby state, the gate of the double gate transistor having a thinner gate oxide film is turned off and that having a thicker gate oxide film is turned on. This arrangement allows a reduction in the leakage currents of both the circuit block and the drive circuit while allowing the drive circuit to deliver or cut off power to the circuit block.

High-speed and low-power consumption CMOS receivers using adaptively-regulated power supply and pseudo differential digital logic to: 1) reduce the power consumption of the transceiver; and, 2) increase the power supply rejection (PSR) during processing the data.

An adaptive supply voltage and body bias apparatus includes a master controller including an operation state value. The apparatus and method includes a dynamic voltage supplier coupled to the master controller operative to receive a supply voltage indicator. The apparatus and method includes an adaptive body biaser coupled to the master controller operative to receive a body bias indicator. Furthermore, the apparatus and method includes a plurality of computing devices each having one of a plurality of threshold voltages. The plurality of computing devices are operative to receive the supply voltage from the dynamic voltage supplier and a bias voltage from the adaptive body biaser for optimized power supply in conjunction with reduction of power leakage in view of the varying threshold voltage of the computing devices.

A semiconductor integrated circuit wherein the circuit area can be minimized, and defects can be detected reliably during a standby status while maintaining the reliability of a gate oxide film. Switching circuit 20 is provided between logic circuit 10 and source voltage V_dd supply terminal. While in an operating status, 0 V voltage is applied to the gate of transistor MP0 of switching circuit 20, and bias voltage V_B equal to or slightly lower than source voltage V_dd is applied to its channel region in order to reduce the threshold voltage of transistor MP0 and increase its current driving capability. While in a standby status, a voltage equal to source voltage V_dd is applied to the gate of transistor MP0, a voltage lower than the source voltage is applied to the source, and bulk bias voltage V_B equal to or higher than source voltage V_dd is applied to the channel region in order to minimize the drain current of transistor MP0, so that current path of logic circuit 10 is cut off, and the occurrence of leakage current is suppressed.

An integrated circuit (100) includes a first input (108) to receive a first operating voltage Vcc and a second input (110) to receive a second operating voltage Vss. Operating circuitry (102) of the integrated circuit is coupled to the first input to power the operating circuitry. A transistor (104) is coupled between the second input and the operating circuitry to selectively provide the second operating voltage to the operating circuitry of the integrated circuit. The well containing the transistor is biased to provide a reverse body effect and reduce the threshold voltage of the transistor to allow operation at very low Vcc.

A clock architecture for a Structured ASIC chip, manufactured using a CMOS process is shown. A via-configurable logic block (VCLB) architecture in the Structured ASIC has a core region containing memory and logic cells arranged in columns that are supplied by a clock network having a global clock network tree and a low-level clock mesh to distribute the global clock signal in a repeating pattern. The clock mesh has a fishbone configuration in outline and allows for scalable expansion of the clock network. In one embodiment 36 global clocks may be provided to the Structured ASIC, with four clocks per logic cell. The VCLB Structured ASIC chip is manufactured on a 28 nm CMOS process lithographic node, having several metal layers but preferably is programmable on a single via layer.

To minimize static leakage of an integrated circuit, a charge pump generates a negative voltage to be applied to a “sleep” transistor cascaded to a logic gate of the integrated circuit. An adaptive leakage controller determines continuously or periodically whether to adjust the negative voltage to minimize the static leakage. A negative voltage regulator adjusts the negative voltage depending on the determination. Some embodiments determine whether to adjust the negative voltage by monitoring one or more parameters of the sleep transistor. Some embodiments determine whether to adjust the negative voltage by monitoring one or more parameters of an emulated sleep transistor.

The present invention provides a power gating structure having data retention and intermediate modes and able to operate under multiple modes. A conventional power gating structure has only turn-on and turn-off functions, and is used to suppress a leakage current problem which has become more and more serious in advance manufacture processes, under a turn-off mode. However, in a memory circuit, such as latch, register and SRAM, when the power gate is turned off, a new power gating structure is required for data retention. The power gating structure of the present invention can be set into one of 4 different operational modes: a data retention mode for maintaining the static noise margin of the memory, an intermediate mode for reducing the interference on ground and power levels, an active mode used when the circuit operates in normal condition, and a standby mode used when the circuit does not operate.

A power supply detection circuit biased by at least two power supply voltages for controlling a signal driver circuit. Upstream and downstream amplifiers, powered by upstream and downstream power supply voltages, respectively, process an original control signal to produce a differential signal via output signal electrodes. Capacitances coupling respective ones of the output signal electrodes to the downstream power supply voltage and the circuit reference potential discharge and charge respective ones of the output signal electrodes in relation to initial receptions of the upstream and downstream power supply voltages and original control signal, following which voltage clamp circuitry maintains such discharged and charged states pending reception of the original control signal in a predetermined state.

In a low power consumption mode in which prior data is retained upon power shutdown, the return speed thereof is increased. While use of an existent data retaining flip-flop may be considered, this is not preferred since it increases area overhead such as enlargement of the size of a cell. A power line for data retention for power shutdown is formed with wirings finer than a usual main power line. Preferably, power lines for a data retention circuit are considered as signal lines and wired by automatic placing and mounting. For this purpose, terminals for the power line for data retention are previously designed by providing the terminals therefor for the cell in the same manner as in the existent signal lines. Additional layout for power lines is no longer necessary for the cell, which enables a decrease in the area and design by an existent placing and routing tool.

A domino logic circuit is configured to reduce power consumption. In a first embodiment, a sleep switch grounds the dynamic node during sleep mode. In a second embodiment, a low-swing circuit at the output reduces the output and keeper transistor gate voltage swings. A third embodiment combines those two techniques.

System and method for providing power to circuitry while avoiding a large transient current. A preferred embodiment comprises a distributed switch (such as switch arrangement 400) with a plurality of switches (such as switch 405) coupling a power supply to the circuitry. Each switch is individually controlled by a control signal and is turned on sequentially. Also coupled to each switch is a pre-driver circuit (such as pre-driver circuit 410). The pre-driver circuit comprises a potential adjust circuit (such as potential adjust circuit 505) that rapidly adjusts a voltage potential at the switch and a rate adjust circuit (such as the rate adjust circuit 520) that accelerates the power ramp-up across the switch once transient currents are no longer a concern. Adjusting the voltage potential so that the switch operates in a saturation mode increases an effective capacitance across the switch and thereby retarding the power ramp-up across the switch.

An integrated circuit device comprising at least one signal processing module and a power gating control module arranged to control gating of at least one power supply to at least a part of the at least one signal processing module. The power gating control module is arranged to receive at least one operating parameter; configure at least one power gating setting of the power gating control module based at least partly on the at least one received operating parameter; and apply power gating for at least part of the at least one signal processing module in accordance with the at least one configured power gating setting.