187results about "Power reduction by control/clock signal" patented technology

Some embodiments include apparatuses and methods using a supply node to receive a die voltage; a delay line to stretch and squish a first clock signal in response to changes in the die voltage to generate a second clock signal; a frequency clamp circuit to receive the second clock signal and generate a third clock signal that is clamped below a frequency; and a squash controller to squash the third clock signal when the die voltage crosses at least one of a first threshold and a second threshold.

Various example embodiments for supporting power optimizations for electronic circuits are presented. Various example embodiments for supporting power optimizations for electronic circuits may be configured to support power optimizations for a block of an electronic circuit. Various example embodiments for supporting power optimizations for a block of an electronic circuit may be configured to support a reduction in power consumption by a clock distribution tree of the block of the electronic circuit. Various example embodiments for supporting a reduction in power consumption by a clock distribution tree of a block of an electronic circuit may be configured to reduce power consumption by the clock distribution tree of the block of the electronic circuit by supporting root clock throttling for the block of the electronic circuit, based on a workload on the block of the electronic circuit, to reduce power consumption by the clock distribution tree of the block of the electronic circuit.

A pipeline circuit and a pipeline operating method are provided. The pipeline circuit includes a gating circuit that is configured to receive an input signal at an input end and selectively output the input signal as an output signal at an output end. In a first mode, the gating circuit receives the input signal that has been gated to output as the output signal. In a second mode, the gating circuit receives the input signal to output as the output signal.

A semiconductor device includes a retention circuit configured to retain a data value during a power gating operation, a non-retention circuit configured not to retain a data value during the power gating operation, a clock management unit (CMU) configured to provide a first operation clock to the retention circuit and provide a second operation clock to the non-retention circuit, and a power management unit (PMU) configured to provide a reference clock used to generate the first and second operation clocks to the CMU, generate a first isolation signal to permit a first signal to be output from the CMU, and generate a second isolation signal to permit a second signal to be output from the retention circuit and to permit a third signal to be output from the non-retention circuit.

Certain aspects of the present disclosure are directed towards techniques for power management. The techniques provide an optimal staggering delay time between transmission of enable signals to power switches coupled (e.g., electrically coupled) to logic circuits and a power source. The optimal staggering delay time may allow enabling or turning on of the power switches in a staggered, sequential fashion while reducing power up latency of the logic circuits.

A system includes a first sense amplifier having a first data input, a second data input, a clock input configured to receive a first clock signal, a first output, and a second output. The system also includes a second sense amplifier having a first data input, a second data input, a clock input configured to receive a second clock signal, a first output, and a second output. The first data input of the second sense amplifier is coupled to the first data input of the first sense amplifier, and the second data input of the second sense amplifier is coupled to the second data input of the first sense amplifier. The system also includes a set-reset (S-R) latch coupled to the first output and the second output of the first sense amplifier, and coupled to the first output and the second output of the second sense amplifier.

Technologies and implementations for a wake-up circuit. The wake-up circuit may be configured to reduce a peak value of current draw during waking up of an electronic device. The reduction of the peak value of current draw facilitates a reduction of electrical burden on various components of related circuit. Managing wake-up of circuits may include managing wake up of memory.

A system includes a first sense amplifier having a first data input, a second data input, a clock input configured to receive a first clock signal, a first output, and a second output. The system also includes a second sense amplifier having a first data input, a second data input, a clock input configured to receive a second clock signal, a first output, and a second output. The first data input of the second sense amplifier is coupled to the first data input of the first sense amplifier, and the second data input of the second sense amplifier is coupled to the second data input of the first sense amplifier. The system also includes a set-reset (S-R) latch coupled to the first output and the second output of the first sense amplifier, and coupled to the first output and the second output of the second sense amplifier.

A compute-in-memory (CIM) system includes a first leader-follower (L / F) flip-flop (FF), a suspender unit and a multiplication unit. The first L / F FF is configured to receive a data signal. The first L / F FF includes: a first leader FF configured to receive the data signal and a first follower FF configured to generate a signal first_Q_follow that represents a output signal of the first L / F FF. The multiplication unit is configured to receive a weight signal W and the signal first_Q_follow and generate a first product signal. The suspender unit is configured, during a given cycle of the first clock signal, detect that a first scenario is true in which all bits b(k) of the data signal equal logical zero and accordingly suppress latching from being performed by the first L / F FF, and control the multiplication unit to generate the first product signal as being equal to logical zero.

A system includes a measuring device, a processing device and a signal generating device. The measuring device is configured to measure a voltage difference between a first node and a second node. The processing device is coupled between the first node and the second node. The signal generating device is configured to provide a first clock signal to the processing device to adjust the voltage difference, configured to generate the first clock signal according to a first enable signal and a second clock signal, and configured to align an edge of the first enable signal with an edge of the second clock signal. A method and a device are also disclosed herein.

A level shift circuit (1) includes first to fourth P-type transistors, first and second N-type transistors, and a pull-up circuit (30). The first N-type transistor and the first P-type transistor are disposed between the input node and the output node, and the second P-type transistor is disposed between the first power supply and the output node. The second N-type transistor and the third P-type transistor are arranged between the inverted input node and the inverted output node, and the fourth P-type transistor is arranged between the first power supply and the inverted output node. The pull-up circuit (30) is configured to pull up the second node to the third power supply when the first node is converted from the high level to the low level, and pull up the first node to the third power supply when the second node is converted from the high level to the low level.

The invention discloses a circuit which comprises a logic circuit and a power switch module, and the power switch module comprises a plurality of switches, a voltage detection circuit and a control circuit. Each switch of the plurality of switches comprises a control end, a first end and a second end, the first end is coupled to a supply voltage, and the second end is coupled to the logic circuit; and the plurality of switches comprise a first switch and a plurality of second switches, and the control end of the first switch receives a power supply enabling signal. The voltage detection circuit is used for detecting whether a voltage of the second end of the first switch is higher than a reference voltage so as to generate a detection result. The control circuit is used for generating an output power enable signal to the plurality of second switches according to the detection result.

A semiconductor device includes a first regulator electrically connected to a first power supply line, a second regulator electrically connected to a second power supply line, a control circuit configured to control the first and second regulators, and at least two functional circuit modules electrically connectable to the first power supply line and the second power supply line. When all the functional circuit modules are set to a power-on state (active mode), the control circuit controls the first regulator to output a voltage to the first power supply line and the second regulator to output a voltage to the second power supply line, and when some functional circuit modules are set to a power-off state (standby mode), the control circuit controls the first regulator to output a voltage to the first power supply line and the second regulator not to output a voltage to the second power supply line.

A circuit includes a power management circuit configured to receive a first or second control signal, and to supply a first, second or third supply voltage. The power management circuit includes a first level shifter circuit, a first header circuit and a latch circuit. The first level shifter circuit is configured to generate a fourth control signal in response to a fifth control signal. The fourth control signal is a level shifted version of the fifth control signal. The first header circuit is configured to supply a first supply voltage of a first voltage supply to a first node in response to the first control signal, or a second supply voltage of a second voltage supply to a second node in response to a first level shifted signal. The latch circuit is configured to generate a first output control signal in response to the first and the fourth control signal.

The present invention discloses a chip structure and a chip function control method, wherein the chip structure includes a programmable register circuit, a latch circuit, a core circuit, and a multiplexer circuit. The programmable register circuit and the latch circuit are located in a first power domain. When the first power domain is activated, the latch circuit is driven to read a set value to generate a latch signal. The core circuit and the multiplexer circuit are located in a second power domain. The activation timing of the first power domain is earlier than the activation timing of the second power domain. When the second power domain is activated, the multiplexer circuit receives the latch signal and outputs a function signal to the core circuit from the output end. The present invention can improve the efficiency and convenience of chip development, enhance the flexibility of chip function design, reduce the power consumption of the battery power supply, and increase the service life of the chip.

A semiconductor device includes a voltage supply circuit including a first pad to which a first source voltage that is generated from an external power source is applied and a second pad to which a second source voltage that is generated from the external power source is applied and configured to generate an internal voltage based on at least one of the first source voltage and the second source voltage and an internal voltage supply circuit configured to generate the internal voltage by supplying less than all of the second source voltage to the first source voltage when a level of the second source voltage is a set voltage level or higher, when generating the internal voltage based on the first source voltage.

A system includes a measuring device, a processing device and a signal generating device. The measuring device is configured to measure a voltage difference between a first node and a second node. The processing device is coupled between the first node and the second node. The signal generating device is configured to provide a first clock signal to the processing device to adjust the voltage difference, configured to generate the first clock signal according to a first enable signal and a second clock signal, and configured to align an edge of the first enable signal with an edge of the second clock signal. A method and a device are also disclosed herein.

A control apparatus, a control system, and a carrier are provided, and belong to the field of electronic technologies. A first isolation unit in the control system can receive a first level signal output by a first control unit and a second level signal output by a first controlled unit, and can output a first control signal to the first controlled unit. The first controlled unit can output the second level signal to the first isolation unit under an action of the first control signal. Based on this, even if the first control unit is faulty, the first isolation unit can continue to output the first control signal to the first controlled unit based on the second level signal output by the first controlled unit. This implements isolation of a fault of the first control unit, and effectively improves reliability of the control system.

A power gating circuit including: a power gating transistor; a gate bias generating circuit configured to provide a gate bias control signal to the gate of the power gating transistor; and a body bias generating circuit configured to provide a body bias control signal to the body of the power gating transistor, wherein when the power gating transistor is turned on, the gate bias generating circuit provides the gate bias control signal having a positive voltage level and the body bias generating circuit provides the body bias control signal having the positive voltage level, and when the power gating transistor is turned off, the gate bias generating circuit provides the gate bias control signal having a ground voltage level or a negative voltage level, and the body bias generating circuit provides the body bias control signal having the ground voltage level or the negative voltage level.

The present subject matter relates to an electronic system comprising gated circuitry, a first regulator circuit directly coupled to the gated circuitry, always-on circuitry, a second regulator circuit directly coupled to the always-on circuitry, and a switch circuit coupled between an output of the first regulator circuit and an output of the second regulator circuit. The always-on circuitry includes control logic configured to activate the second regulator circuit and deactivate the first regulator circuit and the switch circuit in a sleep mode and activate the first regulator circuit and the switch circuit in an active mode.

A semiconductor device includes a retention circuit configured to retain a data value during a power gating operation, a non-retention circuit configured not to retain a data value during the power gating operation, a clock management unit (CMU) configured to provide a first operation clock to the retention circuit and provide a second operation clock to the non-retention circuit, and a power management unit (PMU) configured to provide a reference clock used to generate the first and second operation clocks to the CMU, generate a first isolation signal to permit a first signal to be output from the CMU, and generate a second isolation signal to permit a second signal to be output from the retention circuit and to permit a third signal to be output from the non-retention circuit.

A buffer circuit includes a power control circuit, an inverting circuit, and a voltage adjustment circuit. The power control circuit is configured to provide voltages based on an input signal and a mode signal, and the inverting circuit is configured to receive and invert the voltages to generate an output signal. The voltage adjustment circuit is configured to adjust voltage levels based on the mode signal and the output signal.

The present disclosure relates to a circuit unit, a logic circuit, a processor, and a computing apparatus. A circuit unit is provided, including: an output terminal (OUT); an output stage (105), configured to provide an output signal to the output terminal; a first node (A), to which an input of the output stage is connected; and a feedback stage (107) that receives the output signal at the output terminal and selectively provides feedback to the node. A logic circuit is further provided, including an input stage that receives a signal input, and the circuit unit. The first node receives a signal based on an output of the input stage.

An apparatus, including: a current generating circuit configured to generate a first current; a first current mirror including a first field effect transistor (FET) and a second FET, wherein the first FET is coupled to the current generating circuit such that the first current flows through the first FET; a first switching device coupled between a gate of the first FET and a gate of the second FET; and a capacitor coupled between a first voltage rail and the gate of the second FET.

The present disclosure relates to a power domain management circuit and a system on chip. The power domain management circuit includes: an enable unit, configured to generate an enable signal with a first preset level in a case of receiving an isolation set signal, or to generate an enable signal with a second preset level in a case of receiving a reset indication signal; and a clamping unit, electrically connected to the enable unit, and configured to clamp an initial signal transmitted from a first power domain to a second power domain to generate a target signal with a third preset level in a case of receiving the enable signal with the first preset level, or to skip clamping the initial signal to generate a target signal with a level that varies with a level of the initial signal in a case of receiving the enable signal with the second preset level.

The semiconductor device of the embodiment includes a circuit block and a clock circuit that provides a clock signal to the circuit block at a specific time. The clock circuit includes: an output circuit that outputs a clock signal to the circuit block; and a control circuit that controls the timing of the clock signal output by the output circuit. The threshold voltage of the transistor in the output circuit that at least uses the clock signal as an input / output signal is a first threshold voltage, and the threshold voltage of the transistor constituting the control circuit is a second threshold voltage that is higher than the first threshold voltage.

The present invention provides an electronic device. The electronic device includes a core circuit and a detection circuit. The core circuit receives a first clock signal and a second clock signal, respectively. The core circuit generates a first operating state and a second operating state based on the first clock signal and the second clock signal, respectively. The detection circuit detects the relationship between the first operating state and the second operating state and generates a reset signal. The reset signal is used to reset the relationship between the first operating state and the second operating state to an initial corresponding relationship and eliminate the effects of electromagnetic interference on the electronic device.

A controller for a switching mode power converter (SMPC) module for use in a multi-phase SCMP is disclosed, comprising: a signal generator configured to generate a periodic signal and a clock, each having a frequency and a signal phase, for controlling the switching mode power converter module; a first clock input and a second clock input, the first clock input and the second clock input being configured to receive respective first and second clock signals having the frequency and respective first and second phases from an adjacent controller; and wherein the signal generator includes a phase adjustment circuit configured to adjust the phase of the periodic signal to be equidistant from the first and second phases, wherein the phase adjustment circuit determines an error signal based on an offset between the phase and a midpoint between the first and second phases, and a feedback circuit configured to adjust the phase based on the error signal.

Disclosed is a semiconductor integrated circuit comprising a master chip including a first buffer circuit coupled to a first power line that is supplied with a first voltage and a first supply circuit that supplies a second voltage, having a lower voltage level than the first voltage, to a first through line in response to a control signal, and a slave chip, coupled to the first through line, including a second buffer circuit coupled to a second power line supplied with the second voltage and a second supply circuit that supplies the second voltage to a second through line in response to the control signal, which indicates whether the master chip and the slave chip are stacked.

An apparatus, including: a clock gating circuit, CGC, including: a clock gating device (920) configured to selectively gate / pass a selected clock signal based on an enable signal to generate an output clock signal; and a clock selection circuit (930) configured to select a non- complementary clock signal or a complementary clock signal to generate the selected clock signal based on the output clock signal and the non-complementary clock signal or the complementary clock signal.