36 results about "Logical circuit" patented technology

The invention discloses a quantum circuit conversion method and system, electronic equipment and a storage medium, and relates to the technical field of quantum circuit conversion, and the method comprises the steps: extracting a feature vector of a logic quantum circuit based on initial quantum bit mapping; the feature vector is input into a pre-trained decision tree, recommendation parameters of a line conversion algorithm are obtained, the decision tree is constructed by a training set, and the feature vector of each sample corresponds to the optimal parameter of the decision tree, namely the parameter with the minimum number of physical line gates; and configuring a line conversion algorithm by using recommended parameters, converting a logic line into a physical line, and ensuring that all two quantum bit gates meet quantum computer connected graph constraints and are equivalent in function. According to the method, adaptive parameter configuration can be achieved through the feature vectors and the decision tree, the line conversion quality is effectively improved, the number of physical line gates is remarkably reduced, and the quantum program execution efficiency is improved on the premise that function equivalence and connectivity are guaranteed.

The invention relates to a quantum bit mapping method based on a cross-graph attention mechanism and a universal compiler, and the training method of a quantum bit mapping model based on the cross-graph attention mechanism comprises the steps: executing an intra-graph adjacency aggregation operation according to hardware node information in a hardware topological graph, and obtaining an updated hardware node vector; executing intra-graph adjacency aggregation operation according to logic node information in the quantum logic circuit to obtain an updated logic node vector; calculating the matching degree of the updated hardware node vector and the logic node vector, and performing cross-graph attention updating on the logic node vector and the hardware node vector based on the matching degree; inputting the hardware node vector and the logic node vector after pooling processing into a quantum bit mapping model to be trained, and outputting a mapping quality prediction value; and constructing a loss function based on the mapping quality true value and the mapping quality predicted value, and training a graph neural network model by adopting a gradient descent method. According to the method, the optimal path combination can be automatically selected to reduce the calculation complexity.

The invention discloses a digital-to-analog converter interface circuit supporting LVDS / CMOS dual-mode input. The digital-to-analog converter interface circuit comprises an ESD protection circuit, a DEMUX multiplexer, an MUX multiplexer, an LVDS receiver, an inverter chain and a digital logic circuit. The output end of the ESD protection circuit is connected with the DEMUX demultiplexer; the digital logic circuit is used for generating a synchronous control signal according to an external mode switching signal and coordinating the working state of each module; the DEMUX demultiplexer distributes an input signal output by the ESD protection circuit to a corresponding signal processing path under the action of a control signal output by the digital logic circuit; the LVDS receiver receives the LVDS signal, converts the LVDS signal into a single-ended CMOS signal, and outputs the single-ended CMOS signal to the MUX multiplexer; the inverter chain is used for receiving a CMOS signal; and the MUX multiplexer outputs a control signal according to the digital logic circuit, so that one of the two paths of input signals is selected to be output to the DAC core circuit. According to the invention, LVDS / CMOS dual-mode input is efficiently supported in a single chip, and meanwhile, the requirements of high speed, low power consumption and time sequence consistency are met.

This invention discloses a method and system for extracting and associating physical and logical circuits in a DC control and protection system. The method includes: constructing physical circuits based on engineering design drawings and optical cable documents; parsing the graphical program of the DC control and protection device to extract communication-related symbol information and constructing logical circuits; and representing the circuit data using a directed graph to associate the physical and logical circuits. This invention can efficiently realize the automatic construction and association of communication circuits, improving the efficiency of communication circuit diagnosis, debugging, and operation and maintenance in ultra-high voltage DC control and protection systems.

The invention provides a series battery management system, a management method, a communication method and a medium, the system correspondingly configures a battery controller for each battery in series batteries, and the battery controllers are connected in series through communication links and communicate with an MCU controller; the MCU controller and the battery controller both work in a low-voltage power supply domain, a non-isolated interface is adopted for data transmission, and the method comprises the following steps: acquiring electric quantity information of each battery, and determining a working mode of the corresponding battery; the switch state in the battery controller is adjusted to realize battery access switching, and power supply of the level converter and the digital logic circuit is ensured; meanwhile, self-adaptive level conversion is carried out through a level converter according to the potential difference between the adjacent levels of battery controllers. All chips in the system work in a low-voltage power supply domain, the response speed of the system is high, the system is not limited by the number of series battery packs, and the system has good expansibility and is suitable for battery management in the fields of electric automobiles, energy storage and the like.

The application provides a method for generative heterogeneous logic optimization based on critical path partitioning. The method includes: converting a digital logic circuit into an And-Inverter Graph (AIG) format; partitioning the AIG using reinforcement learning based on critical path information of the circuit to obtain critical-path-aware partitions so as to reduce influence of critical path changes brought by the partitioning on timing performance; respectively and automatically exploring an optimized structure and synthesis flow suitable for each partition using the reinforcement learning method; selecting optimization operators for various structures using a reinforcement learning agent guided by area-delay metrics and optimizing each partition; and merging the optimized partitions in the AIG format. In the application, the digital logic circuit is partitioned based on critical paths, and reinforcement learning is used to explore and optimize structures and strategies based on area and delay.

Device comprising: logic, part of which is implemented in hardware, the logic comprising: a content recording device (1523), wherein the content recording device (1523) receives a first signal from a capture device (120), the first signal including an indication of captured content; a metadata recording device (1524) receiving a second signal from one or more sensors, the second signal including an indication of content metadata (156), the content metadata (156) indicating a relationship between the captured content (154) and a cooperating capture device; and a content sender (1525), wherein the content sender (1525) causes an information element (158) to be sent to a content sink device, the information element (158) including an indication of the captured content (154) and the content metadata (156).

A circuit is configured for transforming input data in a neural network to output data. The circuit includes inter-connected arithmetic logic circuits and a control circuit sending a sequence of configuration settings to configure the inter-connected arithmetic logic circuits over one or more cycles. The inter-connected arithmetic logic circuits jointly perform at least one of a softmax or a sigmoidal linear unit (SiLU) operation on the input data. The inter-connected arithmetic logic circuits include an exponential circuit generating a first exponential of a fractional part of an input and a second exponential of an integer part of the input, a multiplier circuit multiplying the first exponential and the second exponential into a first intermediate variable, an accumulator circuit summing multiple intermediate variables relating to exponentials of multiple inputs, and a reciprocal circuit generating a reciprocal of a second intermediate variable that is input to the reciprocal circuit.

A system, method and apparatus for executing a sequence analysis pipeline on genetic sequence data includes a integrated circuit formed of a set of hardwired digital logic circuits that are interconnected by physical electrical interconnects. One of the physical electrical interconnects forms an input to the integrated circuit connected with an electronic data source for receiving reads of genomic data. The hardwired digital logic circuits are arranged as a set of processing engines, each processing engine being formed of a subset of the hardwired digital logic circuits to perform one or more steps in the sequence analysis pipeline on the reads of genomic data. Each subset of the hardwired digital logic circuits is formed in a wired configuration to perform the one or more steps in the sequence analysis pipeline.

The invention relates to a chip system, a startup and shutdown manager, a power supply circuit and electronic equipment, and relates to the technical field of terminals. The chip system comprises a startup and shutdown manager, a power supply circuit and a data processing system, wherein the startup and shutdown manager comprises a digital logic circuit. The digital logic circuit is used for responding to the input of the device button and sending a first pulse signal to the power supply circuit through the enabling output end, and the first pulse signal is used for controlling the power supply circuit to supply power to the data processing system. In response to a constant electric signal received by the feedback controlled end from the feedback output end of the power supply circuit or the feedback output end of the data processing system, a first power supply signal is sent to the power supply circuit through the enabling output end, and the first power supply signal is used for controlling the power supply circuit to continuously supply power to the data processing system. Therefore, the cost can be reduced.

The invention relates to a safety module used in civil and military aircraft, in which the control of power layers is carried out via a safety analysis algorithm on an internal programmable digital logic circuit, where the temperature, current, and voltage values of the hardware are monitored with a contactless and integrated sensor in order to detect situations of overheating, excessive power consumption, overvoltage, spark, and gas – smoke emission.

The application discloses a one-time fuse trimming circuit based on an SPI communication protocol and belongs to the field of electronic circuits, comprising an SPI communication module and a fuse burning and writing digital logic circuit; the SPI communication module comprises a normal mode and a fuse mode; the normal mode comprises data bits, control bits and redundant bits; the fuse mode comprises a fuse address bit, a fuse control bit, a fuse mode bit, a fuse flag bit and a fuse enable bit; the fuse burning and writing digital logic circuit comprises a FIFO unit, an interlocking unit, a rising edge trigger unit and a fuse burning and writing execution unit. The application reuses the general SPI communication protocol, can temporarily reuse the SPI channel to burn and write the fuse according to a special method, can burn and break the end flag fuse after burning and writing the fuse, permanently closes the burning and writing path, is safe and reliable, will not appear misoperation, and saves a large amount of interface resources.

The utility model discloses a circuit structure of an ultrasonic flowmeter, which comprises a digital logic circuit, a digital-analog mixed signal circuit and an analog signal circuit, the digital-analog mixed signal circuit is connected with the digital logic circuit and the analog signal circuit, the digital logic circuit is connected with an ultrasonic transmitting transducer, and the analog signal circuit is connected with an ultrasonic receiving transducer; power line cathodes of the digital logic circuit, the digital-analog mixed signal circuit and the analog signal circuit are gathered in the PCB and are connected to the same grounding node to form a star-shaped grounding structure; the grounding node is electrically connected with a ground wire. According to the utility model, power supplies and ground wires of different functional modules are subjected to single-point grounding, so that the noise of the digital logic circuit can be limited within a specific circuit range, and the quality of ultrasonic echo signals can be remarkably improved.

The application relates to the technical field of quantum computing, and discloses a quantum circuit mapping method and system based on deep reinforcement learning. The method is characterized in that: the original logical quantum circuit is parsed and simplified into a ZX-graph, and then the ZX-graph is converted into a quantum circuit dependency graph, so that the calculation complexity is significantly reduced, the mapping task of a large-scale quantum circuit can be processed within a reasonable time, a Markov decision process environment is constructed by using the quantum circuit dependency graph and quantum chip parameters, a deep reinforcement learning intelligent agent is trained by using the Markov decision process environment, an optimal mapping strategy optimization model is obtained, and the optimal mapping strategy optimization model can output the corresponding optimal quantum bit mapping scheme of the current logical circuit to be mapped, so that the quantum chip of various topological structures can be adapted, and the generalization ability and adaptability of the mapping scheme are improved.

In some examples, a circuit includes a first transistor (312), a second transistor (314), a first resistor (318), and a digital logic circuit (106). The first transistor has a control terminal and first and second terminals. The second transistor has a control terminal and first and second terminals, the first terminal of the second transistor coupled to the second terminal of the first transistor. The first resistor has first and second terminals, the first terminal of the first resistor coupled to the control terminal of the second transistor, and the second terminal of the first resistor coupled to the first terminal of the second transistor. The digital logic circuit has an output terminal and first and second input terminals, the output terminal of the digital logic circuit coupled to the control terminal of the second transistor, the first input terminal of the digital logic circuit coupled to a data transmit input terminal (TXD) of the circuit, and the second input terminal of the digital logic circuit coupled to a data receive output terminal (RXD) of the circuit.

The application discloses a kind of based on deep learning's efficient simplified digital logic circuit method, system, electronic equipment and storage medium, comprising: constructing logic synthesis dataset, the logic synthesis dataset includes training set and test set, input data in the logic synthesis dataset is the circuit of RTL verilog description;Logic synthesis environment is constructed to input data is preprocessed, and efficient simplified digital logic circuit model based on deep learning is constructed;Efficient simplified digital logic circuit model based on deep learning is trained using the circuit of preprocessed training set, until efficient simplified digital logic circuit model converges;Using the efficient simplified digital logic circuit model based on deep learning that is trained, and logic optimization is carried out on test set, to test the logic optimization capability of efficient simplified digital logic circuit model.The application can efficiently optimize circuit, and its effect is better than the method of traditional node-by-node application single optimization algorithm.

The invention discloses an FPGA triple modular redundancy method and device based on a data area and electronic equipment, and relates to the technical field of digital system fault tolerance, and the method comprises the steps: abstracting a circuit netlist into a directed graph; specifying a reinforcement object; for each reinforcement object, starting from the reinforcement object, carrying out retrograde search traversal in the reverse direction of signal transmission, and combining data paths formed by found nodes and cross nodes into a data area of the reinforcement object; merging the data areas with the cross nodes; and performing triple modular redundancy on the basis of the merged data area. On the basis of the circuit netlist, the circuit netlist is abstracted into a digraph form, and triple modular redundancy design is performed in a targeted manner by searching for data paths, dividing data areas and finding out parts which have great influence on the sequential logic circuit, so that the overhead can be saved, and the security reinforcement effect can be improved.

The invention relates to a precision reconfigurable high-speed time domain analog-to-digital converter, which comprises a voltage-time converter used for converting a received input voltage signal into a time pulse signal so as to transmit the time pulse signal to a reconfigurable pipeline time-to-digital converter, and outputting a one-bit digital code to a digital logic circuit at the same time; the reconfigurable pipeline time-to-digital converter comprises n stages of pipelines, and the total effective stage number of the n stages of pipelines is controlled by a first configuration signal. The quantization precision of each level of assembly line is independently configured between 1.5 bits and 2 bits, and the n levels of assembly lines work in parallel in an odd-even assembly line level alternating mode; each stage of assembly line is quantized and generates a current stage of digital code, and the quantized residual time quantity is amplified as output and provided for the next stage of assembly line; and the digital logic circuit sums all the received digital codes into M-bit effective digital codes according to weights. The device can adapt to various high-speed application scenes with different precision requirements.

The application provides a method, device and storage medium for optimizing a digital logic circuit layout, comprising the following steps: determining a first layout of the digital logic circuit, wherein the first layout comprises a plurality of macro cells and a plurality of standard cells; determining a channel formed between adjacent macro cells; determining a target step parameter of the standard cell according to a position of the standard cell and the channel based on an optimization target of the digital logic circuit, wherein the optimization target comprises at least one of a line length target, a density target and a timing target; and adjusting the standard cell based on the target step parameter to optimize the layout of the digital logic circuit. The method provided by the application can realize automatic layout optimization of the digital logic circuit, reduce the influence of the channel on the layout optimization, and further improve the performance of the chip.

The invention discloses a method and system for efficiently simplifying a digital logic circuit based on deep learning, electronic equipment and a storage medium, and the method comprises the steps: constructing a logic comprehensive data set which comprises a training set and a test set, and the input data in the logic comprehensive data set is a circuit described by RTL verilog; constructing a logic comprehensive environment to pre-process input data, and constructing an efficient simplified digital logic circuit model based on deep learning; training an efficient simplified digital logic circuit model based on deep learning by using a circuit of the preprocessed training set until the efficient simplified digital logic circuit model converges; and performing logic optimization on the test set by using the trained efficient simplified digital logic circuit model based on deep learning so as to test the logic optimization capability of the efficient simplified digital logic circuit model. According to the method, the circuit can be efficiently optimized, and the effect of the method is better than that of a traditional method of applying a single optimization algorithm node by node.

Embodiments of a system, method and apparatus are described for reducing power consumption of a battery-powered electronic device. A hardware polling peripheral operates in conjunction with a CPU within the batten -powered electronic device. When the CPU enters a quiescent state in order to save power, the hardware polling peripheral begins the polling cycle that polls one or more I / O pins of the hardware polling peripheral to detect a change in state. Polling is controlled by hardware registers and digital logic circuits without the use of firmware. When the hardware polling peripheral determines that an I / O pin has changed state, it wakes the CPU from the quiescent state via an interrupt.

This invention provides a configurable hardware architecture and bit manipulation method based on Banyan networks, belonging to the fields of digital logic circuits and high-performance computing technology. The invention aims to solve the problems of high hardware overhead, high power consumption, and long latency caused by the need for separate hardware modules—a Banyan network and a barrel shifter—to achieve combined bit-gathering and cyclic shifting operations in existing technologies. The architecture of this invention includes a Banyan network switching module and a control signal generation module. The control signal generation module generates an offset prefix count by superimposing the cyclic shift amount *r* with the original prefix count based on a bit mask, and uses this count to generate control signals for each stage of the Banyan network via an LROTC circuit. Through innovative modifications to the Banyan network control logic, this invention enables a single network to simultaneously perform both advanced bit operations, bit-gathering and cyclic shifting. This invention offers significant advantages such as hardware resource savings, reduced power consumption, improved performance, flexible design, and easy expansion, and can be widely applied in processor design, cryptographic acceleration, digital signal processing, and other fields.

A spatial event map system including server-side data processor that maintains a spatial event map which locates events in a workspace. The spatial event map includes a log of events, entries in the log having a location of an object of the event in the workspace and a time. The system includes logic to send messages including a location of an object of the event in the workspace and a time of the event to client-side network nodes; and to receive messages identifying events that create or modify an object, and to add corresponding entries to the log of events. The events can include history events that are sent to the other client-side network nodes, and added to the log for the corresponding history events, and ephemeral events that are sent to other client-side network nodes without adding corresponding entries in the log.

This invention provides a series battery management system, management method, communication method, and medium. The system assigns a battery controller to each battery cell in the series battery pack. These battery controllers are connected in series via a communication link and communicate with an MCU controller. Both the MCU controller and the battery controllers operate in a low-voltage power domain and use a non-isolated interface for data transmission. The method includes acquiring the power information of each battery cell to determine its operating mode; adjusting the switching states in the battery controllers to achieve battery access switching and ensure power supply to the level converters and digital logic circuits; and simultaneously performing adaptive level conversion based on the potential difference between adjacent battery controllers using the level converters. In this invention, all chips operate in a low-voltage power domain, resulting in a fast system response speed. The system is not limited by the number of series battery packs and has good scalability, making it suitable for battery management in electric vehicles, energy storage, and other fields.

Methods and apparatus for Enhanced IO Interface for PLC program and program-suspend-resume operations. A NAND memory device includes blocks of single-level cell (SLC) memory and multi-level cell (MLC) memory storing n-bits per cell such as quad-level cell (QLC) or penta-level cell (PLC) memory. The NAND memory device further includes a plurality of page buffer latches and logic to copy data from a set of n SLC pages in a block of SLC memory into n respective page buffer latches and copy data from the respective page buffer latches to an MLC page (e.g., QLC or PLC page) in a block of MLC memory. These operations can be extended for NAND memory devices having multiple planes with blocks of SLC and QLC / PLC memory. QLC / PLC program and program-resume operations are supported with optional ECC correction operations.

Sets of digital samples associated with received wireless signals are received, each of the sets of digital samples corresponding to a particular RF path. The sets of digital samples are provided to a plurality of pipelines, each of the plurality of pipelines including a plurality of stages, each of the plurality of stages including one or more digital logic circuits. Sets of interconnect data are generated by the plurality of pipelines based on the sets of digital samples, the sets of interconnect data including at least one accumulating value. The sets of interconnect data are passed between adjacent pipelines of the plurality of pipelines along a direction. A result is generated by a last pipeline of the plurality of pipelines based on the at least one accumulating value.

The invention belongs to the technical field of power system automation, and particularly relates to an intelligent substation secondary circuit modeling method and a related device. The intelligent substation secondary circuit modeling method comprises the steps that based on constructed elements, the relation between the elements is defined in a hierarchical mode, and a model for fusing a physical circuit and a logic circuit is constructed and obtained and serves as a secondary circuit model; when the relation between the elements is defined in a hierarchical mode, the substation module serves as the root of the secondary loop model, the subnet module is arranged below the substation module, the secondary equipment modules are arranged below the subnet module, the secondary equipment modules are connected through the port module, and data interaction is carried out through the data set module. According to the method, the bidirectional fusion model of the physical loop and the logic loop is established, information inconsistency of the bidirectional relation is avoided, and the actual requirements of an existing intelligent substation can be met.

The present application provides a method, computer device, and storage medium for analyzing digital logic circuits. The method includes: obtaining a digital logic circuit to be analyzed; performing circuit grading using triggers of the digital logic circuit as nodes, and selecting a digital logic circuit between any two adjacent levels as a target circuit; wherein the target circuit includes at least one path, and the at least one path includes at least one combinational logic unit; determining a variable sequence of the target circuit, and based on the variable sequence, determining a first result of the at least one combinational logic unit according to a Boolean function; wherein the first result corresponds to the Boolean difference of the output of the at least one combinational logic unit with respect to the input; determining a target path in the at least one path, performing an ITE operation based on the first result corresponding to the target path; and determining an identification result of the target path based on the operation result.

A system, method and apparatus for executing a sequence analysis pipeline on genetic sequence data includes an integrated circuit formed of a set of hardwired digital logic circuits that are interconnected by physical electrical interconnects. One of the physical electrical interconnects forms an input to the integrated circuit connected with an electronic data source for receiving reads of genomic data. The hardwired digital logic circuits are arranged as a set of processing engines, each processing engine being formed of a subset of the hardwired digital logic circuits to perform one or more steps in the sequence analysis pipeline on the reads of genomic data. Each subset of the hardwired digital logic circuits is formed in a wired configuration to perform the one or more steps in the sequence analysis pipeline.