83 results about "Digital integrated circuits" patented technology

The invention discloses a code generation method and system based on multi-objective reinforcement learning, and belongs to the technical field of digital integrated circuit design, and the method comprises the following steps: S1, generating an SFT training data set; s2, generating an MORL data set; s3, performing supervision and fine tuning on the model by taking the SFT training data set as input, so that the model masters the basic RTL code generation capability; s4, taking the MORL data set as input to train the model after supervision and fine tuning in the S3, and realizing multi-objective optimization; and S5, according to a user demand, describing a multi-target constraint through vector rewards, screening non-dominated candidate codes by using Pareto optimization to obtain an optimal RTL code, and outputting the optimal RTL code, vector reward details and a PPA equilibrium curve. According to the method and the system, basic constraints are met, and meanwhile generation of RTL codes with PPA indexes capable of being customized according to requirements is achieved.

The invention relates to the field of function verification of digital integrated circuits, and discloses an atomic-scale computing chip verification method based on a UVM. The method comprises the following steps: firstly, building a UVM simulation verification platform comprising each core component; then, a software program is used for generating test excitation with physical significance, wherein the test excitation comprises information such as configuration, functional, pseudo potential and track files; then respectively inputting the test excitation into the established UVM verification platform and the software reference model; the UVM verification platform applies the test excitation to the to-be-tested design and outputs a calculation result; the reference model also correspondingly generates a reference result; and finally, comparing the output of the to-be-tested design with the output of the reference model, and verifying the correctness of the function of the atomic calculation chip through visual auxiliary analysis and quantitative error analysis. Through excitation generation based on physical constraints and an effective error evaluation method, the function verification problem of the atomic-scale computing chip can be solved.

This invention discloses a high-speed, high-precision voltage descent monitoring circuit, solving the problem of accurate and timely monitoring of voltage descent phenomena in large-scale integrated circuits, belonging to the fields of digital integrated circuit design and power management. This invention provides an optimized design method for ring oscillator point circuits, using standard cell type, threshold, drive capability, and power consumption as variables to find the ring oscillator circuit design with the highest voltage sensitivity, improving the resolution of the voltage descent monitoring circuit; it provides a one-fold, compact ring oscillator layout design to ensure load balance between nodes; it provides a Nyquist counter design to count the number of times nodes flip over a period of time, improving the voltage monitoring range and solving the metastable sampling problem of traditional counters; and it provides a high-speed voltage quantization circuit that processes coarse and fine quantization in parallel, improving the maximum sampling rate and quantization rate of the voltage descent monitoring circuit.

The application discloses a cross-clock domain register synchronization method and device. It relates to the technical field of digital integrated circuit design. The method comprises the following steps: when the target clock domain is unavailable, routing the bus read-write request to a shadow register array driven by a system clock, and writing a write transaction log into a log queue when the write transaction is completed, the write transaction log comprising a target address, write data and byte enable; when the target clock domain changes from unavailable to available and the log queue is not empty, setting the handshake signal of the bus interface to invalid, reading the write transaction log from the log queue according to the write sequence, and writing the write data into the target register through a byte mask circuit according to the target address in the write transaction log; when the target clock domain is available and the log queue is empty, routing the bus read-write request to the target register, and setting the handshake signal of the bus interface to valid. The method realizes register access integrity and sequential consistency in the target clock dynamic change scenario.

The application relates to an integrated circuit analysis method and device, computer equipment and a storage medium. The method comprises the following steps: acquiring a gate-level netlist corresponding to a digital integrated circuit included in a device to be measured, the gate-level netlist being used for describing a plurality of paths included in the digital integrated circuit and at least one logic gate included in a gate circuit on each path; acquiring path information of each path according to the gate-level netlist; calculating a delay increment of each path according to the path information and a preset device degradation model; calculating a failure time of each path according to the delay increment and a failure boundary condition, and taking a path corresponding to a minimum failure time as a critical failure path of the digital integrated circuit. Through the method, a critical failure path causing reliability degradation in an integrated circuit can be analyzed based on circuit load and timing requirements, so that the path is reinforced at an early design stage, and the reliability of the integrated circuit is improved.

The invention provides a processor synchronization system and electronic equipment, and relates to the field of digital integrated circuits, the processor synchronization system comprises a plurality of execution engines, each execution engine is configured to execute an instruction stream, and the instruction stream comprises a synchronization mark instruction used for indicating a dependency relationship across the execution engines; each synchronous control module is embedded in the corresponding execution engine, and each synchronous control module is configured to generate a synchronous request signal or a synchronous event signal according to the current state of the execution engine in response to the execution of the execution engine to the synchronous mark instruction; and the inter-engine synchronization module is coupled with the plurality of execution engines to receive the synchronization request signals and the synchronization event signals and return synchronization completion signals to the corresponding execution engines when the dependency relationship is detected to be met, so that all explicit state access operations can be eliminated, and the performance of the execution engines is improved. And conversion of a synchronization mechanism from software explicit scheduling to hardware implicit response is realized.

The embodiment of the invention relates to the field of digital integrated circuits, and discloses a parameterized synchronous register control method and a controller, the control method comprises the following steps: parameterized configuration is carried out on a synchronous register, the configuration at least comprises data bit width, a reset value and operation mode information, and the operation mode information is used for dynamically adjusting asynchronous reset; performing synchronous zero clearing and write enabling effective priority and updating strategy; when the asynchronous reset takes effect, setting the output as a reset value, and judging whether an abnormal protection function is triggered or not according to the operation mode; when the synchronous zero clearing takes effect, the output is set as a reset value under the driving of a clock; when the write enable takes effect, the input is updated to the output under the driving of the clock, and input validity detection is carried out at the same time. Through parameterized configuration, compatibility of the register to any data bit width is realized, priority control of asynchronous reset, synchronous zero clearing and write enabling is realized, the reliability of the system is ensured, and the robustness of the system is improved.

A computer-implemented method, system and computer program product for recommending design changes in designing a digital integrated circuit. An analysis of the digital integrated circuit being designed is performed, where the result of such an analysis involves violations being identified and stored. A stored violation, such as a cross-domain, cross-hierarchy and multi-cycle violation, may then be analyzed to identify a root cause of the violation using a rule. Such a rule may be used for triaging various failures in the cross-domain, cross-hierarchy and / or multi-cycle violation of the digital integrated circuit. A design change in the design of the digital integrated circuit may then be recommended based on the identified root cause of the violation. In this manner, the root cause of failures are effectively identified in the design of digital integrated circuits using an offline analysis of cross-domain, cross-hierarchy and / or multi-cycle violations using a rules-based approach.

The invention belongs to the technical field of circuit system simulation, and particularly relates to a digital integrated circuit function logic and port characteristic unified modeling method, which specifically comprises the following steps: aiming at a digital integrated circuit, dividing the digital integrated circuit into logic modules and electrical ports, and determining the logic direction of each port; each port is associated with a port electrical characteristic model, and the port electrical characteristic model is a parameterized behavior-level model and is used for describing the electrical characteristics of the port; and establishing an internal function logic model for describing internal functions for each logic module, wherein the internal function logic model is seamlessly integrated with the port electrical characteristic model.

The invention discloses a method and a system for improving resolution and linearity of a time sequence generator based on an FPGA (Field Programmable Gate Array), and belongs to the technical field of automatic test equipment. In order to solve the problem that an existing FPGA time sequence generator is difficult to consider high resolution, large dynamic range and high linearity at the same time, a multi-phase clock and coarse and fine delay lines of a carry chain are adopted to form a three-level time interpolation framework, and picosecond interpolation in the large dynamic range is achieved with extremely few logic resources; meanwhile, a time measurement channel is constructed in the chip to obtain actual physical delay, the actual physical delay is transmitted to the upper computer to execute a selection algorithm, and a target delay code with the minimum integral nonlinear error is screened out to update the delay code table. According to the invention, non-linear deviation caused by bottom hardware wiring is effectively overcome, the accuracy of time sequence edge placement and the system test rate are remarkably improved, and the method is mainly used for high-precision time sequence signal generation in digital integrated circuit automatic test equipment.

The application provides a precision-sensitive fine-grained recognition method based on Posit-driven symbolic pattern shaping super-dimensional calculation, and relates to the technical field of digital integrated circuits and artificial intelligence accelerator design. The pre-activation GAP semantic features of the frozen pre-training CNN are taken as input, and prototype Hamming matching is adopted to complete decision. Under the constraint of target deployment bit width, Posit non-uniform quantization is introduced to match the semantic feature distribution of the center, reduce the low bit width quantization error, and improve the low bit width precision; meanwhile, through the learning bipolar projection of quantization perception, the sign margin and dimension contribution are directly shaped, the Hamming separation between classes is expanded, and the reachable precision saturation level is raised. Since the super-dimensional calculation has the class number decoupling characteristic, when the number of classes is expanded, only the on-chip storage resources and the number of parallel comparisons need to be linearly increased, which has better energy efficiency and resource scaling characteristics compared with the traditional fully connected classification head, and significantly improves the hardware implementation friendliness on FPGA or special accelerators.

The application discloses a kind of FPGA-based timing generator resolution and linearity promotion method and system, belong to automatic test equipment technical field.For the problem that existing FPGA timing generator is difficult to consider high resolution, large dynamic range and high linearity, the application adopts multi-phase clock and carry chain coarse, fine delay line to form three-stage time interpolation architecture, to realize picosecond-level interpolation of large dynamic range with very few logic resources;At the same time, the actual physical delay is obtained by constructing a time measurement channel in the chip, and is transmitted to the host computer to execute the selection algorithm, and the target delay code with the smallest integral nonlinear error is selected to update the delay code table.The application effectively overcomes the nonlinear deviation caused by the underlying hardware wiring, significantly improves the accuracy of timing edge placement and the system test rate, and is mainly used for generating high-precision timing signals in digital integrated circuit automatic test equipment.

The embodiment of the invention discloses a multi-data-type multiplier and a method for realizing multiplication of multiple types of data, relates to the technical field of digital integrated circuits, and is convenient for realizing the multiplier supporting data operation of multiple data types at lower cost, so that the area of the integrated circuit and power consumption resources are saved. The method comprises the following steps: basic multiplication units of at least two data types, wherein the basic multiplication units are used for realizing mantissa part or fixed-point number multiplication of floating-point numbers of predetermined data types through combinational operation; the control unit is used for selecting basic multiplication unit combinations of different data types according to the data types of the input matrix; the input matrix is decomposed into a plurality of parts, and the parts are respectively transmitted to corresponding basic multiplication units for operation; and performing shift and accumulation operation on the operation result of each part. The method is suitable for an integrated circuit design scene.

This invention belongs to the field of avionics component testing technology, and discloses a universal DIP-packaged digital integrated circuit chip testing device and method, solving the technical problem of poor versatility of DIP-packaged integrated circuits of different models and functions. It effectively solves the problems of poor versatility, inconvenient pin connections, and low testing efficiency in existing DIP-packaged digital integrated circuit chip testing, achieving rapid, accurate, and convenient testing of different DIP-packaged digital integrated circuit chips.

The present disclosure provides an address translation addressing method, device and electronic equipment, and relates to the technical fields of artificial intelligence, data processing and digital integrated circuits. The specific implementation scheme is: predicting a first page granularity identifier corresponding to an address translation request, searching a storage array according to the first page granularity identifier to obtain a candidate address translation entry, performing consistency verification on the first page granularity identifier and a second page granularity identifier in the candidate address translation entry, and in response to a verification result indicating that the first page granularity identifier and the second page granularity identifier are consistent, determining that the candidate address translation entry is a target address translation entry obtained by addressing. The present application realizes single-path searching through a prediction mechanism, significantly reduces the dynamic flip power consumption when supporting multi-granularity mapping, solves the energy efficiency ratio bottleneck caused by multi-granularity support, and can eliminate the addressing conflict of different granularity pages when sharing a storage array while maintaining low-latency searching.

The invention relates to the technical field of digital integrated circuit design, and discloses a pre-judgment type request suspension method and device, and the method comprises the steps: a request register sends a pre-judgment query request identity label of a first write-in request to a pre-judgment type suspension logic processing module in a current clock period, and a request cache register sends a pre-judgment query request identity label of a second write-in request to a pre-judgment type suspension logic processing module in a next clock period; and sending the query request identity identifier of the first write-in request and the input cache information to a pre-judgment type suspension logic processing module, performing cache query based on the pre-judgment query request identity identifier of the first write-in request in the current time period, storing a query back pressure result of the first write-in request, and storing the query back pressure result of the first write-in request in the pre-judgment type suspension logic processing module. And obtaining a request downstream register state in the next clock period based on the query request identity identifier of the first write request, generating write enable based on the request downstream register state and the query back pressure result of the current clock period, and storing the input cache information based on the write enable. According to the invention, the request blocking rate is reduced.

The invention discloses a frequency regulation circuit and a system on chip, and relates to the technical field of digital integrated circuits, and the circuit comprises a load monitoring module which is connected with a plurality of working units in a target system and is used for monitoring loads of the connected working units and sending corresponding frequency regulation requests; the load matching module is connected with the load monitoring module and is used for determining a frequency adjustment scheme corresponding to the load state combination of the plurality of working units based on the frequency adjustment requests corresponding to the plurality of working units, and the frequency adjustment scheme comprises the working units of which the frequencies need to be adjusted and the corresponding frequencies to be adjusted; and the frequency selection module is connected with the load matching module and is used for selecting a frequency adjustment mode of a working unit so as to be used for frequency adjustment corresponding to the frequency adjustment scheme.

The invention relates to the technical field of integrated circuit verification, in particular to a queue-based clock frequency deviation monitoring device, which comprises an initialization module used for setting module-related initialization data; the clock event capturing module is used for monitoring the edge of a clock signal in real time and obtaining the accurate simulation time of the moment; the queue management and reference model module is used for storing timestamp information into a dynamic queue as required; the comparison and report module is used for obtaining the size of the queue, comparing the size of the queue with the alarm upper limit and the alarm lower limit in real time and outputting a corresponding report according to a comparison result, the dynamic distribution and efficient operation characteristics of the SystemVerilog queue are utilized, clock events are stored and processed in real time, long-time and multi-clock-domain continuous monitoring is supported, and the real-time performance of the system is improved. An efficient, reliable and low-cost solution is provided for clock verification of a modern digital integrated circuit, and verification completeness and automation level are greatly improved.

The invention discloses a circuit aging overcoming method based on a post-silicon regulation technology, and relates to the field of digital integrated circuit reliability design, and the circuit aging overcoming method comprises the steps: determining a slow path in a plurality of data paths in a monitored circuit, the target trigger in each low-speed path is connected with an establishment time violation early-warning unit, and the establishment time violation early-warning unit generates an establishment time early-warning signal when monitoring that the connected trigger is about to generate an establishment time violation; the target triggers of the multiple low-speed paths are divided into multiple trigger groups, each trigger group corresponds to one clock adjusting unit, and the target trigger of each low-speed path in each trigger group is connected with the corresponding clock adjusting unit; and the clock adjusting unit configures the clock edge delay arrival time of the connected trigger based on the establishment time early warning signal so as to realize the effect of overcoming circuit aging. The method can effectively overcome circuit aging and improve circuit reliability.

The present application belongs to the technical field of large-scale digital integrated circuit, and particularly relates to a low-power-consumption high-reliability data verification circuit, method and nonvolatile memory. The low-power-consumption high-reliability data verification circuit comprises a verification enable register, a data verification enable control circuit, a state digital logic detection circuit, a verification register and a verification circuit. The data verification enable control circuit is responsible for managing and triggering data verification operation under the control of the verification enable register. The state digital logic detection circuit is used for calculating and storing n-bit binary actual state code values of all nonvolatile memories to be verified according to a verification logic algorithm. The verification register is used for storing n-bit binary ideal state code values under the condition that the stored data of the nonvolatile memories to be verified are all correct. The verification circuit is used for verifying and comparing the actual state code values output by the state digital logic detection circuit with the ideal state code values stored in the verification register. The present application provides a low-power-consumption, small-area, low-cost and high-reliability solution for nonvolatile memory programming and state correctness verification.

This disclosure provides an interface protocol converter and an electronic device, relating to the field of digital integrated circuits. The interface protocol converter includes: a read conversion module configured to convert the interface protocol of the read channel of an Advanced Scalable Interface (ASPI) into the interface protocol of a Static Random Access Memory (SRAM); the read conversion module includes: a read address FIFO memory; a read request expansion unit; a read identity FIFO memory; and a read data control FIFO memory; and a write conversion module configured to convert the interface protocol of the write channel of an ASPI into the interface protocol of a SRAM. By optimizing the data path structure, deep optimization of the SRAM interface characteristics is achieved, which can significantly reduce conversion latency and hardware resource consumption, while achieving higher bandwidth utilization and energy efficiency.

The application discloses a kind of digital integrated circuit layout post wire length and line delay collaborative prediction method, comprising: constructing preliminary version heterogeneous graph based on the connection information of circuit netlist;From netlist file and process file, the features used for prediction are extracted;The features extracted are added to the corresponding node and edge of preliminary version heterogeneous graph, to obtain final version heterogeneous graph;Construct prediction model;The constructed prediction model is trained;Final version heterogeneous graph is input into the prediction model that training is completed, and finally the prediction result of wire length and the prediction result of line delay are obtained.The model used in the application introduces multi-task learning framework, considers the collaborative relationship of wire length and line delay, in this case, by the model, wire length and line delay are predicted, not only can reduce the time cost of training and reasoning, improve the prediction efficiency, but also can ensure the deep integration and full use of wire length and line delay related information, overcome the problem that the two indicators are relatively independent in the prior art.

The invention provides a cross-voltage-domain stable register circuit, and relates to the technical field of digital integrated circuit design, and the cross-voltage-domain stable register circuit comprises a level conversion circuit which is used for receiving a write-in trigger data string in a first voltage domain and converting the write-in trigger data string into a converted data string in a second voltage domain; the data string identification module is configured in a second voltage domain and is used for correspondingly outputting a write 1 control signal or a write 0 control signal as a write control signal when identifying that the corresponding write trigger data string is a preset write 1 data string or a preset write 0 data string according to the converted data string; and the latch circuit is used for latching the write-in control signal and writing 1 or zero into the register according to the write-in control signal. The method has the beneficial effects that when the first voltage domain needs to write the data into the register of the second voltage domain, the data in the register cannot be influenced when abnormal fluctuation (such as power-on and power-off) occurs in the first voltage domain.

The invention discloses a method for constructing a rear-end layout data set of a digital integrated circuit based on parameter regulation and control. The method comprises the following steps: acquiring an RTL code of the digital integrated circuit, identifying a physical unit represented by the RTL code, and acquiring a physical layout effect related parameter corresponding to each physical unit; based on a plurality of regulation targets, a plurality of parameters are selected from the physical layout effect related parameters for regulation, and a netlist is formed; adjusting a macro cell, and determining a layout plan; based on the determined layout plan, all physical units in the netlist are placed in corresponding chip areas, clock distribution construction is carried out, wiring is carried out according to the netlist, and a layout file is obtained; and performing feature extraction on the layout file to obtain a layout and layout features, and generating a layout data set based on the layout and the layout features. According to the method, the problems of data scarcity, high generation cost and diversified requirements in the prior art can be solved, and the digital back-end layout data set of the integrated circuit can be efficiently constructed in a diversified manner.

The invention discloses a complex SoC time sequence optimization-oriented register structure and a design method, and belongs to the field of super-large-scale digital integrated circuits, the design method comprises the following steps: a user register configuration interface unit and a system memory data flow control unit are respectively and correspondingly provided with a set of independent CPU host interfaces; performing frequency division processing on the system clock signal to obtain a register configuration clock signal, wherein the register configuration clock signal is a low-frequency clock; based on a register configuration clock signal, the user register configuration interface unit performs data read-out operation to obtain read-out data and returns the read-out data to a corresponding CPU host interface, and data write-in operation of all function configuration bits of the user register configuration interface unit is copied to a corresponding function control logic unit; and each function configuration bit completes the control logic of the corresponding function under a system clock signal after signal synchronization. According to the invention, the time sequence problems of signal crossing, wiring congestion and the like in the multifunctional configuration register in the complex SoC can be solved.

The present disclosure provides a processor synchronization system and electronic equipment, relating to the field of digital integrated circuits, the processor synchronization system comprising: a plurality of execution engines, each execution engine configured to execute an instruction stream, the instruction stream containing a synchronization marker instruction indicating a dependency relationship across execution engines; a plurality of synchronization control modules, each synchronization control module embedded in a corresponding execution engine, each synchronization control module configured to generate a synchronization request signal or a synchronization event signal in response to the execution engine executing the synchronization marker instruction, according to the current state of the execution engine; and an inter-engine synchronization module coupled with the plurality of execution engines to receive the synchronization request signal and the synchronization event signal, and return a synchronization completion signal to the corresponding execution engine when detecting that the dependency relationship is satisfied, capable of eliminating all explicit state access operations, and realizing the transformation of the synchronization mechanism from software explicit scheduling to hardware implicit response.

This invention relates to the field of extended picocell base station technology, and particularly to a 5G extended picocell base station system and its control method. The system includes a picocell host and several extension units. The picocell host includes a first GNSS receiver, a first clock synchronization generator, and a first digital integrated circuit chip. Each extension unit includes a second GNSS receiver, a second clock synchronization generator, and a second digital integrated circuit chip. The first clock synchronization generator is electrically connected to both the first GNSS receiver and the first digital integrated circuit chip. The second clock synchronization generator is electrically connected to both the second GNSS receiver and the second digital integrated circuit chip. The first digital integrated circuit chip is electrically connected to the second digital integrated circuit chip. This allows for rapid switching to other reference sources when the GNSS receiver malfunctions and cannot output a reference 1pps timing pulse, thereby improving synchronization stability.

The application belongs to the technical field of circuit, and particularly relates to a blocking glitch low-power double-edge flip-flop based on TFET, a module, a timing circuit, and a large-scale digital integrated circuit adopting the corresponding timing circuit. The flip-flop is composed of twelve PTFET transistors P1-P12, twelve NTFET transistors N1-N12 and five inverters INV1-INV5. The blocking glitch low-power double-edge flip-flop comprises an input stage, a latch circuit and an output stage. The input stage is composed of INV1, INV2, INV3, INV4, P1, P2, P3, N1, N2 and N3. The latch circuit is composed of P4, P5, P6, P7, P8, P9, P10, P11, N4, N5, N6, N7, N8, N9, N10 and N11. The output stage is composed of P4, N11, P12, N12 and INV5. The latch circuit and the output stage circuit share the devices P4 and N11; the input stage and the output stage both adopt the C cell structure. The application solves the problems of signal competition, vulnerability to glitch signals and high device power consumption in the existing TFET flip-flop circuit.

The application provides a digital integrated circuit TMR reinforcement decision method based on multi-target parameter optimization. Original data of a designed circuit is acquired, a complex nonlinear relationship between a replacement decision and circuit parameters is accurately captured through a feedforward neural network, network parameters are optimized in combination with a genetic algorithm, the prediction accuracy and convergence speed of the feedforward neural network are significantly improved to obtain four cost functions, minimization of the four cost functions is taken as an optimization target, a multi-target evolutionary algorithm NSGA-II is used to solve the optimization target to obtain a Pareto solution set, the limitation of traditional single-target optimization is overcome, and a Pareto solution with the minimum comprehensive evaluation value is selected from the Pareto solution set to finally determine a final replacement scheme. The application predicts a replacement time-consuming simulation through a cost function, automatically searches an optimal solution in combination with an optimization algorithm, greatly shortens a design cycle, reduces manual intervention, and in addition, an optimization direction can be flexibly adjusted through a weight adjustment mechanism, so that diversified design requirements are met.