151 results about "Digital integrated circuits" patented technology

The invention discloses a perceptually optimized wiring time sequence prediction method for a digital integrated circuit, electronic equipment and a storage medium, and the method comprises the steps: constructing a heterogeneous graph according to a circuit netlist, fusing the heterogeneous graph with feature vectors corresponding to all units and interconnection lines, inputting the fused heterogeneous graph into a trained heterogeneous graph neural network, and obtaining graph network embedding; inputting the feature matrix of the layout into the trained convolutional neural network to obtain convolutional network embedding; splicing graph network embedding and convolutional network embedding to obtain multi-modal local embedding; constructing a feature sequence of the path according to a connection relationship between a logic unit and an interconnection line in the path by multi-modal local embedding, and inputting the feature sequence of the path into the trained Transform network to obtain a path delay residual prediction value after wiring; and adding the path delay value after layout and the path delay residual prediction value after wiring, and finally obtaining a path delay prediction value after wiring. According to the method, the path delay after wiring can be accurately and efficiently predicted before wiring.

A digital-integrated-circuit timing monitoring method based on a graph convolutional neural network. The method comprises: determining a plurality of candidate monitoring nodes in a target circuit, and the connection relationship between the plurality of candidate monitoring nodes (101); determining feature information of the target circuit on the basis of device property information of the plurality of candidate monitoring nodes (102); inputting into a trained target graph convolutional neural network model the feature information of the target circuit and the connection relationship between the plurality of candidate monitoring nodes, such that the graph convolutional neural network model outputs determination results of the plurality of candidate monitoring nodes, wherein the determination results comprise a first determination result indicating that a candidate monitoring node is a monitoring node, and a second determination result indicating that a candidate node is not a monitoring node (103); on the basis of the determination results, which are output by the graph convolutional neural network model, determining at least one effective monitoring node from among the plurality of candidate monitoring nodes (104); and performing timing monitoring on the target circuit on the basis of the at least one monitoring node (105).

The invention discloses a digital back-end full-process script design method, and relates to the field of digital integrated circuit design, and the method comprises the steps: receiving an RTL behavior level netlist, a process library file and a constraint file as input, and generating a library configuration file valeeb.tcl; a gate-level netlist and a corresponding comprehensive report are generated by using a library configuration file valerib.tcl; performing logic synthesis according to the behavior level netlist and the make syn to generate a gate level netlist, and generating layout and wiring data through make out; according to the layout and wiring data, antenna inspection is carried out through a make ant command, design rule inspection is carried out through a make drc command, and comparison inspection of a generated layout and a schematic diagram is carried out through a make lvs command; performing power consumption analysis according to the layout and wiring data; and performing IR analysis according to the parasitic parameters. Aiming at the problem that the chip digital back-end design process is low in efficiency in the prior art, the design efficiency is improved.

The invention discloses a code generation method and system based on multi-objective reinforcement learning, and belongs to the technical field of digital integrated circuit design, and the method comprises the following steps: S1, generating an SFT training data set; s2, generating an MORL data set; s3, performing supervision and fine tuning on the model by taking the SFT training data set as input, so that the model masters the basic RTL code generation capability; s4, taking the MORL data set as input to train the model after supervision and fine tuning in the S3, and realizing multi-objective optimization; and S5, according to a user demand, describing a multi-target constraint through vector rewards, screening non-dominated candidate codes by using Pareto optimization to obtain an optimal RTL code, and outputting the optimal RTL code, vector reward details and a PPA equilibrium curve. According to the method and the system, basic constraints are met, and meanwhile generation of RTL codes with PPA indexes capable of being customized according to requirements is achieved.

The invention relates to the field of function verification of digital integrated circuits, and discloses an atomic-scale computing chip verification method based on a UVM. The method comprises the following steps: firstly, building a UVM simulation verification platform comprising each core component; then, a software program is used for generating test excitation with physical significance, wherein the test excitation comprises information such as configuration, functional, pseudo potential and track files; then respectively inputting the test excitation into the established UVM verification platform and the software reference model; the UVM verification platform applies the test excitation to the to-be-tested design and outputs a calculation result; the reference model also correspondingly generates a reference result; and finally, comparing the output of the to-be-tested design with the output of the reference model, and verifying the correctness of the function of the atomic calculation chip through visual auxiliary analysis and quantitative error analysis. Through excitation generation based on physical constraints and an effective error evaluation method, the function verification problem of the atomic-scale computing chip can be solved.

The invention relates to a logic comprehensive stage delay prediction method and system based on machine learning, and belongs to the technical field of digital integrated circuit design automation. According to the method, a concept in the field of natural language processing is used for reference, a time sequence path is analogous to a sentence in a natural language processing task, and a basic element forming the sentence is called token. One time sequence path is formed by connecting a plurality of standard units and a wire net, and each token forming one time sequence path contains both the information of the standard units and the information of the wire net. The method comprises the following steps: firstly, predicting the physical size of a line network in a time sequence path by using a graph attention network, and then capturing the time sequence correlation and physical correlation of each part of the whole time sequence path by using an LSTM-Attention network. According to the method, the time sequence performance after wiring is accurately and efficiently fed forward to the logic synthesis process, so that time sequence optimization and time sequence convergence in the logic synthesis stage are guided, and the number of iterations of chip design is greatly reduced.

A computer-implemented method, system, and computer program product for recommending design changes when designing a digital integrated circuit. An analysis of the digital integrated circuit to be designed is performed, the result of such analysis being the identification and storage of violations. A stored violation, e.g., a cross-domain, cross-hierarchy, and / or multi-cycle violation, can then be analyzed to identify a root cause of the violation using a rule. Such a rule can be used to rank various defects in the cross-domain, cross-hierarchy, and / or multi-cycle violation of the digital integrated circuit. A design change when designing the digital integrated circuit can then be recommended based on the identified root cause of the violation.In this way, the root cause of defects in digital integrated circuit design can be effectively identified through offline analysis of cross-domain, cross-hierarchical and / or multi-cycle violations using a rule-based approach.

An optoelectronic module. In some embodiments, the optoelectronic module includes a substrate; a digital integrated circuit, on an upper surface of the substrate; a photonic integrated circuit, secured in a pocket of the substrate, the pocket being in the upper surface of the substrate; and an analog integrated circuit, on the photonic integrated circuit.

The invention belongs to the technical field of large-scale digital integrated circuits, and particularly relates to a foreground high-precision ADC nonlinear harmonic calibration circuit and calibration method. Comprising a pre-calibration ADC output code register used for registering an output code of a pre-calibration ADC; a nonlinear harmonic OTP calibration register; a nonlinear harmonic calibration register; the calibration coefficient selector is used for selectively outputting the nonlinear harmonic OTP calibration register or the calibration coefficient stored in the nonlinear harmonic calibration register; the control state machine is used for controlling a multiplexing time sequence of the error calculation storage compensation module and the calibration coefficient selector; the error calculation, storage and compensation module is used for calculating an output code of the ADC before calibration and a calibration coefficient selected and output by the calibration coefficient selector in a corresponding state so as to gradually realize calculation and storage of a nonlinear harmonic error, and carrying out error compensation calibration on the output code of the ADC before calibration; according to the invention, the problem of poor linearity of the output signal of the high-precision ADC is solved.

The embodiment of the utility model provides an equipment mainboard, which at least comprises a first control board and a second control board, and the first control board and the second control board are connected through a golden finger; wherein the first control panel at least comprises a first processing module, a second processing module, a first basic input / output module, a second basic input / output module and a first digital integrated circuit module, the first processing module is connected with the second processing module, and the first processing module and the second processing module are respectively connected with the first digital integrated circuit module; the first processing module is connected with the first basic input and output module, and the second processing module is connected with the second basic input and output module; the second control board at least comprises a second digital integrated circuit module and a power management module, and the second digital integrated circuit module is connected with the power management module. Diversity can be configured, various spare parts can be freely selected for adaptation, flexibility is high, and practicability is high.

A computer-implemented method, system and computer program product for recommending design changes in designing a digital integrated circuit. An analysis of the digital integrated circuit being designed is performed, where the result of such an analysis involves violations being identified and stored. A stored violation, such as a cross-domain, cross-hierarchy and multi-cycle violation, may then be analyzed to identify a root cause of the violation using a rule. Such a rule may be used for triaging various failures in the cross-domain, cross-hierarchy and / or multi-cycle violation of the digital integrated circuit. A design change in the design of the digital integrated circuit may then be recommended based on the identified root cause of the violation. In this manner, the root cause of failures are effectively identified in the design of digital integrated circuits using an offline analysis of cross-domain, cross-hierarchy and / or multi-cycle violations using a rules-based approach.

This invention discloses a high-speed, high-precision voltage descent monitoring circuit, solving the problem of accurate and timely monitoring of voltage descent phenomena in large-scale integrated circuits, belonging to the fields of digital integrated circuit design and power management. This invention provides an optimized design method for ring oscillator point circuits, using standard cell type, threshold, drive capability, and power consumption as variables to find the ring oscillator circuit design with the highest voltage sensitivity, improving the resolution of the voltage descent monitoring circuit; it provides a one-fold, compact ring oscillator layout design to ensure load balance between nodes; it provides a Nyquist counter design to count the number of times nodes flip over a period of time, improving the voltage monitoring range and solving the metastable sampling problem of traditional counters; and it provides a high-speed voltage quantization circuit that processes coarse and fine quantization in parallel, improving the maximum sampling rate and quantization rate of the voltage descent monitoring circuit.

The application discloses a cross-clock domain register synchronization method and device. It relates to the technical field of digital integrated circuit design. The method comprises the following steps: when the target clock domain is unavailable, routing the bus read-write request to a shadow register array driven by a system clock, and writing a write transaction log into a log queue when the write transaction is completed, the write transaction log comprising a target address, write data and byte enable; when the target clock domain changes from unavailable to available and the log queue is not empty, setting the handshake signal of the bus interface to invalid, reading the write transaction log from the log queue according to the write sequence, and writing the write data into the target register through a byte mask circuit according to the target address in the write transaction log; when the target clock domain is available and the log queue is empty, routing the bus read-write request to the target register, and setting the handshake signal of the bus interface to valid. The method realizes register access integrity and sequential consistency in the target clock dynamic change scenario.

This invention discloses a parasitic parameter extraction method based on a target detection network, belonging to the field of parasitic parameter extraction. The method includes the following steps: establishing a parasitic capacitance pattern library; creating a dataset that matches the characteristics of the layout interconnects; training the target detection network using the self-built dataset and optimizing the network by modifying the loss function; using the trained network to predict the layout image, and subsequently processing the network's prediction results to obtain parasitic parameter values. This invention aims to provide a simple, alternative solution for establishing parasitic parameter pattern libraries and pattern matching for digital integrated circuits.

The invention relates to the technical field of integrated circuit optimization, in particular to a digital integrated circuit optimization method and system. The method comprises the following steps: acquiring process parameter data, and constructing a parameter space response curve of the process parameter data; generating a process precision dense grid based on the parameter space response curve; extracting a layout topological structure of the process precision dense grid; performing time sequence frequency spectrum conversion on the process parameter data to obtain circuit time sequence frequency spectrum data; constructing a circuit three-dimensional tensor by using the process parameter data, the circuit time sequence frequency spectrum data and the layout topological structure, and detecting a path tensor track to obtain circuit track data; therefore, by introducing high-precision data modeling and dynamic constraint in each link, the limitation of a traditional circuit optimization method is broken through, the precision, stability and performance of integrated circuit design are greatly improved, and a finer and more efficient circuit optimization process is ensured.

The application relates to an integrated circuit analysis method and device, computer equipment and a storage medium. The method comprises the following steps: acquiring a gate-level netlist corresponding to a digital integrated circuit included in a device to be measured, the gate-level netlist being used for describing a plurality of paths included in the digital integrated circuit and at least one logic gate included in a gate circuit on each path; acquiring path information of each path according to the gate-level netlist; calculating a delay increment of each path according to the path information and a preset device degradation model; calculating a failure time of each path according to the delay increment and a failure boundary condition, and taking a path corresponding to a minimum failure time as a critical failure path of the digital integrated circuit. Through the method, a critical failure path causing reliability degradation in an integrated circuit can be analyzed based on circuit load and timing requirements, so that the path is reinforced at an early design stage, and the reliability of the integrated circuit is improved.

The invention provides a processor synchronization system and electronic equipment, and relates to the field of digital integrated circuits, the processor synchronization system comprises a plurality of execution engines, each execution engine is configured to execute an instruction stream, and the instruction stream comprises a synchronization mark instruction used for indicating a dependency relationship across the execution engines; each synchronous control module is embedded in the corresponding execution engine, and each synchronous control module is configured to generate a synchronous request signal or a synchronous event signal according to the current state of the execution engine in response to the execution of the execution engine to the synchronous mark instruction; and the inter-engine synchronization module is coupled with the plurality of execution engines to receive the synchronization request signals and the synchronization event signals and return synchronization completion signals to the corresponding execution engines when the dependency relationship is detected to be met, so that all explicit state access operations can be eliminated, and the performance of the execution engines is improved. And conversion of a synchronization mechanism from software explicit scheduling to hardware implicit response is realized.

The embodiment of the invention relates to the field of digital integrated circuits, and discloses a parameterized synchronous register control method and a controller, the control method comprises the following steps: parameterized configuration is carried out on a synchronous register, the configuration at least comprises data bit width, a reset value and operation mode information, and the operation mode information is used for dynamically adjusting asynchronous reset; performing synchronous zero clearing and write enabling effective priority and updating strategy; when the asynchronous reset takes effect, setting the output as a reset value, and judging whether an abnormal protection function is triggered or not according to the operation mode; when the synchronous zero clearing takes effect, the output is set as a reset value under the driving of a clock; when the write enable takes effect, the input is updated to the output under the driving of the clock, and input validity detection is carried out at the same time. Through parameterized configuration, compatibility of the register to any data bit width is realized, priority control of asynchronous reset, synchronous zero clearing and write enabling is realized, the reliability of the system is ensured, and the robustness of the system is improved.

A computer-implemented method, system and computer program product for recommending design changes in designing a digital integrated circuit. An analysis of the digital integrated circuit being designed is performed, where the result of such an analysis involves violations being identified and stored. A stored violation, such as a cross-domain, cross-hierarchy and multi-cycle violation, may then be analyzed to identify a root cause of the violation using a rule. Such a rule may be used for triaging various failures in the cross-domain, cross-hierarchy and / or multi-cycle violation of the digital integrated circuit. A design change in the design of the digital integrated circuit may then be recommended based on the identified root cause of the violation. In this manner, the root cause of failures are effectively identified in the design of digital integrated circuits using an offline analysis of cross-domain, cross-hierarchy and / or multi-cycle violations using a rules-based approach.

The invention belongs to the technical field of circuit system simulation, and particularly relates to a digital integrated circuit function logic and port characteristic unified modeling method, which specifically comprises the following steps: aiming at a digital integrated circuit, dividing the digital integrated circuit into logic modules and electrical ports, and determining the logic direction of each port; each port is associated with a port electrical characteristic model, and the port electrical characteristic model is a parameterized behavior-level model and is used for describing the electrical characteristics of the port; and establishing an internal function logic model for describing internal functions for each logic module, wherein the internal function logic model is seamlessly integrated with the port electrical characteristic model.

The invention discloses a method and a system for improving resolution and linearity of a time sequence generator based on an FPGA (Field Programmable Gate Array), and belongs to the technical field of automatic test equipment. In order to solve the problem that an existing FPGA time sequence generator is difficult to consider high resolution, large dynamic range and high linearity at the same time, a multi-phase clock and coarse and fine delay lines of a carry chain are adopted to form a three-level time interpolation framework, and picosecond interpolation in the large dynamic range is achieved with extremely few logic resources; meanwhile, a time measurement channel is constructed in the chip to obtain actual physical delay, the actual physical delay is transmitted to the upper computer to execute a selection algorithm, and a target delay code with the minimum integral nonlinear error is screened out to update the delay code table. According to the invention, non-linear deviation caused by bottom hardware wiring is effectively overcome, the accuracy of time sequence edge placement and the system test rate are remarkably improved, and the method is mainly used for high-precision time sequence signal generation in digital integrated circuit automatic test equipment.

The application provides a precision-sensitive fine-grained recognition method based on Posit-driven symbolic pattern shaping super-dimensional calculation, and relates to the technical field of digital integrated circuits and artificial intelligence accelerator design. The pre-activation GAP semantic features of the frozen pre-training CNN are taken as input, and prototype Hamming matching is adopted to complete decision. Under the constraint of target deployment bit width, Posit non-uniform quantization is introduced to match the semantic feature distribution of the center, reduce the low bit width quantization error, and improve the low bit width precision; meanwhile, through the learning bipolar projection of quantization perception, the sign margin and dimension contribution are directly shaped, the Hamming separation between classes is expanded, and the reachable precision saturation level is raised. Since the super-dimensional calculation has the class number decoupling characteristic, when the number of classes is expanded, only the on-chip storage resources and the number of parallel comparisons need to be linearly increased, which has better energy efficiency and resource scaling characteristics compared with the traditional fully connected classification head, and significantly improves the hardware implementation friendliness on FPGA or special accelerators.

The application discloses a kind of FPGA-based timing generator resolution and linearity promotion method and system, belong to automatic test equipment technical field.For the problem that existing FPGA timing generator is difficult to consider high resolution, large dynamic range and high linearity, the application adopts multi-phase clock and carry chain coarse, fine delay line to form three-stage time interpolation architecture, to realize picosecond-level interpolation of large dynamic range with very few logic resources;At the same time, the actual physical delay is obtained by constructing a time measurement channel in the chip, and is transmitted to the host computer to execute the selection algorithm, and the target delay code with the smallest integral nonlinear error is selected to update the delay code table.The application effectively overcomes the nonlinear deviation caused by the underlying hardware wiring, significantly improves the accuracy of timing edge placement and the system test rate, and is mainly used for generating high-precision timing signals in digital integrated circuit automatic test equipment.

The embodiment of the invention discloses a multi-data-type multiplier and a method for realizing multiplication of multiple types of data, relates to the technical field of digital integrated circuits, and is convenient for realizing the multiplier supporting data operation of multiple data types at lower cost, so that the area of the integrated circuit and power consumption resources are saved. The method comprises the following steps: basic multiplication units of at least two data types, wherein the basic multiplication units are used for realizing mantissa part or fixed-point number multiplication of floating-point numbers of predetermined data types through combinational operation; the control unit is used for selecting basic multiplication unit combinations of different data types according to the data types of the input matrix; the input matrix is decomposed into a plurality of parts, and the parts are respectively transmitted to corresponding basic multiplication units for operation; and performing shift and accumulation operation on the operation result of each part. The method is suitable for an integrated circuit design scene.

This invention belongs to the field of avionics component testing technology, and discloses a universal DIP-packaged digital integrated circuit chip testing device and method, solving the technical problem of poor versatility of DIP-packaged integrated circuits of different models and functions. It effectively solves the problems of poor versatility, inconvenient pin connections, and low testing efficiency in existing DIP-packaged digital integrated circuit chip testing, achieving rapid, accurate, and convenient testing of different DIP-packaged digital integrated circuit chips.

The present disclosure provides an address translation addressing method, device and electronic equipment, and relates to the technical fields of artificial intelligence, data processing and digital integrated circuits. The specific implementation scheme is: predicting a first page granularity identifier corresponding to an address translation request, searching a storage array according to the first page granularity identifier to obtain a candidate address translation entry, performing consistency verification on the first page granularity identifier and a second page granularity identifier in the candidate address translation entry, and in response to a verification result indicating that the first page granularity identifier and the second page granularity identifier are consistent, determining that the candidate address translation entry is a target address translation entry obtained by addressing. The present application realizes single-path searching through a prediction mechanism, significantly reduces the dynamic flip power consumption when supporting multi-granularity mapping, solves the energy efficiency ratio bottleneck caused by multi-granularity support, and can eliminate the addressing conflict of different granularity pages when sharing a storage array while maintaining low-latency searching.

The invention relates to the technical field of digital integrated circuit design, and discloses a pre-judgment type request suspension method and device, and the method comprises the steps: a request register sends a pre-judgment query request identity label of a first write-in request to a pre-judgment type suspension logic processing module in a current clock period, and a request cache register sends a pre-judgment query request identity label of a second write-in request to a pre-judgment type suspension logic processing module in a next clock period; and sending the query request identity identifier of the first write-in request and the input cache information to a pre-judgment type suspension logic processing module, performing cache query based on the pre-judgment query request identity identifier of the first write-in request in the current time period, storing a query back pressure result of the first write-in request, and storing the query back pressure result of the first write-in request in the pre-judgment type suspension logic processing module. And obtaining a request downstream register state in the next clock period based on the query request identity identifier of the first write request, generating write enable based on the request downstream register state and the query back pressure result of the current clock period, and storing the input cache information based on the write enable. According to the invention, the request blocking rate is reduced.

The invention discloses a frequency regulation circuit and a system on chip, and relates to the technical field of digital integrated circuits, and the circuit comprises a load monitoring module which is connected with a plurality of working units in a target system and is used for monitoring loads of the connected working units and sending corresponding frequency regulation requests; the load matching module is connected with the load monitoring module and is used for determining a frequency adjustment scheme corresponding to the load state combination of the plurality of working units based on the frequency adjustment requests corresponding to the plurality of working units, and the frequency adjustment scheme comprises the working units of which the frequencies need to be adjusted and the corresponding frequencies to be adjusted; and the frequency selection module is connected with the load matching module and is used for selecting a frequency adjustment mode of a working unit so as to be used for frequency adjustment corresponding to the frequency adjustment scheme.

The invention relates to the technical field of integrated circuit verification, in particular to a queue-based clock frequency deviation monitoring device, which comprises an initialization module used for setting module-related initialization data; the clock event capturing module is used for monitoring the edge of a clock signal in real time and obtaining the accurate simulation time of the moment; the queue management and reference model module is used for storing timestamp information into a dynamic queue as required; the comparison and report module is used for obtaining the size of the queue, comparing the size of the queue with the alarm upper limit and the alarm lower limit in real time and outputting a corresponding report according to a comparison result, the dynamic distribution and efficient operation characteristics of the SystemVerilog queue are utilized, clock events are stored and processed in real time, long-time and multi-clock-domain continuous monitoring is supported, and the real-time performance of the system is improved. An efficient, reliable and low-cost solution is provided for clock verification of a modern digital integrated circuit, and verification completeness and automation level are greatly improved.