106 results about "Verilog" patented technology

The invention relates to the field of digital circuit experiment teaching, in particular to a digital circuit experiment platform and method applying a multi-modal large model and a medium, and the method comprises the steps: inputting experiment task description, analyzing and extracting structured semantic information, and forming task representation; retrieving a circuit function block from the electronic component knowledge base, constructing a context enhancement cue word, guiding a multi-modal large language model to generate a Verilog HDL code, and outputting the Verilog HDL code after grammar check and function verification; a Yosys tool is used for carrying out logic synthesis on the codes to generate a standard JSON netlist, and then the standard JSON netlist is converted into an SVG-format circuit diagram through a Netlistsvg tool; and an electronic component knowledge base updating mechanism is constructed to realize knowledge cyclic evolution and adaptive enhancement, so that the intelligent level and practical training efficiency of circuit experiment teaching are remarkably improved.

The invention relates to a software and hardware debugging method, system and device of a generative RISC-V SoC and a storage medium, and relates to the field of RISC-V SoC. The method comprises the following steps: constructing an RISC-V SoC generator by using Chisel, wherein the RISC-V SoC generator comprises a parameterized template file; receiving user-defined parameter change information, and changing the template file according to the user-defined parameter change information to obtain an RISC-V SoC generation file; the RISC-V SoC generation file is compiled through a compiling tool, and a Verilog RTL code of the RISC-V SoC is generated; when a software simulation instruction is received, the Verilog RTL code is used for building a software simulation environment, a simulation top-layer file is created according to the software simulation environment, and software simulation is carried out; and when an FPGA prototype verification instruction is received, establishing an FPGA prototype verification environment by using the Verilog RTL code, creating a top-layer file according to the FPGA prototype verification environment, and performing FPGA prototype verification. The method has the technical effects that the defined generator framework is utilized, a user can generate the self-defined RISC-V SoC only by changing simple parameters, and the design flexibility and efficiency are improved.

The embodiment of the invention provides a system-on-chip bus verification method and device and electronic equipment, and relates to the technical field of chips. The method comprises the steps of obtaining a source memory mapping configuration file in a preset format, performing format conversion to obtain a target memory mapping configuration file which comprises a class method of an access address of a slave device, determining a device combination, obtaining access related information by calling the class method of the slave device in the device combination, and generating a corresponding verification case, and performing verification. A source memory mapping configuration file is converted into a target memory mapping configuration file in a System Verilog language format with a clear code structure, so that when a verification case corresponding to a master device combination needs to be generated, the verification case corresponding to the master device combination is generated by calling a class method of an access address of each slave device corresponding to the combination in the target memory mapping configuration file; therefore, the access related information of each slave device required for generating the verification case can be obtained, so that the generation efficiency of the verification case is effectively improved.

The invention provides a Verilog-based multi-code-rate LDPC (Low Density Parity Check) encoder under a CCSDS (Consultative Committee for Space Data System) standard and an encoding method, belongs to the technical field of information encoding, and solves the problems that the storage space of the LDPC encoder is wasted and the consumption of matrix resources stored and generated by the encoder is high. The LDPC encoder comprises a control module, a storage module, a cyclic shift module, a check bit calculation module and a code word register module. According to the multi-code-rate LDPC code encoder, the flexibility of the LDPC code encoder is improved by achieving design and construction of the multi-code-rate LDPC code encoder, encoding can be achieved in practical application more easily, meanwhile, the storage space of the LDPC code encoder can be saved, storage resources can be saved, and implementation of a satellite encoder in a deep space environment is facilitated.

The invention discloses a Verilog vulnerability detection method generated based on a graph traversal rule, and the method comprises the steps: firstly receiving a Verilog source code as a target detection code, generating and fusing three code structures, and forming an attribute graph VeriPG; secondly, acquiring natural language description information of a target vulnerability, and extracting a potential vulnerability judgment condition by utilizing a judgment condition LLMs; and then generating a vulnerability detection rule of the target vulnerability based on the VeriPG and a vulnerability judgment condition drive detection rule LLMs, and verifying the generated vulnerability detection rule. And finally, designing and deploying a rule executor, and executing graph traversal on the verified vulnerability detection rule to complete Verilog vulnerability detection. According to the method, the relationship between the control logic and the data can be comprehensively described, and the Verilog security vulnerability detection method with high accuracy, high automation and high adaptability is constructed.

The invention provides a digital-analog hybrid verification method for a clock chip, and the method comprises the steps: building a test top layer based on an analog circuit top layer of the clock chip, and extracting an analog verilog circuit model; completing module-level simulation by using an analog circuit to obtain a nonlinear parameter and a jitter clock parameter; the nonlinear parameters and the jitter clock parameters are inserted into a verilog circuit model to complete nonlinear modeling, and a digital-analog hybrid simulation environment is built in cooperation with a digital RTL / digital netlist; and applying test excitation in a digital-analog hybrid simulation environment to lock the phase-locked loop, and periodically acquiring data to calculate a jitter index so as to complete digital-analog hybrid simulation verification of the clock chip. According to the method, the nonlinear TDC, DTC and DCO models and the jitter clock model are introduced into the digital-analog hybrid verification of the clock chip, so that the simulation can be closer to a real scene, the simulation result is more reliable, and the simulation speed is higher.

The invention discloses a dispersion effect method based on Angelov improvement, which comprises the following steps of: improving an equivalent circuit topological structure of an original Angelov model, and introducing a series structure of a current source Idsac and a capacitor Cb between a drain electrode and a source electrode; the alternating current output conductance gds is connected with the current source in parallel, and the gds is corrected mainly through Verilog-A codes; on-chip testing is carried out on the GaN HEMT at normal temperature, and direct current characteristics and S parameter testing results of the device are obtained through IVCAD software; and performing parameter extraction on the improved model by adopting ICCAP software to obtain fitting results of direct current characteristics and alternating current characteristics of the device. According to the method, the topological structure of the equivalent circuit is improved, the finally proposed dispersion effect model can accurately represent drain-source current, alternating current transconductance and alternating current output conductance of the device in DC and AC working states, meanwhile, separation of DC / AC characteristic fitting parameters is effectively achieved, the model parameter extraction complexity is reduced, and the model extraction time is greatly shortened.

The invention discloses a general modeling method for a semiconductor device based on weight prediction network optimization, which is characterized by comprising the following steps of: acquiring original I-V characteristic data of the semiconductor device through actual measurement or TCAD simulation, and modeling I-V characteristics of the semiconductor device by adopting a weight prediction network model; the method comprises the following steps of: constructing and training a weight prediction network model, then converting the weight prediction network model into an SPICE model through a Verilog-A language, finally putting the SPICE model into a test circuit for simulation, and comparing with a TCAD simulation result, specifically comprising the steps of constructing and training the weight prediction network model, and converting the weight prediction network model into the SPICE model. According to the method, a complex data preprocessing process does not need to be carried out, a complex loss function does not need to be designed, the weight prediction network model is converted into a model capable of being used for SPICE simulation, and compared with a traditional neural network model, higher precision can be obtained, and the method is suitable for being applied to SPICE simulation. An efficient and reliable method is provided for academic research and industrial application of circuit design and process collaborative optimization (DTCO) of novel devices.

The invention provides an automatic conversion method from an SPICE model to a Verilog-A model, and relates to the technical field of integrated circuit simulation, and the method comprises the steps: obtaining test data of a to-be-modeled device, carrying out the normalization processing of the test data, and obtaining the normalized test data and a normalization parameter; training an initial neural network model according to the normalized test data to obtain a trained neural network model; extracting a weight matrix and an offset vector of each network layer from the network structure information of the trained neural network model, and scaling the weight matrix and the offset vector based on the normalized parameter to obtain a scaled parameter; and according to the zoomed parameters and the network structure information of the trained neural network model, generating a simulation model code conforming to a Verilog-A grammar specification. According to the method, efficient and accurate conversion from the neural network model to the Verilog-A model is realized.

The invention discloses a digital back-end netlist conversion and physical verification method and system, a computer and a medium, and the method comprises the steps: exporting a GDS file after layout and wiring from a digital back-end, and completing layout information by fusing standard unit data in a process design suite; exporting a Verilog netlist file from a digital back end; the Verilog netlist file is subjected to netlist format conversion, and a CDL file is obtained; manually calibrating the CDL file, and establishing electrical equivalence of the module-level power supply network and the standard power supply network; and configuring an LVS verification rule, using the calibrated CDL file as a schematic diagram netlist, using an SP netlist generated by the GDS as a layout netlist, explicitly setting a power supply network name, and finally executing LVS verification. According to the method, the electrical connection consistency of the CDL file and the GDS layout can be realized through a standardized power supply network naming mapping mechanism, the LVS verification passing rate is improved, and the manual debugging cost is reduced.

The invention discloses a multi-defect fault modeling method and device in a standard unit. The method comprises the following steps: acquiring a DSPF netlist of the standard unit; converting the DSPF netlist into a switch-level Verilog netlist according to a transistor connection relationship in the DSPF netlist, and constructing a directed graph of a standard cell; selecting a multi-defect fault modeling area on a standard unit according to layout information of the standard unit in the DSPF netlist, and determining a plurality of target interconnection lines influenced by parasitic elements in the multi-defect fault modeling area; according to the directed graph, determining a front-and-back logic connection relation of the multiple target interconnection lines, and according to the front-and-back logic connection relation, determining input and output of a multi-defect fault model to be established; and according to the input, the output and the multiple target interconnection lines, generating a multi-defect fault model so as to solve the problem that the existing fault model cannot completely cover multi-defect fault behaviors, and finally, the diagnosis result precision and the resolution are very low.

To address the problems that existing device models fail to simultaneously consider the effects of dislocations on both drain current and gate leakage current, the models for dislocation effects on drain current fail to dynamically simulate charge capture and release, and the gate leakage current models fail to fully consider the effects of dislocations, the present invention discloses a modeling method for a GaN HEMT device model that considers dislocation effects. The modeling method includes: establishing a model for the effects of dislocations on GaN HEMT drain current; establishing a model for the effects of dislocations on GaN HEMT gate leakage current; integrating the models for the effects of dislocations on GaN HEMT drain current and gate leakage current into a surface potential-based model to obtain a GaN HEMT device model that considers dislocation effects and describes it using the Verilog‑A language; and providing a parameter extraction method for the GaN HEMT device model that considers dislocation effects.

The application discloses a Verilog RTL code reinforcing method and related equipment, relates to the programming technical field, and mainly aims at solving the problem that there is no proper reinforcing method to make the circuit resist 0 and 1 error flip. The method comprises the following steps: obtaining a time sequence logic code section of an original Verilog RTL code file containing time sequence logic; performing format identification on the time sequence logic code section to generate a time sequence logic identification version code file; determining a flip-flop code in the code section with the format identification; and adding redundant combination logic voting circuit code to the flip-flop code to reinforce the original Verilog RTL code. The application is used in the Verilog RTL code reinforcing process.

The invention provides a USB measurement and control system collaborative verification platform building method based on the combination of System Verilog and a C language, and relates to the technical field of FPGA testing, the method is based on a Cadence IES simulation environment to build a verification platform of a layered tree topology architecture, the verification platform is independent of a tested design project file, a three-level system structure is adopted, and the verification platform is provided with a three-level architecture; the rtl design layer is used for storing a source code file of a to-be-tested USB measurement and control system baseband processing FPGA (Field Programmable Gate Array) described by adopting a register transmission level; and the tb test platform layer adopts a modular design and comprises a dutif interface definition module, a dutrap design packaging module, a tb test control module and a tbtop top layer integration module. According to the USB measurement and control system collaborative verification platform building method based on the combination of the System Verilog and the C language, intelligent generation of a verification environment is achieved through an automatic script, and the configuration complexity is remarkably reduced; and a parameterized configuration mechanism is adopted, so that different types of USB measurement and control systems can be quickly adapted, and excellent adaptability is shown.

The invention belongs to the technical field of embedded system design, and particularly relates to a method for expanding an EMMC interface based on a parallel bus. Setting a transplantable parallel bus expansion EMMC interface logic circuit so as to realize communication between the parallel bus and the EMMC interface of the EMMC chip; according to the circuit for realizing the parallel bus expansion EMMC interface logic based on the Verilog language, the function that an embedded system data processing module expands a large-capacity storage data recording function is realized, and the universality and portability of the large-capacity storage EMMC interface logic are improved.

The invention provides a hardware synthesis method and system based on structured Python, and belongs to the technical field of high-level synthesis. The invention provides a hardware synthesis method based on structured Python. The method comprises the following steps: receiving a structured Python algorithm code written by a user; analyzing the structured Python algorithm code to generate an abstract syntax tree, and converting the abstract syntax tree into an intermediate representation; scheduling the intermediate representation according to a preset comprehensive mode to obtain a target intermediate representation adaptive to a hardware time sequence; calling a predefined hardware library module, traversing the target intermediate representation, and generating a synthesizable Verilog hardware code; and based on the input and output interface of the Verilog hardware code, automatically generating a corresponding test platform file and a test case, and carrying out simulation verification on the Verilog hardware code.

The invention provides a process library file processing method and device.In the process library file processing method, character strings in a Verilog hardware netlist file are converted into corresponding constants, a corresponding constant sequence is obtained, the constant sequence serves as a db file to be stored, and when the db file needs to be used, the process library file can be used as a process library file. According to the method, the constant sequence is converted according to the sequence to obtain the corresponding Verilog hardware netlist file, so that the storage space required by the db file is reduced, the occupied hard disk is small, the reading is performed in the process of converting the db file in the constant sequence form into the Verilog file, and the reading efficiency is improved.

The invention discloses a digital BPL long-wave time service receiving device and method capable of automatically compensating high-stability output pulse per second, and the device comprises an FPGA unit, an A / D conversion unit, a program programming storage unit, a storage unit, and a constant-temperature crystal oscillator. Converting the 14-bit digital signal into a second pulse signal and standard time; the A / D conversion unit is used for converting the wireless digital long-wave analog signal into a digital signal with the width of 14 bits; hardware is designed on the basis of an FPGA, receiving and processing of BPL long-wave time service information are achieved in combination with a verilog HDL, the automatic compensation high-stability second pulse output method can dynamically compensate the second pulse output initial position according to the received long-wave time service message information, stable second pulses are provided for other systems, and the accuracy of second pulse output is improved. The long-wave time service system can be used as an effective supplementary means for satellite time service and wired time service, and can provide standard time information and second pulse signals for users in real time in a long-wave time service system coverage area.

The application discloses a simulation vector automatic generation method based on an agent model and aiming at assertion coverage, which comprises the following steps: lightweight simulation vector automatic generation, which is used for an assertion statement in a System Verilog file, wherein a precondition only involves module input; agent model generation, which is used for an agent model of an assertion with a complex precondition in a System Verilog file; and multi-assertion simulation vector automatic generation, which is used for generating a simulation vector for simultaneously activating multiple assertions. The application has the advantages of simple principle, simple operation and efficiency improvement.

This invention belongs to the field of triple mode redundancy (TMR) technology, and particularly relates to a selective TMR conversion method and system based on two-stage decoupling. The method includes acquiring the Verilog design code to be converted and parsing the circuit signals; calculating the dynamic activity of each circuit signal, dividing the circuit signals into critical and non-critical circuit signals, and forming a list of critical circuit signals; reading the list of critical circuit signals, traversing each assignment statement in the Verilog design code to be converted, and identifying whether the current circuit signal is a critical circuit signal; performing TMR operation on the identified critical circuit signals, and using logical assignment to make the replica signals track the original signals in real time for the identified non-critical circuit signals, thus completing the selective TMR conversion. This invention completely decouples the two stages of dynamic activity analysis of circuit signals and selective conversion of source code, and performs true / pseudo-TMR splitting processing.

The invention discloses a satellite-borne laser communication telemetering and remote control system and a multi-protocol interface unified management method thereof, and relates to the technical field of aerospace measurement and control and embedded systems, the satellite-borne laser communication telemetering and remote control system comprises an on-chip system which takes an FPGA as a hardware platform and is constructed in cooperation with a MicroBlaze soft core processor and a Verilog program, and layered architecture is carried out; the upper-layer task management module is responsible for configuration, execution and data monitoring of task instructions and unified management and control of different load devices; the communication interface middleware module is used for abstracting and packaging a bus CAN (Controller Area Network), an interface RS422 and an underlying communication interface of the Ethernet; by introducing the interface middleware and realizing based on the MicroBlaze soft core processor, an upper-layer application and a bottom-layer hardware interface are separated, various communication interfaces are supported, the interface coupling degree is reduced, and unified scheduling and centralized management of the communication interfaces are realized, so that the telemetering and remote control system can efficiently run in a multi-task and multi-interface environment; and flexible configuration and expansion are supported.

The invention provides a method and system for automatically generating a matching code based on an FPGA, and the method comprises the steps: compiling a Verilog test code and a test vector, and storing the Verilog test code and the test vector in a table, the test code supporting dynamic parameterization setting; reading software and hardware information to be tested, executing a code output process based on the test code and the test vector, and generating code matching data corresponding to the software and hardware information; generating a corresponding verification step for each process in the code output processes, verifying the code matching data and the test vector generated by each process in the code output processes in sequence, if verification succeeds, performing the next code output process, and storing the verification steps and the verification result in a basic test plan; and automatically generating a code configuration file corresponding to the software and hardware information in combination with the basic test plan for the test vector of which the code is successfully output. According to the method and the device, the FPGA design verification is comprehensively optimized intelligently and automatically, and the efficiency and the accuracy of generating the code configuration file in the FPGA design are improved.

The invention discloses a method and device for generating a FDSOI MOSFET model based on BSIMIMG, which is applied to the field of integrated circuit design, and includes: a BSIMIMG back channel device model and a BSIMIMG positive channel device model, wherein the BSIMIMG back channel device model is merged into the BSIMIMG positive channel device model in the form of a controlled source; wherein the BSIMIMG positive channel device model is generated based on a new BSIMIMG standard model and positive channel device model parameters extracted from an FDSOI MOSFET device, and the BSIMIMG back channel device model is generated based on a new BSIMIMG standard model and back channel device model parameters extracted from an FDSOI MOSFET device, and the new BSIMIMG standard model is obtained by modifying the Verilog‑a code of the BSIMIMG standard model. The device model accuracy when the back channel is turned on is improved by the invention.

A Verilog-designed asynchronous event conflict verification method and system, which includes a Verilog language parsing module, a basic device identification module, a suspected asynchronous event automatic extraction module, and an asynchronous event port confirmation module. The verification system analyzes suspected ports of asynchronous events in large-scale logic designs through a static analysis method, models input and output ports through a manual analysis method, and finally verifies the problem through a simulation verification method, thereby ultimately improving the reliability of large-scale logic design products.

This invention discloses a quality inspection method for compact transistor models based on machine learning, belonging to the field of semiconductor device modeling and EDA. The method includes: receiving a Verilog-A model file and a JSON configuration file defining geometric dimensions and simulation parameters; performing syntax checks and generating OSDI shared objects using the OpenVAF compiler; performing physical consistency verification, including the Gummel symmetry test (GST) and energy conservation checks; extracting device-level DC and AC characteristic indicators; and conducting circuit-level benchmark tests, determining model stability through simulation time and convergence of different unit circuits. This invention constructs a full-link automated evaluation framework from syntax to physical characteristics, effectively solving the problems of physical rationality and simulation convergence of machine learning models in integrated circuit design, and significantly improving model development efficiency and reliability.

The invention discloses a construction method of a Verilog HDL (Hardware Description Language) code model and a related device. Firstly, a basic Butterworth filter and a VCode template are created in GCKontrol, and an IP core equivalent to an addition and subtraction operation unit in the filter is designed in Vivado based on service requirements. Then configuring a VCode template port to be consistent with the addition and subtraction operation unit to generate a VCode module, after the addition and subtraction operation unit is replaced, enabling a GCKontrol code generation directory to point to a Vivado path, and finally instantiating an IP core to the VCode module to complete model generation. According to the method, GCKontrol and IP core multiplexing are combined, automatic standardized code generation is achieved, manual work and skill dependence are reduced, efficiency and interface consistency are improved, and errors and development cost risks are reduced.

The present invention relates to the field of chips, and particularly to a debugging method for ATPG test vectors, an electronic device, and a storage medium. The ATPG parses and loads a first type of simulation database generated by a Verilog simulator. The ATPG performs simulation according to test vectors to generate a second type of simulation database, obtains a set of mismatched test vectors, the instances corresponding to each mismatched test vector, and the mismatched output pins. The test vectors in the set of mismatched test vectors are the test vectors for which the first type of output response data signal observed at the output pins of the chip model does not match the expected response in the test vectors. When the user designates a test vector in the set of mismatched test vectors as the target test vector, the source of the mismatch of the target test vector can be obtained, and the tracing efficiency is high.

The application belongs to the technical field of semiconductor device modeling and EDA, and discloses a method for extracting parameters of a compact model of an anti-radiation SiGe HBT based on a physical mechanism. The method prepares a test structure array containing different geometric sizes and doping, obtains direct current / alternating current characteristics through multi-dose point irradiation of a 60Co gamma ray, establishes a logarithmic-linear or saturation exponential degradation equation based on an irradiation damage mechanism, embeds a standard MEXTRAM / HICUM model in the form of a Verilog-A subcircuit, adds a dose input pin, extracts degradation coefficients to construct a total dose-key parameter degradation mapping library, and integrates the library with an EDA tool to realize irradiation environment simulation. The application shortens the anti-radiation circuit design cycle from 6 months to 2 weeks, and the model-measured error is less than 5% after 1 Mrad irradiation, so the application is suitable for the design of anti-radiation integrated circuits such as spaceborne phased arrays and space communication.

The invention discloses a Verilog-based adaptive time-frequency aliasing interference identification method and system. The method comprises the following steps: acquiring a time-frequency aliasing signal; according to the prior carrier frequency and the sampling frequency of the target signal, the actual fuzzy frequency is dynamically calculated by using the HOBs-DEC algorithm; the method comprises the following steps: acquiring a power spectrum of a signal, identifying the number of effective spectral lines based on an actual fuzzy frequency and a preset threshold, and carrying out first classification on the signal: if the number of the effective spectral lines is not less than a first threshold, judging that the signal comprises an AM or single-carrier signal; otherwise, determining that the signal comprises a comb spectrum, MSK or Gaussian white noise signal; extracting a square spectrum characteristic of the signal, and identifying whether the signal is an AM signal or a single carrier signal; and extracting single spectrum and / or square spectrum characteristics of the signal, and identifying the signal as a comb spectrum, an MSK signal or a Gaussian white noise signal. According to the method, the processing speed of the recognition process can be improved, and the applicability and the stability in an actual scene are enhanced.

The present invention discloses a logic synthesis circuit area prediction method based on GNN-Transformer, the method comprising: constructing a logic synthesis circuit area prediction data set, the data set RTL verilog describes the circuit, and an optimization sequence composed of a series of optimization operators provided by a logic synthesis tool, and the area of ​​the circuit after synthesis as a label; constructing a logic synthesis circuit area prediction model based on GNN-Transformer. The present invention can make more accurate predictions for circuits of different scales by utilizing the spatiotemporal information from the circuit and the optimization sequence, and considering the impact of the large span of data labels of circuits of different scales on model training.