64 results about "Verilog" patented technology

The invention relates to the field of digital circuit experiment teaching, in particular to a digital circuit experiment platform and method applying a multi-modal large model and a medium, and the method comprises the steps: inputting experiment task description, analyzing and extracting structured semantic information, and forming task representation; retrieving a circuit function block from the electronic component knowledge base, constructing a context enhancement cue word, guiding a multi-modal large language model to generate a Verilog HDL code, and outputting the Verilog HDL code after grammar check and function verification; a Yosys tool is used for carrying out logic synthesis on the codes to generate a standard JSON netlist, and then the standard JSON netlist is converted into an SVG-format circuit diagram through a Netlistsvg tool; and an electronic component knowledge base updating mechanism is constructed to realize knowledge cyclic evolution and adaptive enhancement, so that the intelligent level and practical training efficiency of circuit experiment teaching are remarkably improved.

The embodiment of the invention provides a system-on-chip bus verification method and device and electronic equipment, and relates to the technical field of chips. The method comprises the steps of obtaining a source memory mapping configuration file in a preset format, performing format conversion to obtain a target memory mapping configuration file which comprises a class method of an access address of a slave device, determining a device combination, obtaining access related information by calling the class method of the slave device in the device combination, and generating a corresponding verification case, and performing verification. A source memory mapping configuration file is converted into a target memory mapping configuration file in a System Verilog language format with a clear code structure, so that when a verification case corresponding to a master device combination needs to be generated, the verification case corresponding to the master device combination is generated by calling a class method of an access address of each slave device corresponding to the combination in the target memory mapping configuration file; therefore, the access related information of each slave device required for generating the verification case can be obtained, so that the generation efficiency of the verification case is effectively improved.

The invention discloses a Verilog vulnerability detection method generated based on a graph traversal rule, and the method comprises the steps: firstly receiving a Verilog source code as a target detection code, generating and fusing three code structures, and forming an attribute graph VeriPG; secondly, acquiring natural language description information of a target vulnerability, and extracting a potential vulnerability judgment condition by utilizing a judgment condition LLMs; and then generating a vulnerability detection rule of the target vulnerability based on the VeriPG and a vulnerability judgment condition drive detection rule LLMs, and verifying the generated vulnerability detection rule. And finally, designing and deploying a rule executor, and executing graph traversal on the verified vulnerability detection rule to complete Verilog vulnerability detection. According to the method, the relationship between the control logic and the data can be comprehensively described, and the Verilog security vulnerability detection method with high accuracy, high automation and high adaptability is constructed.

The invention provides an automatic conversion method from an SPICE model to a Verilog-A model, and relates to the technical field of integrated circuit simulation, and the method comprises the steps: obtaining test data of a to-be-modeled device, carrying out the normalization processing of the test data, and obtaining the normalized test data and a normalization parameter; training an initial neural network model according to the normalized test data to obtain a trained neural network model; extracting a weight matrix and an offset vector of each network layer from the network structure information of the trained neural network model, and scaling the weight matrix and the offset vector based on the normalized parameter to obtain a scaled parameter; and according to the zoomed parameters and the network structure information of the trained neural network model, generating a simulation model code conforming to a Verilog-A grammar specification. According to the method, efficient and accurate conversion from the neural network model to the Verilog-A model is realized.

The invention discloses a digital back-end netlist conversion and physical verification method and system, a computer and a medium, and the method comprises the steps: exporting a GDS file after layout and wiring from a digital back-end, and completing layout information by fusing standard unit data in a process design suite; exporting a Verilog netlist file from a digital back end; the Verilog netlist file is subjected to netlist format conversion, and a CDL file is obtained; manually calibrating the CDL file, and establishing electrical equivalence of the module-level power supply network and the standard power supply network; and configuring an LVS verification rule, using the calibrated CDL file as a schematic diagram netlist, using an SP netlist generated by the GDS as a layout netlist, explicitly setting a power supply network name, and finally executing LVS verification. According to the method, the electrical connection consistency of the CDL file and the GDS layout can be realized through a standardized power supply network naming mapping mechanism, the LVS verification passing rate is improved, and the manual debugging cost is reduced.

To address the problems that existing device models fail to simultaneously consider the effects of dislocations on both drain current and gate leakage current, the models for dislocation effects on drain current fail to dynamically simulate charge capture and release, and the gate leakage current models fail to fully consider the effects of dislocations, the present invention discloses a modeling method for a GaN HEMT device model that considers dislocation effects. The modeling method includes: establishing a model for the effects of dislocations on GaN HEMT drain current; establishing a model for the effects of dislocations on GaN HEMT gate leakage current; integrating the models for the effects of dislocations on GaN HEMT drain current and gate leakage current into a surface potential-based model to obtain a GaN HEMT device model that considers dislocation effects and describes it using the Verilog‑A language; and providing a parameter extraction method for the GaN HEMT device model that considers dislocation effects.

The application discloses a Verilog RTL code reinforcing method and related equipment, relates to the programming technical field, and mainly aims at solving the problem that there is no proper reinforcing method to make the circuit resist 0 and 1 error flip. The method comprises the following steps: obtaining a time sequence logic code section of an original Verilog RTL code file containing time sequence logic; performing format identification on the time sequence logic code section to generate a time sequence logic identification version code file; determining a flip-flop code in the code section with the format identification; and adding redundant combination logic voting circuit code to the flip-flop code to reinforce the original Verilog RTL code. The application is used in the Verilog RTL code reinforcing process.

The invention provides a USB measurement and control system collaborative verification platform building method based on the combination of System Verilog and a C language, and relates to the technical field of FPGA testing, the method is based on a Cadence IES simulation environment to build a verification platform of a layered tree topology architecture, the verification platform is independent of a tested design project file, a three-level system structure is adopted, and the verification platform is provided with a three-level architecture; the rtl design layer is used for storing a source code file of a to-be-tested USB measurement and control system baseband processing FPGA (Field Programmable Gate Array) described by adopting a register transmission level; and the tb test platform layer adopts a modular design and comprises a dutif interface definition module, a dutrap design packaging module, a tb test control module and a tbtop top layer integration module. According to the USB measurement and control system collaborative verification platform building method based on the combination of the System Verilog and the C language, intelligent generation of a verification environment is achieved through an automatic script, and the configuration complexity is remarkably reduced; and a parameterized configuration mechanism is adopted, so that different types of USB measurement and control systems can be quickly adapted, and excellent adaptability is shown.

The invention provides a hardware synthesis method and system based on structured Python, and belongs to the technical field of high-level synthesis. The invention provides a hardware synthesis method based on structured Python. The method comprises the following steps: receiving a structured Python algorithm code written by a user; analyzing the structured Python algorithm code to generate an abstract syntax tree, and converting the abstract syntax tree into an intermediate representation; scheduling the intermediate representation according to a preset comprehensive mode to obtain a target intermediate representation adaptive to a hardware time sequence; calling a predefined hardware library module, traversing the target intermediate representation, and generating a synthesizable Verilog hardware code; and based on the input and output interface of the Verilog hardware code, automatically generating a corresponding test platform file and a test case, and carrying out simulation verification on the Verilog hardware code.

The invention provides a process library file processing method and device.In the process library file processing method, character strings in a Verilog hardware netlist file are converted into corresponding constants, a corresponding constant sequence is obtained, the constant sequence serves as a db file to be stored, and when the db file needs to be used, the process library file can be used as a process library file. According to the method, the constant sequence is converted according to the sequence to obtain the corresponding Verilog hardware netlist file, so that the storage space required by the db file is reduced, the occupied hard disk is small, the reading is performed in the process of converting the db file in the constant sequence form into the Verilog file, and the reading efficiency is improved.

The invention discloses a digital BPL long-wave time service receiving device and method capable of automatically compensating high-stability output pulse per second, and the device comprises an FPGA unit, an A / D conversion unit, a program programming storage unit, a storage unit, and a constant-temperature crystal oscillator. Converting the 14-bit digital signal into a second pulse signal and standard time; the A / D conversion unit is used for converting the wireless digital long-wave analog signal into a digital signal with the width of 14 bits; hardware is designed on the basis of an FPGA, receiving and processing of BPL long-wave time service information are achieved in combination with a verilog HDL, the automatic compensation high-stability second pulse output method can dynamically compensate the second pulse output initial position according to the received long-wave time service message information, stable second pulses are provided for other systems, and the accuracy of second pulse output is improved. The long-wave time service system can be used as an effective supplementary means for satellite time service and wired time service, and can provide standard time information and second pulse signals for users in real time in a long-wave time service system coverage area.

The application discloses a simulation vector automatic generation method based on an agent model and aiming at assertion coverage, which comprises the following steps: lightweight simulation vector automatic generation, which is used for an assertion statement in a System Verilog file, wherein a precondition only involves module input; agent model generation, which is used for an agent model of an assertion with a complex precondition in a System Verilog file; and multi-assertion simulation vector automatic generation, which is used for generating a simulation vector for simultaneously activating multiple assertions. The application has the advantages of simple principle, simple operation and efficiency improvement.

This invention belongs to the field of triple mode redundancy (TMR) technology, and particularly relates to a selective TMR conversion method and system based on two-stage decoupling. The method includes acquiring the Verilog design code to be converted and parsing the circuit signals; calculating the dynamic activity of each circuit signal, dividing the circuit signals into critical and non-critical circuit signals, and forming a list of critical circuit signals; reading the list of critical circuit signals, traversing each assignment statement in the Verilog design code to be converted, and identifying whether the current circuit signal is a critical circuit signal; performing TMR operation on the identified critical circuit signals, and using logical assignment to make the replica signals track the original signals in real time for the identified non-critical circuit signals, thus completing the selective TMR conversion. This invention completely decouples the two stages of dynamic activity analysis of circuit signals and selective conversion of source code, and performs true / pseudo-TMR splitting processing.

The invention discloses a satellite-borne laser communication telemetering and remote control system and a multi-protocol interface unified management method thereof, and relates to the technical field of aerospace measurement and control and embedded systems, the satellite-borne laser communication telemetering and remote control system comprises an on-chip system which takes an FPGA as a hardware platform and is constructed in cooperation with a MicroBlaze soft core processor and a Verilog program, and layered architecture is carried out; the upper-layer task management module is responsible for configuration, execution and data monitoring of task instructions and unified management and control of different load devices; the communication interface middleware module is used for abstracting and packaging a bus CAN (Controller Area Network), an interface RS422 and an underlying communication interface of the Ethernet; by introducing the interface middleware and realizing based on the MicroBlaze soft core processor, an upper-layer application and a bottom-layer hardware interface are separated, various communication interfaces are supported, the interface coupling degree is reduced, and unified scheduling and centralized management of the communication interfaces are realized, so that the telemetering and remote control system can efficiently run in a multi-task and multi-interface environment; and flexible configuration and expansion are supported.

This invention discloses a quality inspection method for compact transistor models based on machine learning, belonging to the field of semiconductor device modeling and EDA. The method includes: receiving a Verilog-A model file and a JSON configuration file defining geometric dimensions and simulation parameters; performing syntax checks and generating OSDI shared objects using the OpenVAF compiler; performing physical consistency verification, including the Gummel symmetry test (GST) and energy conservation checks; extracting device-level DC and AC characteristic indicators; and conducting circuit-level benchmark tests, determining model stability through simulation time and convergence of different unit circuits. This invention constructs a full-link automated evaluation framework from syntax to physical characteristics, effectively solving the problems of physical rationality and simulation convergence of machine learning models in integrated circuit design, and significantly improving model development efficiency and reliability.

The invention discloses a construction method of a Verilog HDL (Hardware Description Language) code model and a related device. Firstly, a basic Butterworth filter and a VCode template are created in GCKontrol, and an IP core equivalent to an addition and subtraction operation unit in the filter is designed in Vivado based on service requirements. Then configuring a VCode template port to be consistent with the addition and subtraction operation unit to generate a VCode module, after the addition and subtraction operation unit is replaced, enabling a GCKontrol code generation directory to point to a Vivado path, and finally instantiating an IP core to the VCode module to complete model generation. According to the method, GCKontrol and IP core multiplexing are combined, automatic standardized code generation is achieved, manual work and skill dependence are reduced, efficiency and interface consistency are improved, and errors and development cost risks are reduced.

The present invention relates to the field of chips, and particularly to a debugging method for ATPG test vectors, an electronic device, and a storage medium. The ATPG parses and loads a first type of simulation database generated by a Verilog simulator. The ATPG performs simulation according to test vectors to generate a second type of simulation database, obtains a set of mismatched test vectors, the instances corresponding to each mismatched test vector, and the mismatched output pins. The test vectors in the set of mismatched test vectors are the test vectors for which the first type of output response data signal observed at the output pins of the chip model does not match the expected response in the test vectors. When the user designates a test vector in the set of mismatched test vectors as the target test vector, the source of the mismatch of the target test vector can be obtained, and the tracing efficiency is high.

The application belongs to the technical field of semiconductor device modeling and EDA, and discloses a method for extracting parameters of a compact model of an anti-radiation SiGe HBT based on a physical mechanism. The method prepares a test structure array containing different geometric sizes and doping, obtains direct current / alternating current characteristics through multi-dose point irradiation of a 60Co gamma ray, establishes a logarithmic-linear or saturation exponential degradation equation based on an irradiation damage mechanism, embeds a standard MEXTRAM / HICUM model in the form of a Verilog-A subcircuit, adds a dose input pin, extracts degradation coefficients to construct a total dose-key parameter degradation mapping library, and integrates the library with an EDA tool to realize irradiation environment simulation. The application shortens the anti-radiation circuit design cycle from 6 months to 2 weeks, and the model-measured error is less than 5% after 1 Mrad irradiation, so the application is suitable for the design of anti-radiation integrated circuits such as spaceborne phased arrays and space communication.

The invention discloses a Verilog-based adaptive time-frequency aliasing interference identification method and system. The method comprises the following steps: acquiring a time-frequency aliasing signal; according to the prior carrier frequency and the sampling frequency of the target signal, the actual fuzzy frequency is dynamically calculated by using the HOBs-DEC algorithm; the method comprises the following steps: acquiring a power spectrum of a signal, identifying the number of effective spectral lines based on an actual fuzzy frequency and a preset threshold, and carrying out first classification on the signal: if the number of the effective spectral lines is not less than a first threshold, judging that the signal comprises an AM or single-carrier signal; otherwise, determining that the signal comprises a comb spectrum, MSK or Gaussian white noise signal; extracting a square spectrum characteristic of the signal, and identifying whether the signal is an AM signal or a single carrier signal; and extracting single spectrum and / or square spectrum characteristics of the signal, and identifying the signal as a comb spectrum, an MSK signal or a Gaussian white noise signal. According to the method, the processing speed of the recognition process can be improved, and the applicability and the stability in an actual scene are enhanced.

The present invention discloses a static concealment method and electronic device for a Latch PUF unit circuit in a chip. The method comprises: using the Verilog language to instantiate standard cells corresponding to an inverter, a buffer, a first multiplexer, a second multiplexer, a first NAND gate, and a second NAND gate; generating a circuit netlist for the Latch PUF unit circuit based on the standard cells; placing each standard cell based on the circuit netlist, interconnecting and routing each standard cell, and performing instruction adjustment after the interconnection routing to obtain a Latch PUF unit circuit; and randomly placing multiple Latch PUF unit circuits in a chip layout according to random coordinates. The method of the present invention can effectively eliminate the circuit characteristics and image characteristics of the Latch PUF, thereby reducing the possibility of being identified or located by an attacker and improving the security of the chip.

The application provides a Verilog generation verification method and device for a multi-modal circuit design specification, and relates to the technical field of artificial intelligence. The method comprises the following steps: acquiring a circuit code dataset, generating a first group of circuit pictures, using a large language model to perform natural language description, and constructing a multi-modal circuit dataset; a second group of circuit pictures is generated according to Python code, and a multi-modal general dataset is constructed; a multi-modal large language model is fine-tuned and trained; prompt words are customized for different tasks, a plurality of task agents are constructed according to the prompt words and the trained multi-modal large language model; a core interactive agent is designed, and the core interactive agent and the plurality of task agents are used to complete a circuit design, circuit verification and circuit knowledge question and answer task. The application can improve the circuit design verification accuracy and shorten the design verification time.

This invention provides an intelligent RTL code generation method and system based on MCP and Agent collaboration. The method involves: acquiring user-input circuit design requirements; initializing the Agent and large language model environment, configuring the Agent's role definition and system prompts; performing compilation and syntax checking; obtaining execution feedback results from EDA simulation tools to determine if compilation passed; generating a structured error correction report; the Agent receiving the structured error correction report and generating corrected Verilog RTL code; resubmitting the code until it passes compilation checks or reaches a preset iteration threshold. This invention significantly improves the compilability and correctness of generated code and reduces the threshold and cost of manual design by constructing an automated closed-loop process of "code generation – syntax checking – error parsing – iterative repair."

The application discloses a single-photon avalanche diode modeling method based on Verilog-A, which comprises the following steps: model parameter definition and initialization; judging the state of the single-photon avalanche diode, if the avalanche is closed, performing statistical model calculation, judging whether the avalanche state is opened according to the statistical model calculation result, if the avalanche is opened, performing electrical model calculation, updating the avalanche state according to the electrical model calculation result and the quenching threshold current based on Gaussian distribution, and outputting each current; the statistical model calculation comprises calculating the photon detection event time, the dark count event occurrence time and the post-pulse trigger time; the electrical model calculation comprises calculating the leakage current and the segmented avalanche current, and calculating the junction charge of the SPAD cathode-anode, the parasitic capacitance charge of the SPAD cathode-substrate and the parasitic capacitance charge of the SPAD anode-substrate, so as to calculate the corresponding current according to the charge-current relationship. The application can comprehensively reflect the working characteristics of the device.

The present disclosure relates to a computer-implemented method (200) and a system (100) for implementing a real-number System Verilog model of a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) for accelerated mixed-signal functional verification. The method (200) includes establishing (202) an Analog net including a Thevenin voltage and a Thevenin resistance at drain, source, and gate terminals of the MOSFET, and extracting (204) effective voltages and effective resistances from the drain, source, and gate terminals of the MOSFET. The method (200) includes establishing (206) a fast quadratic solver to compute drain to source MOSFET current, drain to source MOSFET voltage, and drain to source MOSFET resistance. The method (200) includes driving (208) feedback of the drain to source MOSFET current in terms of a drive voltage and a drive resistance to the Analog net, and attaining (210) a circuit convergence in real-time through an event-driven mechanism at a particular timestamp.

This invention discloses a method for input independence analysis of large-scale digital circuits based on BDD. The method converts the circuit Verilog file into a NAND graph (AIG) and performs logic optimization to extract the sets of input and output variables. It then converts the AIG network into a global BDD representation and reduces the number of nodes. A multivariate product term cube is constructed with respect to input groups S and X. The Boolean derivative of Di with respect to each input variable in input group S is calculated, and the result is logically ORed to obtain the synthesis sensitivity function diff_or_i. The method then performs the logical inverse operation and full quantization, extracts the specific logical assignment vector of input group L, and determines the independence of Di with respect to input group S. This method avoids the computational bottleneck of exponential complexity and still possesses good computational performance and scalability in large-scale digital circuits. Its independence determination results are unique and reliable, and it can be widely applied in scenarios such as logic synthesis, formal verification, security and testability analysis.

The invention discloses a large-scale digital circuit input independence analysis method based on BDD, and the method comprises the steps: converting a circuit Verilog file into a NAND graph AIG, carrying out the logic optimization, and extracting an input and output variable set; converting the AIG network into global BDD representation and reducing the number of nodes; constructing a multivariable product term cube about the input groups S and X; and calculating Boolean differential of the Di about each input variable in the input group S, carrying out logic OR operation on the result to obtain a comprehensive sensitivity function diffori, taking logic inverse operation and executing full-scale quantization, extracting a specific logic assignment vector of the input group L, and judging the independence of the Di about the input group S. The method avoids the operation bottleneck of exponential complexity, and still has good calculation performance and expandability in a large-scale digital circuit; the independence judgment result is unique and reliable, and the method can be widely applied to scenes such as logic synthesis, form verification, safety and testability analysis and the like.

The invention discloses a silicon controlled rectifier device Verilog-A modeling method based on a gating circulation unit. The method comprises the following steps of: 1, improving a GRU model according to an actual condition; 2, using TCAD simulation to describe the nonlinear transient response of the SCR device under the ESD stress condition, and generating a data set of a GRU neural network; 3, performing neural network training by using the improved GRU model in the step 1 and the data set generated in the step 2 to obtain a convergent GRU model; step 4, carrying out serialization on the converged GRU model trained in the step 3, and realizing the serialization by using Verilog-A; and step 5, evaluating the GRU neural network model realized in the step 4. According to the method, analysis on complex physical phenomena is avoided, high fitting precision is achieved, the model building efficiency is improved, the physical design of a circuit is completely fuzzy, and the method can be used as a modeling method for covering intellectual property.

The invention relates to an RTL level segmentation method and system for multiple FPGAs, the method and system are applied to the related technical field of the FPGAs, the FPGAs refer to Field-Program Gate Array, the RTL level refers to a Register Transfer Level register transfer level, and the method comprises the steps that an RTL design file is received and statically analyzed in detail to obtain an RTL design processing file and an RTL tree structure file; segmenting the RTL design processing file to obtain a segmentation result file comprising a plurality of segmentation areas; performing RTL segmentation on the RTL tree structure file to obtain a plurality of RTL file lists and boundary interconnection information corresponding to a plurality of segmentation regions; performing parallel synthesis according to the plurality of RTL file lists to obtain a plurality of comprehensive netlist Verilog files; binding the plurality of comprehensive netlist Verilog files by using a time division multiplexing channel according to the boundary interconnection information to obtain a plurality of bound netlist Verilog files and constraint files; and according to the plurality of binding netlist Verilog files and constraint files, carrying out top layer constraint and layout wiring, and then carrying out multi-FPGA verification. The technical effect of the invention is that the design code can be better verified on multiple FPGAs.

Disclosed in the present application are a circuit simulation verification method and apparatus, and an electronic device and a storage medium. The method comprises: using a hardware description language such as a Verilog-AMS modeling language to create a simulation model for a circuit device, wherein the simulation model is provided with a timer and several first simulation points, and the timer is used for generating second simulation points; acquiring an input signal of the current first simulation point and an input signal of the previous first simulation point during a simulation verification process; determining whether the input signal of the current first simulation point is the same as the input signal of the previous first simulation point; if not, controlling the timer to periodically generate second simulation points; and if so, controlling the simulation model to enter a sleep mode, wherein in the sleep mode, the timer stops generating second simulation points. The present application can reduce the number of simulation points while ensuring the simulation precision, and has a relatively high simulation speed.

The invention relates to a user datagram protocol (UDP) communication method realized based on a Vitis HLS, and belongs to the technical field of Ethernet. According to the invention, a UDP communication protocol is realized through Vitis HLS, a UDP communication module is designed on an FPGA by using a C + + high-level language, and the UDP communication module comprises a receiving module and a sending module. The receiving module and the sending module only realize partial protocols and functions used in use, including an ARP protocol, a Ping function based on an ICMP protocol, a UDP protocol and the like. Other unused protocols or functions can be further realized based on the design. According to the method, the module design of the FPGA is realized by using the Vitis HLS, so that the design efficiency can be improved, a designer does not need to master hardware description languages such as Verilog HDL and the like, and the development difficulty is reduced to a certain extent.