11 results about "Verilog" patented technology

This invention belongs to the field of triple mode redundancy (TMR) technology, and particularly relates to a selective TMR conversion method and system based on two-stage decoupling. The method includes acquiring the Verilog design code to be converted and parsing the circuit signals; calculating the dynamic activity of each circuit signal, dividing the circuit signals into critical and non-critical circuit signals, and forming a list of critical circuit signals; reading the list of critical circuit signals, traversing each assignment statement in the Verilog design code to be converted, and identifying whether the current circuit signal is a critical circuit signal; performing TMR operation on the identified critical circuit signals, and using logical assignment to make the replica signals track the original signals in real time for the identified non-critical circuit signals, thus completing the selective TMR conversion. This invention completely decouples the two stages of dynamic activity analysis of circuit signals and selective conversion of source code, and performs true / pseudo-TMR splitting processing.

This invention discloses a quality inspection method for compact transistor models based on machine learning, belonging to the field of semiconductor device modeling and EDA. The method includes: receiving a Verilog-A model file and a JSON configuration file defining geometric dimensions and simulation parameters; performing syntax checks and generating OSDI shared objects using the OpenVAF compiler; performing physical consistency verification, including the Gummel symmetry test (GST) and energy conservation checks; extracting device-level DC and AC characteristic indicators; and conducting circuit-level benchmark tests, determining model stability through simulation time and convergence of different unit circuits. This invention constructs a full-link automated evaluation framework from syntax to physical characteristics, effectively solving the problems of physical rationality and simulation convergence of machine learning models in integrated circuit design, and significantly improving model development efficiency and reliability.

The application belongs to the technical field of semiconductor device modeling and EDA, and discloses a method for extracting parameters of a compact model of an anti-radiation SiGe HBT based on a physical mechanism. The method prepares a test structure array containing different geometric sizes and doping, obtains direct current / alternating current characteristics through multi-dose point irradiation of a 60Co gamma ray, establishes a logarithmic-linear or saturation exponential degradation equation based on an irradiation damage mechanism, embeds a standard MEXTRAM / HICUM model in the form of a Verilog-A subcircuit, adds a dose input pin, extracts degradation coefficients to construct a total dose-key parameter degradation mapping library, and integrates the library with an EDA tool to realize irradiation environment simulation. The application shortens the anti-radiation circuit design cycle from 6 months to 2 weeks, and the model-measured error is less than 5% after 1 Mrad irradiation, so the application is suitable for the design of anti-radiation integrated circuits such as spaceborne phased arrays and space communication.

This invention provides an intelligent RTL code generation method and system based on MCP and Agent collaboration. The method involves: acquiring user-input circuit design requirements; initializing the Agent and large language model environment, configuring the Agent's role definition and system prompts; performing compilation and syntax checking; obtaining execution feedback results from EDA simulation tools to determine if compilation passed; generating a structured error correction report; the Agent receiving the structured error correction report and generating corrected Verilog RTL code; resubmitting the code until it passes compilation checks or reaches a preset iteration threshold. This invention significantly improves the compilability and correctness of generated code and reduces the threshold and cost of manual design by constructing an automated closed-loop process of "code generation – syntax checking – error parsing – iterative repair."

The application discloses a single-photon avalanche diode modeling method based on Verilog-A, which comprises the following steps: model parameter definition and initialization; judging the state of the single-photon avalanche diode, if the avalanche is closed, performing statistical model calculation, judging whether the avalanche state is opened according to the statistical model calculation result, if the avalanche is opened, performing electrical model calculation, updating the avalanche state according to the electrical model calculation result and the quenching threshold current based on Gaussian distribution, and outputting each current; the statistical model calculation comprises calculating the photon detection event time, the dark count event occurrence time and the post-pulse trigger time; the electrical model calculation comprises calculating the leakage current and the segmented avalanche current, and calculating the junction charge of the SPAD cathode-anode, the parasitic capacitance charge of the SPAD cathode-substrate and the parasitic capacitance charge of the SPAD anode-substrate, so as to calculate the corresponding current according to the charge-current relationship. The application can comprehensively reflect the working characteristics of the device.

The invention discloses a method, a device and equipment for predicting circuit performance of a transistor, relates to the technical field of computer aided design of integrated circuits and semiconductor devices, and aims to solve the problem that an existing compact model constructed based on TCAD simulation is difficult to accurately map real process fluctuation of a field effect transistor. And circuit-level power consumption and performance prediction results are not accurate. The method comprises the following steps: acquiring TCAD simulation data and actual measurement data of the field effect transistor; training a neural network model according to the TCAD simulation data to obtain a TCAD prior model; according to the measured data, a transfer learning method is adopted to carry out fine tuning on the TCAD prior model, and a target prediction model is obtained; and performing circuit-level simulation on the field effect transistor based on a Verilog-A compact model to obtain a circuit-level power consumption and performance prediction result. The method for predicting the circuit performance of the transistor is used for improving the circuit-level power consumption and the performance prediction result of the field effect transistor.

The application discloses a kind of based on SiP chip's transient radiation effect circuit level fault simulation system and method, including clock signal generation module, fault injection module, ADC simulation module, voltage comparator simulation module, FPGA simulation module, DAC simulation module and level driver simulation module;Clock signal generation module is connected with ADC simulation module, DAC simulation module and FPGA simulation module, and the output end of ADC simulation module and voltage comparator simulation module is connected with the input end of FPGA simulation module, and the input end of DAC simulation module and level driver simulation module is connected with the output end of FPGA simulation module;Each simulation module includes IBIS model and SPICE circuit level model / Verilog behavior level model;The present application establishes the SiP system level simulation model including each chip simulation module and signal transmission module in SiP interior.Given simulation model input signal and transient radiation excitation, the output signal of entire SiP system level simulation model can be obtained.

The application discloses a kind of based on Verilog's adaptive time-frequency aliasing interference identification method and system, method includes: collection time-frequency aliasing signal;According to the priori carrier frequency of target signal and sampling frequency, actual blur frequency is dynamically calculated using the proposed HOBs-DEC algorithm;Obtain the power spectrum of signal, based on actual blur frequency and preset threshold to identify the number of effective spectral lines, signal is classified for the first time: if the number of effective spectral lines is not less than the first threshold, then determine that signal includes AM or single carrier signal;Otherwise, determine that signal includes comb spectrum, MSK or Gaussian white noise signal;Extract the square spectral feature of signal, identify the signal as AM signal or single carrier signal;Extract the single spectrum and / or square spectral feature of signal, identify the signal as comb spectrum, MSK signal or Gaussian white noise signal.The method of the application can improve the processing speed of the identification process, enhance the applicability and stability in actual scene.

A gate-level netlist cross-clock domain automatic analysis method and system, through including simulation library automatic abstraction module, Verilog program analysis module, gate-level netlist clock tree and reset tree inference module, cross-clock domain feature identification module, violation display module, carries out Verilog language analysis, simulation library automatic abstraction, gate-level netlist clock tree inference, gate-level netlist reset tree inference, cross-clock domain feature circuit identification and violation display step, can analyze the cross-clock domain risk of programmable logic design gate-level netlist by the method of static analysis and accurately locate the design defects, improve the programmable logic design reliability.

The application discloses an arithmetic operation unit of independent carry register, and belongs to the technical field of computer processor design. A 64-base column structure is adopted, 8 bits of each column are equal to 6 data bits plus 2 carry bits, and 8 columns are simultaneously operated through a single 64-bit adder. The carry is stored in the independent register with the high 2 bits in the column, the carry register in the column embeds the carry in the data column, and the serial carry chain is eliminated. The parallel adder array uses 8 6-bit adders to work simultaneously, and there is no cascading dependence. A carry delay propagation circuit supports a configurable threshold, and the carry is temporarily not carried out during the operation process, and is processed in batches when needed. Compared with the traditional serial carry chain, the delay of the application is reduced by 8 times, the complexity is reduced from O(64) to O(8), the number of transistors is reduced by 77%, from 2300 to 532, the power consumption is reduced by 87.5%, the gate circuit flip is reduced from 64 levels to 8 levels, and parallel operation is supported throughout the process. The application is realized by using Verilog HDL, can be adapted to FPGA and ASIC, can integrate the existing CPU architecture, does not need to change the instruction set, the compiler is automatically optimized, and the program does not need to be adjusted.