1134 results about "Hardware acceleration" patented technology

A computer system implements a unified framework integrating an adaptive elastic funnel (AEF) with a convergent intelligence fabric (CIF) for multi-agent AI collaboration. The system provides a universal multi-modal key-value subsystem for sharing partial computations, implements hybrid placement strategies for dynamic memory management, and incorporates quantum-resistant secure enclaves. The architecture integrates hardware acceleration through GPU-FPGA hybrid caching and neuromorphic processors, applies adaptive energy and thermal management across hardware generations, and implements autonomous flash resource orchestration with multi-dimensional wear management. The system orchestrates tensor workflows using hierarchical scheduling, enables cross-agent collaboration with privacy preservation, and supports continuous learning without catastrophic forgetting. This integration delivers unprecedented computational efficiency and security in high-dimensional decision-making environments while supporting incremental adoption through modular interfaces.

The present invention relates to adaptive multi-state encoding and processing in virtualized computing environments. The system includes a virtualized state selection module that dynamically transitions between binary, ternary, quaternary, and higher-order encoding states based on workload, bandwidth, security posture, and compliance requirements. A virtual encoding engine utilizes hardware-accelerated components, such as vFPGAs, vGPUs, and cTPUs, to enhance encoding throughput. A compliance-driven feedback controller continuously monitors encoding efficiency, threat levels, and adherence to mandates such as GDPR, HIPAA, and FIPS 140-3. Additional features include AI-based anomaly detection, federated model refinement, distributed ledger-backed audit trails, and quantum-resistant encoding techniques. By integrating intelligent encoding decisions with scalable compliance enforcement, the system enables high-performance, secure, and regulation-ready data processing across distributed cloud and edge environments, delivering measurable improvements in system responsiveness, data integrity, and operational trust.

A new transaction barrier synchronization primitive enables executing threads and asynchronous transactions to synchronize across parallel processors. The asynchronous transactions may include transactions resulting from, for example, hardware data movement units such as direct memory units, etc. A hardware synchronization circuit may provide for the synchronization primitive to be stored in a cache memory so that barrier operations may be accelerated by the circuit. A new wait mechanism reduces software overhead associated with waiting on a barrier.

Technologies for configuring flexible hardware-accelerated rules in a Service Function Chaining (SFC) architecture are described. A DPU includes an acceleration hardware engine to provide a single accelerated data plane, and a processing device that generates a first virtual bridge and a second virtual bridge. The first virtual bridge is controlled by a first network service hosted on the DPU and has a first set of one or more network rules. The second virtual bridge has a second set of one or more user-defined network rules. The processing device generates a combined set of network rules based on the first set of one or more network rules and the second set of one or more user-defined network rules. The acceleration hardware engine processes network traffic data in the single accelerated data plane using the combined set of network rules.

Technologies for creating an optimized and accelerated network pipeline using a network pipeline abstraction layer (NPAL) for policy-based routing (PBR) over Service Function Chaining (SFC) are described. A DPU includes acceleration hardware engine to provide a single accelerated data plane. A processing device can generate a first virtual bridge and a second virtual bridge, the first virtual bridge to be controlled by a first network service hosted on the DPU and having a set of one or more network rules, and the second virtual bridge having a policy-based routing policy (PBR policy). The processing device can add the virtual port between the first virtual bridge and the second virtual bridge. The acceleration hardware engine, in the single accelerated data plane, can route network traffic data using the PBR policy and process the network traffic data using the set of one or more network rules.

The invention discloses a configurable number-theory transformation parallel computing acceleration method and device for a post quantum cryptographic algorithm, and relates to the technical field of cryptographic algorithms. The number theory transformation is a calculation bottleneck in lattice-based post-quantum cryptography and PQC; a hardware accelerator specially designed for number theory transformation (NTT) is an effective solution for improving the execution speed. At present, a mainstream design neglects the influence of the scale of a calculation array, so that the design of an NTT calculation circuit is poor in flexibility and low in memory utilization rate, and a two-dimensional reconfigurable number theory transformation acceleration circuit is provided; the method is applied to a key generation stage, an encryption stage and a decryption stage of the post-quantum cryptographic algorithm. The NTT reconfigurable computing circuit provided by the invention can keep the utilization rate of hardware resources, and is suitable for mobile terminal equipment with limited resources; the NTT circuit adopts a low-complexity memory mapping scheme, so that the address control logic is greatly simplified, and the hardware overhead is reduced.

A system and method for detecting anomalies in encrypted network traffic without decrypting encrypted payloads is disclosed. The invention comprises a hardware-accelerated pipeline including a packet acquisition unit configured to extract observable header attributes and timestamp values, a signal analysis unit implemented using digital signal processing circuitry to generate temporal and spectral characteristics of encrypted packet flows, and a morphometric extraction unit that produces encrypted-flow descriptors based on statistical dispersion, burst patterns, and ciphertext variability. A behavioral graph construction unit generates graph-structured representations of encrypted flows using incremental state-transition encoding. An artificial-intelligence inference unit employing a tensor-processing processor performs multi-stage anomaly analysis through temporal reconstruction, attention-based weighting of descriptors, and graph-structural deviation assessment to compute anomaly scores without decrypting any payload. A secure response control unit evaluates the scores against policy thresholds and performs mitigation actions while preserving confidentiality.

The invention relates to the field of artificial intelligence, in particular to an AI accelerator construction method and a related device. The method comprises the following steps: importing machine learning models of different AI frames through a multi-frame adaptation interface, and converting the machine learning models into linear algebraic dialect representation by adopting an MMIR dialect conversion chain; through target-independent optimization processing, core calculation semantics in linear algebraic dialects are reserved, and linear algebraic dialect representation is reconstructed into optimization intermediate representation with an efficient data flow structure; identifying target hardware characteristics of the target hardware; adaptively executing hardware optimization processing matched with target hardware characteristics on the optimization intermediate representation; and converting the target intermediate representation into a hardware operation unit executable by the target hardware, loading the hardware operation unit into the target hardware to obtain an AI accelerator, thereby running the hardware operation unit on the target hardware through the AI accelerator, scheduling corresponding computing resources in the target hardware, and completing hardware acceleration of the machine learning model.

The invention discloses a hardware accelerator and equipment oriented to triple sparse matrix multiplication and an application method thereof.The hardware accelerator comprises a high-bandwidth memory HBM, a crossbar switch network and an on-chip processing unit which are connected in sequence, and the on-chip processing unit comprises a hierarchical cache module, a global controller and a plurality of computing chips; each calculation piece comprises an RA calculation array, a TP calculation array and a local controller, wherein the RA calculation array and the TP calculation array are respectively used for executing front-end operation T = R * A and rear-end operation C = T * P in triple sparse matrix multiplication. The method aims at solving the problem that when a traditional universal processor processes triple sparse matrix multiplication, due to irregular memory access, uneven calculation load and sharp increase of middle parts and results, huge off-chip data carrying is confronted with serious performance and energy efficiency bottlenecks, and the calculation performance and energy efficiency of triple sparse matrix multiplication are improved.

The invention relates to the technical field of integrated circuit design and artificial intelligence hardware acceleration, and particularly discloses a quantization precision adaptive switching hardware acceleration architecture. Hardware is divided into a static area and a dynamic area, wherein the static area comprises a pre-processing module, a post-processing module, a control module and a reconfigurable logic loading control block which run all the time; the dynamic region bears a quantization and inverse quantization module composed of a plurality of reconfigurable logic units. The method is characterized in that a model precision instruction is analyzed through a control module, and a reconfigurable logic file with corresponding precision is dynamically loaded to a dynamic area from external starting equipment by a loading control block according to an internal address mapping table, so that seamless switching of different quantization precision is realized on the hardware level, and the whole chip does not need to be burnt again. According to the design, through a modularized and reconfigurable hardware structure, the limitation of fixed-precision hardware in coping with diversified AI models is effectively solved, and the deployment flexibility and energy efficiency are remarkably improved.

A self-optimizing and self-programming computing system (SOSPCS) design framework that achieves both programmability and flexibility and exploits computing heterogeneity [e.g., CPUs, GPUs, and hardware accelerators (HWAs)] is provided. First, at compile time, a task pool consisting of hybrid tasks with different processing element (PE) affinities according to target applications is formed. Tasks preferred to be executed on GPUs or accelerators are detected from target applications by neural networks. Tasks suitable to run on CPUs are formed by community detection to minimize data movement overhead. Next, a distributed reinforcement learning-based approach is used at runtime to allow agents to map the tasks onto the network-on-chip-based heterogeneous PEs by learning an optimal policy based on Q values in the environment.

The invention discloses a high-speed data processing and exchanging method and system based on Zynq UltraScale + MPSoCs, and belongs to the technical field of data processing.The method comprises the steps that nanosecond-level synchronous pulses are generated through a PL end of Zynq, initial multi-modal data are collected, the transmission rate and integrity are analyzed through a double-SERDES controller of the PL end, and a dynamic data processing matrix is constructed; pL and PS end data flow distribution is simulated and optimized through a preset multi-data granularity scale, and an exchange instruction set is generated; in combination with an on-chip bus topology, a first data exchange path is formed through DMA-OCM interaction and hardware accelerator adaptation, and a second data exchange path is obtained by adjusting sub-channel allocation and bus priority; and the operation state parameters of the second data exchange path are written back to the data frame state attribute bar corresponding to the dynamic data processing matrix in real time, so that efficient processing and dynamic optimization of the multi-modal data are realized, and the system stability and the transmission efficiency are improved.

A neural-symbolic hybrid system for generating binary document formats directly from natural language input comprises a binary-aware hierarchical tokenizer operating across four levels (binary bytes, structural elements, semantic content, and concepts), a constraint satisfaction engine with 64 parallel processing cores for enforcing structural integrity and mathematical consistency, format-specific processors for Excel, PowerPoint, PDF, and CAD documents, and a formal verification system generating mathematical proofs of correctness. The system includes custom AI Document Generation Processor (AIDGP) silicon spanning 600 mm2 with specialized cores providing 500 TOPS processing power. Performance characteristics include 99.7% structural accuracy, 100% format compliance, 15.3 second average generation time for complex documents, and distributed capacity of 1,000,000 documents per hour. The system eliminates intermediate conversion steps while maintaining semantic preservation through hardware-accelerated constraint satisfaction and formal verification engines ensuring structural integrity, format compliance, and security through AES-256 encryption and automated regulatory compliance across 25+ international standards.

The invention discloses a pulse neural network hardware accelerator and a data processing method, and the accelerator is characterized in that a low-power-consumption three-stage pipeline CPU module is used for receiving input data, scheduling an SNN network acceleration instruction, and sending the input data to an asynchronous edge SNN hardware accelerator module through a coprocessor interface; the asynchronous edge SNN hardware accelerator module comprises a pulse data encoding and decoding module, L neuromorphic kernels and an on-chip network, the pulse data encoding and decoding module encodes input data into a pulse form and sends the pulse form into the neuromorphic kernels, and the neuromorphic kernels are used for performing calculation based on the data in the pulse form; the network-on-chip is used for communication between the neuromorphic kernels, and the connection between neurons before and after synapses in the neuromorphic kernels is realized by adopting a synaptic cross array. According to the invention, the data processing acceleration performance can be greatly improved.

The invention aims to provide a SiamFC-pytorch tracking model pre-processing and post-processing acceleration method and a SiamFC-pytorch tracking model pre-processing and post-processing acceleration system based on an NPU (Network Processing Unit). The system is realized based on a Yulong810SOC, and comprises a video input module (1), a hardware decoding module (2), a detection module (3), a tracking module (4) and a turntable control module (5), the method comprises the following steps: a, a video input module receives a video stream, and the video stream is decoded into an original image in a YUV format through a hardware decoding module; b, the detection module runs a YOLOv5 model through a neural network engine of the NPU; c, an NPU pre-processing and post-processing unit of the tracking module executes template branch pre-processing, search branch pre-processing and search branch post-processing on the YUV image and the target initial bounding box; and d, the turntable control module adjusts the posture of the camera turntable according to the real-time coordinates of the target. The method is applied to the technical field of computer vision and artificial intelligence hardware acceleration.

The invention discloses a generative AI model real-time rendering engine construction method and related equipment thereof, and relates to the technical field of man-machine interaction, and the method comprises the steps: obtaining multi-modal semantic information input by a user, and converting the multi-modal semantic information into a patent vector and a constraint parameter; constructing a lightweight generation model, and directly generating a renderable intermediate representation by adopting the lightweight generation model; constructing a rendering pipeline based on the generated intermediate representation, and converting the intermediate representation into a visual image; capturing user operation in real time, dynamically updating constraint conditions of a generated model, triggering increment generation, and optimizing system performance by adopting a model lightweight, hardware acceleration and hybrid rendering strategy; through the time filtering and space constraint technology, the generated content is consistent in time and space. According to the method, the problems of low generation speed and low rendering efficiency in the fusion process of the generative AI model and the real-time rendering engine are solved, and the efficiency and quality of visual image generation and rendering are improved.

The invention provides an unmanned aerial vehicle six-degree-of-freedom hardware acceleration IP core implementation method and electronic equipment, and belongs to the technical field of calculation acceleration, and the method comprises the steps: packaging a six-degree-of-freedom kinematics equation of an unmanned aerial vehicle and parameters thereof to form an IP core; an IP core is loaded on the FPGA; the six-degree-of-freedom calculation of the unmanned aerial vehicle is carried out on the FPGA through the loaded IP core, and the calculation period of the six-degree-of-freedom of the unmanned aerial vehicle is controlled based on the clock period of the FPGA. According to the invention, the six-degree-of-freedom calculation period of the unmanned aerial vehicle is controlled through the clock period of the FPGA, so that the updating process from the input data of the IP core to the output data of the IP core is a fixed period and does not fluctuate along with the change of the input data or the calculation state; therefore, the technical problem of serious periodic jitter during six-degree-of-freedom calculation of the existing unmanned aerial vehicle is solved, and the credibility and the control stability of the simulation model are improved.

The invention relates to the technical field of fuel cell monitoring and health management, and discloses an intelligent cooperative high-power proton exchange membrane fuel cell life prediction and fault diagnosis method and system, and the method comprises the following steps: S1, collecting multi-dimensional data of a stack key region in real time through a distributed sensing array; s2, removing noise and abnormal values of the collected data, and carrying out feature extraction; s3, constructing a dual-model collaborative prediction framework; s4, inputting the real-time features into the double models; s5, generating a maintenance strategy and early warning; according to the invention, special hardware accelerators such as a graphic processing unit or a field-programmable gate array are integrated on the edge computing module, so that the processing speed and efficiency of high-frequency and multi-source sensor data at a local end are remarkably improved; a distributed computing framework is adopted in a cloud analysis module to process mass feature data transmitted by an edge end, so that the capability and scale of the system for performing deep analysis on the health state of the fuel cell, accurately predicting the remaining service life and quickly tracing the fault are enhanced.

An apparatus to facilitate hardware acceleration of resource barriers in a graphics environment is disclosed. The apparatus includes resource barrier hardware circuitry for processing cores and a graphics pipeline to: receive a resource barrier instruction to transition a resource utilized by the graphics pipeline from a first usage to a second usage; responsive to the resource barrier instruction, cause a draw group marker having a current draw group count to be sent to an end of the graphics pipeline to track completion of each stage of the graphics pipeline; increment the current draw group count to a new draw group count for each new draw group of the graphics pipeline; and determine that a current signal stage of the graphics pipeline is complete for a current draw group responsive to a done count for the current signal stage being less than or equal to the current draw group count.

A hardware accelerator including tiles arranged in a systolic array. At each of the tiles, the systolic array receives a first input block that includes first input matrix elements of a first input matrix. In each of a plurality of multiplication iterations, at each of the tiles, the systolic array receives a respective second input block. The systolic array computes tile products of the first input matrix elements and second input matrix elements included in the second input blocks. The systolic array adds the tile products to column-wise partial sums and transmits the column-wise partial sums to subsequent tiles along accumulator rings included in array columns of the systolic array. In a subset of the multiplication iterations, the systolic array outputs product block rows of a product matrix. The product block rows each include product matrix blocks computed as rows of the column-wise partial sums.

The invention provides a memory management method, a memory controller and an effective data positioning circuit unit. The method comprises the following steps: determining a plurality of candidate virtual blocks according to respective valid data count values of a plurality of virtual blocks; obtaining a mapping table bitmap corresponding to each candidate virtual block, determining a plurality of target virtual blocks based on the mapping table bitmaps, and generating a corresponding integrated mapping table bitmap; obtaining one or more sub-mapping tables according to the integrated mapping table bitmap; and generating an effective data table according to the physical address in the sub-mapping table and the physical address contained in the target virtual block. According to the method, the candidate objects for garbage collection are subjected to secondary screening in a hardware acceleration mode to determine the optimal target combination, and the mapping relation of the candidate objects is integrated to obtain the physical address of the corresponding effective data, so that the effective data table is made to improve the efficiency of garbage collection operation, and the reading burden of a storage device is reduced.

The invention belongs to the technical field of energy storage, and particularly relates to a portable energy storage power supply offline grid-connected detection and expansion system, which comprises a power grid access module, a multi-rate power grid state detection module, a central control module, a self-adaptive isolation module, an energy management module, an expansion battery interface module and a man-machine interaction and communication module, the multi-rate power grid state detection module is used for providing ultra-fast response to power grid transient abnormity and accurate monitoring of power grid steady-state parameters at the same time, and comprises a transient abnormity rapid detection sub-module and a comprehensive parameter accurate detection sub-module. And the self-adaptive isolation module is directly associated with the transient abnormity rapid detection sub-module. Through a hardware acceleration detection mechanism of the transient abnormity rapid detection sub-module and a high-speed solid-state relay array of the self-adaptive isolation module, the system can respond to transient overvoltage, rapid frequency deviation or zero crossing abnormity and complete isolation action.

The invention discloses a traffic incident detector system based on a domestic intelligent DSP and a detection method. The system comprises a video acquisition unit, a data exchange and storage unit, an intelligent processing core and a communication interaction unit. The intelligent processing core adopts a heterogeneous SoC chip integrating a multi-core DSP, an NPU and an FFT hardware acceleration module, the FFT module is responsible for video frame frequency domain enhancement, the NPU runs a deep learning model to carry out target detection, and the multi-core DSP executes multi-target parallel tracking and event judgment. And the data exchange and storage unit supports direct carrying of data among the modules through a unified physical address space and a DMA mechanism. The method comprises the following steps: carrying out NPU target detection on a video subjected to environment self-adaptive preprocessing; a multi-core DSP is used for tracking a target in parallel and judging an event; and finally, alarm information is generated and reported. Through heterogeneous hardware division and software and hardware cooperation, high-real-time and high-precision edge analysis is realized, and the detection reliability is improved.

The invention relates to a reconfigurable multi-channel polynomial multiplier architecture and an implementation method thereof, and belongs to the technical field of post-quantum cryptography hardware acceleration. The architecture comprises a scheduler, a twiddle factor memory bank, a bank address routing module, a bank array and a reconfigurable butterfly unit array. According to the architecture, a cyclic decoupling multi-channel NTT / INTT / PWM algorithm is used, flexible configuration of the degree of parallelism and the flow line depth can be supported, and the adaptability of a memory access control strategy is improved; a conflict-free memory mapping scheme based on interleaved storage is adopted, so that storage and read-write of polynomial coefficients are irrelevant to polynomial length and a calculation stage, NTT / INTT / PWM access modes are unified, and hardware resource overhead is greatly reduced; and a conflict-free detection algorithm oriented to multi-channel assembly line design is adopted, so that the utilization rate of hardware resources is remarkably improved.

The invention belongs to the field of machine learning, discloses an expert parallelism processing method and system for a large language model based on MoE, and realizes efficient parallel processing of the MoE model by dynamically distributing expert quantization bit width and sparse mode, predicting and prefetching to-be-activated expert parameters, grouping tokens to generate task queues and dynamically configuring hardware accelerators. Firstly, an importance score is calculated based on expert historical activation frequency, weight distribution and a model structure, so that quantization precision and a sparse proportion are adaptively allocated, and resource waste and precision loss of a unified strategy are avoided; secondly, predicting an expert to be activated by using a current layer hidden state and a historical activation sequence, loading parameters to a special cache in advance, reducing high-bandwidth memory access, and relieving bandwidth peak scrambling; moreover, tokens are grouped through a token-expert mapping table, a task queue is created, and dynamic configuration of a systolic array is combined, so that the problem of expert heterogeneity after compression is solved, and efficient and parallel hybrid precision matrix operation is ensured.

The invention discloses a transformer substation safety risk prediction and alarm system based on edge calculation, and belongs to the technical field of power system safety monitoring. The system comprises a sensing layer equipment group, an edge computing device, a cloud edge collaborative management platform and an intelligent alarm linkage system. The sensing layer equipment group acquires multi-source data in real time through a broadband current transformer, an ultrahigh frequency partial discharge detection array and a micro-meteorological monitoring module; the edge computing device performs local risk prediction by adopting a lightweight model generated by knowledge distillation, and realizes millisecond response in combination with FPGA hardware acceleration; the cloud edge collaboration platform realizes model dynamic optimization through federated learning and incremental updating; and the intelligent alarm system triggers a light stripe coding alarm and priority instruction sequence based on the multi-source fusion confidence coefficient. The problems that a traditional system is lagged in response, slow in model updating, difficult in multi-source data fusion, weak in privacy protection and the like are solved, and real-time prediction and accurate disposal of the safety risk of the transformer substation are achieved.

The invention provides a multi-magnetic accurate positioning method based on APSO-LM fusion, and solves the technical contradictions that global search and local convergence are unbalanced and the resolving efficiency is low in the existing multi-magnetic accurate positioning technology. The method comprises the following steps: constructing a magnetic moment calibration module, selecting a sensor array calibration point, collecting magnetic field data, and calculating a precise magnetic moment amplitude based on a magnetic dipole model; an NSS-VMGT initial positioning result is input through a parameter initialization module, APSO and LM algorithm parameters are configured, and particle vectors are normalized; generating a particle swarm by using an APSO global search module, and iteratively screening a global optimal parameter as an LM initial value; calculating a residual error and a Jacobian matrix by means of an LM local refining module, and iteratively optimizing and outputting a magnetic source position and a magnetic moment; and the dynamic compensation module is used for calibrating clock skew and inhibiting environment interference. The device is realized based on STM32H743, and comprises a 7 * 7 lis2mdltr sensor array, a dual-chip data acquisition link, an APSO-LM algorithm hardware acceleration module and an upper computer interaction unit.

The invention discloses a wound tissue imaging and auxiliary diagnosis system, which belongs to the technical field of wound tissue detection and comprises a hardware platform and an upper computer system. The hardware platform comprises a data acquisition module, a preprocessing and fusion module and a communication and control module; and the upper computer system is used for receiving the protocol packet and carrying out data analysis, coordinate system alignment and multispectral image waveband registration. According to the wound tissue imaging and auxiliary diagnosis system, a heterogeneous computing architecture is adopted, FPGA assembly line processing and ARM control are combined, power consumption and the size are remarkably reduced, and high-precision wound detection and real-time decision support are achieved through multispectral and three-dimensional data fusion, hardware acceleration preprocessing and AI driving analysis.

The invention relates to the technical field of space flight and aviation, in particular to a low-delay communication control system and method for an analog machine in a fixed flight training course. The control system comprises a multi-source sensor fusion module, a data simplification processing module, a dynamic time delay optimization communication framework, a distributed intelligent decision-making terminal, a virtual-real mapping synchronous controller, a milli delay regulation and control module and an intelligent sensing alarm interaction module. According to the invention, 4G, 5G and satellite double links are integrated, an optimal link is dynamically selected by adopting a Q-Learning algorithm, millisecond-level time delay control is realized, transmission reliability is improved through a packet loss rate compensation algorithm, multi-sensor data is fused based on an FPGA hardware accelerator and an EKF algorithm, and a data compression ratio is improved in combination with Huffman coding and Kalman filtering. The bandwidth requirement is greatly reduced, through software and hardware collaborative optimization, the end-to-end time delay is reduced to be within hundreds of milliseconds, the virtual-real synchronization precision is improved to the centimeter level, and the decision response speed is improved by two times.

The invention provides a control structure of a rope-driven dexterous hand, the rope-driven dexterous hand and a robot, and relates to the field of robotics.The control structure comprises a master-slave driver, the master-slave driver comprises a master control chip and a plurality of slave control chips connected with the master control chip, each slave control chip is integrated with an FOC algorithm hardware acceleration module, and the FOC algorithm hardware acceleration module is connected with the master control chip. Wherein the number of the slave control chips is equal to that of finger driving motors of the rope-driven dexterous hand, the slave control chips and the finger driving motors are in one-to-one correspondence, and each slave control chip is connected to the corresponding finger driving motor through one three-phase full-bridge driver.