1863 results about "High bandwidth" patented technology

The invention discloses a power distribution fusion terminal real-time video reasoning method based on an SDNN, relates to the technical field of intelligent power grid monitoring, and aims to solve the problems of high delay, high bandwidth consumption, low power consumption and the like caused by insufficient utilization of computing power resources of an existing power distribution terminal and dependence on a cloud on video processing in the prior art. And the problem of poor adaptability of the model in a complex power grid scene is solved. Firstly, a power grid special sample library is constructed, and data quality is optimized through time domain key frame extraction and a stratified sampling mechanism; carrying out enhanced training on the lightweight model by adopting transfer learning and multi-modal confrontation; designing an intermediate representation conversion and hierarchical caching mechanism to realize efficient model compiling and heterogeneous hardware deployment; edge-side real-time reasoning is realized based on dynamic frame sampling and statistical threshold detection; finally, a self-adaptive feedback closed loop is driven through reinforcement learning, and incremental updating of the model and dynamic allocation of resources are achieved. The real-time performance of power distribution equipment anomaly detection is remarkably improved, and meanwhile the model memory occupancy rate is reduced.

The invention belongs to the field of artificial intelligence, and discloses a scheduling strategy selection large model training method based on reinforcement learning, and the method comprises the steps: constructing a virtualized cluster environment; generating training data; carrying out large model base pre-training; learning environment interaction is reinforced; performing priority experience playback training; performing near-end strategy optimization; carrying out multi-expert strategy distillation; policy security verification is carried out; carrying out progressive online deployment; and feedback driving continuous optimization is carried out. According to the method, the resource topology, the task portrait and the dynamic load feature are decomposed to the special agent, and structured semantic tags such as a high-bandwidth demand task and a critical overheat node are generated, so that the heterogeneous resource state recognition accuracy is improved by 40%, and the multi-dimensional feature fusion efficiency is improved by 35%.

The invention belongs to the technical field of radars, and discloses a vehicle-mounted multi-source radar converged communication system based on a FlexRay bus and a synchronization method of the vehicle-mounted multi-source radar converged communication system based on the FlexRay bus. The FlexRay communication bus supports a static and dynamic dual-channel structure and has a deterministic communication capability, and the maximum bandwidth can reach 10Mbps; the distributed radar controller is connected with each radar node and used for collecting local radar data, packaging timestamps and uploading the data through FlexRay; the time synchronization controller is used for realizing nanosecond synchronization through a FlexRay global clock mechanism and broadcasting clock signals to all radar nodes; the fusion processing unit is used for intensively receiving all radar data and carrying out target detection and data fusion based on a unified time sequence; and the main control coordination module is used for upwards communicating with the automatic driving domain controller and downwards uniformly coordinating the behaviors of the subsystems. The system has the capabilities of accurate time sequence, multi-source data fusion, fault-tolerant control and the like, and is a high-reliability communication platform supporting intelligent driving decision making.

The invention provides a GNSS (Global Navigation Satellite System) anti-interference receiver system based on radio frequency front end-INS (Inertial Navigation System) combined assistance, which adopts a dual-core ARM Cortex-A9 and a programmable logic unit for layered decoupling, and realizes real-time receiving and processing of a high-bandwidth data stream, closed-loop control of an interference suppression link and quick response of a navigation path and a strategy decision. All the modules efficiently cooperate through AXI-Lite register mapping, interrupt signals, a shared state buffer area and a timer synchronization mechanism. By controlling bus and state buffer mapping to keep consistency and supporting a module-level independent debugging and system-level soft reset mechanism under hot start, the expandability of subsystem cascade debugging, fault module positioning and online updating is realized. In the aspects of module architecture, data channels and cooperation mechanisms, the structure order, efficient communication and control closed loop are realized, and an embedded multi-module cooperation anti-interference platform which is suitable for a high-interference environment, multi-channel fusion processing and navigation task real-time response is constructed.

The invention relates to the technical field of power distribution station supervision, in particular to an intelligent auxiliary and artificial intelligence visual gateway control method and system for a station building, which monitors network state parameters in real time, calculates a network quality score and dynamically selects an optimal transmission path based on a reinforcement learning algorithm. Comprising a high bandwidth mode, a low delay mode and a disaster recovery backup mode, stage processing and dynamic compression are performed on transmission data according to data types and network quality scores, link switching and a local caching mechanism are automatically triggered when a network is abnormal, and finally, multi-gateway load balancing and visual monitoring are realized through a software defined network architecture. The problem of transmission delay or interruption caused by the fact that a static data transmission framework cannot adapt to network state changes in the prior art is effectively solved, and the reliability and the real-time performance of data transmission are remarkably improved through dynamic path optimization, intelligent hierarchical transmission and a fault self-healing mechanism.

The invention relates to the technical field of motor detection, and discloses a motor instantaneous torque measurement method and system based on a high-bandwidth sensor, and the method comprises the steps: synchronously collecting a torque signal and a multi-source interference variable through the high-bandwidth sensor, and forming an original torque sequence after time synchronization superposition; extracting disturbance frequency characteristics through multi-scale wavelet transform and spectral analysis; a pre-trained adaptive filter model is utilized to generate a filter coefficient matched with the working condition, and primary filtering is completed; residual fluctuation is suppressed in combination with Kalman state estimation, and an optimized torque estimation value is obtained; parameter self-adaptive compensation is realized through online calibration weight updating, and a stable torque measurement sequence is output; load abrupt change pre-judgment and threshold value dynamic updating are achieved based on time-frequency correlation analysis, and finally rapid measurement convergence after working condition abrupt change is ensured through a closed-loop reset mechanism. According to the method, the problem of low instantaneous torque measurement precision in the prior art can be solved.

The invention provides a DCU-based high-performance sparse stiffness matrix vector multiplication method, which comprises the following steps of: according to a sparse stiffness matrix, dividing a non-zero element into a plurality of calculation unit blocks by rows, pre-loading non-zero element data to an L1 shared memory or a register file through an on-chip shared memory controller of the DCU, a high-bandwidth crossbar switch of the DCU is used for realizing data copying and transmission; starting multi-row fusion execution for a short row of which the row non-zero element is lower than a DCU single-instruction multi-data width threshold value; constructing a wavefront scheduler based on a DCU asynchronous computing engine: binding an independent instruction cache region for each wavefront, and loading a multiply-add operation instruction set in advance through a prefetch instruction queue; a calculation unit state register is established, and when a wavefront scheduler ready signal is triggered, a scalar unit of the DCU is activated to execute calculation; and realizing cross-thread block reduction by adopting a DCU atomic operation accelerator. According to the method, the calculation throughput and the memory bandwidth utilization rate of large-scale structural mechanics stiffness matrix vector multiplication are effectively improved.

The invention discloses a memory prefetching control method and device, a storage medium and a program product, and relates to the technical field of computers. A heterogeneous logic model covering multiple access modes is constructed, a prefetch strategy candidate set is generated based on standard logic models corresponding to different access modes, the expression limitation of a single model on complex multi-mode access features is broken through, and access laws in different scenes can be comprehensively covered; through calculation, sorting and screening of the prefetch cost, targeted evaluation of the strategy is realized, bandwidth load aggravation and resource waste caused by redundant prefetch are avoided, and optimization of the target prefetch strategy in the aspects of low delay and high bandwidth utilization rate is ensured. According to the method and the device, the problems that a fixed logic model is difficult to adapt to dynamic diverse memory access behaviors and resource utilization is low in efficiency in the prior art are solved, and the technical effects that the method does not need to depend on fixed logic, can dynamically adapt to the change of the access mode through flexible combination and strategy screening of heterogeneous models, and is particularly suitable for terminal equipment with limited resources are achieved.

Stacked devices and methods of fabrication are provided. Die-to-wafer (D2W) direct-bonding techniques join layers of dies of various physical sizes, form factors, and foundry nodes to a semiconductor wafer, to interposers, or to boards and panels, allowing mixing and matching of variegated dies in the fabrication of 3D stacked devices during wafer level packaging (WLP). Molding material fills in lateral spaces between dies to enable fan-out versions of 3D die stacks with fine pitch leads and capability of vertical through-vias throughout. Molding material is planarized to create direct-bonding surfaces between multiple layers of the variegated dies for high interconnect density and reduction of vertical height. Interposers with variegated dies on one or both sides can be created and bonded to wafers. Logic dies and image sensors from different fabrication nodes and different wafer sizes can be stacked during WLP, or logic dies and high bandwidth memory (HBM) of different geometries can be stacked during WLP.

A photonic integrated circuit (PIC) disposed on a substrate and comprising a semiconductor die hosting an active portion and a passive portion mutually coupled, the active portion being configured to consume electrical power when activated, and the passive portion comprising an optical transmission medium configured to propagate an optical signal to or from the active portion of the PIC; an electronic integrated circuit (EIC) electrically coupled to the active portion of the PIC and comprising components that electrically operate on the active portion of the PIC; and a packaging compound at least partially encapsulating the PIC, the packaging compound defining a cavity on a side of the semiconductor die that is opposite from the substrate, the cavity being filled with an optically transparent medium such that the optical signal can be received from or transmitted to the passive portion of the PIC through the cavity.

The invention relates to the field of edge computing data security, in particular to an integrity auditing method and system in an edge computing environment. The problem that an existing cloud auditing model is high in delay and large in bandwidth consumption in an edge scene is mainly solved. A lightweight audit challenge is generated through random sampling, data block aggregation operation is executed at an edge node, Merkel Hash tree path evidence is extracted, and integrity proof of dual verification is formed; and the aggregated evidence and the path evidence are verified by using bilinear mapping, so that efficient and credible auditing is realized. Dynamic data updating and accurate positioning of damaged blocks are supported, communication overhead is remarkably reduced, and real-time credibility of edge data is guaranteed.

The invention relates to the technical field of satellite network communication, and discloses a multi-source multi-path scheduling method for remote sensing data transmission, which comprises the following steps of: firstly, establishing an index table for remote sensing data by using a space-time name formed by a service type, an acquisition area, acquisition time, a node identifier and a data category; and the controller analyzes time and space constraints in the request, selects a plurality of source nodes meeting conditions from an index table, calculates priorities according to parameters such as residual bandwidth, round-trip delay and packet loss rate, and selects a plurality of non-overlapping high-quality paths. And then adding a service type, a path number, a path state report and a flow proportion field in the interest packet and the data packet, so that the source node sends segmented data in parallel according to a preset proportion. And the forwarding node reports the link change in real time, and the controller dynamically adjusts the path set and the shunt weight, thereby ensuring that the high-bandwidth and low-delay data transmission performance is continuously obtained in a topology and load rapid change scene.

The invention discloses a vehicle-mounted communication system based on a distributed architecture and a vehicle, and relates to the technical field of communication, a plurality of edge computing devices are respectively configured as root ports and end nodes, and high-speed connection between the root ports and the end nodes is realized by utilizing a PCIe switch, so that the characteristics of high bandwidth and low delay of PCIe can be fully utilized, and the communication efficiency is improved. The data transmission efficiency is greatly improved, so that the fluency of the vehicle-mounted computing platform in processing a large amount of data is guaranteed, the root port is provided with the shared storage space, the root port and the end node can directly perform data transmission in the shared storage space through the PCIe switch, intermediate links of data transmission are further reduced, and the transmission delay is reduced. Therefore, the problem that the communication efficiency is reduced due to the fact that blocking is prone to occurring under the condition of large-batch data throughput under communication interconnection of the Ethernet can be solved, and the technical effect of improving the communication efficiency is achieved.

The invention discloses a DC fault arc identification method and device based on a wavelet transform algorithm, and the method comprises the steps: collecting a DC line current signal through a high-bandwidth current sensor, carrying out the digitalization of a signal conditioning circuit and a high-speed ADC, and sequentially carrying out the preprocessing of the elimination of baseline drift through differential filtering and the suppression of specific frequency interference through adaptive notch; performing 3-8-layer multi-scale decomposition on the pure signal by adopting a Daubechies wavelet basis, preferably selecting high-frequency detail coefficients from the first layer to the third layer, and creatively fusing a multi-scale energy entropy representing energy distribution randomness and a time domain kurtosis representing transient impact to form a composite characteristic quantity; a threshold value (threshold value = mean value + adaptive coefficient * standard deviation) is dynamically generated based on sliding time window historical data, the adaptive coefficient is dynamically adjusted according to the load type, the resistive load is 1.8-2.2, and the inductive / capacitive load is 2.5-3.5; and when the composite characteristic quantity exceeds a threshold value and the sample proportion is greater than or equal to 85% within the duration of 0.5-5ms, a tripping execution mechanism is triggered.

Package structure with folded die arrangements and methods of fabrication are described. In an embodiment, a package structure includes a first die and vertical interposer side-by-side. A second die is face down on an electrically connected with the vertical interposer, and a local interposer electrically connects the first die with the vertical interposer.

An apparatus using in-memory compute (IMC) chiplet devices for inference-time compute acceleration. The apparatus is configured to accelerate the workload computations for neural network models, such as those for Large Language Models (LLMs) and reasoning models. The apparatus achieves high throughput and low latency using a chiplet design, digital IMC (DIMC) based engines, efficient die-to-die (D2D) interconnects, block floating point (BFP) numerics, and large high bandwidth on-chip memories. With modular chiplets and efficient interconnects, the accelerator apparatus can be easily scaled to accelerate workloads for models of different sizes. The DIMC configuration within the chiplet slices also improves computational performance and reduces power consumption by integrating computational functions and memory fabric. And by dynamically switching between precision levels based on real-time analysis of a target workload, computational efficiency can be optimized while maintaining the necessary level of accuracy for each step of the workload computation.

The invention discloses a hardware accelerator and equipment oriented to triple sparse matrix multiplication and an application method thereof.The hardware accelerator comprises a high-bandwidth memory HBM, a crossbar switch network and an on-chip processing unit which are connected in sequence, and the on-chip processing unit comprises a hierarchical cache module, a global controller and a plurality of computing chips; each calculation piece comprises an RA calculation array, a TP calculation array and a local controller, wherein the RA calculation array and the TP calculation array are respectively used for executing front-end operation T = R * A and rear-end operation C = T * P in triple sparse matrix multiplication. The method aims at solving the problem that when a traditional universal processor processes triple sparse matrix multiplication, due to irregular memory access, uneven calculation load and sharp increase of middle parts and results, huge off-chip data carrying is confronted with serious performance and energy efficiency bottlenecks, and the calculation performance and energy efficiency of triple sparse matrix multiplication are improved.

The invention relates to the technical field of Internet of Things communication transmission, and discloses an Internet of Things data intelligent transmission method and system, and the method comprises the steps: abstracting the performance of a multi-source heterogeneous link through a software defined network controller, dynamically generating a slice template, carrying out the traffic marking and priority scheduling, constructing a multi-path target constraint optimization model, and carrying out the optimization of the multi-path target constraint optimization model. And in combination with a network function virtualization mechanism, multi-level intelligent transmission is implemented at edge nodes, and a final transmission control instruction is generated. In the prior art, in a heterogeneous multi-network environment, low-delay, high-reliability and high-bandwidth transmission cannot be guaranteed at the same time, and especially in an industrial automation scene, technical problems that a control instruction is easy to delay and a monitoring data bandwidth is limited exist. According to the invention, the overall transmission reliability and bandwidth utilization efficiency are improved through the dynamic priority traffic scheduling based on network slices, the multipath reliability product model and the dynamic batch processing and progressive compression technology based on real-time link feedback.

The invention discloses a single crystal turbine blade crystal orientation defect detection system based on adaptive optics, particularly relates to the field of nondestructive testing, and is used for solving the problem that thermal damage and signal consistency are difficult to consider in acoustic imaging of complex structural parts. Through partition energy threshold setting, dynamic pulse planning, photoacoustic processing and unified coordinate cross-subarea data synthesis, local thermal damage caused by excessive concentration of energy is effectively avoided in the material detection process, and the requirement for collecting high-bandwidth signals can be met in a large range. The signal-to-noise ratio and the detection efficiency are improved by regulating and controlling pulse energy and a scanning path, the amplitude comparability and the image coherence among regions are ensured through signal normalization correction and subregion image set splicing, high-resolution and comprehensive-coverage acoustic mapping is output, the crystal orientation defects of the single crystal turbine blade are positioned and evaluated, the detection precision is improved, the measurement period is shortened, and the method is suitable for large-scale popularization and application. And the method has an applicable value for aero-engine parts requiring rapid and high-precision nondestructive detection.

The present invention relates to the technical field of wireless communications, and provides a processor, a chip, a network device and a wireless communication data processing method wherein the processor comprises: at least one general purpose computing core configured to execute a general purpose computing task; at least one tensor calculation core configured to perform a matrix multiplication task; at least one wireless communication computing core configured to execute a preset wireless communication computing task; the general computing core, the tensor computing core and the wireless communication computing core are all in communication connection with the shared memory, and the shared memory is configured to be used for data transmission among the computing cores. Various special computing cores are integrated on the processor, a shared memory architecture is adopted, efficient on-chip data interaction between a communication computing task and an AI computing task is achieved, and the method has the advantages of being low in delay, high in bandwidth and high in integration level.

Various aspects of the present disclosure set forth IC dies, microelectronic assemblies, as well as related devices and packages. One aspect relates to disaggregating 3D monolithic memory and compute functions to enable tight coupling for fast memory access at high bandwidth. Another aspect relates to microelectronic assemblies relate to nano-TSVs with 3D monolithic memory. Further aspects relate to die stitching and the use of glass carrier structures in microelectronic assemblies. Various aspects disclosed herein advantageously provide a robust set of implementations that may enable significant improvements in terms of optimizing performance of individual IC dies, microelectronic assemblies including one or more of such dies, and IC packages and devices including one or more of such microelectronic assemblies.

The invention relates to a dynamic routing and flow balancing method and system for a regionalized network topology, and the method comprises the steps: dividing a satellite network into a plurality of partitions, and distributing a core node for traffic scheduling and routing calculation for each partition; each core satellite node responds to each traffic demand, and bandwidth and traffic distribution in each partition are adjusted through a multi-anchor-segment routing method and a preset linear programming model; and each satellite node dynamically adjusts the route of each traffic demand through a probability forwarding scheduling method based on geometric topology according to the relative position of the satellite node and the target node. According to the method, low delay, high bandwidth utilization rate, load balance and efficient fault recovery of the satellite network are realized through network partitioning, a multi-anchor-segment routing method and probability forwarding based on geometric topology.

The invention relates to an eVTOL (electric vertical take-off and landing aircraft)-oriented multipath transmission optimization and dynamic path selection method, and aims to solve the problems of bandwidth, delay and packet loss of an eVTOL aircraft in high-throughput video data transmission. According to the method, key performance indexes such as bandwidth, delay and packet loss rate of a path are monitored in real time, and path selection is optimized in combination with flight state data, so that low-delay and high-bandwidth transmission of a panoramic video stream is ensured. An improved multi-path load balancing strategy is adopted, the flow is distributed according to the path score and the bandwidth margin, network congestion is avoided, and the data transmission stability is improved. By enhancing an MPQUIC protocol and optimizing multi-path cooperative transmission, a low-delay path is preferentially selected to transmit high-priority data. A redundant transmission mechanism ensures that data can still be reliably transmitted through other paths even if a part of paths lose packets. The method provides technical support for the construction of an immersive eVTOL driving experience platform, meets the requirements of low time delay, high bandwidth and high sense of reality, and has a wide application prospect.

A package includes a photonic integrated circuit (PIC) disposed on a substrate and comprising a semiconductor die hosting an active portion and a passive portion mutually coupled, the active portion being configured to consume electrical power when activated, and the passive portion comprising an optical transmission medium configured to propagate an optical signal to or from the active portion of the PIC; an electronic integrated circuit (EIC) electrically coupled to the active portion of the PIC and comprising components that electrically operate on the active portion of the PIC; and a packaging compound at least partially encapsulating the PIC, the packaging compound defining a cavity on a side of the semiconductor die that is opposite from the substrate, the cavity being filled with an optically transparent medium such that the optical signal can be received from or transmitted to the passive portion of the PIC through the cavity.

The invention belongs to the technical field of artificial intelligence chip and robot control, and relates to a heterogeneous calculation and control fusion chip control system and method, a robot and a storage medium. A GPU, an NPU, a BPU and an MCU are integrated in a central large core cluster, a communication network subunit and a memory control subunit are matched, and a low-delay data channel is constructed in a chip, so that perception, cognition and control instructions can be directly interacted, the cross-chip communication delay is reduced, and the real-time performance is improved. The three-level cache module is accessed through the memory control subunit, high-bandwidth sharing and centralized scheduling are achieved, data migration is reduced, the bandwidth bottleneck is relieved, and the complex task processing efficiency is improved. A trust root subunit is arranged in each unit, chip-level trusted verification and access isolation are provided, and the reliability under key action control and security sensitive scenes is enhanced.

The invention discloses a differential signal transmission link, a high-speed differential signal transmission composite chip and an intra-core differential signal transmission link configuration method. A strip line is arranged in a perforated cylinder in a penetrating manner, two differential microstrip lines are horizontally arranged at two ends of the perforated cylinder, one end of one differential microstrip line is connected with the upper end of the strip line, and one end of the other differential microstrip line is connected with the lower end of the strip line; the conductor strip and the two grounding strips in each differential microstrip line are arranged on the total slide glass side by side in the length direction of the total slide glass, the conductor strip is arranged between the two grounding strips, and the multiple capacitors and the multiple inductors are alternately arranged on the conductor strip in the length direction of one side of the conductor strip. The plurality of conductive blocks are uniformly arranged on the conductor belt along the length direction of the other side of the conductor belt; a high-bandwidth storage chip and a GPU chip in the high-speed differential signal transmission composite chip are horizontally arranged on a PCB composite board in parallel, and a differential signal transmission system is arranged among the PCB composite board, the high-bandwidth storage chip and the GPU chip in a penetrating mode.

A photonic integrated circuit (PIC) disposed on a substrate and comprising a semiconductor die hosting an active portion and a passive portion mutually coupled, the active portion being configured to consume electrical power when activated, and the passive portion comprising an optical transmission medium configured to propagate an optical signal to or from the active portion of the PIC; an electronic integrated circuit (EIC) electrically coupled to the active portion of the PIC and comprising components that electrically operate on the active portion of the PIC; and a packaging compound at least partially encapsulating the PIC, the packaging compound defining a cavity on a side of the semiconductor die that is opposite from the substrate, the cavity being filled with an optically transparent medium such that the optical signal can be received from or transmitted to the passive portion of the PIC through the cavity.

The invention relates to the technical field of motor fault diagnosis, and discloses a multi-degree-of-freedom resonant excitation motor dynamic vibration test system and a test method, the system injects a specific harmonic current into a motor through closed-loop control and calculation and a high-bandwidth harmonic injection driver, so that the actual vibration of the tested motor tracks a preset target vibration profile in real time. In the testing process, the cross-spectral density of multi-point vibration signals is analyzed, and a transmission path and a collection area of vibration energy in a motor structure are calculated; and meanwhile, the electromagnetic impedance and the mechanical impedance of the motor are identified and decoupled on line by superposing a broadband disturbance signal in the driving current. In combination with energy flow analysis and an impedance decoupling result, the method can accurately position a vibration abnormal position, clearly causes whether a fault source is from mechanical structure characteristic change or electromagnetic part performance change from a physical level, and realizes deep and accurate diagnosis of the dynamic characteristics of the motor.

The invention discloses a vehicle-mounted video transmission hybrid topology network, and relates to the technical field of vehicle-mounted video communication. The vehicle-mounted video transmission hybrid topology network comprises a plurality of transmission nodes, each transmission node comprises at least one input port and at least one output port, and the plurality of transmission nodes form a hybrid network of a tree topology structure and a daisy chain topology structure; wherein the tree topology structure in the hybrid network comprises a root node and a plurality of subordinate sub-nodes, the daisy chain topology structure is a sub-branch of the tree topology structure, and the hybrid network comprises a main link and a standby link which are used for signal transmission. Through innovative designs such as hybrid topology, dynamic bandwidth allocation, data retransmission, redundant channels, routing address query and the like, high bandwidth, low delay and high reliability in the field of vehicle-mounted video transmission are realized.

The invention relates to the technical field of signal crosstalk prevention, and provides an FFC wire harness signal crosstalk prevention method and device, electronic equipment and a storage medium. The method comprises the steps of performing frequency spectrum and time domain feature extraction processing on an original FFC signal to obtain a basic signal parameter set, constructing an FFC wire harness electromagnetic model according to FFC wire harness geometric data, and performing multi-conductor transmission line parameter extraction processing according to the basic signal parameter set and the FFC wire harness electromagnetic model to obtain a distribution parameter matrix. And performing Pareto multi-objective optimization processing on the signal arrangement sequence and daemon insertion of the distribution parameter matrix to obtain an optimal signal sequence and a daemon scheme, and performing microstructure configuration processing of the overall shielding layer and the grounding network according to the optimal signal sequence and the daemon scheme to obtain a shielding arrangement scheme. According to the invention, through fine modeling and multi-target collaborative optimization, the FFC wire harness realizes low crosstalk, high bandwidth and low electromagnetic radiation in a high-frequency and high-speed transmission environment.