1296 results about "High bandwidth" patented technology

The invention relates to the technical field of motor detection, and discloses a motor instantaneous torque measurement method and system based on a high-bandwidth sensor, and the method comprises the steps: synchronously collecting a torque signal and a multi-source interference variable through the high-bandwidth sensor, and forming an original torque sequence after time synchronization superposition; extracting disturbance frequency characteristics through multi-scale wavelet transform and spectral analysis; a pre-trained adaptive filter model is utilized to generate a filter coefficient matched with the working condition, and primary filtering is completed; residual fluctuation is suppressed in combination with Kalman state estimation, and an optimized torque estimation value is obtained; parameter self-adaptive compensation is realized through online calibration weight updating, and a stable torque measurement sequence is output; load abrupt change pre-judgment and threshold value dynamic updating are achieved based on time-frequency correlation analysis, and finally rapid measurement convergence after working condition abrupt change is ensured through a closed-loop reset mechanism. According to the method, the problem of low instantaneous torque measurement precision in the prior art can be solved.

The invention relates to the field of edge computing data security, in particular to an integrity auditing method and system in an edge computing environment. The problem that an existing cloud auditing model is high in delay and large in bandwidth consumption in an edge scene is mainly solved. A lightweight audit challenge is generated through random sampling, data block aggregation operation is executed at an edge node, Merkel Hash tree path evidence is extracted, and integrity proof of dual verification is formed; and the aggregated evidence and the path evidence are verified by using bilinear mapping, so that efficient and credible auditing is realized. Dynamic data updating and accurate positioning of damaged blocks are supported, communication overhead is remarkably reduced, and real-time credibility of edge data is guaranteed.

The invention discloses a hardware accelerator and equipment oriented to triple sparse matrix multiplication and an application method thereof.The hardware accelerator comprises a high-bandwidth memory HBM, a crossbar switch network and an on-chip processing unit which are connected in sequence, and the on-chip processing unit comprises a hierarchical cache module, a global controller and a plurality of computing chips; each calculation piece comprises an RA calculation array, a TP calculation array and a local controller, wherein the RA calculation array and the TP calculation array are respectively used for executing front-end operation T = R * A and rear-end operation C = T * P in triple sparse matrix multiplication. The method aims at solving the problem that when a traditional universal processor processes triple sparse matrix multiplication, due to irregular memory access, uneven calculation load and sharp increase of middle parts and results, huge off-chip data carrying is confronted with serious performance and energy efficiency bottlenecks, and the calculation performance and energy efficiency of triple sparse matrix multiplication are improved.

The present invention relates to the technical field of wireless communications, and provides a processor, a chip, a network device and a wireless communication data processing method wherein the processor comprises: at least one general purpose computing core configured to execute a general purpose computing task; at least one tensor calculation core configured to perform a matrix multiplication task; at least one wireless communication computing core configured to execute a preset wireless communication computing task; the general computing core, the tensor computing core and the wireless communication computing core are all in communication connection with the shared memory, and the shared memory is configured to be used for data transmission among the computing cores. Various special computing cores are integrated on the processor, a shared memory architecture is adopted, efficient on-chip data interaction between a communication computing task and an AI computing task is achieved, and the method has the advantages of being low in delay, high in bandwidth and high in integration level.

The invention relates to a dynamic routing and flow balancing method and system for a regionalized network topology, and the method comprises the steps: dividing a satellite network into a plurality of partitions, and distributing a core node for traffic scheduling and routing calculation for each partition; each core satellite node responds to each traffic demand, and bandwidth and traffic distribution in each partition are adjusted through a multi-anchor-segment routing method and a preset linear programming model; and each satellite node dynamically adjusts the route of each traffic demand through a probability forwarding scheduling method based on geometric topology according to the relative position of the satellite node and the target node. According to the method, low delay, high bandwidth utilization rate, load balance and efficient fault recovery of the satellite network are realized through network partitioning, a multi-anchor-segment routing method and probability forwarding based on geometric topology.

The invention belongs to the technical field of artificial intelligence chip and robot control, and relates to a heterogeneous calculation and control fusion chip control system and method, a robot and a storage medium. A GPU, an NPU, a BPU and an MCU are integrated in a central large core cluster, a communication network subunit and a memory control subunit are matched, and a low-delay data channel is constructed in a chip, so that perception, cognition and control instructions can be directly interacted, the cross-chip communication delay is reduced, and the real-time performance is improved. The three-level cache module is accessed through the memory control subunit, high-bandwidth sharing and centralized scheduling are achieved, data migration is reduced, the bandwidth bottleneck is relieved, and the complex task processing efficiency is improved. A trust root subunit is arranged in each unit, chip-level trusted verification and access isolation are provided, and the reliability under key action control and security sensitive scenes is enhanced.

The invention discloses a differential signal transmission link, a high-speed differential signal transmission composite chip and an intra-core differential signal transmission link configuration method. A strip line is arranged in a perforated cylinder in a penetrating manner, two differential microstrip lines are horizontally arranged at two ends of the perforated cylinder, one end of one differential microstrip line is connected with the upper end of the strip line, and one end of the other differential microstrip line is connected with the lower end of the strip line; the conductor strip and the two grounding strips in each differential microstrip line are arranged on the total slide glass side by side in the length direction of the total slide glass, the conductor strip is arranged between the two grounding strips, and the multiple capacitors and the multiple inductors are alternately arranged on the conductor strip in the length direction of one side of the conductor strip. The plurality of conductive blocks are uniformly arranged on the conductor belt along the length direction of the other side of the conductor belt; a high-bandwidth storage chip and a GPU chip in the high-speed differential signal transmission composite chip are horizontally arranged on a PCB composite board in parallel, and a differential signal transmission system is arranged among the PCB composite board, the high-bandwidth storage chip and the GPU chip in a penetrating mode.

The invention relates to the technical field of motor fault diagnosis, and discloses a multi-degree-of-freedom resonant excitation motor dynamic vibration test system and a test method, the system injects a specific harmonic current into a motor through closed-loop control and calculation and a high-bandwidth harmonic injection driver, so that the actual vibration of the tested motor tracks a preset target vibration profile in real time. In the testing process, the cross-spectral density of multi-point vibration signals is analyzed, and a transmission path and a collection area of vibration energy in a motor structure are calculated; and meanwhile, the electromagnetic impedance and the mechanical impedance of the motor are identified and decoupled on line by superposing a broadband disturbance signal in the driving current. In combination with energy flow analysis and an impedance decoupling result, the method can accurately position a vibration abnormal position, clearly causes whether a fault source is from mechanical structure characteristic change or electromagnetic part performance change from a physical level, and realizes deep and accurate diagnosis of the dynamic characteristics of the motor.

The invention discloses a circuit, a data processing method, equipment, a medium and a program product in the technical field of computers. In the application, the three-dimensional heterogeneous computing body layer can adapt to diversified computing power requirements, and is beneficial to realizing higher routing and higher data transmission efficiency between nodes. The shared cache layer is beneficial to realizing cache consistency of different heterogeneous computing nodes, and the cache utilization rate is improved. The internal interconnection module and the external interconnection module provided by the interface layer are easy to realize internal and external efficient communication. A first channel controller provided by the control layer can realize direct connection of physical channels between the control layer and the three-dimensional heterogeneous computing body layer and direct connection of physical channels between the control layer and the shared cache layer; a second channel controller provided by the control layer can realize direct connection of physical channels between the control layer and the interface layer; therefore, the communication delay between different levels can be reduced, the data transmission efficiency between different levels can be improved, and a high-bandwidth application scene can be met.

The invention discloses an optimal beam forming design method under semantic communication service quality constraint, and belongs to the technical field of wireless communication. An optimal beam forming design method is provided for a multi-input single-output digital semantic communication system; an end-to-end semantic performance and compression ratio model is utilized to establish a relational expression of end-to-end semantic performance and a signal-to-noise ratio, and an optimal beam is constructed with the purposes of meeting semantic communication service quality and minimizing transmitting power; dual constraints of transmission time delay and semantic communication service quality are met, and meanwhile, an optimal beam is constructed by minimizing a semantic energy consumption target; through a Dinkelbach method and a matched filtering strategy, the optimal wave beam meeting the requirements of transmission delay and semantic communication service quality at the same time is designed under the target of minimum semantic energy consumption, and the robustness and the resource utilization rate of a semantic communication system under the conditions of high bandwidth, high reliability and limited resources can be remarkably improved.

The invention provides a memory computing chip and a manufacturing method thereof, which are characterized in that a logic chip with a computing processor, a buffer chip and a DRAM (dynamic random access memory) chip (or a DRAM chip stack) are vertically stacked through silicon through holes, and the chips can be directly communicated through the silicon through holes, so that the chip area can be saved, the integration level is high, the wafer processing difficulty is reduced, and the manufacturing cost is reduced. The logic chip can visit the low-speed DRAM chip in parallel in a large number through the buffer chip, high-bandwidth and large-capacity cache is provided, inter-chip communication between the buffer chip and the logic chip does not need a physical layer interface, and cost of hardware resources is greatly reduced.

The invention discloses a multi-rule template quintuple rule matching method and device based on an FPGA, and the method comprises the steps: storing a plurality of rule templates through a high-bandwidth memory, carrying out the cascading of the rule templates, and carrying out the rule matching of quintuple information in a to-be-processed message, carrying out the matching in a non-cascading / cascading manner, and carrying out the rule matching of the quintuple information in a to-be-processed message. And obtaining an action strategy of the to-be-processed message. The matching information of each template is flexible and configurable, a complex matching function is realized through cascading of the templates, the number of the templates is effectively reduced, and system resources are reduced.

The invention discloses a power plant remote monitoring and fault diagnosis system based on a 5G network, and belongs to the technical field of remote monitoring, fault diagnosis and operation control. Comprising an on-site intelligent sensing and control terminal, a cloud intelligent operation and maintenance platform and a remote operation and display terminal. According to the invention, the characteristics of high bandwidth and ultra-low delay of the 5G network are fully utilized, and real-time acquisition, edge early warning analysis and high-speed transmission of multi-dimensional data of the power plant are realized; fusion of big data and artificial intelligence of a cloud intelligent operation and maintenance platform is provided, and accurate monitoring of the operation state of the power plant equipment, intelligent early warning of abnormity, rapid diagnosis of a fault source, real-time closed-loop execution of a remote control instruction and continuous optimization of a full-life-cycle predictive maintenance strategy can be realized. According to the invention, the safety, the stability and the operation and maintenance management efficiency of power plant operation are obviously improved, and the operation cost is effectively reduced.

The invention belongs to the technical field of wireless optical communication, and particularly relates to a mobile edge computing task unloading and resource allocation method in wireless optical communication assisted by an unmanned aerial vehicle. According to the method, the data model, the queue model and the communication model are constructed, a task unloading strategy is optimized, and efficient and low-power-consumption edge computing resource allocation is achieved; an optimization technology is adopted to decompose a long-term optimization problem into sub-problems of each time slot, and the sub-problems are solved through a continuous convex approximation algorithm and a BFGS algorithm; finally, joint optimization of task unloading, computing resources, transmitting power, task return transmitting power, time slot scheduling and UAV trajectory is realized, and an optimization framework with more fine granularity in multi-dimensional allocation is formed. The characteristics of flexibility of the unmanned aerial vehicle and high bandwidth of wireless optical communication are utilized, the long-term throughput of the system is improved, the long-term power consumption of Internet of Things equipment is reduced, the high real-time performance of task processing is ensured, and the method is suitable for outdoor mobile Internet of Things application scenes with strict requirements for low power consumption and high real-time performance.

The invention relates to the technical field of Internet of Things data processing, in particular to a multi-modal data real-time processing method for an Internet of Things gateway, and the method comprises the steps: obtaining multi-source operation data, and packaging the multi-source operation data into a standard operation data set; obtaining high-bandwidth modal data in the standard operation data set; when the maximum link delay time is greater than a preset delay abnormal threshold value, obtaining a version effective fingerprint of the target model and a local model fingerprint; when a model version abnormity diagnosis result is obtained, calculating information redundancy; obtaining correction delay time, and comparing the correction delay time with a preset normal reference delay interval; and when the correction delay time is greater than or equal to the upper limit value of the normal reference delay interval, adjusting the current decision period. By monitoring delay in real time, diagnosing consistency of model versions, eliminating redundant information and executing link adjustment, accurate processing of high-bandwidth modal data is realized, and real-time performance and reliability of Internet of Things gateway data processing are improved.

The invention discloses a multi-modal sensor abstract description and packaging method and system based on software definition. Firstly, a unified sensor abstract description model based on software definition is introduced, so that hardware independence is realized, and the differences of a bottom-layer multi-mode sensor in the aspects of interfaces, protocols and data formats can be effectively shielded; secondly, abstract packaging of data is achieved through an autonomous information processing module, and high-bandwidth and high-redundancy original data is converted into low-bandwidth and high-value structured information; in addition, by means of automatic registration, discovery, scheduling and control mechanisms of the sensor management control module on sensor resources, the system realizes a real plug-and-play function. According to the invention, by deploying the autonomous information processing modules at various sensor nodes, the original sensing data is preprocessed, and standardized data packaging with semantic consistency is output, so that the operation load of the central controller is reduced, and the information processing efficiency and the system response capability are also improved.

The invention belongs to the field of machine learning, discloses an expert parallelism processing method and system for a large language model based on MoE, and realizes efficient parallel processing of the MoE model by dynamically distributing expert quantization bit width and sparse mode, predicting and prefetching to-be-activated expert parameters, grouping tokens to generate task queues and dynamically configuring hardware accelerators. Firstly, an importance score is calculated based on expert historical activation frequency, weight distribution and a model structure, so that quantization precision and a sparse proportion are adaptively allocated, and resource waste and precision loss of a unified strategy are avoided; secondly, predicting an expert to be activated by using a current layer hidden state and a historical activation sequence, loading parameters to a special cache in advance, reducing high-bandwidth memory access, and relieving bandwidth peak scrambling; moreover, tokens are grouped through a token-expert mapping table, a task queue is created, and dynamic configuration of a systolic array is combined, so that the problem of expert heterogeneity after compression is solved, and efficient and parallel hybrid precision matrix operation is ensured.

The invention discloses a high-spatial-resolution distributed optical fiber sound wave sensing system based on FPGA real-time demodulation. The system comprises a narrow linewidth laser source module, a first coupler, a high-bandwidth sweep frequency signal modulation module, a circulator, a coherent receiving and photoelectric conversion module and an FPGA integrated module. A laser source emitted by the narrow linewidth laser source module is divided into about 10% of reference light and about 90% of detection light through the first coupler. The FPGA integrated module is connected with the high-bandwidth sweep frequency signal modulation module, and transmits a sweep frequency radio frequency pulse signal and a frequency shift radio frequency pulse signal to the high-bandwidth sweep frequency signal modulation module; the high-bandwidth sweep frequency signal modulation module is connected with the sensing optical fiber through the circulator so as to output sweep frequency optical pulses; the sensing optical fiber is connected with the coherent receiving and photoelectric conversion module through the circulator to transmit Rayleigh backscattered light; the coherent receiving and photoelectric conversion module is connected with the FPGA integrated module, and the FPGA integrated module carries out signal processing to obtain vibration information on the optical fiber.

The invention relates to the technical field of task scheduling, and discloses a scheduling control method and device for a multi-core real-time processing system and a computer storage medium, and the method comprises the steps: when a target process has a high-bandwidth operation request, executing a first bandwidth preemption operation based on a bandwidth lock mechanism, scheduling a target processor core corresponding to the target process to preempt a first shared resource required by the high-bandwidth operation request; the first shared resource comprises a CPU shared resource; based on a dynamic bandwidth preemption priority mechanism, executing a second bandwidth preemption operation according to the process priority and the task information of the target process so as to schedule a task execution unit of the target process to preempt a second shared resource; the second shared resources at least comprise global shared resources. Visibly, the scheduling reliability and accuracy between the processor cores and the main devices of the multi-core CPU in the multi-core real-time processing system can be improved, the problems of inner competition and outer competition are solved at the same time, and therefore the real-time performance of the system is improved.

A high bandwidth factorized power system comprises a discontinuous-mode regulator supplying the input of a fixed-ratio power converter providing an output voltage. The discontinuous-mode regulator delivers power to the fixed ratio converter in a series of operating cycles, each cycle comprising an input phase during which energy is drawn from the input source to an inductor and an output phase during which energy is delivered from the inductor to the regulator output. A controller begins the input phase of an operating cycle of the regulator after the end of the output phase upon sensing that the output voltage is below a minimum voltage threshold.

The invention relates to the technical field of large language model deployment, and discloses a large language model weight inverse quantization reasoning device and method.The method comprises the steps that low-precision weight data is transmitted to a high-bandwidth storage from a host and then transmitted to an on-chip storage through the high-bandwidth storage; data conversion from a low-precision format to a high-precision format is completed in the on-chip memory, the data is multiplied by an inverse quantization factor to obtain recovered high-precision weight data, and the functional unit is responsible for executing general matrix multiplication of input data and the high-precision weight data after inverse quantization. And pipeline parallel execution of the inverse quantization operation and the general matrix multiplication operation is realized through a double-buffering technology. According to the invention, on the basis of a dual-path inverse quantization architecture of the vector processing unit and a dual-buffer mechanism in the on-chip memory, the problem of hardware adaptation of low-precision calculation is solved, and efficient execution of a low-precision conversion algorithm is realized under the condition of limited hardware resources.

The invention relates to the technical field of hydrological monitoring, in particular to a hydrological intelligent monitoring method and system based on 5G-LoRa-Beidou multimode fusion, and the method comprises the following steps: S1, data collection: monitoring hydrological environment data in real time through a plurality of environment sensors, and transmitting the environment data to a hydrological monitoring terminal in various signal forms; s2, data receiving and primary processing: the hydrological monitoring terminal receives the environmental data and performs primary processing on the environmental data, including signal analysis, format conversion and analog-to-digital conversion, so as to generate digital format data suitable for further transmission; according to the invention, by fusing the characteristics of 5G high bandwidth and high speed, LoRa long-distance low power consumption and Beidou short message wide coverage, the problem of single communication coverage limitation of traditional hydrological monitoring is solved, intelligent selection (optimal selection according to bandwidth, real-time performance, network coverage and power consumption weighted score) is combined with a communication mode, the transmission efficiency and low power consumption are considered, and the deployment and maintenance cost is reduced.

The invention discloses a transmission type communication system and method based on low-frequency carrier waves and high-frequency modulation. The transmission type communication system and method are suitable for complex medium environments such as deep sea, strata and biological tissues. Aiming at the contradiction that the traditional low-frequency communication bandwidth is insufficient and the high-frequency communication penetrating power is poor, according to the scheme, a low-frequency carrier wave (30Hz-100kHz) and a high-frequency modulation signal (such as OFDM (Orthogonal Frequency Division Multiplexing) and 256QAM (Quadrature Amplitude Modulation)) are fused through a nonlinear signal superposition technology to generate a composite carrier wave signal, long-distance penetration is realized by utilizing the low attenuation characteristic of the low-frequency carrier wave, and meanwhile, the data rate is improved through high-frequency modulation. Application scenes comprise deep sea detection (300-meter high-definition video return), a brain-computer interface (implantable antenna transmission neural signal) and an intelligent power grid (underground pipe network monitoring). Through the physical layer-information layer collaborative design, the physical boundary limitation of traditional communication is broken through, and high penetrability, high bandwidth and strong anti-interference capability are achieved.

A radar system injects a calibrated current at a signal generator during a reset portion and acquisition portion of each chirp period. The signal generator employs “gear-switching” to reduce PLL bandwidth during an acquisition phase and to increase the phase lock loop (PLL) bandwidth during a reset phase. By employing gear switching to change the bandwidth of the PLL circuit during the different portions of each chirp period, the length of the reset period is reduced, thus improving overall efficiency of the radar system while maintaining good performance.

A voltage regulator having a multiple of main stages and at least one accelerated voltage regulator (AVR) bridge is provided. The main stages may respond to low frequency current transients and provide DC output voltage regulation. The AVR bridges are switched much faster than the main stages and respond to high frequency current transients without regulating the DC output voltage. The AVR bridge frequency response range can overlap with the main stage frequency response range, and the lowest frequency to which the AVR bridges respond may be set lower than the highest frequency to which the main stages respond.

Methods for fabricating flexible interposers for providing electrical connection between devices mounted at different vertical positions with respect to a substrate or a planar interposer. A bonded structure may comprise a bent flexible interposer extending from a first interposer portion between a main device on the substrate or the planar interposer and a second interposer portion above the main device and above or below a device positioned above the main device and electrically connected to the main device via a bent portion of the flexible interposer.

The invention discloses a tensor extension calculation method and device based on TPU, a medium and a product, and relates to the technical field of chips, and the method comprises the steps: analyzing a tensor extension request, and obtaining the first dimension information of an original tensor and the second dimension information of a target tensor; determining a tensor expansion demand according to the first dimension information and the second dimension information; according to the tensor expansion requirement, data, needing to be subjected to dimension expansion, in the original tensor is carried to a control memory or a vector memory from a high-bandwidth memory of the TPU, and in combination with a tensor broadcasting mechanism on the TPU, target tensor data is formed and stored in the high-bandwidth memory again through parallel processing of all the core computing units. According to the technical scheme of the embodiment of the invention, a tensor extension algorithm capable of accurately adapting to TPU hardware features is provided, so that the TPU native supports the extension calculation of the tensor dimension, the blank of the TPU function is filled, and the calculation parallelism and the transmission efficiency in the tensor extension calculation are improved.

The invention relates to an AI processor and method based on storage and calculation integration, three-dimensional integration and operator separation. The AI processor comprises a storage layer; the calculation layer and the storage layer are stacked in the vertical direction through a three-dimensional integrated connection structure, and a three-dimensional integrated high-speed channel is generated and used for executing calculation tasks in a large language model; the standardized memory interface is used for being connected with an external main control chip; the calculation task comprises a pre-filling stage and a decoding stage; the scheduling module configures the main control chip to interact data with the storage layer through the standardized memory interface so as to execute the pre-filling stage; the scheduling module configures the computing layer to interact data with the storage layer through the three-dimensional integrated high-speed channel so as to execute the decoding stage, the pre-filling stage is processed by utilizing the large computing power advantage of a main control chip, and the decoding stage is processed by utilizing the three-dimensional stacked high-bandwidth advantage, so that accurate matching of the computing power and the bandwidth is realized; and the large model reasoning efficiency is obviously improved.

A wafer-on-wafer formed memory and logic device can enable high bandwidth transmission of data directly between a memory die and a logic die. The memory die can be formed as one of many memory dies on a first semiconductor wafer. The logic die can be formed as one of many logic dies on a second semiconductor wafer. The first and second wafers can be bonded via a wafer-on-wafer bonding process. The memory and logic device can be singulated from the bonded first and second wafers.

The invention discloses a channel scheduling and bandwidth allocation method, system and device for cloud desktop communication, and the method comprises the steps: obtaining a data frame set, allocating a corresponding priority identifier according to a channel type to which each data frame belongs, and embedding the priority identifier of each data frame into a special field of a frame structure; the data frames are inserted into the corresponding sending queues according to the priority identifiers, each priority corresponds to one sending queue, the data frames are extracted from all the sending queues in sequence according to a preset scheduling strategy to be sent, and the preset scheduling strategy at least supports a priority preemptive mode or a weighted fair queuing mode; and collecting network state parameters in real time, and dynamically adjusting the bandwidth quota of the channel corresponding to each data frame through a feedback closed-loop mechanism based on the network state parameters. According to the invention, the rapid transmission of high-priority data frames is ensured, and the delay of real-time interaction is reduced; resources are flexibly allocated according to the network state, and the bandwidth utilization rate is improved.