69 results about "Root complex" patented technology

Secure communication provided with secure and non-secure root ports. One embodiment comprises: a plurality of cores; a memory controller to couple to a memory; an interconnect fabric coupled to the plurality of cores and the memory controller; and a root complex to support end-to-end encrypted channels between devices, the root complex comprising: a root port to receive non-posted requests from a requestor device, the root port to associate a first tag value with a non-posted request to indicate whether the non-posted request is received over an end-to-end encrypted channel; and a bridge device to transmit the non-posted request with the first tag value and to subsequently receive a completion message including the first tag value, wherein the root port is to determine whether the completion message is to be encrypted in accordance with the end-to-end encrypted channel based on the first tag value.

A system includes a host device, a memory expanding device, and a switch connecting the host device and the memory expansion device, wherein the host device includes a cache controller including a prefetch support circuit configured to generate prefetch information, a root complex configured to transmit the prefetch information to the memory expanding device and receive prefetch data from the memory expanding device, and one or more prefetch buffers storing the prefetch data, and the memory expanding device includes a memory device and a memory controller including a prefetch decision circuit configured to read the prefetch data from the memory device based on the prefetch information received from the host device and prefetch the prefetch data to the host device.

Disclosed are a computing device for accessing a memory expander using a compute express link (CXL) interconnect and an operating method thereof. The computing device may include a processor, a memory, and a root complex configured to be connected with the processor, the memory, and a memory expander. The processor may recognize whether the memory expander is connected to the root complex. The processor may update a physical address space of the computing device based on a recognition that the memory expander is connected to the root complex.

The invention discloses a PCIe (Peripheral Component Interconnect Express) exchange switch testing device and a PCIe exchange switch testing method, and aims to overcome the defects of long testing time, incapability of comprehensively covering a testing scene and high testing cost in the prior art. The device comprises root complex equipment, executable equipment enumeration, storage space allocation and test process control. An upstream port of the to-be-tested PCIe exchange switch is connected with the root complex device, and a downstream port of the to-be-tested PCIe exchange switch can be in extensible connection with the endpoint device or in cascade connection with other PCIe exchange switches; the end point equipment supports EP-RC, EP-EP transaction routing and data return; the PCIe connector establishes a physical link. The method comprises the following steps: establishing a PCIe link, distributing a bus number and the like, sending test data by utilizing a DMA function, comparing data consistency, marking an abnormal port, resending a test transaction, and polling all ports to complete test coverage. According to the device and the method, the test efficiency can be improved, the cost can be reduced, multi-chip parallel test and abnormal port marking can be realized, and the device and the method are suitable for board-level function test and burn-in test of the PCIe exchange switch.

The invention discloses a PCIe (Peripheral Component Interconnect Express) switch with NTB (Network Temporary Broadcasting) ports supporting multicast, which comprises at least one NTB port, the NTB port is used for communicating with a root complex or other PCIe switches, and each NTB port comprises an address translation module and a multicast management module. Wherein the address conversion module is used for converting an address in a read-write data packet into a specified PCIe bus domain, and the multicast management module is in communication connection with the address conversion module and is used for determining whether multicast is carried out or not according to the converted address and carrying out data transmission. The PCIe switch not only can be additionally connected with one or more root conjunctions to realize security isolation of the PCIe domain, but also can improve the utilization rate of bandwidth by utilizing the advantages of multicast.

Systems, methods, and a bridge device for a data storage device array that enables data transfer between data storage devices without transferring data to the host system are described. The bridge device receives a data transfer command from the host system, such as a fused read and write command, and converts it to separate read and write commands for the source and destination storage devices. The bridge device may operate in a non-volatile memory express over fabric (NVMe-oF) environment and manage the command queues, connection verifications, and command conversions to enable data transfer among storage devices connected to a shared peripheral component interface express (PCIe) root complex without using host network bandwidth or memory.

The invention discloses a PCIe switch capable of modifying hardware configuration. The PCIe switch comprises at least one port, a message manager, a security manager and a configuration management module. Wherein each port is connected with a root complex, an application program runs on the root complex, the message managers are mapped in base address registers of the ports in a one-to-one correspondence mode and used for information exchange between the root complex and the security manager, and the security manager is in communication connection with the message managers and used for analyzing, verifying and replying messages of the root complex. And the configuration management module is in communication connection with the security manager, and configures the PCIe switch based on the configuration information. According to the PCIe switch, batch data transmission and information interaction between the root complex and the PCIe switch can be realized, and only the application subjected to authorization verification has the authority to modify the configuration, so that the PCIe switch can modify the configuration according to the application requirement on the root complex, and the PCIe switch is high in flexibility, safe, reliable and easy to expand.

A method for reducing latency in a peripheral component interconnect express (PCIe) link between a PCIe root complex and a PCIe device is provided. The method includes measuring, by the PCIe device, a throughput of data transmission that is sent to a buffer of the PCIe device. The method includes determining, by the PCIe device, a latency tolerance reporting (LTR) value based on the measured throughput. The method includes transmitting, by the PCIe device, the LTR value to the PCIe root complex at an estimated time point via the PCIe link, wherein the estimated time point is prior to a time at which a buffer switching operation occurs.

Embodiments of the present disclosure provide an access acceleration system for storage devices. The system comprising: a central processing unit, a Peripheral Component Interconnect Express (PCIe) device, a storage device, a computing chip and memories, wherein: the PCIe device comprises a root complex device, a PCIe switch, and a PCIe endpoint; the central processing unit is in communication connection with an upstream port of the PCIe switch through the root complex device, the storage device is in communication connection with a downstream port of the PCIe switch, the computing chip is in communication connection with a downstream port of the PCIe switch through the PCIe endpoint, and the storage device and the computing chip are in communication connection with different downstream ports of the PCIe switch, respectively; and the central processing unit and the computing chip are electrically connected to different one of the memories.

The invention discloses a switching communication device, a switching communication method and a server, relates to the technical field of computers, and realizes equipment-level decoupling and resource pooling basis by actively managing a GPU (Graphics Processing Unit) through a second interface configured to be in a root complex mode. The on-chip management system and the switching logic module form a control core, a data switching strategy is dynamically executed, and conversion from passive forwarding to autonomous management is achieved. And the virtual port module performs software definition and dynamic allocation on network resources, so that the flexibility of resource utilization is improved. Meanwhile, MAC ports in two modes of direct connection and exchange are supported, so that the device can flexibly construct a high-performance direct connection network or a large-scale exchange network, and the limitation of fixed topology is broken through. And the data processing module ensures high efficiency of data conversion between different interface protocols. According to the device, the communication efficiency and schedulability between the GPUs are improved by integrating high-speed exchange, intelligent management, resource virtualization and flexible networking capabilities.

The invention discloses a PCIE password card, a communication method and device thereof and a medium, and relates to the technical field of computer hardware. The password card comprises: a main PCIE chip device, which comprises a first PCIE endpoint port, a security algorithm engine, and a PCIE root complex port; the first PCIE endpoint port is used for communicating with an upper computer, and the security algorithm engine is used for performing operation acceleration of a security algorithm based on a random number generated in the quantum random number generator; the slave PCIE chip equipment comprises a second PCIE endpoint port and an anti-quantum algorithm engine; the second PCIE endpoint port is connected with the PCIE root complex port, and the anti-quantum algorithm engine is used for performing calculation in a quantum calculation environment based on a random number generated in the quantum random number generator; and the quantum random number generator is used for generating a random number based on the quantum mechanics principle. According to the technical scheme, quantum attacks can be resisted, and the safety and reliability of the password card are improved.

A plurality of upstream dummy ports (PPs) of the first circuit die, each upstream PP having a connection to a respective one of the at least two root complex devices; a plurality of downstream PPs of the second circuit die, each set of downstream PPs having a connection to a respective one of the at least two endpoints; an inter-die data interface between the first and second circuit dies, the inter-die data interface having an adaptation layer port at each circuit die that operates according to an adaptation layer protocol; channel routing logic disposed within the first and second circuit dies to map at least one of the sets of upstream PPs and a respective set of downstream PPs to respective adaptation layer ports of the first and second circuit dies; and a processor disposed within one of the first and second circuit dies to configure the channel routing logic within the two circuit dies.

Secure communication provided with secure and non-secure root ports. One embodiment comprises: a plurality of cores; a memory controller to couple to a memory; an interconnect fabric coupled to the plurality of cores and the memory controller; and a root complex to support end-to-end encrypted channels between devices, the root complex comprising: a root port to receive non-posted requests from a requestor device, the root port to associate a first tag value with a non-posted request to indicate whether the non-posted request is received over an end-to-end encrypted channel; and a bridge device to transmit the non-posted request with the first tag value and to subsequently receive a completion message including the first tag value, wherein the root port is to determine whether the completion message is to be encrypted in accordance with the end-to-end encrypted channel based on the first tag value.

A technique of non-disruptive fault isolation for an input / output (I / O) subsystem includes processing circuitry at a root complex interposed between a plurality of server platforms and a plurality of I / O switches receiving, via an I / O switch among the plurality of I / O switches, notification of downstream port containment of an I / O port to which an I / O adapter is coupled. In response to receipt of the notification, the processing circuitry notifies the plurality of attached server platforms of the downstream port containment to cause the plurality of server platforms to refrain from attempting communication of I / O traffic via the I / O adapter. The processing circuitry waits a containment interval, and thereafter, releases the containment to permit resetting of the I / O adapter.

The invention relates to the technical field of computers, and provides a data transmission method, a programmable logic controller system and electronic equipment. According to the method, a central controller obtains data to be transmitted from local storage of a corresponding high-speed peripheral component interconnection endpoint; the central controller generates a data write-in request and sends the data write-in request to a corresponding high-speed peripheral component interconnection endpoint, and the data write-in request is used for indicating to write to-be-transmitted data into a target address corresponding to a high-speed peripheral component interconnection root complex; after receiving a data writing request, the high-speed peripheral component interconnection endpoint encapsulates data to be transmitted into a memory writing transaction message, and sends the memory writing transaction message to the high-speed peripheral component interconnection root complex, so that the high-speed peripheral component interconnection root complex writes the data to be transmitted into a target address; according to the method, the central controller is configured on the EP side, the EP initiatively initiates the write transaction, and the data is directly pushed to the RC DDR, so that the system delay is remarkably reduced.

The embodiment of the invention provides a PCIE link hot plug scene detection and repair method and device, and the method comprises the steps: executing an initialization operation which at least comprises the steps: enabling a hot plug management module to receive and forward a reset control signal between a root complex and an end point through configuration, and obtaining the information of connected PCIE equipment; collecting link state data and physical plugging state information from a register of the PCIE controller and a pin related to hot plugging; judging whether the PCIE link is in an abnormal state or not based on link state data and the physical plugging state information; and in response to the abnormal state of the PCIE link, selecting a repair strategy according to the type of the abnormal state, generating a repair control sequence containing a reset control signal, and issuing the repair control sequence through the hot plug management module to trigger link recovery. By adopting the above scheme, rapid detection and automatic repair of the abnormal state of the PCIE link and stable recovery of the link can be realized.

The embodiment of the application discloses a delay tolerance reporting method, a PCIe switch and a storage medium. The method comprises the following steps: a downlink port module generates a delay tolerance message based on a first delay tolerance message, transmits the delay tolerance message to an uplink port module in the same partition according to a standard TLP message routing mechanism, generates a second delay tolerance message based on a minimum delay tolerance value, and controls the uplink port module to report the second delay tolerance message to a root complex. The embodiment of the application generates a delay tolerance message based on a first delay tolerance message, transmits the delay tolerance message from a downlink port module to an uplink port module in the same partition according to a standard TLP message routing mechanism, does not need to set a complex hardware signal line, and only transmits the delay tolerance message to the uplink port module in a software mode. The uplink port module collects delay tolerance values transmitted by each downlink port module, and then finds a minimum delay tolerance value, thereby reducing the occupation of physical resources.

The application provides an interconnection method between devices compatible with a PCIe structure and related devices, and the interconnection method is applied to a heterogeneous system, the heterogeneous system comprising a host and a plurality of devices connected to the host, and the method comprises: a first device changing a type of a data path of the first device according to a preset control character received from a second device or the host; and the first device after the type is changed and the second device realizing interconnection; wherein the preset control character is an instruction conforming to a PCIe communication protocol and capable of controlling the first device to change the type of the data path of the first device, and the type of the data path is a root complex (RC) type or an endpoint device (EP) type. The application can realize interconnection between devices by switching the device type, and can reduce data transmission delay of interconnection between devices in a heterogeneous computing system.

The application discloses a kind of switching communication device and method, server, it is related to computer technical field, by being configured as the second interface of root complex mode actively manages GPU, equipment level decoupling and resource poolization foundation are realized.The on-chip management system and switching logic module constitute control core, dynamically execute data exchange strategy, realize from passive forwarding to the change of autonomous management.Virtual port module carries out software definition and dynamic allocation to network resource, improve the flexibility of resource utilization.Meanwhile, support the MAC port of two modes of direct connection and switching, so that device can flexibly build high-performance direct connection network or large-scale switching network, break the limit of fixed topology.Data processing module then ensures the efficiency of data conversion between different interface protocols.The device improves the communication efficiency and schedulability between GPUs by integrating high-speed switching, intelligent management, resource virtualization and flexible networking capabilities.

The embodiment of the invention discloses a delay tolerance report method, a PCIe switch and a storage medium. The method comprises the following steps: controlling a downlink port module to generate a delay-tolerant message based on a first delay-tolerant message, transmitting the delay-tolerant message to an uplink port module of the same partition according to a standard TLP message routing mechanism, generating a second delay-tolerant message based on a minimum delay-tolerant value, and transmitting the second delay-tolerant message to an uplink port module of the same partition according to a standard TLP message routing mechanism. And controlling the uplink port module to report the second delay tolerance message to the root complex. According to the embodiment of the invention, the delay-tolerant message is generated based on the first delay-tolerant message, the delay-tolerant message is transmitted from the downlink port module to the uplink port module of the same partition according to a standard TLP message routing mechanism, a complex hardware signal line does not need to be arranged, and the delay-tolerant message is transmitted to the uplink port module only in a software mode, so that the delay-tolerant message transmission efficiency is improved. And the uplink port module gathers the delay tolerance values transmitted by the downlink port modules, and searches the minimum delay tolerance value, so that the occupation of physical resources is reduced.

Apparatuses and methods for an integrated device with trusted execution environment (TEE) confidential computing support are disclosed. An apparatus and method for extending IO device security protocols to an integrated processor. For example, an example processor package includes: a plurality of cores to execute instructions; an interconnect structure coupled to the plurality of cores; a memory interface circuit coupled to the interconnect structure, the memory interface circuit to couple the plurality of cores to one or more memories; a root complex comprising: a security circuit operable as a root of trust (RoT) and a bridge to the interconnect structure, the security circuit for establishing secure communications with one or more root complex integrated endpoint (RCiEP) devices integrated into the processor package; and a security protocol and data model (SPDM) engine of the security circuit for providing RCiEP encryption and SPDM protocol services to establish a secure communication channel with each RCiEP device.

The invention provides a method for adjusting a timeout time range of a root complex, a network chip and electronic equipment. The method comprises the steps that a substrate management controller system acquires a working load parameter of a data processing unit in real time; the baseboard management controller system obtains the current load level of the data processing unit according to the working load parameters of the data processing unit; the baseboard management controller system dynamically determines the timeout time range of the root complex according to the current load level of the data processing unit; and the baseboard management controller system configures the completion timeout time of the corresponding root port on the host side according to the determined timeout time range of the root complex. According to the technical scheme, the response capability and the processing efficiency of the system can be improved.

A communication system capable of establishing communication without imposing excessive restrictions on the startup order of a plurality of communication devices is provided. The communication system is provided with a plurality of communication devices. In the communication system, the plurality of communication devices communicate with each other. When a startup request for starting up a communication device is acquired, if other communication devices that communicate with each other are in a startup completion state (S12: YES), a driver DR1 for a root complex RC is executed by an execution device in step S13. When a startup request for starting up a communication device is acquired, if other communication devices that communicate with each other are not in a startup completion state (S12: NO), a driver DR2 for an endpoint EP is executed by the execution device.

Embodiments of the present disclosure relate to a toolbox for communicating data between a root complex and an endpoint. An example kit for connecting between a root complex and an endpoint in a computing device includes a first port configured to connect to the root complex, a second port configured to connect to the endpoint, a first physical layer connected to the first port, and a second physical layer connected to the second port, and a first data link layer and a second data link layer, the first data link layer being connected between the second data link layer and the first physical layer, and the second data link layer being connected between the first data link layer and the second physical layer. The first physical layer, the first data link layer, the second physical layer, and the second data link layer are configured to form one or more channels for communicating data between the root complex and the endpoint.

A processor package module includes a socket having a first side and a second side, where the second side includes interconnect joints. The socket further includes a root complex and a non-root complex over the first side. An interconnect layer is on the first side of the socket and has one or more levels of routing traces. A first set of socket pins connects the root complex and non-root package to the interconnect layer, where the first set of socket pins terminate at the interconnect layer.

The present application relates to the technical field of address translation request scheduling, and particularly relates to an address translation request aggregation scheduling method and system. The present application maintains a pending request filter table, each table entry corresponding to a 4KB address range, recording address translation requests that have been sent but have not received responses. When a new request is received, the 4KB base address to which the virtual address belongs is calculated and the filter table is queried: if there is a corresponding table entry, the request is added to the associated waiting queue, and the new request is not sent; if there is no corresponding table entry, the new request is sent and a new table entry is created. Thus, during the waiting response period, subsequent requests in the same address range are aggregated, the number of repeated requests is reduced from N times to 1 time, the root complex load is significantly reduced, redundant transactions are reduced, and the hardware overhead is extremely low.

Tightly-coupled, loosely connected distributed systems can be implemented more energy efficient and optimized for computational overhead via multi-protocol heterogeneous packet-based transport. When receiving a plurality of packets from a root complex where contents of each packet from the plurality of packets organized in accordance with a first protocol, a sequence number is added to each packet and a packet type is identified. Every packet in the first plurality of packets is encapsulated into at least one packet organized in accordance with a second protocol to form a second plurality of packets organized in accordance with the second protocol. All the packets from the second plurality of packets can be handled via Direct Memory Access. A write-only communication scheme can be implemented using doorbell and command registers for more efficient data reading and writing in distributed systems.

The application discloses a kind of non-transparent bridge PCIe exchange circuit dynamic burn-in device and method, adopt root complex CPU, endpoint device, port mode configuration line, port interconnection bus and device state indication line, cover the physical layer of circuit, data link layer and transaction layer and non-transparent bridge address conversion and exchange function, so that circuit is carried out dynamic burn-in according to normal working frequency and bus interface rate during burn-in;The application does not need to be externally connected root complex CPU and numerous PCIe endpoint devices for each non-transparent bridge PCIe exchange circuit, and only one root complex CPU is needed on the whole burn-in board, the connection mode of root complex CPU greatly saves the cost of components on burn-in board;The application improves the density of burn-in device on the same area burn-in board because of the reduction of peripheral PCIe device, more circuits can be burn-in in the same burn-in high-temperature box, and test cost is saved.

The invention belongs to the related technical field of computer hardware, and discloses an FPGA-based PCIe root complex integration system, which comprises a soft core processor, a memory module and an I / O module, when the soft core processor responds to a PCIe transmission task, an AXI transaction is sent to an XDMA module, the XDMA module packages the AXI transaction into a PCIe TLP packet, and the PCIe TLP packet is sent to endpoint equipment through a PCIe link; when the soft-core processor responds to the UART interrupt request, the soft-core processor sends the UART request to the UART module through a control interface of the soft-core processor, and the UART module starts a data transceiving interface of the soft-core processor to realize data interaction between the soft-core processor and external equipment; when the soft core processor responds to the PCIe link interruption request, the soft core processor sends the PCIe link request to the XDMA module, the XDMA module receives a PCIe TLP packet returned from the PCIe link, analyzes the PCIe TLP packet into an AXI transaction and then returns the AXI transaction to the soft core processor, and the soft core processor stores the received AXI transaction in the corresponding SDRAM. According to the PCIe root complex integrated system, the power consumption and the size of the PCIe root complex integrated system can be reduced, the transmission delay is reduced, and the interruption delay and the bus competition are reduced.

This application discloses a computer interface testing system, relating to the field of computer technology. By employing a link parameter monitoring module, a multi-dimensional indicator monitoring module, a traffic indicator testing module, and a version switching control module working together, this system tests the multi-dimensional indicator parameters of the root complex under test when switching between current test software, and dynamically tests the traffic indicators of the root complex under test under various test modes. This solves the problems that using a preset fixed version of test software simulation cannot handle switching tests between different versions of test software, and that using a preset fixed version simulation method cannot efficiently test the performance parameters of the root complex. Therefore, this invention not only enables testing the performance parameters of the root complex under various different versions of test software, but also improves the efficiency of root complex performance testing without the need for simulation software.