34 results about "Processor node" patented technology

The invention discloses an NUMA scheduling method and device in a large model training scene, equipment and a medium, and relates to the technical field of artificial intelligence, and the method comprises the steps: collecting a target cluster topological relation configuration file; obtaining a target affinity strategy corresponding to the graphics processor demand of the current large model training task, and if the target affinity strategy is a first affinity strategy, screening out candidate processor nodes including candidate NUMA nodes from the processor nodes based on the topological relation configuration file, the candidate NUMA nodes are the NUMA nodes of which the idle number of the graphics processor meets the requirements of the graphics processor under a single NUMA node, and determining a target NUMA node from the candidate NUMA nodes according to the performance communication score of each candidate NUMA node; and when the training container is started, scheduling each graphics processor under the target NUMA node to complete a current large model training task. The efficiency of large model training is improved, and the cost is reduced.

The invention relates to a modeling and formalized verification method for cache consistency protocol verification, and the method comprises the steps: building a protocol model which comprises a plurality of processor nodes, directory nodes and a communication mechanism through a structured modeling mode, and constructing an asynchronous message mechanism to simulate disordered concurrent communication; protocol behavior rules such as processor requests, directory responses and network receiving are defined, protocol property invariants are set, semantic constraints such as data consistency, confirmation before writing and sharing state legality are covered, model verification is carried out in a state space traversal mode, breadth-first search and a symmetry recognition mechanism are supported, and the method is suitable for the protocol behavior rules. A protocol error or deadlock state is effectively found, a traceable error path is generated, a verifier can automatically generate source codes through a compiler and operate on a host platform, and rapid verification and result output of a protocol model are achieved. The method has good protocol adaptability and model reusability, and is suitable for formalized verification of various cache consistency protocols.

Methods and systems are described herein for adaptive beamforming and interference mitigation using a time synchronized scalable cohered on-array processing system (“system”). The system may be a phased array implementing a software-defined radio using multi-input-multi-output antenna elements. The system includes multiple subarray elements which are configured into a tiered array of scalable subarrays that performs intermediary collation, coherence, noise reduction, and adaptive beamforming operations through processor nodes disposed between tiers. The intermediary collation operations process discrete portions of node excitation data to enable the phased array to generate an adaptive beam profile that directs high-directionality beams toward desired targets while adaptively partitioning interference sources between subarray elements. Further, the system makes use of a scalable multidimensional array to provide telecommunication and electromagnetic wave manipulation operations for applications of varying scale.

The invention discloses a double-target cloud workflow scheduling method under an edge heterogeneous cluster, which constructs a double-target optimization model aiming at an edge heterogeneous cluster application scene, and maximizes the service quality while satisfying the energy consumption constraint. A scheduling algorithm based on distributed mixed integer programming is designed on the basis of decomposition of an original problem, energy consumption and service quality are optimized according to processor node characteristics and load conditions, and scheduling of an edge heterogeneous cluster is achieved. The edge heterogeneous computing cluster scheduling can be effectively balanced in the aspects of multi-objective optimization, heterogeneous resource adaptation, real-time performance, dynamic performance and the like, so that an efficient computing solution is provided for the fields.

The invention provides a cluster computing resource isolation method and device, electronic equipment and a storage medium, and relates to the technical field of cluster computing resource management. And scheduling the containerized task to an adaptive physical graphics processor node based on the information, intercepting a resource access request during task operation, allocating an isolated video memory space and a computing context according to an allocated virtual graphics processor resource limit, and dynamically maintaining an isolated state of multiple tasks, so that the task access efficiency is improved. The problems of inter-task interference, limited hardware compatibility, insufficient resource allocation flexibility and low utilization rate caused by lack of a flexible virtualization scheme for decoupling from hardware and imperfect resource scheduling and isolation mechanisms in the prior art can be solved.

Methods and systems are described herein for adaptive beamforming and interference mitigation using a time synchronized scalable cohered on-array processing system (“system”). The system may be a phased array implementing a software-defined radio using multi-input-multi-output antenna elements. The system includes multiple subarray elements which are configured into a tiered array of scalable subarrays that performs intermediary collation, coherence, noise reduction, and adaptive beamforming operations through processor nodes disposed between tiers. The intermediary collation operations process discrete portions of node excitation data to enable the phased array to generate an adaptive beam profile that directs high-directionality beams toward desired targets while adaptively partitioning interference sources between subarray elements. Further, the system makes use of a scalable multidimensional array to provide telecommunication and electromagnetic wave manipulation operations for applications of varying scale.

The present application discloses a processor system, which relates to the field of computer technology. The system includes a processor node, a scheduler, and a system storage space with a third task set constructed. The processor node includes: a processor and a node storage space; a scheduler for screening a reference processor from the processor; screening a target task set from a candidate task set based on the task volume information of the reference task set, wherein the reference task set is a first task set in the processor storage space possessed by the reference processor, and the candidate task set includes: a reference task set, a second task set in the processor node where the reference processor is located, and a third task set; distributing the reference task to the target task set; and a reference processor for executing the tasks stored in the candidate task set. Through the present application, the technical problem of low processing efficiency of read and write requests in the related art is solved, and the technical effect of improving the processing efficiency of read and write requests is achieved.

The application discloses a network topology acquisition method and device, equipment and medium, and relates to the field of distributed heterogeneous computing systems. The dynamic host configuration protocol client integrated in the network communication module of each graphics processor node obtains the internet protocol address of the corresponding graphics processor node from the pre-stored multiple internet protocol addresses of the host node, and sends information containing the obtained internet protocol address to the host node, thereby realizing the automatic registration of each graphics processor node in the network of the distributed computing system, and establishing a node table according to the information sent by each dynamic host configuration protocol client through the host node, so that each graphics processor node can determine the network topology in the distributed computing system according to the node table, and the registration of the graphics processor on the network can be realized without relying on the central processor connected with the graphics processor, thereby improving the flexibility and scalability of the network topology.

This invention provides a multi-node dynamic management method and system based on a PCIe switch. The system includes a PCIe switch and a multi-processor node connected to the PCIe switch. Each multi-processor node includes one upstream port node and multiple downstream port nodes. The upstream port node is used for PCIe switch link configuration, data processing, data distribution, and data management. The downstream port nodes are used to receive and process data allocated by the upstream port node and output the processed data. The method includes defining the upstream and downstream port nodes within the multi-processor node; the upstream port node performs link configuration, data processing, data distribution, and data management on the PCIe switch; and the downstream port nodes receive and process the distributed data. The method and system of this invention can increase the rate of product data exchange and processing, and provide fault-tolerant backup capabilities and health monitoring capabilities to improve reliability.

The invention provides an online dynamic adjustment method, system and device for control parameters and a medium, and the method comprises the steps: collecting storage use data from each processor node, processing state fluctuation in a multi-node environment through employing a distributed collection protocol, and obtaining the current storage occupation proportion of each node; determining high-load state nodes by adopting a threshold comparison method according to the current storage occupation proportion of each node; analyzing a storage state of a processor node adjacent to the high-load state node, and determining a target node of the migration task; and sending a part of data packets of the high-load node to a target node through a transmission path based on an encrypted transmission protocol to complete online dynamic adjustment. According to the method, real-time monitoring of the storage state is realized in a multiprocessor environment, and storage resources are dynamically balanced through a collaboration mechanism among nodes.

The present invention provides a rapidIO network management method, aiming to provide a method for reducing software operation anomalies caused by network congestion. This solution is achieved through the following technical solutions: Each processor node on the signal processing module is interconnected through a rapidIO network switch to form a rapidIO sub-network, and the rapidIO sub-networks on each module are interconnected to form a rapidIO backbone network. The master node in the sub-network maintains the status of each node in the sub-network, executes fault handling measures when an anomaly occurs, and periodically sends the sub-network status to the master node of the main module. The master node of the main module maintains the status of each sub-network. When the master node of the main module fails, the master node of the backup module maintains the status of the backbone network.

An autonomous repeater system includes a processor node, a storage device, and two or more nodes. The processor node includes a processor, software, and a processor communication device. The software autonomously and continuously queries latitude data, longitude data, and signal-to-noise ratio data from two or more nodes and calculates a target latitude and a target longitude for each node using the latitude data, the longitude data, and the signal-to-noise ratio data received from the two or more nodes. The processor communication device is operatively connected to the processor to transmit or receive the latitude data, longitude data, and signal-to-noise ratio data between the two or more nodes and the processor and transmitting the target latitude and the target longitude calculated for each node. Each node includes a node communication device that transmits and receives data between the two or more nodes and the computer processor.

The application discloses a data processing method and device based on a neural network model and electronic equipment, and relates to the technical field of data processing, and comprises the following steps: merging N network layers of a neural network model to obtain M network layer groups; the network layers in each network layer group are calculated in parallel on a same general processor node; target network layers corresponding to a plurality of first input data are determined, the first input data are expanded based on the dimension characteristics of the target network layer groups to which the target network layers belong, the expanded first input data are calculated through a target general processor node where the target network layer group is located, second input data are output, and the target network layers corresponding to the second input data are updated; and in response to the target network layer being the Nth network layer, third input data output by the Nth network layer are taken as output data of the neural network model. The application shortens the calculation time and reduces the time delay.

Disclosed herein is a system and method for a mesh wireless network, deployable via an aircraft, drone, or other airborne system. Wide area network (WAN) connectivity is provided via a backhaul interface selected from a modem, satellite transceiver, wired module, or other wireless interface. Nodes are powered internally by portable supplies such as batteries, solar, wind, or kinetic energy, enabling continuous operation. The system enables rapid deployment in conflict zones, disaster areas, maritime or remote searches, and mass casualty events, with uninterrupted connectivity even when nodes are damaged or lost. Each node is portable, durable, and water-resistant, with housing comprised of resilient materials to withstand explosions, ammunition, and extreme weather. Multiple nodes form a mesh Wi-Fi network, with traffic routable via any node connected to a backhaul channel. Each node includes a processor for routing and inter-node communication. Nodes may also implement encryption, anti-jamming, and overlapping densities to maintain connectivity.

Methods and systems are described herein for adaptive beamforming and interference mitigation using a time synchronized scalable cohered on-array processing system (“system”). The system may be a phased array implementing a software-defined radio using multi-input-multi-output antenna elements. The system includes multiple subarray elements which are configured into a tiered array of scalable subarrays that performs intermediary collation, coherence, noise reduction, and adaptive beamforming operations through processor nodes disposed between tiers. The intermediary collation operations process discrete portions of node excitation data to enable the phased array to generate an adaptive beam profile that directs high-directionality beams toward desired targets while adaptively partitioning interference sources between subarray elements. Further, the system makes use of a scalable multidimensional array to provide telecommunication and electromagnetic wave manipulation operations for applications of varying scale.

The techniques described herein relate to systems and methods for executing a verifiable confidential computation using both an MPC network and a blockchain network. An exemplary method includes: assigning using at least one smart contract in the blockchain network: a first owner node that stores private data, a plurality of controller nodes that each store a respective data share of the private data, a first analyst node that indicates a respective computation of the secure MPC to execute on each corresponding data share stored on the plurality of controller nodes, and a plurality of processor nodes that execute each respective computation of the secure MPC on each corresponding data share and output a result; executing the secure MPC on the private data of the first owner node using the plurality of controller nodes, the first analyst node, and the plurality of processor nodes; recording the result on a blockchain.

The disclosure provides a kind of computing node, the detection method and equipment of computing node, it is related to computer technical field, by powering on computing node, BMC detects the type of central processing unit according to the configuration pin of mainboard, configures communication link;According to the deployment environment of rack in situ pin determination computing node, and load the out-of-band monitoring strategy corresponding to deployment environment;According to power supply configuration detection whether there is voltage conversion module, adjust I2C rate;The configuration information of graphics processor node connected with computing node is detected, and the switch and central processing unit are configured;According to the interconnection mode of switch downstream in situ state determination switch, and carry out global address space mapping;Control complex programmable logic device to central processing unit power on.In this way, the adaptability, stability, reliability and performance of computing node can be improved, signal attenuation and jitter in transmission process are reduced, and data transmission efficiency and quality are improved.

A new and improved technique for computerized processing of data for exploration and production of hydrocarbons and reservoir simulations that includes a multi-channel quality of service (QoS) in a group of high performance computing (HPC) clusters (which may collectively be referred to as a "data processing system"). The data processing system may be logically segregated into several logical subclusters and may have several publisher nodes, controlled by a master scheduler, serving several groups of processor nodes (the subscriber nodes) that execute different processing applications independently of each other. Multiple datawriters (DW) may send data through multiple channels of compute nodes, whenever there is a free master node. The multi-channels are established and take place as part of the multi-channel quality of service (QoS) settings.

The invention relates to the technical field of data processing, and particularly discloses a Nifi data consanguinity map construction method and device, a terminal and a medium, and the method comprises the steps: calling a Nifi data interface, and obtaining processor data and connection data between processors; adding processor nodes as processing nodes to the source graph, and adding connection edges between the processing nodes to the source graph; traversing all processing nodes in the source graph to find an initial processing node, and identifying a table in the initial processing node to generate an initial blood resource node; and performing depth-first search on all subsequent processing nodes of the initial processing node, and generating a blood relationship associated with the initial blood relationship resource node to complete data blood relationship map construction. According to the method, a complex data flow relationship of Nifi is clearly mapped by a graph theory model, all subsequent processing nodes of an initial node are traversed through DFS, a complete blood relationship is constructed, and full-path coverage is realized.

Systems and methods for flexible edge computing are provided that include a central controller communicatively coupled to a plurality of processor nodes forming a distributed compute mesh, wherein the central controller includes a memory storing edge computing algorithms which, when executed, cause the central controller to perform operations comprising receiving, in real-time, task data characterizing compute workloads from a compute client, energy data characterizing local energy availability and pricing proximate the processor nodes, and compute market pricing data, determining a predicted profitability and predicted operational suitability associated with executing the one or more compute workloads at each of the plurality of processor nodes based on the task data, the energy data, the compute data, and routing the one or more compute workloads to one or more of the plurality of processor nodes having a highest predicted profitability or highest predicted operational suitability.

The application discloses an open multifunctional low-delay high-stability interconnection method and belongs to the technical field of communication and network interconnection. The method comprises the following steps: establishing passive point-to-point physical connection based on an industry standard among a plurality of accelerator processor nodes; realizing nanosecond-level precision global virtual clock synchronization among the nodes through a Sideband management channel independent of a main data channel; based on the synchronized clock, adopting a time window-restricted forward credit flow control mechanism to complete the cooperative reservation and authorization of link time periods and receiving buffer resources before data transmission; the sender sends data through the main data channel within the authorized time window, and the receiver verifies the compliance of the data arrival time; all control signaling is transmitted through the Sideband channel and is physically isolated from the high-speed data channel. The application realizes open and compatible, low-power-consumption and high-bandwidth physical interconnection, provides nanosecond-level low-delay and high-deterministic data transmission capacity, and improves the communication efficiency and system stability of a large-scale computing cluster.

The invention provides a resource allocation method and device for a processor cluster, electronic equipment, a medium and a product. Relates to the field of computer science. The method is applied to a server, and comprises the steps of obtaining a task specification of a to-be-processed task, constructing a resource mirror image of a target processor node in real time, carrying out pre-push check processing based on the resource mirror image and the task specification to generate a corresponding resource judgment result, determining a to-be-cleaned workload list, resource release information and a scheduling feasibility analysis result, and generating a corresponding interactive card based on the resource judgment result, the to-be-cleaned workload list, the resource release information and the scheduling feasibility analysis result, and performing resource allocation processing based on the interactive card. Based on the method provided by the invention, the resource utilization rate and the service reliability of the GPU cluster can be improved.

Methods and systems are described herein for adaptive beamforming and interference mitigation using a time synchronized scalable cohered on-array processing system ("system"). The system may be a phased array implementing a software-defined radio using multi-input-multi-output antenna elements. The system includes multiple subarray elements which are configured into a tiered array of scalable subarrays that performs intermediary collation, coherence, noise reduction, and adaptive beamforming operations through processor nodes disposed between tiers. The intermediary collation operations process discrete portions of node excitation data to enable the phased array to generate an adaptive beam profile that directs high- directionality beams toward desired targets while adaptively partitioning interference sources between subarray elements. Further, the system makes use of a scalable multidimensional array to provide telecommunication and electromagnetic wave manipulation operations for applications of varying scale.

The memory access method of the computing device and the related device and method are applied to a first computing device associated with an open segment cache. The method comprises the following steps: first, in response to a memory access instruction initiated by a meta-thread executed on the first computing device, obtaining a target open segment address and a target offset from the memory access instruction; then, based on the target open segment address, obtaining a corresponding open segment data structure from the local memory of the first computing device, wherein the open segment data structure at least comprises a target physical device identifier and a target physical base address; thereafter, based on the target physical base address and the target offset, determining an actual physical access address; finally, based on the target physical device identifier, initiating a physical memory access request carrying the actual physical access address to a second computing device, thereby improving the compatibility and efficiency of data communication between multiple heterogeneous processor nodes in an extended network.

This application provides a verification system, a design verification method, and related equipment. The verification system includes: a slave device module, a listening filter module, and a reference model connected to each other. The slave device module sends a normalized address to the listening filter module to query the corresponding cache line status information. The listening filter module queries the cache line status information based on the normalized address and compares it with the output of the reference model to determine the verification result. The listening filter module includes a design under test (DUT), which includes a local node monitoring unit storing the cache line directory within the corresponding processor node and a remote node monitoring unit storing a cache line directory shared among the processor nodes. Based on the local node monitoring unit and the remote node monitoring unit, the DUT provides different directory query modes. The reference model is a model that performs co-simulation with the DUT to verify the accuracy of the design.

The embodiment of the invention provides a memory access method for computing equipment and related equipment, the method is applied to first computing equipment, the first computing equipment is provided with an open segment cache in an associated manner, and the method comprises the following steps: firstly, responding to a memory access instruction initiated by a meta-thread executed on the first computing equipment; obtaining a target open field address and a target offset from the memory access instruction; then, based on the target open segment address, a corresponding open segment data structure is obtained from a local memory of the first computing device, and the open segment data structure at least comprises a target physical device identifier and a target physical base address; then, based on the target physical base address and the target offset, determining an actual physical access address; and finally, based on the target physical device identifier, initiating a physical memory access request carrying the actual physical access address to the second computing device, thereby improving the compatibility and efficiency of data communication among the multiple heterogeneous processor nodes in the extended network.

A data server system includes a central processing unit (CPU) and a baseboard management controller (BMC) disposed on a motherboard, an Ethernet switch, a plurality of processor nodes, a first bus, a second bus and a first optical transceiver disposed on a baseboard, and a second optical transceiver, a third optical transceiver and a physical layer chip (PHY) disposed on an optical module board. The BMC is connected to the CPU. The Ethernet switch is connected to the CPU and the BMC. The processor nodes are connected to the Ethernet switch and the CPU. The first and second buses are connected to the CPU and the processor nodes. The first optical transceiver is connected to the Ethernet switch. The second optical transceiver is connected to the first optical transceiver. The PHY is connected to the second optical transceiver. The third optical transceiver is connected to the PHY.

The application provides an orthopedic surgery robot remote surgery control method, system, device and computer readable storage medium. The method comprises the following steps: a local master end receives a feedback data packet sent by a remote master end through a wireless communication network, and records a data packet receiving timestamp and a data packet receiving duration; a data packet transmission delay duration is calculated according to a data packet sending timestamp and the data packet receiving timestamp; if the data packet transmission delay duration is less than the data packet receiving duration, the local master end dynamically allocates a processor node with idle resources to receive and process the data packet; and in response to the operation of a local user, the local master end sends a control instruction to the remote master end through the wireless communication network to control the orthopedic surgery robot to perform surgery. According to the embodiment of the application, the orthopedic surgery robot can be remotely controlled with lower delay.

The utility model discloses a server and a server system. The server comprises a processor node, an optical module, a retimer and a control module, a first interconnection signal transmission end of the processor node is connected with a second interconnection signal transmission end of the retimer, a third interconnection signal transmission end of the retimer is connected with a fourth interconnection signal transmission end of the optical module, and a fifth interconnection signal transmission end of the optical module is connected with the switching module; the in-place signal output end of the optical module is connected with the in-place signal detection end of the control module, and the reset signal output end of the control module is connected with the reset signal input end of the re-timer. According to the utility model, the in-place detection of the optical module can be realized, so that the server can obtain the plugging condition of the optical module in time.

A data server system includes a central processing unit (CPU) and a baseboard management controller (BMC) disposed on a motherboard, an Ethernet switch, a plurality of processor nodes, a first bus, a second bus and a first optical transceiver disposed on a baseboard, and a second optical transceiver, a third optical transceiver and a physical layer chip (PHY) disposed on an optical module board. The BMC is connected to the CPU. The Ethernet switch is connected to the CPU and the BMC. The processor nodes are connected to the Ethernet switch and the CPU. The first and second buses are connected to the CPU and the processor nodes. The first optical transceiver is connected to the Ethernet switch. The second optical transceiver is connected to the first optical transceiver. The PHY is connected to the second optical transceiver. The third optical transceiver is connected to the PHY.