8 results about "Processor node" patented technology

A new and improved technique for computerized processing of data for exploration and production of hydrocarbons and reservoir simulations that includes a multi-channel quality of service (QoS) in a group of high performance computing (HPC) clusters (which may collectively be referred to as a "data processing system"). The data processing system may be logically segregated into several logical subclusters and may have several publisher nodes, controlled by a master scheduler, serving several groups of processor nodes (the subscriber nodes) that execute different processing applications independently of each other. Multiple datawriters (DW) may send data through multiple channels of compute nodes, whenever there is a free master node. The multi-channels are established and take place as part of the multi-channel quality of service (QoS) settings.

Systems and methods for flexible edge computing are provided that include a central controller communicatively coupled to a plurality of processor nodes forming a distributed compute mesh, wherein the central controller includes a memory storing edge computing algorithms which, when executed, cause the central controller to perform operations comprising receiving, in real-time, task data characterizing compute workloads from a compute client, energy data characterizing local energy availability and pricing proximate the processor nodes, and compute market pricing data, determining a predicted profitability and predicted operational suitability associated with executing the one or more compute workloads at each of the plurality of processor nodes based on the task data, the energy data, the compute data, and routing the one or more compute workloads to one or more of the plurality of processor nodes having a highest predicted profitability or highest predicted operational suitability.

The application discloses an open multifunctional low-delay high-stability interconnection method and belongs to the technical field of communication and network interconnection. The method comprises the following steps: establishing passive point-to-point physical connection based on an industry standard among a plurality of accelerator processor nodes; realizing nanosecond-level precision global virtual clock synchronization among the nodes through a Sideband management channel independent of a main data channel; based on the synchronized clock, adopting a time window-restricted forward credit flow control mechanism to complete the cooperative reservation and authorization of link time periods and receiving buffer resources before data transmission; the sender sends data through the main data channel within the authorized time window, and the receiver verifies the compliance of the data arrival time; all control signaling is transmitted through the Sideband channel and is physically isolated from the high-speed data channel. The application realizes open and compatible, low-power-consumption and high-bandwidth physical interconnection, provides nanosecond-level low-delay and high-deterministic data transmission capacity, and improves the communication efficiency and system stability of a large-scale computing cluster.

The memory access method of the computing device and the related device and method are applied to a first computing device associated with an open segment cache. The method comprises the following steps: first, in response to a memory access instruction initiated by a meta-thread executed on the first computing device, obtaining a target open segment address and a target offset from the memory access instruction; then, based on the target open segment address, obtaining a corresponding open segment data structure from the local memory of the first computing device, wherein the open segment data structure at least comprises a target physical device identifier and a target physical base address; thereafter, based on the target physical base address and the target offset, determining an actual physical access address; finally, based on the target physical device identifier, initiating a physical memory access request carrying the actual physical access address to a second computing device, thereby improving the compatibility and efficiency of data communication between multiple heterogeneous processor nodes in an extended network.

This application provides a verification system, a design verification method, and related equipment. The verification system includes: a slave device module, a listening filter module, and a reference model connected to each other. The slave device module sends a normalized address to the listening filter module to query the corresponding cache line status information. The listening filter module queries the cache line status information based on the normalized address and compares it with the output of the reference model to determine the verification result. The listening filter module includes a design under test (DUT), which includes a local node monitoring unit storing the cache line directory within the corresponding processor node and a remote node monitoring unit storing a cache line directory shared among the processor nodes. Based on the local node monitoring unit and the remote node monitoring unit, the DUT provides different directory query modes. The reference model is a model that performs co-simulation with the DUT to verify the accuracy of the design.

A data server system includes a central processing unit (CPU) and a baseboard management controller (BMC) disposed on a motherboard, an Ethernet switch, a plurality of processor nodes, a first bus, a second bus and a first optical transceiver disposed on a baseboard, and a second optical transceiver, a third optical transceiver and a physical layer chip (PHY) disposed on an optical module board. The BMC is connected to the CPU. The Ethernet switch is connected to the CPU and the BMC. The processor nodes are connected to the Ethernet switch and the CPU. The first and second buses are connected to the CPU and the processor nodes. The first optical transceiver is connected to the Ethernet switch. The second optical transceiver is connected to the first optical transceiver. The PHY is connected to the second optical transceiver. The third optical transceiver is connected to the PHY.

Systems and methods for flexible edge computing are provided that include a central controller communicatively coupled to a plurality of processor nodes forming a distributed compute mesh, wherein the central controller includes a memory storing edge computing algorithms which, when executed, cause the central controller to perform operations comprising receiving, in real-time, task data characterizing compute workloads from a compute client, energy data characterizing local energy availability and pricing proximate the processor nodes, and compute market pricing data, determining a predicted profitability and predicted operational suitability associated with executing the one or more compute workloads at each of the plurality of processor nodes based on the task data, the energy data, the compute data, and routing the one or more compute workloads to one or more of the plurality of processor nodes having a highest predicted profitability or highest predicted operational suitability.