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16 results about "Processor node" patented technology

Processor nodes. The processor nodes drive all functions in the storage system. Each node consists of a Power® server that contains POWER7® or POWER7+™ processors and memory.

Cluster computing resource isolation method and device, electronic equipment and storage medium

The invention provides a cluster computing resource isolation method and device, electronic equipment and a storage medium, and relates to the technical field of cluster computing resource management. And scheduling the containerized task to an adaptive physical graphics processor node based on the information, intercepting a resource access request during task operation, allocating an isolated video memory space and a computing context according to an allocated virtual graphics processor resource limit, and dynamically maintaining an isolated state of multiple tasks, so that the task access efficiency is improved. The problems of inter-task interference, limited hardware compatibility, insufficient resource allocation flexibility and low utilization rate caused by lack of a flexible virtualization scheme for decoupling from hardware and imperfect resource scheduling and isolation mechanisms in the prior art can be solved.
Owner:CHINA UNICOM ONLINE INFORMATION TECHNOLOGY CO LTD

System and method for scalable on-array processing and interference mitigation using adaptive beamforming

Methods and systems are described herein for adaptive beamforming and interference mitigation using a time synchronized scalable cohered on-array processing system (“system”). The system may be a phased array implementing a software-defined radio using multi-input-multi-output antenna elements. The system includes multiple subarray elements which are configured into a tiered array of scalable subarrays that performs intermediary collation, coherence, noise reduction, and adaptive beamforming operations through processor nodes disposed between tiers. The intermediary collation operations process discrete portions of node excitation data to enable the phased array to generate an adaptive beam profile that directs high-directionality beams toward desired targets while adaptively partitioning interference sources between subarray elements. Further, the system makes use of a scalable multidimensional array to provide telecommunication and electromagnetic wave manipulation operations for applications of varying scale.
Owner:CHAOS IND INC

Online dynamic adjustment method, system and equipment for control parameters and medium

The invention provides an online dynamic adjustment method, system and device for control parameters and a medium, and the method comprises the steps: collecting storage use data from each processor node, processing state fluctuation in a multi-node environment through employing a distributed collection protocol, and obtaining the current storage occupation proportion of each node; determining high-load state nodes by adopting a threshold comparison method according to the current storage occupation proportion of each node; analyzing a storage state of a processor node adjacent to the high-load state node, and determining a target node of the migration task; and sending a part of data packets of the high-load node to a target node through a transmission path based on an encrypted transmission protocol to complete online dynamic adjustment. According to the method, real-time monitoring of the storage state is realized in a multiprocessor environment, and storage resources are dynamically balanced through a collaboration mechanism among nodes.
Owner:BEIJING POLYTECHNIC COLLEGE

Autonomous Repeater System

An autonomous repeater system includes a processor node, a storage device, and two or more nodes. The processor node includes a processor, software, and a processor communication device. The software autonomously and continuously queries latitude data, longitude data, and signal-to-noise ratio data from two or more nodes and calculates a target latitude and a target longitude for each node using the latitude data, the longitude data, and the signal-to-noise ratio data received from the two or more nodes. The processor communication device is operatively connected to the processor to transmit or receive the latitude data, longitude data, and signal-to-noise ratio data between the two or more nodes and the processor and transmitting the target latitude and the target longitude calculated for each node. Each node includes a node communication device that transmits and receives data between the two or more nodes and the computer processor.
Owner:THE UNITED STATES OF AMERICA AS REPRESENTED BY THE SECRETARY OF THE NAVY

System and method for a deployable mesh wireless network

Disclosed herein is a system and method for a mesh wireless network, deployable via an aircraft, drone, or other airborne system. Wide area network (WAN) connectivity is provided via a backhaul interface selected from a modem, satellite transceiver, wired module, or other wireless interface. Nodes are powered internally by portable supplies such as batteries, solar, wind, or kinetic energy, enabling continuous operation. The system enables rapid deployment in conflict zones, disaster areas, maritime or remote searches, and mass casualty events, with uninterrupted connectivity even when nodes are damaged or lost. Each node is portable, durable, and water-resistant, with housing comprised of resilient materials to withstand explosions, ammunition, and extreme weather. Multiple nodes form a mesh Wi-Fi network, with traffic routable via any node connected to a backhaul channel. Each node includes a processor for routing and inter-node communication. Nodes may also implement encryption, anti-jamming, and overlapping densities to maintain connectivity.
Owner:SOCRANSKY ALEXANDER

Computing node, method and device for detecting computing node

ActiveCN121056310BHardware monitoringTransmissionGlobal address spaceGraphics
The disclosure provides a kind of computing node, the detection method and equipment of computing node, it is related to computer technical field, by powering on computing node, BMC detects the type of central processing unit according to the configuration pin of mainboard, configures communication link;According to the deployment environment of rack in situ pin determination computing node, and load the out-of-band monitoring strategy corresponding to deployment environment;According to power supply configuration detection whether there is voltage conversion module, adjust I2C rate;The configuration information of graphics processor node connected with computing node is detected, and the switch and central processing unit are configured;According to the interconnection mode of switch downstream in situ state determination switch, and carry out global address space mapping;Control complex programmable logic device to central processing unit power on.In this way, the adaptability, stability, reliability and performance of computing node can be improved, signal attenuation and jitter in transmission process are reduced, and data transmission efficiency and quality are improved.
Owner:INSPUR SUZHOU INTELLIGENT TECH CO LTD

High performance and grid computing with multi-channel data distributor quality of service

PCT designated stageWO2026148289A1Qos quality of serviceData processing system
A new and improved technique for computerized processing of data for exploration and production of hydrocarbons and reservoir simulations that includes a multi-channel quality of service (QoS) in a group of high performance computing (HPC) clusters (which may collectively be referred to as a "data processing system"). The data processing system may be logically segregated into several logical subclusters and may have several publisher nodes, controlled by a master scheduler, serving several groups of processor nodes (the subscriber nodes) that execute different processing applications independently of each other. Multiple datawriters (DW) may send data through multiple channels of compute nodes, whenever there is a free master node. The multi-channels are established and take place as part of the multi-channel quality of service (QoS) settings.
Owner:SAUDI ARABIAN OIL CO

Flexible edge computing and data center mesh network for optimizing computational and energy efficiency utilizing available processing resources

PendingUS20260186843A1Data centerProcessor node
Systems and methods for flexible edge computing are provided that include a central controller communicatively coupled to a plurality of processor nodes forming a distributed compute mesh, wherein the central controller includes a memory storing edge computing algorithms which, when executed, cause the central controller to perform operations comprising receiving, in real-time, task data characterizing compute workloads from a compute client, energy data characterizing local energy availability and pricing proximate the processor nodes, and compute market pricing data, determining a predicted profitability and predicted operational suitability associated with executing the one or more compute workloads at each of the plurality of processor nodes based on the task data, the energy data, the compute data, and routing the one or more compute workloads to one or more of the plurality of processor nodes having a highest predicted profitability or highest predicted operational suitability.
Owner:ENNOFLOW TECHNOLOGIES INC

An open multi-functional low-latency high-stability interconnection method

The application discloses an open multifunctional low-delay high-stability interconnection method and belongs to the technical field of communication and network interconnection. The method comprises the following steps: establishing passive point-to-point physical connection based on an industry standard among a plurality of accelerator processor nodes; realizing nanosecond-level precision global virtual clock synchronization among the nodes through a Sideband management channel independent of a main data channel; based on the synchronized clock, adopting a time window-restricted forward credit flow control mechanism to complete the cooperative reservation and authorization of link time periods and receiving buffer resources before data transmission; the sender sends data through the main data channel within the authorized time window, and the receiver verifies the compliance of the data arrival time; all control signaling is transmitted through the Sideband channel and is physically isolated from the high-speed data channel. The application realizes open and compatible, low-power-consumption and high-bandwidth physical interconnection, provides nanosecond-level low-delay and high-deterministic data transmission capacity, and improves the communication efficiency and system stability of a large-scale computing cluster.
Owner:SHENZHEN WANDTEC OPTRONICS CO LTD

Resource allocation method and device for processor cluster, electronic equipment, medium and product

The invention provides a resource allocation method and device for a processor cluster, electronic equipment, a medium and a product. Relates to the field of computer science. The method is applied to a server, and comprises the steps of obtaining a task specification of a to-be-processed task, constructing a resource mirror image of a target processor node in real time, carrying out pre-push check processing based on the resource mirror image and the task specification to generate a corresponding resource judgment result, determining a to-be-cleaned workload list, resource release information and a scheduling feasibility analysis result, and generating a corresponding interactive card based on the resource judgment result, the to-be-cleaned workload list, the resource release information and the scheduling feasibility analysis result, and performing resource allocation processing based on the interactive card. Based on the method provided by the invention, the resource utilization rate and the service reliability of the GPU cluster can be improved.
Owner:CHINA UNITED NETWORK COMM GRP CO LTD +2

Memory access method of computing device and related device

ActiveCN122045080BAccess methodProcessor node
The memory access method of the computing device and the related device and method are applied to a first computing device associated with an open segment cache. The method comprises the following steps: first, in response to a memory access instruction initiated by a meta-thread executed on the first computing device, obtaining a target open segment address and a target offset from the memory access instruction; then, based on the target open segment address, obtaining a corresponding open segment data structure from the local memory of the first computing device, wherein the open segment data structure at least comprises a target physical device identifier and a target physical base address; thereafter, based on the target physical base address and the target offset, determining an actual physical access address; finally, based on the target physical device identifier, initiating a physical memory access request carrying the actual physical access address to a second computing device, thereby improving the compatibility and efficiency of data communication between multiple heterogeneous processor nodes in an extended network.
Owner:SUZHOU YIZHU INTELLIGENT TECH CO LTD

Verification system, design verification method and related device

PendingCN122285435AReference modelingProcessor node
This application provides a verification system, a design verification method, and related equipment. The verification system includes: a slave device module, a listening filter module, and a reference model connected to each other. The slave device module sends a normalized address to the listening filter module to query the corresponding cache line status information. The listening filter module queries the cache line status information based on the normalized address and compares it with the output of the reference model to determine the verification result. The listening filter module includes a design under test (DUT), which includes a local node monitoring unit storing the cache line directory within the corresponding processor node and a remote node monitoring unit storing a cache line directory shared among the processor nodes. Based on the local node monitoring unit and the remote node monitoring unit, the DUT provides different directory query modes. The reference model is a model that performs co-simulation with the DUT to verify the accuracy of the design.
Owner:海光信息技术(成都)有限公司

Memory access method of computing device and related device

The embodiment of the invention provides a memory access method for computing equipment and related equipment, the method is applied to first computing equipment, the first computing equipment is provided with an open segment cache in an associated manner, and the method comprises the following steps: firstly, responding to a memory access instruction initiated by a meta-thread executed on the first computing equipment; obtaining a target open field address and a target offset from the memory access instruction; then, based on the target open segment address, a corresponding open segment data structure is obtained from a local memory of the first computing device, and the open segment data structure at least comprises a target physical device identifier and a target physical base address; then, based on the target physical base address and the target offset, determining an actual physical access address; and finally, based on the target physical device identifier, initiating a physical memory access request carrying the actual physical access address to the second computing device, thereby improving the compatibility and efficiency of data communication among the multiple heterogeneous processor nodes in the extended network.
Owner:SUZHOU YIZHU INTELLIGENT TECH CO LTD

Data server system

ActiveUS12671922B2TransceiverOptical Module
A data server system includes a central processing unit (CPU) and a baseboard management controller (BMC) disposed on a motherboard, an Ethernet switch, a plurality of processor nodes, a first bus, a second bus and a first optical transceiver disposed on a baseboard, and a second optical transceiver, a third optical transceiver and a physical layer chip (PHY) disposed on an optical module board. The BMC is connected to the CPU. The Ethernet switch is connected to the CPU and the BMC. The processor nodes are connected to the Ethernet switch and the CPU. The first and second buses are connected to the CPU and the processor nodes. The first optical transceiver is connected to the Ethernet switch. The second optical transceiver is connected to the first optical transceiver. The PHY is connected to the second optical transceiver. The third optical transceiver is connected to the PHY.
Owner:SQ TECH (SHANGHAI) CORP +1

Server and server system

ActiveCN223956035UDigital data processing detailsOptical ModuleProcessor node
The utility model discloses a server and a server system. The server comprises a processor node, an optical module, a retimer and a control module, a first interconnection signal transmission end of the processor node is connected with a second interconnection signal transmission end of the retimer, a third interconnection signal transmission end of the retimer is connected with a fourth interconnection signal transmission end of the optical module, and a fifth interconnection signal transmission end of the optical module is connected with the switching module; the in-place signal output end of the optical module is connected with the in-place signal detection end of the control module, and the reset signal output end of the control module is connected with the reset signal input end of the re-timer. According to the utility model, the in-place detection of the optical module can be realized, so that the server can obtain the plugging condition of the optical module in time.
Owner:广州壁仞智能科技有限公司 +1

Flexible edge computing and data center mesh network for optimizing computational and energy efficiency utilizing available processing resources

PCT designated stageWO2026143156A1Processor nodeEdge computing
Systems and methods for flexible edge computing are provided that include a central controller communicatively coupled to a plurality of processor nodes forming a distributed compute mesh, wherein the central controller includes a memory storing edge computing algorithms which, when executed, cause the central controller to perform operations comprising receiving, in real-time, task data characterizing compute workloads from a compute client, energy data characterizing local energy availability and pricing proximate the processor nodes, and compute market pricing data, determining a predicted profitability and predicted operational suitability associated with executing the one or more compute workloads at each of the plurality of processor nodes based on the task data, the energy data, the compute data, and routing the one or more compute workloads to one or more of the plurality of processor nodes having a highest predicted profitability or highest predicted operational suitability.
Owner:ENNOFLOW TECHNOLOGIES INC