A
central processing unit, CPU (10, 20), comprising: a
processing circuit arrangement; and a
control unit extracting instructions from a memory unit (18), the instructions causing the
control unit to: to execute respective threads (210, 212, 214) by means of the
processing circuitry, which threads are held in a local
run queue (205) associated with the
processing circuitry and with a poller, wherein the
control unit interleaves the execution of the respective threads (210, 212, 214) and the poller, randomly selects the poller to be executed after the execution of a thread in the local
run queue (205) from a shared poller array (240), and wherein the execution of the poller by the processing circuitry causes the poller to determine whether the CPU has a task to perform for a device external to the CPU; after clearing the local
run queue (205), checking a buffer (215) shared by a group of CPUs comprising the CPU and one or more additional CPUs for threads to be executed; taking a stack of threads (220, 222, 224, 226, 228) associated with the group of CPUs from the run
queue of the buffer (215); to place the stack of threads (220, 222, 224, 226, 228) into the local run
queue (205); and to execute, by the processing circuitry, a respective thread in the stack of threads (220, 222, 224, 226, 228) from the local run
queue (205).