28 results about "CPU time" patented technology

The invention relates to the technical field of computer security, in particular to a security isolation method for an edge computing node of the Internet of Things, which comprises the following steps of: identifying a trust domain in the edge computing node of the Internet of Things, defining a sensitive data source, and generating a sensitive data identifier set, and based on the sensitive data identifier set, planning minimum central processing unit time and maximum memory bandwidth for each isolation domain to form an isolation domain resource limit, and establishing initial security isolation configuration. According to the method, the identification mechanism based on the sensitive data identification set is introduced into the edge computing node of the Internet of Things, the definition of the trust domain can be realized, and the resource limit is constructed in combination with the minimum central processing unit time and the maximum memory bandwidth of each isolation domain, so that the basic distribution mode of computing resources is restrained, and the computing efficiency is improved. And resources are prevented from being occupied by high-frequency low-priority tasks. After a data entry is positioned on a system level and stain marks are applied according to sensitive attributes, sensitive data images have identifiable features on a memory level.

The invention discloses a process monitoring method, system and device for a baseboard management controller and a medium, and relates to the technical field of server management, and the method comprises the steps: continuously collecting CPU occupation information of a target process from an information collection file through a kernel interface based on a preset sampling time interval, and calculating the CPU utilization rate of the target process, and calculating a target parameter based on the CPU utilization rate in the preset sliding time window, analyzing the target parameter and the CPU utilization rate based on a preset threshold value, and determining the CPU state of the target process. According to the method, the CPU usage rate of each process can be continuously calculated by periodically sampling the CPU occupation information and the system CPU time of the target process, the CPU usage condition of the target process is analyzed based on the sliding time window, sampling and analysis can be automatically carried out, whether abnormity exists or not is monitored in real time, and the monitoring efficiency of the target process is improved.

The invention discloses a real time operating system (RTOS) multi-task priority scheduling and real-time control method based on advanced RISC machines (ARM), and relates to the technical field of embedded computing and control. Comprising the following steps: S1, time slice management setting: dividing CPU time according to a preset time period to obtain time slices; s2, performing task scheduling: setting each task according to a task control block, and performing context switching and priority arbitration through an OSScheduler () function; and S3, performing exception response: performing forced interruption and exception recovery operation through a set multi-stage exception classification mechanism. Through a three-level decision model and a partition response mechanism, it can be ensured that a high-priority task can be responded in time within strict time constraints, the hard real-time requirement is met, meanwhile, CPU time is divided through a fixed time slice, a counter is updated through timer interruption, and therefore the time deviation of task execution can be reduced, and the task execution efficiency is improved. And the certainty of the system is improved.

Estimated and actual processor runtimes improve computer functioning in fairly sharing computing resources. Today's computers and cloud-based services serve many users and many software applications sharing CPU resources. An operating system thus implements a scheduling policy that fairly allocates CPU time. A scheduler thread implements the scheduling policy based on estimated processor runtimes, and actual processor runtimes, associated with tasks. The operating system may maintain running tallies or totals for a user / group / organization based on credits (e.g., the estimated processor runtimes) and / or on penalties (e.g., the actual processor runtimes). The scheduler thread may select tasks for worker threads based on the credits and / or the penalties, thus ensuring that no user / group / organization unfairly consumes CPU time.

The application discloses a kind of multi-level data structure, generation and dynamic rendering method and system, according to the size of estimated charge-discharge test data, the size of the storage space of the single index data unit of the index data of multi-level data is set;Test data generated in the charge-discharge test process is written in the application data in multi-level data, after writing each test data, its index information is written in the index data unit of multi-level data;According to the address pointer in each index data unit, the index record of all application data is extracted;According to vertical scroll offset and the height of each row data, the height of current rendering interface obtains the starting row and end row of rendering;According to the extracted index record, all row data between starting row and end row are obtained and rendered;The application only needs to load the index information of each level data, according to the index information, load and render charge-discharge test data, reduce memory occupation and CPU time, improve the efficiency of battery test.

This application discloses a dual-network synchronous switch and a dual-network synchronous switching method, relating to the field of network communication technology. The dual-network synchronous switch comprises a field programmable gate array (FPGA) and a central processing unit (CPU). The FPGA includes a high-speed interface processing module, a time frame module, a MAC processing module, a clock synchronization module, a time maintenance module, an FPGA time interaction module, and a data exchange module. The CPU includes a data processing module, a CPU time interaction module, and an Ethernet MAC module. This application implements clock information exchange through the FPGA time interaction module and the CPU time interaction module, and data exchange through the data exchange module and the data processing module. The Ethernet MAC module encapsulates the received clock information and data, which can then be communicated with other networks after encapsulation, thereby achieving clock synchronization and data exchange between the dual networks.

The invention belongs to the field of integrated circuit design automation, and discloses a multi-PVT corner establishment retention time characterization method and a related device.The method comprises the steps that firstly, an initial search interval is pre-estimated through a logical effort analysis method, and a key area is quickly locked; secondly, introducing a bias item into a test point generated based on binary interpolation through hypothesis interpolation error distribution to form a bias test point, and solving an optimal bias amount by taking a minimum expected interval length as a target so as to obtain an optimal test point; and finally, executing simulation and outputting a representation result. By adopting the method, the characterization efficiency is remarkably improved, a higher convergence speed is realized in a steep transformation and multi-PVT angular point scene, the problems of interpolation stagnation and low speed of a dichotomy method are effectively solved, the sign-off level precision is ensured, meanwhile, the simulation iteration times and CPU time consumption are greatly reduced, and an efficient and reliable solution is provided for a chip time sequence bottleneck.

The invention discloses a historical load and real-time state-based resource available amount prediction method and system, and relates to the technical field of big data analysis, and the method comprises the steps: collecting data to form a CPU data set and a GPU data set; removing abnormal values and carrying out feature coding to form a structured feature matrix; extracting a CPU time sequence rule, and introducing an attention mechanism to dynamically adjust and predict a CPU available interval; capturing GPU long-period stage features, and predicting a GPU available interval in combination with a historical stage computing power demand rule; and integrating the available intervals of the two into a global resource matrix, and matching new task resource requirements to judge whether migration is needed or not. The system comprises a data acquisition module, a feature processing module, an available prediction module and a task judgment module which work cooperatively. According to the method, the historical load and the real-time state are fused, the prediction accuracy of the available resource amount is improved, resource scheduling is optimized, failure of tasks due to insufficient resources is avoided, and the computing power resource utilization rate is increased.

The invention provides a multi-core heterogeneous SOC resource optimization method and system, and belongs to the technical field of multi-core heterogeneous system.The multi-core heterogeneous SOC resource optimization method comprises the steps that according to the real-time resource requirement of a to-be-processed task, the CPU time slice quota and the AI accelerator computing power unit quota corresponding to the to-be-processed task are determined; dynamically allocating a CPU time slice quota and an AI accelerator computing power unit quota to a container for executing a to-be-processed task through a container scheduling layer; determining a delay demand and a bandwidth demand of communication between the containers according to a communication demand of data transmission between the containers; and selecting a communication protocol for data transmission between the containers according to the delay demand and the bandwidth demand, and completing data transmission between the containers through the inter-core communication layer. According to the invention, through dynamic allocation of task resources in the multi-core heterogeneous SOC and adaptive selection of a communication protocol, high-efficiency data transmission for a multi-task scene in the multi-core heterogeneous SOC is realized.

The present invention relates to a circuit structure for fine-tuning the square-wave control phase of a brushless DC motor. The circuit structure comprises a PWM configuration register that generates six n-bit PWM signals based on rotor position; a 3-8 decoder that divides the signals into six signals, namely, bit 1 through bit 6; an expansion module that expands the bit 1 through bit 6 signals into n-bit identical signals, resulting in 6n-bit signals; an n-bit AND gate module that performs an AND operation on the expanded 6n-bit signals and the 6n-bit PWM configuration signals; and an n-bit OR gate module that receives the six fused signal groups and performs an OR operation on the six n-bit PWM configuration signals. The circuit structure and method for fine-tuning the square-wave control phase of a brushless DC motor employing the present invention fine-tunes the phase advance or lag by changing the duty cycle configuration register, thereby improving motor operating efficiency without requiring complex software programming. Hardware implementation of the commutation process simplifies software implementation and reduces CPU time, freeing the CPU for other safety controls.

The application relates to an intelligent cockpit system based on a Type I virtualization technology and a resource division method thereof. The system comprises a hardware platform, at least one virtualization-supported processor, memory, storage device and peripheral device; a Type I virtualization management program running on the hardware platform and directly managing hardware resources; a first virtual customer system running an embedded Linux system and used for driving an instrument display screen; and a second virtual customer system running an Android system and used for driving a central control display screen. Two independent customer systems are virtually generated on a single hardware platform through the Type I virtualization management program, and embedded Linux and Android are respectively run to support the functions of the instrument screen and the central control screen. Through CPU time-sharing scheduling, independent memory division, device direct connection and sharing combination, efficient isolation and reuse of resources are realized, so that the hardware resource utilization rate is effectively improved, and the system cost and power consumption are reduced.

The invention provides a time sequence synchronization method in a software HDL co-simulation system. A clock management module and a DPI mutual exclusion lock module on a software side are included. A DUT model at a hardware side; the DPI interface is used for instruction interaction between a software side and a hardware side; the method comprises the following steps: S1, a clock management module accesses a DPI mutual exclusion lock module to obtain a DPI interface state; s2, when the state of the DPI is that the DPI is idle, the clock management module obtains the time point of calling the DPI last time and the current CPU time point, and the time interval of the software side is obtained through calculation; s3, determining the number of simulation cycles of the DUT model based on the time interval; and S4, calling a DPI interface by the clock management module to push the simulation loop number of turns of the DUT model, and repeating the steps S1 to S4 until the co-simulation is finished so as to realize the time sequence synchronization of the simulation time domain and the software side.

The invention provides a MicroROS-oriented lightweight adaptive real-time task scheduling method and system, and the method comprises the steps: building an isolation type double-layer scheduling frame, and distributing a MicroROS event task and a real-time task to different scheduling layers; the real-time task layer adopts a scheduling strategy combining priority preemption and time slice rotation, and the event task layer adopts a non-preemption type collaborative execution strategy; shared resource competition is processed through a dynamic priority improvement mechanism, and when a real-time task applies for a shared resource, the priority of the shared resource is automatically improved to the highest priority of waiting for the resource and safety increment; and dynamically adjusting the CPU time quota of the event task layer, and dynamically optimizing resource allocation based on a self-adaptive time window model according to the real-time task load, the event queue depth and the task execution time. According to the method, an isolated double-layer scheduling framework is adopted, and the cooperative scheduling of a real-time task and a MicroROS communication task under resource constraints is realized in combination with a dynamic priority lifting and self-adaptive time window model.

The present invention provides a method, device, and equipment for automatically selecting a virtual machine hot migration acceleration solution. The method includes the following steps: after receiving a request to perform virtual machine hot migration, parsing automatic acceleration parameters; when it is determined that automatic migration acceleration needs to be started according to the parsed parameter values, calling a first virtualization interface to obtain the CPU time of the virtual machine; calculating the average CPU utilization rate through the CPU time; when the average CPU utilization rate is greater than a set first threshold, calling a second virtualization interface to obtain the memory usage status; calculating the memory utilization rate according to the obtained memory usage status; when the memory utilization rate is greater than a set second threshold, selecting an automatic convergence solution; calling a third virtualization interface to configure parameters for the selected acceleration solution to complete the migration. According to the running state of the virtual machine, a suitable migration acceleration solution is automatically selected to avoid the occurrence of migration failure problems caused by users' unfamiliarity with relevant technical principles.

This disclosure relates to a method, apparatus, electronic device, and storage medium for calculating CPU utilization. The method for calculating CPU utilization includes: obtaining the CPU execution time corresponding to a process; determining the total CPU time corresponding to the process based on the CPU execution time and the number of available cores of the process; determining CPU usage information based on the duration of each available core at each frequency; determining the maximum CPU processing capacity based on the total CPU time and the frequency corresponding to each core in the CPU; and determining the CPU utilization rate corresponding to the process based on the CPU execution time, total CPU time, CPU usage information, and maximum CPU processing capacity. The method provided by this disclosure can automatically calculate the CPU utilization rate corresponding to a process, improving the accuracy and reliability of CPU utilization.

The present application provides a method for obtaining key function call features, a knowledge retrieval method, a device, and a medium, which relate to the field of operating system technology. The method includes: obtaining a function call feature graph; inputting a prompt word template and a function call feature graph into a multimodal large model to obtain key function call features output by the multimodal large model; wherein the key function call features include a target call flow in multiple call flows, the total CPU time proportion of the last call function in the target call flow, the CPU time proportion of the last call function's own logic, and the CPU time proportion of the last call function calling the next function; the target call flow is the call flow with the largest total CPU time proportion of the last call function in the multiple call flows. In this embodiment, the multimodal large model is used to extract key function call features from the function call feature graph, so that more function call detail information can be obtained from the function call feature graph.

The invention discloses an eBPF-based transaction request CPU resource time consumption acquisition method and system, and belongs to the technical field of computer system performance monitoring. According to the method, an eBPF program is implanted in a kernel, a probe is deployed at a task scheduling key point, the execution time of a transaction request on a CPU is captured in real time, and the CPU time is accurately associated with a unique identifier of the transaction request through eBPF mapping. The system comprises a request identification module, an eBPF probe module, a time calculation module and a data output module. The problem that transaction data and CPU resource information are isolated in an existing monitoring technology is solved, fine-grained resource monitoring and analysis are achieved, the method is suitable for performance optimization and resource management of a high-concurrency system, resource bottlenecks can be recognized in advance, and the system stability and the resource utilization rate can be improved.

The application provides a timing synchronization method in a software HDL co-simulation system, comprising a clock management module and a DPI mutex module on the software side, a DUT model on the hardware side, and a DPI interface for instruction interaction between the software side and the hardware side; the method comprises the following steps: S1: the clock management module accesses the DPI mutex module to obtain the state of the DPI interface; S2: when the state of the DPI interface is idle, the clock management module obtains the time point of the previous call of the DPI interface and the current CPU time point, and calculates the time interval of the software side; S3: the number of simulation loop cycles of the DUT model is determined based on the time interval; S4: the clock management module calls the DPI interface to advance the number of simulation loop cycles of the DUT model, and steps S1 to S4 are repeated until the co-simulation ends, so as to realize the timing synchronization between the simulation time domain and the software side.

The invention provides a partition system process CPU utilization rate monitoring system and a control method thereof, and the system comprises a local collection module which is deployed in each partition, collects the CPU time data of all processes in the partition in real time, and calculates the CPU utilization rate of the processes; the global coordination module receives the data acquired by the local acquisition module in each partition in real time, performs data aggregation and unified storage, and does not directly participate in process monitoring in the partition; the exception detection module is used for distinguishing process exceptions, local acquisition module exceptions and data transmission exceptions according to the stored data; an isolation adaptive distributed architecture design is adopted, and a local acquisition module is set to only access CPU time data of an internal process of a partition where the local acquisition module is located; and meanwhile, a global coordination module is arranged and does not directly intervene in process scheduling in the partition, so that the damage of traditional cross-partition monitoring to an isolation boundary is avoided, and the standard requirements of core partition systems such as ARINC653 and the like are met.

This invention relates to the field of security auditing technology, specifically to a method and system for security auditing industrial control systems (ICS). The method includes the following steps: collecting data on cycle time, start timestamp, completion timestamp, CPU time slice usage, and peak memory usage for critical control, communication, and security tasks of a real-time operating system (RTOS). This invention collects data on cycle time, timestamps, CPU usage, and memory usage of critical ROS tasks, sets task execution time boundaries and resource consumption envelopes, and then uses historical data statistics and logical rule deduction to construct a set of expected relationship rules between task timing and resource consumption. Simultaneously, it specifies the key length for symmetric and asymmetric encryption, initialization vector generation, hash algorithm selection, key derivation parameters, and encryption operation context, thereby establishing a comprehensive and specific baseline for ICS behavioral norms.

The invention aims to provide a database cluster system and method based on a Linux lightweight virtualization technology. The database cluster system based on the Linux lightweight virtualization technology comprises a physical layer, a database cluster layer, a database cluster layer and a database cluster layer, wherein the physical layer is provided with standard x86 server hardware; the operating system layer is provided with a Linux operating system which supports cgroup and LXC functions; the virtualization layer is used for creating an independent resource control group for each application or a key component thereof based on a cgroup function of a Linux kernel, and accurately controlling a CPU time slice, a memory usage and recovery strategy, a block device I / O bandwidth and weight, and a network bandwidth and priority; and the application layer is a key big data application component which comprises an FE / BE node of a database service Apache Dores, a calculation engine and a Web service which are respectively operated in independent LXC containers. According to the method, efficient utilization of hardware resources, strong isolation between applications, stability guarantee, rapid elastic expansion of the resources and smooth seamless evolution from a single-machine all-in-one machine to a distributed cluster can be realized, so that a hardware input curve is smoother.

The invention discloses a resource scheduling method and device in a vehicle-mounted virtualization environment. The method comprises the following steps: acquiring a virtual machine set currently running in a vehicle-mounted virtualization system; extracting a static security attribute and a dynamic load feature corresponding to each virtual machine, determining a real-time urgency factor of each virtual machine, and determining a dynamic scheduling weight of each virtual machine according to the real-time urgency factor of each virtual machine; then, controlling a global scheduler to allocate physical resources to each virtual machine at the starting moment of a global scheduling period according to the dynamic scheduling weight; in the current physical CPU time slice, controlling a local scheduler to perform task-level preemption scheduling on the current virtual machine based on an earliest deadline priority strategy; the global scheduler is controlled to dynamically allocate the physical CPU time slices by fusing the static security attributes and the dynamic load characteristics, so that the resource allocation efficiency in the vehicle-mounted virtual environment can be improved, and the real-time performance and the security of the vehicle-mounted application are effectively guaranteed.

The invention discloses a distributed query method and system based on a Pipeline model, belongs to the technical field of databases, and aims to solve the technical problem of how to improve query response speed and assembly line processing capacity for a time sequence database. Comprising the following steps: mapping a logic query plan into a physical query plan with a standardized Next interface based on a volcano model operator hierarchical architecture; the method comprises the following steps: splitting a physical query plan into a plurality of Pipeline Tasks based on time slices and operator complexity, and scheduling the Pipeline Tasks in a pull mode of a volcano model; based on the task type and the system load, setting a CPU time slice threshold value, dynamically adjusting the threshold value, and when the task execution time exceeds the CPU time slice threshold value, swapping out the currently executed task; and data transmission and query collaborative operation among distributed nodes is realized through outbound and inbound which are used as operators in the volcano model.

The application provides a data processing method and an electronic device. The method comprises: obtaining first capacitance data; obtaining first difference data corresponding to the first capacitance data based on the first capacitance data; generating first touch report point information corresponding to the first capacitance data according to the first difference data; saving the first difference data as first reference difference data and saving the first touch report point information as first reference touch report point information; obtaining second capacitance data; processing the second capacitance data to obtain second difference data corresponding to the second capacitance data; determining a difference value between the second difference data and the first reference difference data, denoted as a first difference value; and if the first difference value is less than a first threshold value, using the first reference touch report point information as second touch report point information corresponding to the second capacitance data. In this way, the CPU time occupied by the touch process can be reduced, thereby reducing the load and power consumption of the touch process.

The present application belongs to the field of integrated circuit design automation, and discloses a multi-PVT corner setup hold time characterization method and related device. The method first uses a logic effort analysis method to estimate an initial search interval, and quickly locks the key area. Secondly, a bias term is introduced in the test points generated based on binary interpolation by assuming an interpolation error distribution to form a biased test point, and the optimal bias is solved by minimizing the expected interval length, thereby obtaining the optimal test point. Finally, the simulation output characterization result is executed. The method significantly improves the characterization efficiency, realizes faster convergence speed in the steep transition and multi-PVT corner scene, effectively overcomes the interpolation stagnation and binary slow speed problem, ensures the sign level precision, greatly reduces the simulation iteration number and CPU time consumption, and provides an efficient and reliable solution for chip timing bottleneck.

A memory reclamation method, electronic device, and storage medium are disclosed, relating to the field of storage technology. The method is applied to an electronic device. In response to a memory allocation request, when the current amount of free memory is below the high memory threshold but above the low memory threshold, the electronic device can wake up an asynchronous reclamation thread. The electronic device can control the asynchronous reclamation thread to run on a CPU small core and / or based on a second priority, and reclaim memory during operation; wherein the second priority is lower than a first priority pre-set for the asynchronous reclamation thread; the CPU time slice corresponding to the second priority is shorter than the CPU time slice corresponding to the first priority; the CPU time slice represents the maximum duration for which the asynchronous reclamation thread can run continuously on the CPU. This method can alleviate the lag issues caused by memory reclamation in electronic devices.

The application discloses a resource available quantity prediction method and system based on historical load and real-time state, relates to the technical field of big data analysis, and collects data to form CPU data set and GPU data set; removes abnormal values and carries out feature coding to form a structured feature matrix; extracts CPU time sequence rules, introduces an attention mechanism to dynamically adjust a predicted CPU available interval; captures GPU long-period stage features, combines historical stage computing power demand rules to predict a GPU available interval; integrates both available intervals into a global resource matrix, matches new task resource demand to determine whether migration is needed. The system comprises data acquisition, feature processing, available prediction and task judgment modules, and the modules work cooperatively. The application combines historical load and real-time state, improves resource available quantity prediction accuracy, optimizes resource scheduling, avoids task failure due to insufficient resources, and improves computing power resource utilization.

A hypervisor of an embedded device switches CPU resources allocated to each virtual machine. CPU cores are allocated to the respective virtual machines so as to overlap each other by an adjustment margin between the guest OSs for which the number of CPU cores needs to be adjusted. For the CPU cores allocated in an overlapping manner, a CPU time is given to only one OS (the other OS is not operated). When the load between the guest OSs changes, the guest OS / virtual machine to which the CPU time is given is switched. Further, for example, control of allocating a dummy process is performed so that the guest OS to which it is not possible to allocate a CPU time due to switching does not allocate a real process.