609 results about "Single event upset" patented technology

A single event upset hardened latch circuit is disclosed. The single event hardened latch circuit includes a first dual-port inverter and a second dual-port inverter. An input is coupled to the first dual-port inverter via a first set of pass gates. The first dual-port inverter is coupled to the second dual-port inverter via a second set of pass gates. The output is connected to the first and second dual-port inverters.

The invention provides a test system and method for a single event effect of an SRAM (System Random Access Memory) type FPGA (Field Programmable Gate Array). The test system comprises a single chip microcomputer processor, an RS232 interface circuit, a USB (Universal Serial Bus) interface circuit, a test FPGA and a storage unit. The test system and method can be used for fault injection tests of a configuration memory and a BRAM (Battery Random Access Memory) of the SRAM type FPGA, and single event function interrupting detection, single event locking detection and single event turning detection including single event turning detection for a configuration storage region, the BRAM and a trigger of the SRAM type FPGA are realized. The invention has the advantages of simplicity in operation, entirety in detection, high accuracy, good real-time property and strong universality.

The invention provides an SRAM type FPGA single particle irradiation test system and method. The test system comprises a host computer, a current monitoring acquisition plate and a test plate. The current monitoring acquisition plate comprises a current monitoring acquisition FPGA, a current acquisition unit, a power supply module and a first communication interface; the test plate comprises a control processing FPGA, a refreshing chip, an SRAM, a configuration PROM, a storage PROM, a second communication interface and a detected FPGA; the host computer is in charge of flow control and data processing; the current monitoring acquisition plate is in charge of power-on and power-off of the test plate and monitoring and testing of FPGA currents; and the test plate is in charge of processing a command sent by the host computer and performing work such as single particle overturning, single particle function interruption detection and the like. According to the invention, the refreshing chip is utilized to replace some of the reconfiguration modules in a conventional irradiation test system so that a detected chip can be more conveniently and reliably refreshed; and the system and method provided by the invention can realize static and dynamic overturning testing on a trigger, and more reliable trigger overturning data can be obtained by combing the two methods.

Apparatus and methods for reducing single-event upsets (SEUs) in latch-based circuitry (e.g., static random access memory (SRAM) cells) and other digital circuitry. According to an exemplary embodiment, a latch-based circuit includes a radiation-hardened latch having first and second cross-coupled inverters and first and second programmable resistance devices (PRDs). The first PRD is coupled between the output of the first inverter and the input of the second inverter. The second PRD is coupled between the output of the second inverter and the input of the first inverter. The PRDs may be programmed to low or high-resistance states. When SET to a low-resistance state, the latch of the latch-based circuitry may be accessed to read the current logic state stored by the latch or to write a new logic state into the latch. When RESET to a high-resistance state, the latch is in a radiation-hard state, thereby preventing the latch from generating SEUs.

The invention discloses a configuration, refreshing and program upgrading integrated system for an SRAM (Static Random Access Memory) type FPGA (Field Programmable Gate Array), belongs to the technical field of aerospace and aims to solve the problem of SEU (Single Event Upset) of the SRAM type FPGA in a spatial irradiation environment. The configuration, refreshing and program upgrading integrated system has a capability of performing program upgrading on the SRAM type FPGA which is in on-orbit work for a long time. The configuration, refreshing and program upgrading integrated system comprises an on-site programmable logic gate array SRAM type FPGA, a comprehensive management anti-fuse FPGA, a configuration program storage chip PROM (Programmable Read-Only Memory), an on-orbit upgrading program storage chip EEPORM (Electrically-Erasable Programmable Read-Only Memory) and an RS422 interface chip. The configuration, refreshing and program upgrading integrated system disclosed by the invention can be used for effectively solving the problem of the SEU of the SRAM type FPGA which is in on-orbit work for a long time and correcting the SEU and single event accumulation inside the SRAM type FPGA without being shut down, also has the function of on-orbit program upgrading of the SRAM type FPGA, and has the characteristics of instantaneity, reliability, flexibility, universality and low cost.

A latch circuit having three latch stages generates a majority output value from the stages, senses when the latch stage outputs are not all equal, and feeds the majority output value back to inputs of the latch stages to reload the latch stages. The latch circuit uses a not-equal gate whose output is an error signal that can be monitored to determine when a single-event upset has occurred. A master stage is controlled by a first multiplexer which receives one system clock signal, while a slave stage is controlled by a second multiplexer which receives another system clock signal, and the latch stage outputs are connected to respective inputs of the not-equal gate, whose output is connected to second inputs of the multiplexers. The latch circuit is part of a latch control system, and reloading of the latch stages takes less than one cycle of the system clock (less than 500 picoseconds).

The invention relates to a fault simulation system and a fault analysis method for single event upset in a large scale integrated circuit SRAM-type FPGA (Field Programmable Gate Array). The fault simulation system comprises a host computer and a control board, wherein the control board comprises a fault injection module, a fault detecting module and a fault analyzing module. The fault simulation system and the fault analysis method provided by the invention are flexible to use, low in cost, high in simulation precision, fast in simulation speed and free from any physical damage to a chip.

In-place resynthesis for static memory (SRAM) based Field Programmable Gate Arrays (FPGAs) toward reducing sensitivity to single event upsets (SEUs). Resynthesis and remapping are described which have a low overheard and improve FPGA designs without the need of rerouting LUTs of the FPGA. These methods include in-place reconfiguration (IPR), in-place X-filling (IPF), and in-place inversion (IPV), which reconfigure LUT functions only, and can be applied to any FPGA architecture. In addition, for FPGAs with a decomposable LUT architecture (e.g., dual-output LUTs) an in-place decomposition (IPD) method is described for remapping a LUT function into multiple smaller functions leveraging the unused outputs of the LUT, and making use of built-in hard macros in programmable-logic blocks (PLBs) such as carry chain or adder. Methods are applied in-place to mapped circuits before or after routing without affecting placement, routing, and design closure.

The present system comprises a radiation tolerant programmable logic device having logic modules and routing resources coupling together the logic modules. Configuration data lines providing configuration data control the programming of the logic modules and the routing resources. Error correction circuitry coupled to the configuration data lines analyzes and corrects any errors in the configuration data that may occur due to a single event upset (SEU).

The present system also comprises a method for correcting errors in a programmable logic device having configuration data to program the programmable logic device. The method comprises a background reading of the configuration data. Next, the configuration data is analyzed for errors. Finally, the configuration data is then corrected and the configuration data is rewritten if errors are located.

A Programmable Logic Device (PLD) is provided with configuration memory cells displaying a superior soft error immunity by combating single event upsets (SEUs) as the configuration memory cells are regularly refreshed from non-volatile storage depending on the rate SEUs may occur. Circuitry on the PLD uses a programmable timer to set a refresh rate for the configuration memory cells. Because an SEU which erases the state of a small sized memory cell due to collisions with cosmic particles may take some time to cause a functional failure, periodic refreshing will prevent the functional failure. The configuration cells can be DRAM cells which occupy significantly less space than the SRAM cells. Refresh circuitry typically provided for DRAM cells is reduced by using the programming circuitry of the PLD. Data in the configuration cells of the PLD are reloaded from either external or internal soft-error immune non-volatile memory.

The invention provides an anti-single-event-upset error checking and correction method for memory, which comprises: (1) receiving K-bit information data from CPU; (2) generating N-bit check data A corresponding to the K-bit information data; (3) storing the K-bit information data and the N-bit check data A to a memory; (4) reading the K-bit information data from the memory and regenerating a N-bit check data B corresponding to the K-bit information data; (5) performing XOR operation on the check data A and the check data B to obtain a corrector; and (6) locating error in the information data and the check data A by the corrector. If one or two bits of data error occurs, the data error is corrected and correct data is outputted; if two bits or testable more than three bits of data error occurs, the information that non-correctable error occurs is prompted. The method has strong error correction ability, simple operation, and one-bit or two-bit error of memory caused by single event effect is effectively corrected.

Sequential storage circuitry for an integrated circuit is disclosed that comprises storage circuitry comprising: a first storage element for storing, during a first phase of a clock signal, a first indication of an input data value received by said sequential storage circuitry; a second storage element coupled to an output of said first storage element, for storing a second indication of said input data value during a second phase of said clock signal; and error detection circuitry for detecting a single event upset error in any of said first and second storage elements comprising: two additional storage elements for storing third and fourth indications of said input data value respectively in response to a pulse signal derived from said clock signal; comparison circuitry for comparing said third and fourth indications of said input data value; and further comparison circuitry for comparing during a first phase of said clock signal said first indication and at least one of said third and fourth indications, and for comparing during a second phase of said clock signal said second indication and at least one of said third and fourth indications; and output circuitry for correcting any detected errors in said storage circuitry and for outputting an output value; said output circuitry being responsive to no match by said comparison circuitry to output said first indication during a first phase of said clock signal and said second indication during said second phase of said clock signal, and said output circuitry being responsive to a match by said comparison circuitry to output a value in dependence upon comparisons performed by said further comparison circuitry; said output circuitry being responsive to a match by said further comparison circuitry during a first phase of said clock signal to output said first indication during said first clock cycle and to a no match to output an inverted value of said first indication; and said output circuitry being responsive to a match by said further comparison circuitry during a second phase of said clock signal to output said second indication during said second phase of said clock signal and to a no match to output an inverted value of said second indication.

An integrated circuit 2 includes logic circuitry 10 and sequential storage elements 8 . Both the logic circuit 10 and sequential storage elements 8 can be subject to particle strikes giving rise to single event upset errors. These single event upset errors can be detected by detecting a transition in the stored value stored by the sequential storage elements 8 occurring outside of a valid transition period associated with that sequential storage element 8.

The invention provides a multilevel fault tolerance reinforcement satellite information processing system based on an SRAM (Static Random Access Memory) FPGA (Field Programmable Gate Array), and relates to satellite information processing. The invention aims at solving the problems that when the SRAM FPGA is used as a satellite information processing system, the system reliability is influenced by single event upset and latch-up effects and the like, and a satellite practical task is not combined with a protection measure. The system is realized through the following modules including a memory module, a checking and control module, a memory configuration module, a state storage Flash module, an IO/BUS module, an anti-latch power supply module and a main processing module, wherein the memory module is used for data storage and program loading of a main processing module; the checking and control module is used for single event upset effect immunization; the memory configuration module is used for storing initial configuration files and remote updating configuration files; the state storage Flash module is used for realizing the data access state; the IO/BUS module is used for realizing communication and control; the anti-latch power supply module is used for system single event latch-up effect protection and power supplying to each module; and the main processing module is used for data processing and satellite event management. The multilevel fault tolerance reinforcement satellite information processing system based on the SRAM FPGA is applied to the technical field of satellites.

The invention belongs to the technical field of field programmable gate array (FPGA), and particularly relates to a circuit and a method having the function of resisting the single event upset (SEU) effect for an SRAM FPGA device. The SEU-resisting circuit comprises a read-back circuit, a fine-grained refresh circuit and a two-dimensional CRC calibration circuit. A bus state machine controls the read-back circuit to read information stored in a programming point in a read-back register in the read-back circuit, and then, the two-dimensional CRC calibration circuit calibrates the information and writes the address of the programming point generating the SEU effect in an SEU register; and an internal processor generates a fine-grained refreshing bit stream via the fine-grained refresh circuit based on the output of the SEU register, and the refreshing bit stream is written in an internal programming point of the FPGA chip via a self-configuration interface. The programming point generating the SEU error in the FPGA is refreshed again, thereby realizing the SEU-resistant function. Meanwhile, the invention also reduces the time and power consumption for reconstructing the FPGA after the SEU generation.

The invention discloses a single event upset-resistant satellite-borne data processing system. The system comprises a CPU, a FLASH FPGA, an SDRAM, a first NOR FLASH, an SRAM FPGA and a NAND FLASH, wherein data, an address and a control bus of the CPU are connected with the FLASH FPGA and the SDRAM; the FLASH FPGA is connected with the first NOR FLASH, the SRAM FPGA and the NAND FLASH; an EMI module of the CPU has an ECC encoding/decoding function; the FLASH FPGA is used for CPU software guidance, SRAM FPGA configuration and refreshing and NAND FLASH control; all logic of the FLASH FPGA is subjected to triple modular redundancy design; the SDRAM is used for CPU software running, and stored data is subjected to ECC encoding so as to realize "single-error-correcting and double-error-detecting" fault tolerance; and the first NOR FLASH is used for storing a startup program of the CPU, an application of the CPU and a configuration program of the SRAM FPGA. The system has the advantages of high reliability, in-orbit updating, low cost and large storage capacity, and can realize single event upset resistance.

A built in self test (BIST) circuit is provided for a programmable logic device (PLD) constructed from fixed or hard core logic that includes circuitry to write recurring patterns of bits in the configuration memory in a frame by frame manner and read the cell state to enable the validation of every configuration bit at power up. The BIST circuitry can further be used to program the recurring patterns into the configuration memory, and then read frames of the configuration memory to detect the occurrence of single event upsets (SEU) that corrupt data in the configuration memory. The recurring patterns programmed do not require time consuming functional configuration of the PLD, and can be done in a production environment after power up without knowledge of how the PLD will later be configured. No soft logic is needed to form the BIST circuit, enabling 100% test coverage of the programmable configuration memory cells.

Disclosed is an SRAM type FPGA single event upset effect simulation method. The method includes the steps that firstly, design and process parameters of a device to be simulated are acquired; secondly, a three-dimensional geometrical shape of the device is constructed through a modeling tool, and doped areas, doping concentration, discretization strategies and the like of the device are set; thirdly, the design and process parameters of the device are calibrated according to an I-V characteristic curve of the device; fourthly, a meshed device structure is generated, and the mesh is refined on a channel, the light doped area and a PN junction border; fifthly, a device-level TCAD simulation method or a device-level TCAD and circuit-level Spice hybrid simulation method is selected according to the circuit scale and practical conditions of the device; sixthly, characteristics of incident heavy ions are acquired by using a radiating particle characteristic tool to conduct calculation; seventhly, physical model parameters, simulation time, boundary conditions and the like are set, and single event effect simulation of the device is carried out through a TCAD tool; eighthly, particles different in energy are selected to be simulated again according to simulation results; ninthly, the simulation results are acquired through a simulation data analysis tool.

A method and system are provided for accelerated detection of soft error rates (SER) in integrated circuits (IC's) due to transient particle emission. An integrated circuit is packaged for accelerated transient particle emission by doping the underfill thereof with a transient-particle-emitting material having a predetermined emission rate. The emission rate is substantially constant over a predetermined period of time for testing. Accelerated transient-particle-emission testing is performed on the integrated circuit. Single-event upsets due to soft errors are detected, and a quantitative measurement of SER is determined.

Sequential storage circuitry for a integrated circuit is provided, comprising a first storage element, a second storage element and an additional storage element. The first storage element stores, during a first phase of a clock signal, a first indication of an input data value received by the sequential storage circuitry. The second storage element is coupled to an output of the first storage element, and stores a second indication of the input data value during a second phase of the clock signal. The additional storage element is driven by a pulse signal derived from the clock signal, and is arranged on occurrence of that pulse signal to store a third indication of the input data value. Error detection circuitry is then provided for detecting a single event upset error in either the first storage element or the second storage element. In particular, during the first phase of the clock signal, the error detection circuitry detects the single event upset error in the first storage element if there is a difference in the input data value as indicated by the first indication and the third indication. Further, during the second phase of the clock signal, the error detection circuitry detects a single event upset error in the second storage element if there is a difference in the input data value as indicated by the second indication and the third indication. Such an arrangement provides a simple mechanism for detecting soft errors in both the first storage element and the second storage element using only one additional storage element.

Through the research and improvement of error-correcting codes and error-detecting codes, the anti-SEE system and method based on synchronizing redundant threads and coding technique enables this coding technique to quickly detect the SEU (single event upset) occurring in register file and meanwhile design the both-threaded mechanism of the processor into a redundant both-threaded mechanism. When the register file of a thread is found with SEU, the register data with upset error will be corrected through replacing this register file with the register file of the other redundant thread; through the comparison mechanism of synchronous execution results in the layer of redundant both-threaded instructions, the pipelined circuit is judged whether there is SET (single-event transient) error. If such error occurs, it will be quickly eliminated from the pipeline through the designed redundant thread pipeline restart mechanism. This method satisfactorily solves the two frequent and difficult problems: SMU of register file in processor and pipeline SET.

The invention discloses a device for detecting the single event effect of a 1553B interface circuit. The device is connected with a monitoring host through a 1553B bus; in a real 1553B bus communication environment, a tester controls a digital signal processor (DSP) through the monitoring host to transmit various test modes to the tested 1553B interface circuit and execute a multi-scene, multi-vector and multi-round single event effect test; various single event effects such as single event turning, single event latching, single event function interruption and the like of the tested 1553B interface circuit under irradiation of a radiation source can be detected by the DSP; and trial tests under different environmental conditions of high temperature, low temperature, vacuum and the like can be implemented, and reliable and effective test data can be acquired, so the reliability and the credibility of the test data are improved. In the device, a plurality of currents of a protocol logiccircuit, a transceiver and the like in the 1553B circuit can be monitored and controlled by a sampling circuit; and correct and effective feedback control can be provided for data receiving and result analysis.

The invention discloses a method for monitoring a single event upset effect of an FPGA (field programmable gate array) and correcting reloading. The method comprises the steps: an antifuse FPGA reads back a configuration word through a configuration word readback function of an SRAM (static random access memory) type FPGA, compares the configuration word with a correct configuration word pre-stored in an FLASH storage chip, checks whether the SRAM type FPGA generates single event upset or not, and performs reloading through a loading program pre-stored in the FLASH storage chip if the SRAM type FPGA generates the single event upset. The invention also discloses a system for monitoring the single event upset effect of the FPGA and correcting the reloading. The system comprises the FLASH storage chip, the antifuse FPGA and the SRAM type FPGA which are connected in sequence. The method and the system which are disclosed by the invention simulate a time sequence of a PROM (programmable read-only memory) to load the SRAM type FPGA through a loading file pre-stored in the FLASH storage chip; compared with the system adopting a preliminary writing PROM, the system disclosed by the invention has the advantages that the distribution area of a PCB (printed circuit board) is reduced, and equipment minimization is facilitated.

The invention provides an experiment method for a pulsed laser single event upset cross section. The method comprises the steps of scanning and irradiating an inside of a device according to pulsed laser E of a certain value; obtaining a laser single event upset cross section value under the E according to single event upset frequency, irradiation frequency (stationing number of scanning) of the monitored device; and obtaining a Sigma~E curve of the laser single event upset cross section through changing the pulsed laser with different energy for scanning and irradiating. The invention provides technical support for pre-estimating single event upset resistance of a to-be-tested device and enables easier and more practical research on ground pulsed laser simulation of single event effects in the future.