25 results about "Single event upset" patented technology

An SEU-immune trigger includes a master-level data latch that is transparent in response to a first clock signal state and locked in response to a second clock signal state; a slave-level data latch; and a scan slave latch having an input coupled to a scan output of the slave-level data latch, the scan slave latch being transparent in response to the second clock signal state and locked in response to the first clock signal state. The slave-level data latch includes a switching inverter that is disabled when the slave latch is in a transparent state and enabled when the slave latch is in a locked state with a time delay longer than the SEU time period.

The application discloses a fault-tolerant implementation method of a star sensor storage system against single event upsets, and solves the short board of the existing star sensor storage system against single event upsets and the technical problem that the processor internal FLASH capacity is insufficient to implement triple modular redundancy and the like.The method comprises three parts of power-on loading fault-tolerant reading, external SRAM star table dynamic refreshing and internal FLASH data automatic repairing.The ECC error processing is accurate and efficient, and is suitable for the hardware characteristics.The hardware parameters of 32 bytes corresponding to 10 bits of ECC and 32 byte error positioning granularity are adapted, single-bit error is only recorded and not switched to backup, the data accuracy is guaranteed by relying on hardware error correction, double-bit error is temporarily switched to backup reading, the error correction efficiency and data reading fluency are considered, and the real-time operation requirement of the star sensor is met.The application greatly improves the reliability of the star sensor in long-term operation in orbit, and effectively reduces the failure rate in orbit and operation and maintenance cost.

The application provides an anti-single event upset processing method for avionics, which comprises the following steps: step one, defining and initializing a configurable hierarchical check data structure; step two, entering a loop task and obtaining to-be-written data; step three, writing the to-be-written data and a correction detection mode into the data structure; and step four, when the data needs to be read, reading to-be-read data from the data structure in groups. Compared with a traditional triple modular redundancy scheme, the application reduces storage occupation by more than 60%, solves the problem of high cost of directly using Hamming code for real-time correction and detection of memory data in an aviation device, and reduces resource consumption of encoding and decoding while having correction and detection capability, thereby meeting high requirements of the aviation device on real-time performance and resource efficiency.

The application belongs to the technical field of aerospace electronic integrated circuits, and particularly relates to a satellite load FPGA configuration data error correction method and system resisting single event upsets, a double-layer error correction method of "bit-symbol" based on RS decoding operator error correction of a finite field algebra on the basis of a "two out of three" majority voting logic, which can correct single particle independent upsets and multiple copy common mode failures at the same time, and solve the traditional TMR error locking problem. Meanwhile, when configuration data is written into a non-volatile memory, a cross-sector spatial staggered dispersion storage mechanism is introduced, so that the symbols in the same RS code word are separated as much as possible in the physical position, so as to convert the aggregation physical damage into dispersed symbol level errors.

The application provides a single event upset influence quantification index determination method based on program periodic updating, which comprises the following steps: for the instruction Cache in the periodic updating central processing unit (CPU), quantitatively characterizing the influence of single event upset (SEU) on the electronic system as a single event upset (SEU) sensitive area, calculating the error number of the instruction Cache output when the program remains unchanged, constructing a modified physical model of the error number of the instruction Cache output after the program periodic updating step, obtaining the error number of the instruction Cache output after the program periodic updating step, and determining the quantification index of the influence of single event upset (SEU) after the program periodic updating step. The application can realize the quantitative evaluation of the single event upset (SEU) influence alleviating effect of the program periodic updating step, effectively support the quantitative evaluation of the influence of radiation effects on electronic products in the engineering implementation process, effectively support the quantitative evaluation of the reliability of the electronic system, and the quantitative evaluation result is beneficial to the development of airworthiness certification activities.

This application discloses a memory single-event irradiation testing system and method based on multi-dimensional intelligent chart analysis. The system includes a lower-level data acquisition module and a higher-level multi-dimensional intelligent analysis platform. The lower-level data acquisition module writes reference data to the full address of the memory according to the test mode configured by the higher-level computer. During irradiation, it reads the full address data of the memory in real time and compares it with the reference data to capture single-event flip error addresses and error data. The error addresses, error data, real-time irradiation parameters, and test configuration parameters are packaged into raw data and sent to the higher-level computer. The higher-level multi-dimensional intelligent analysis platform is used to configure the test mode, memory operating parameters, and irradiation-related parameters, and generates multi-dimensional intelligent charts based on the raw data. This application provides accurate and reliable data support and visual decision-making basis for memory radiation resistance design optimization, sensitive bit protection strategy formulation, and reliability assessment.

The application discloses a D-type latch based on DICE and resisting multi-node single event upset and clock signal single event upset. Through designing an input circuit composed of one C unit and a delay structure, single event transient pulse of an input signal can be resisted; through composing a latch circuit from four clock-controlled transmission units and a DICE structure, and composing an output circuit from three C units and one inverter, multi-node single event upset can be resisted; through composing a double clock signal circuit from four inverters, the latch can resist clock signal single event upset.

This invention discloses a rapid assessment method for soft error rate caused by single-event effects based on an analytical function library. It addresses the problems of low efficiency and difficulty in supporting large-scale circuit evaluation in traditional TCAD simulation. The method constructs and calibrates device models based on process design kits to obtain accurate electrical characteristics of the calibration device model. Based on multidimensional key irradiation variables, dense TCAD sampling and parametric fitting are performed on the calibration device to construct a response function library. Based on the actual integrated circuit layout, particle transport simulation under radiation conditions is performed in Geant4 to extract the secondary particle set. The corresponding transient current is rapidly synthesized by querying the response function library and interpolating. The current is injected into the SPICE circuit netlist for simulation to determine whether single-event upset has occurred and to calculate the soft error rate. This method achieves an order-of-magnitude improvement in simulation efficiency while maintaining accuracy, making it suitable for rapid radiation resistance assessment and design hardening of complex integrated circuits.

The application discloses a FinFET circuit anti-single event upset layout optimization method based on charge sharing analysis and belongs to the field of integrated circuit radiation effect and anti-radiation reinforcement technology. The method comprises the following steps: calibrating a FinFET device model and determining a single tube sensitive volume through TCAD simulation; analyzing a target circuit to determine a sensitive node and generate an initial layout; constructing a Geant4 circuit model based on the initial layout, locating the sensitive node to determine the circuit sensitive volume distribution; through Monte Carlo simulation, the charge sharing probability two-dimensional distribution graph between the sensitive volumes of adjacent transistors is counted and generated; the layout is iteratively changed to repeat the simulation, and the layout layout which is more conducive to reducing the single event upset risk under the controllable area cost is selected as the optimization scheme. The application realizes the quantitative evaluation of the charge sharing between the sensitive volumes of the FinFET circuit transistor, and provides efficient guidance for the layout-level anti-single event upset reinforcement.

This invention relates to the field of radiation-hardened integrated circuit technology, and particularly to a spaceborne computer system with memory space single-event upset (SOME) detection capability. The system includes: a processor, a bus, a memory, a memory interface controller, an error correction and detection module, and a detection module. The memory contains several memory words, each containing several memory bits and several parity bits. The detection module adjusts the duration of the next detection cycle based on the number of memory words with single-bit errors in the current detection cycle, and performs SOME detection and correction on the memory in each detection cycle via the bus, memory interface controller, and error correction and detection module. The error correction and detection module is connected to the memory through the memory interface controller and is used to detect and correct single-bit errors in each memory word. This solution not only does not consume processor computing resources but also adaptively adjusts the detection cycle duration.

This invention discloses a method, system, and medium for single-event upset (SET) testing of EDAC-hardened memory. The method includes running a single-event test system and initializing the SEU count K; irradiating the EDAC-hardened memory with a high-energy pulsed ion beam at an average flux rate F and starting to count the total irradiation flux Q; determining whether the SEU count of the EDAC-hardened memory's SET test system can be completed within the pulse gap time T2; if it can be completed within the pulse gap time T2, maintaining the same conditions and continuing irradiation until the total irradiation flux Q reaches a preset value; stopping the high-energy pulsed ion beam irradiation and the operation of the SET test system; counting the SEU count K; and calculating the cross-section K / Q of the EDAC-hardened memory. This invention aims to achieve accurate testing of the single-event upset cross-section of EDAC-hardened memory under high-energy pulsed ion beams with drastic flux rate fluctuations, and has the advantages of simple implementation and ease of execution.

The application provides an anti-radiation under-voltage protection circuit, which comprises a bias circuit, a comparison circuit, a threshold voltage adjustment circuit, a hysteresis / output circuit and a voting selector, the bias circuit generates stable bias current for the hysteresis / output circuit to resist the influence of total dose on the hysteresis / output circuit, the comparison circuit generates small under-voltage threshold changing with total dose through a transistor and a resistor to stabilize the transistor conduction voltage in a radiation environment and increase the threshold voltage setting range, the threshold voltage adjustment circuit adjusts the resistance value through an inverter to prevent false flipping, the hysteresis / output circuit generates hysteresis function and performs shaping, improves the anti-radiation property, the three-mode redundancy and the voting selector can effectively improve the single event upset resistance of the circuit; the under-voltage threshold provided by the application changes little with total dose, has certain single event upset resistance, the circuit structure has universality and is suitable for most processes.

This disclosure provides a semiconductor device and a method for manufacturing the same. The device includes: a semiconductor layer; a body region located within the semiconductor layer; a source region and a drain region located within the body region and spaced apart from each other; a gate conductor located above the semiconductor layer and between the source and drain regions; a gate dielectric layer located between the gate conductor and the semiconductor layer; and a field oxide layer surrounding the source and drain regions, at least on the surface of the semiconductor layer. The semiconductor device also includes a doped ring located within the semiconductor layer, with the source and drain regions located within the doped ring, and the field oxide layer surrounding the doped ring. The body region and the doped ring are of a first doping type, and the source and drain regions are of a second doping type, with the first doping type being the opposite of the second doping type. By providing a doped ring with the opposite doping type to the source / drain regions around the source / drain regions, the source / drain regions are isolated from the field oxide layer, thereby solving the technical problems of source / drain punch-through induced by positive charge in the field oxide layer (DIT) and crosstalk between adjacent devices, as well as the large current problem caused by single-event flip-flops (SEE).

The present application relates to the field of integrated circuits, in particular to a single event upset resistant RHS-14T-SRAM circuit and a storage circuit and a chip thereof. The present application reconstructs the original latch structure on the basis of a 6T-SRAM, and then uses the newly added four NMOS to realize polarity reinforcement of the main storage node to enhance the anti-upset capability of the circuit. A set of redundant storage nodes using source isolation reinforcement is provided by using the newly added four PMOS tubes in cooperation with the NMOS tubes, thereby improving the stability of the redundant storage nodes. The new SRAM circuit provided by the present application not only reduces the power consumption of the circuit, but also improves the single event upset resistance of the circuit, and can realize single node upset recovery of all nodes. The problem of performance balance of the traditional circuit is solved, and the present application has a wide application prospect in the field of aerospace.

The application discloses a kind of dynamic three-mode redundancy circuit design methods based on circuit sensitivity, it is related to integrated circuit reliability design technical field, the method is first by the single event upset injection simulation to target circuit, the sensitivity of each circuit module is quantitatively evaluated and classified, distinguish high sensitive module and low sensitive module.Subsequently, high sensitive module is reinforced using static three-mode redundancy structure;For low sensitive module, it is replaced by a kind of dynamic controllable three-mode redundancy structure, the structure includes a main module and two clock-controlled clock circuit controlled controllable redundancy module of clock gating.The start-stop of redundancy module is controlled by constructing the clock gating path based on latch, and the synchronous control signal generated by the path is used to drive output selection circuit, the fast, error-free switching between single-mode energy-saving mode and three-mode redundancy mode is realized.The application ensures high reliability of system, significantly reduces dynamic power consumption and hardware overhead.

This application relates to the field of integrated circuit technology, and in particular to a radiation-resistant method for dynamic adaptive refresh of FPGA based on CPU feedback control. The method includes: analyzing the original configuration bitstream of the FPGA, calculating and storing benchmark verification information, and establishing an access interface; reading the current configuration data of the FPGA configuration memory according to the current refresh strategy through the access interface; verifying the current configuration data based on the benchmark verification information, locating the configuration frame where an error occurs, and calculating the single-event fault rate (SETF); dynamically generating the refresh strategy for the next execution based on the SETF; when an error is detected, extracting the corresponding correct configuration data from the original configuration bitstream, and writing the correct configuration data to the corresponding location in the FPGA configuration memory through the access interface; repeating steps 2 to 5 to achieve adaptive radiation-resistant management; this method can achieve high reliability, low resource overhead, and context-aware radiation resistance.

This application discloses a method, apparatus, medium, and device for simulating single-event upset effects in graphics processing units (GPUs), relating to the field of aerospace computing hardware reliability testing technology. The method includes: measuring the access latency difference between virtual addresses based on a virtual address range; determining, based on the access latency difference, virtual addresses physically located in the same row within the GPU, as well as virtual addresses located in the same memory bank but not in the same row; inputting device parameters and orbital parameters into a preset hammer-iteration number prediction model for prediction, obtaining the corresponding hammer-iteration number for the GPU; performing hammer-iteration tests based on the hammer-iteration number, and the virtual addresses in the same row and those in the same memory bank but not in the same row, obtaining the bit flip rate of the GPU under conditions of protection measures being enabled and disabled; and evaluating the error correction capability level of the protection system based on the bit flip rate. This application is adaptable to the special architecture of GPUs.

The application discloses a high-performance low-power four-point flip self-recovery latch, comprising six transmission gates, 19 Muller units and six clocked Muller units. The application adopts the mode that 19 Muller units and six clocked Muller units form four feedback loops, so that after a single event upset occurs in any one feedback loop, internal nodes can quickly recover to correct logic states through the Muller units and the clocked Muller units, and therefore 7315 four-point flip conditions that may occur in 22 internal nodes can be tolerated. The application uses more clocked Muller units, and therefore the application has a lower power consumption overhead, and is a high-performance low-power four-point flip self-recovery latch.

This invention relates to a time-refreshing method for hardening missile-borne computers against single-event upsets (SWEs), belonging to the field of missile-borne computers. In this invention, a DSP processor (1) and a non-volatile memory (2) are connected via an EMIF bus (3). Software hardened using the SEU method runs in the DSP processor. The non-volatile memory is responsible for backing up the protected data, and the EMIF bus is responsible for supporting data interaction between the DSP processor and the non-volatile memory. This invention does not increase the internal storage space requirements of the DSP; SEU hardening is performed at a certain time period, allowing for time-sharing of DSP computing resources, thus minimizing the impact on normal program execution; the length of data blocks and the cycle of SEU hardening can be flexibly adjusted, achieving a balance between computing resource consumption and SEU hardening effectiveness.

The application relates to an efficient register fault injection method for an embedded processor, which comprises the following steps: analyzing the instruction structure of a processor instruction set, and extracting instructions related to register operation; classifying the instructions related to register operation according to injection timing, constructing a tree graph structure between the instructions and the injection timing, and obtaining a fault injection model of the instruction set related to register operation; obtaining user program instructions, constructing a register fault injection vector suitable for the user program according to the fault injection model; and executing fault injection according to the fault injection vector when the program executes to the instructions. The application realizes accurate injection timing, can more accurately simulate the real situation when the hardware resources are affected by irradiation and flipped, thereby improving the injection efficiency; and can be used in application occasions such as single event upset protection scheme design verification.

The application belongs to the technical field of integrated circuits, and discloses a method for measuring high-energy particle ionization charge particle size, which comprises the following steps: performing irradiation experiments by adopting a mode in which a single high-energy particle is vertically incident on a static random memory circuit provided with multiple pages; in the irradiation experiments, a single event upset threshold of the multiple pages of the static random memory circuit is acquired; and based on the single event upset threshold of the static random memory circuit and a series inter-device spacing of the multiple pages, the high-energy particle ionization charge particle size is determined. The method for measuring high-energy particle ionization charge particle size provided by the application can realize reliable evaluation of the high-energy particle ionization charge particle size.