165 results about "Single event upset" patented technology

The invention relates to the technical field of integrated circuit temperature compensation and high-precision calibration, and discloses a high-density full-temperature trimming method and system based on a fuze chip. The high-density full-temperature trimming method is applied to chip trimming equipment and specifically comprises the following steps that S101, temperature information of a fuze chip is received, the working temperature range of the fuze chip is divided into a plurality of continuous temperature sub-intervals, calibration points are uniformly deployed in each sub-interval, and the temperature information of the fuze chip is acquired; the temperature coordinates of the calibration points are collected in real time through the high-precision temperature sensor and then quantized through the analog-to-digital converter. According to the method, the density of calibration points in subintervals is dynamically adjusted, nonlinear characteristics of a temperature sensitive area are effectively captured, and the local fitting error between adjacent calibration points is reduced to 0.02 DEG C or below in combination with a cubic Hermite interpolation and residual compensation algorithm. In addition, the local fitting error between adjacent calibration points is reduced to 0.02 DEG C or below through application of a redundancy check storage architecture and an interleaving addressing technology. And the single event upset resistance of the calibration parameters is improved.

The invention relates to an FPGA (Field Programmable Gate Array)-based satellite-borne equipment single event upset resisting system and an implementation method. The system comprises an anti-fuse FPGA chip, an SRAM (Static Random Access Memory) FPGA chip and an FPGA chip, the SRAM type FPGA chip is used for completing signal processing; the three FLASH chips are used for solidifying three identical SRAM (Static Random Access Memory) FPGA programs; the anti-fuse FPGA chip reads backup programs from the three FLASH chips respectively at the same time after the equipment is normally powered on, compares the three backup programs, starts to vote when at least two kinds of data are consistent through comparison, brushes the same data into the SRAM type FPGA chip to complete configuration of the FPGA chip, and refreshes the FPGA chip at regular time at the same time. By adopting the method, the single event upset resistance of the FPGA in the space environment can be enhanced, and the method has the advantages of high stability, low cost and the like.

The invention relates to the technical field of chip design, in particular to a test method and system for a chip simulation model. The method comprises the following steps: acquiring chip data, and performing chip circuit logic analysis to obtain circuit logic data; performing signal transmission simulation based on the circuit logic data to obtain signal transmission data; constructing a chip simulation model according to the circuit logic data and the signal transmission data; performing particle bombardment on the chip simulation model to obtain particle data; performing energy spectrum classification based on the particle data to obtain proton data and heavy ion data; performing single event upset fault analysis on the chip simulation model according to the proton data to obtain single event upset data; and performing multi-particle upset fault analysis on the chip simulation model according to the heavy ion data to obtain multi-particle upset fault data. The reliability of the chip in the radiation environment is evaluated and optimized based on the chip design technology, so that the radiation resistance of the chip is improved.

The invention provides an SRAM (Static Random Access Memory) storage unit anti-single particle radiation reinforcement method and system, and relates to the technical field of microelectronics and circuit structure design, a redundant node coupled with a main storage node of an SRAM storage unit is constructed, and the redundant node is used for redundant storage of the logic state of the main storage node; the polarity of a main storage node is reinforced by configuring the main storage node into a circuit structure fully surrounded by a single-type transistor; wherein the redundant node and the main storage node after polarity reinforcement are integrated into a reinforced SRAM (Static Random Access Memory) storage unit. According to the method, circuit-level fusion and collaborative design are carried out on redundancy reinforcement and polarity reinforcement, so that the single event upset resistance of the SRAM unit is improved, and an efficient and enforceable reinforcement design method is provided.

The invention provides a memory error simulation method and device based on a satellite-borne intelligent computing system, a medium and a simulator, and relates to the technical field of satellites. The method comprises the following steps: inputting a deep learning neural network engine into a deep learning reasoning program of a satellite-borne intelligent computing system; executing a deep learning reasoning program to read a process page table; based on the DRAM standard file, the DRAM mapping file and the address mapping relation, determining a memory active area of the deep learning neural network engine in the virtual memory model; performing construction processing on the memory active area, constructing an error injection space represented in a bitmap tree form, and determining an error information injection position in the error injection space according to particle flipping error model information and a Monte Carlo random algorithm; and performing reverse translation processing on the physical address in the virtual memory model, and determining a target virtual address of the deep learning reasoning process. And a single-particle upset memory error and a multi-particle upset memory error caused by space radiation can be effectively simulated.

The invention belongs to the technical field of spaceflight electronic integrated circuits, and particularly relates to a satellite load FPGA configuration data error correction method and system capable of resisting single event upset, in particular to a bit-symbol double-layer error correction method of RS decoding operator error correction based on finite field algebra cascading on the basis of two-out-of-three majority voting logic. Single-particle independent upset and multi-copy common-mode failure can be corrected at the same time, and the problem of traditional TMR error locking is solved. Meanwhile, when configuration data are written into a nonvolatile memory, a cross-sector space staggered and dispersed storage mechanism is introduced, symbols in the same RS code word are separated as far as possible in physical positions, and therefore aggregated physical damage is converted into dispersed symbol-level errors.

The invention provides a single event upset effect-oriented error injection and software fault tolerance system, method and device, relates to the technical field of software reliability processing, and constructs a complete simulation and evaluation framework comprising an error injection module, a processing module and a fault tolerance analysis module. A single event upset error is accurately injected based on a user-defined rule, and the influence of the error on a system operation state is quantified by comparing operation results of a non-error-injection program and an error-injection program. A single event upset error is simulated through instruction-level software error injection, so that the controllability of an error injection process and the repeatability of an experiment are remarkably improved, and dependence on additional hardware equipment is avoided; meanwhile, by establishing a one-time reference operation result, it is avoided that an original program is repeatedly executed in each error injection experiment, the simulation cost is remarkably reduced, and the testing efficiency is improved.

The invention discloses an inter-satellite interconnection routing component radiation hardening method and system, and the method comprises the following steps: obtaining preset radiation hardening configuration parameters in response to a single event upset detection instruction started by a user, the configuration parameters comprising a detection time interval, a detection table item range and a single event upset exception processing strategy; in a system initialization stage, register table entries of a switch chip are backed up through a memory error correction mechanism, a reference table entry backup library is constructed, write operation on the table entries of the switch chip is intercepted during system operation, and the reference table entry backup library is synchronously updated in real time. According to the method, through regular scanning and real-time synchronous backup, efficient detection of single event upset errors is realized, and it is ensured that the system can be found and recovered as soon as possible when upset occurs; a user can set a detection interval, a table item range and a self-defined recovery behavior according to requirements, and extremely high flexibility is provided.

The invention relates to the technical field of software reinforcement, and provides a software reinforcement method for a satellite software system, which comprises the following steps of: identifying the core number of a multi-core CPU (Central Processing Unit) by an application bootstrap program, and starting a plurality of applications to be reinforced according to the core number of the CPU; when a plurality of to-be-reinforced applications are started, determining a master process and one or more slave processes from a plurality of business processes corresponding to the plurality of to-be-reinforced applications by an application bootstrap program, and binding the plurality of to-be-reinforced applications to a plurality of different CPU cores; adding check point functions in the plurality of business processes, wherein input parameters of the check point functions are parameters needing to be compared; and determining whether all the to-be-reinforced applications run normally or not by using the input parameters, and if not, using a corresponding repair method according to the number of the to-be-reinforced applications. Normal operation of the to-be-reinforced application is ensured by adopting corresponding repairing methods according to different conditions, so that the stack data and the global data in the process can be quickly recovered to be normal when single event upset occurs.

The invention discloses a single event upset resistant self-recovery in-memory computing unit design method based on an SRAM (Static Random Access Memory), and relates to a single event upset resistant self-recovery in-memory computing unit design method. The invention aims to solve the problems that the area and the power consumption are usually increased, the stability is difficult to consider and the high-energy-efficiency design of the in-memory computing architecture cannot be met in the existing radiation hardening design. On the premise of guaranteeing high energy efficiency, through circuit structure and layout design and optimization, comprehensive improvement of single event upset resistance, self-recovery capability and stability is achieved, and the design requirement for high stability of a computing architecture in a space memory is met. The invention belongs to the technical field of integrated circuit design.

The application discloses an improved structure anti-single event upset flip-flop circuit and a flip-flop, wherein the flip-flop circuit comprises a logic input circuit, a first main stage gate circuit, a second main stage gate circuit, a third main stage gate circuit, a fourth main stage gate circuit, a first slave stage gate circuit, a second slave stage gate circuit, a third slave stage gate circuit, a fourth slave stage gate circuit, a main stage latch, a slave stage latch and at least one inverter in an electric circuit connection relationship. The application can solve the technical problem that the level of the prior art is flipped and cannot be recovered when a particle is incident on the circuit in a radiation environment.

The present invention discloses a single-particle upset fault injection method and platform, comprising: copying a module to be tested into a fault injection circuit and a non-fault injection circuit, and connecting a state storage unit between the same timing unit in the fault injection circuit and the non-fault injection circuit; controlling the fault injection circuit and the non-fault injection circuit in a circuit structure unit to operate for a specific number of cycles under the same clock, and saving the logic value of the non-fault injection circuit at this time into the state storage unit; injecting a single-particle upset fault into the fault injection circuit in a target circuit structure unit, and judging whether a fault occurs according to the operating state of the target circuit structure unit; if so, repairing the operating state of the target circuit structure unit according to the logic value in the corresponding state storage unit; otherwise, updating the logic value stored in the state storage unit corresponding to the target circuit structure unit, and performing the next fault injection; the present invention can realize continuous and rapid SEU fault injection and repair.

The invention discloses a fault suppression type high-reliability CNN quantitative perception training method and system, and the method comprises the steps: calculating the occurrence probability of an expected single event upset event according to the type and scale of a CNN network layer; according to the expected single event upset event occurrence probability, random fault generation is carried out in the quantitative perception training simulation integer inference process; extracting a model fault propagation path, analyzing a fault propagation influence mechanism, performing a model fault-tolerant capability node test, finding out a sensitive node of which the model precision oscillation exceeds a preset threshold value, and performing targeted fault generation and training on the sensitive node; according to the model structure, layer-by-layer fault iteration training is carried out, convergence results are obtained, the training result of each convergence is used as a pre-training parameter of next simulation fault training until no sensitive node appears, and the quantification process of the CNN is completed. According to the method, the reliability and robustness of the model in a high-radiation environment are remarkably improved.

An SEU-immune trigger includes a master-level data latch that is transparent in response to a first clock signal state and locked in response to a second clock signal state; a slave-level data latch; and a scan slave latch having an input coupled to a scan output of the slave-level data latch, the scan slave latch being transparent in response to the second clock signal state and locked in response to the first clock signal state. The slave-level data latch includes a switching inverter that is disabled when the slave latch is in a transparent state and enabled when the slave latch is in a locked state with a time delay longer than the SEU time period.

The application discloses a fault-tolerant implementation method of a star sensor storage system against single event upsets, and solves the short board of the existing star sensor storage system against single event upsets and the technical problem that the processor internal FLASH capacity is insufficient to implement triple modular redundancy and the like.The method comprises three parts of power-on loading fault-tolerant reading, external SRAM star table dynamic refreshing and internal FLASH data automatic repairing.The ECC error processing is accurate and efficient, and is suitable for the hardware characteristics.The hardware parameters of 32 bytes corresponding to 10 bits of ECC and 32 byte error positioning granularity are adapted, single-bit error is only recorded and not switched to backup, the data accuracy is guaranteed by relying on hardware error correction, double-bit error is temporarily switched to backup reading, the error correction efficiency and data reading fluency are considered, and the real-time operation requirement of the star sensor is met.The application greatly improves the reliability of the star sensor in long-term operation in orbit, and effectively reduces the failure rate in orbit and operation and maintenance cost.

The present application relates to a kind of device equivalent silicon layer thickness and the acquisition method of single event upset LET threshold, belong to space radiation effect simulation experiment technique and anti-radiation hardening technical field, solve the technical problem that device equivalent silicon layer thickness and single event upset LET threshold are difficult to obtain, its acquisition method includes obtaining average proton energy and LET value and range in silicon;Obtain the relationship curve of device single event upset cross section and average proton energy;Extract the energy upper and lower limit corresponding to the single event upset cross section peak of low-energy proton of device;Based on energy lower limit, the equivalent silicon layer thickness of device is calculated;Based on energy upper limit, the proton range, energy and LET value in the sensitive volume of device are calculated;Based on the proton higher than and closest to energy upper limit, the proton range, energy and LET value in the sensitive volume are calculated;The step of obtaining the LET threshold of device single event upset.The method can realize the accurate acquisition of device equivalent silicon layer thickness and single event upset LET threshold.

The disclosure provides a circuit (700) and method for correcting single event upsets, SEUs, or glitches in electronic circuits. The circuit includes rising and falling edge detection sub-circuits (710, 712) connected to a sequential circuit element output (706) which generate signals if the sequential circuit element output changes logic levels, and comparison sub-circuits (716, 724) which compare the signal from the edge detection sub-circuits with a signal generated on an active edge of a clock signal of the sequential circuit element. The comparison sub-circuits detect an SEU or glitch if their two signals do not coincide. First and second gating sub-circuits (720, 728) permit the outputs of the comparison sub-circuits to asynchronously set or reset the sequential circuit element (702).

The invention discloses a single-particle fault automatic detection and processing method and system, a chip and electronic equipment, and relates to the field of chip detection. And before or when the task instruction is sent to the business unit, configuring the temperature threshold value of each heat source and the power supply information of each power supply domain in the business unit. Respectively comparing the acquired real-time temperature and the real-time parameter of each power domain with a temperature threshold and power information, and determining whether a single-particle fault exists or not; if the single-particle fault exists, fault processing is carried out according to a preset processing method; and if the single-particle fault does not exist, a self-checking instruction is sent to the service unit, so that the service unit performs self-checking. According to the method and the device, two main influences of the single event effect, namely single event upset and single event locking, are solved, the reliability of single event fault checking and processing is high, and a related system built by a common device has relatively good space environment adaptability.

The invention relates to the technical field of integrated circuit design, discloses an anti-radiation SRAM (Static Random Access Memory) storage unit and an integrated circuit board, and aims to solve the problems that the SRAM storage unit in the prior art has many sensitive nodes and cannot realize multi-node overturning self-recovery. When any one main storage node is at a low level, due to the characteristics of the NMOS tube, the main storage node cannot become a sensitive node when the node is bombarded by radiation particles. And the other main storage node is matched with the pull-down tube through the logic retainer and is recovered to the original state through the action of the pull-up tube after single event upset. The width-to-length ratios of the pull-down tubes in the two groups of cross-coupled inverters are greater than those of the pull-up tubes, and when a single event upset event occurs in the redundant storage node, the logic of the main storage node corresponding to the redundant storage node can be kept unchanged through the setting that the width-to-length ratios of the pull-down tubes are greater than those of the pull-up tubes, so that the upset self-recovery of multiple nodes is realized.

Embodiments herein describe single event upset (SEU) tolerant flip-flop that includes master latch circuitry, slave latch circuitry, and a tristate driver having an input coupled to an output of the master latch circuitry and an output coupled to a first data input of the slave latch circuitry, where the first tristate driver is configured to inhibit charge transfer from the first data input of the slave latch circuitry to the output of the master latch circuitry.

A single-event upset resistant SRAM cell circuit with fast writing of the present invention includes eight NMOS transistors and six PMOS transistors, sequentially denoted as N1 to N8 and P1 to P6. For storage nodes Q and QB, PMOS transistors P1 and P2 serve as pull-up transistors, NMOS transistors N3 and N4 are controlled and reinforced by redundant nodes S0 and S1, and NMOS transistors N1 and N2 are cross-coupled as pull-down transistors; for redundant nodes S0 and S1, PMOS transistors P3 and P4 are cross-coupled as pull-up transistors, NMOS transistors N5 and N6 serve as pull-down transistors, and are controlled and reinforced by storage nodes Q and QB. Storage nodes Q and QB are connected to two bit lines BL and BLB through NMOS transistors N7 and N8, and the on / off of NMOS transistors N7 and N8 is controlled by word line WL. Storage nodes Q and QB are completely surrounded by NMOS transistors, and this structure is called a polarity reinforcement structure. In the present invention, PMOS transistors P5 and P6 control the on / off of the branches where redundant nodes S0 and S1 are located through storage nodes Q and QB, improving the pull-down ability of the redundant nodes and achieving a faster writing speed.

A single event upset (SEU) hardened flip-flop comprises a master latch and a plurality of slave latches, where an output of the master latch is coupled to a respective input of the slave latches. A Muller element which has an input which is coupled to a respective output of the slave latches and an output which is coupled to a bus keeper. The bus keeper maintains a logic level output in presence of the SEU.

The invention relates to the field of integrated circuits, in particular to an anti-single event upset RHS-14T-SRAM circuit, a storage circuit thereof and a chip. An original latch structure is reconstructed on the basis of a 6T-SRAM (6 T-static random access memory), and polarity reinforcement is performed on a main storage node by utilizing four newly added NMOS (N-channel metal oxide semiconductor), so that the anti-overturning capability of a circuit is enhanced. And a group of redundant storage nodes reinforced by source isolation are provided by matching four newly added PMOS (P-channel Metal Oxide Semiconductor) tubes with NMOS (N-channel Metal Oxide Semiconductor) tubes, so that the stability of the redundant storage nodes is improved. According to the novel SRAM circuit provided by the invention, the power consumption of the circuit is reduced, the single event upset resistance of the circuit is improved, and single node upset recovery of all nodes can be realized; therefore, the problem of performance balance of a traditional circuit is solved, and the circuit has a wide application prospect in the field of aeronautics and astronautics.

The application discloses a kind of support in-orbit program reconfiguration's satellite-borne solid-state memory, belong to electronic information field.Satellite-borne solid-state memory includes control core, data storage array, cache unit, refresh loading circuit, interface unit, program storage unit, control core realizes the control of storage array, parse host computer instruction, bad block management, wear leveling and address management, cache unit effectively prevents single event upset error.Storage array avoids the timing violation of FPGA that can appear under high main frequency and other difficult problems.Load refresh circuit uses refresh loading circuit to refresh FPGA internal program regularly, reduces the influence of single event upset.Interface unit realizes the control management of host computer to satellite-borne solid-state memory.Program storage unit selects storage carrier according to function, storage capacity size, read-write bandwidth requirement.The whole hardware design is with FPGA soft core to realize the control management function of satellite-borne solid-state memory, and special CPU hardware does not have to be designed.

The invention relates to a three-mode trigger layout, a chip and a method for resisting single event upset, and the method comprises the steps: adjusting and designing the layout of a circuit layout of a three-mode redundancy circuit, placing three-mode redundancy trigger units in a staggered manner, isolating the trigger through an internal module, and carrying out the protection ring reinforcement of a voter disposed at the center of the three-mode redundancy trigger units. The external interference is isolated to reduce the probability of voting failure, the multi-bit flipping probability is reduced to ensure the safety of three-copy data by utilizing the modes of overall centralized layout, staggered arrangement of trigger units and protection ring reinforcement of the voter, the interconnection is minimized to reduce the time sequence mismatch problem, and the voting efficiency is improved. Meanwhile, the influence of external interference on the voter is isolated, so that the probability of voting failure is reduced, the bottleneck of traditional layout design is broken through finally, the inherent technical defects of multi-bit flipping, time sequence mismatching and the like induced by particle tracks are solved from the physical level, and a more practical and effective reinforcing scheme is provided for the triple modular redundancy trigger.

The invention discloses a single event upset irradiation test method based on a modularized fifth-generation reduced instruction set soft core. The method is implemented on a ZYNQ chip. The method comprises the following steps: firstly, dividing a fifth-generation reduced instruction set soft core into a plurality of independent circuit modules according to functions, wherein the independent circuit modules comprise a decoder module, a jump processing module, an access control module, an arithmetic logic unit module, a data path module, a static memory module and a write-back circuit module; in the irradiation process, a program burnt by the ZYNQ chip outputs a running result data stream of each module to the upper computer in real time; the upper computer compares the received data with a pre-stored module expected correct value in real time; once data mismatch is found, an error event and a timestamp corresponding to the error event are immediately recorded, and circuit resources occupied by an error event occurrence bit are reversely positioned, so that module-level accurate positioning and vulnerability evaluation of errors caused by single event upset in the soft core are realized. The problem that the error source recognition rate is low when the whole soft core is tested is solved, and the fault resolution and the testing efficiency are remarkably improved.

The invention discloses a rapid analysis method for single event upset of an SRAM (Static Random Access Memory) caused by MeV energy region protons, which comprises the following steps: establishing a target geometric model according to a device structure of the SRAM; constructing a material parameter database; iteratively simulating the transportation process of protons in the target material geometric model and acquiring the total energy deposition of the protons in the sensitive volume based on a material parameter database by adopting a mixed algorithm combining a continuous energy loss model and a discrete scattering model; the total energy deposition of each proton in the sensitive volume is compared with a preset energy deposition threshold value, if the total energy deposition exceeds the threshold value, it is judged that a single event upset event occurs, and the total number of events is counted; and based on the total number of events, the total number of incident protons, the total number of bits of the SRAM and the surface area of the target geometric model, obtaining the single event upset cross section.

When a state machine of the time sequence circuit is influenced by a single event upset (SEU) effect, a state code of the state machine is very easy to change, so that the state machine is in an invalid or error state and cannot be recovered, and the function of the time sequence circuit is failed. Aiming at a state machine based on Hamming distance-3 coding, the invention provides the low-overhead error detection circuit for the Hamming distance-3 five-bit state code, and the resource overhead in the error detection process is greatly reduced by simplifying the judgment logic of a detection unit.

The application discloses an anti-single-event upset reinforced CML latch, a frequency division circuit and equipment, the CML latch of the application comprises a latch circuit composed of NMOS transistors, PMOS transistors for inhibiting the "1 to 0" jump of single-event upset are connected to both input sides of the latch circuit, the signal connected to the gate of one PMOS transistor is a frequency division clock signal clk180-o obtained by current mode to CMOS conversion of the 180-degree phase frequency division clock signal clk180 output by the latch circuit, and the signal connected to the gate of the other PMOS transistor is a frequency division clock signal clk0-o obtained by current mode to CMOS conversion of the 0-degree phase frequency division clock signal clk0 output by the latch circuit. The application aims at achieving anti-single-event upset reinforcement for the CML latch with low overhead, and improving the anti-radiation reinforcement performance of the CML latch.

The invention relates to the technical field of network security, and particularly discloses an Internet of Things equipment edge security access authentication method based on a domestic SoC (System on Chip), which reconstructs a root key in real time by using an SRAM (Static Random Access Memory) physical fingerprint when a chip is powered on, thoroughly abandons static storage of a private key, and completely eradicates a physical cloning risk from the source. On the basis, according to the scheme, a root key and gateway challenge are deeply bound through an SM3 algorithm, and key derivation is carried out by adopting an avalanche linkage mechanism based on cross feedback. The mechanism forcibly determines the one-way dependence of the verification tag on the integrity of the session key, so that any key error caused by hardware faults such as single event upset inevitably causes tag verification failure, thereby effectively blocking the establishment of an invalid secure channel under zero extra hardware cost, and improving the security of the security channel. Therefore, the safe access of the edge device with the self-immunity capability is realized.