183 results about "Single event upset" patented technology

The invention relates to the technical field of integrated circuit temperature compensation and high-precision calibration, and discloses a high-density full-temperature trimming method and system based on a fuze chip. The high-density full-temperature trimming method is applied to chip trimming equipment and specifically comprises the following steps that S101, temperature information of a fuze chip is received, the working temperature range of the fuze chip is divided into a plurality of continuous temperature sub-intervals, calibration points are uniformly deployed in each sub-interval, and the temperature information of the fuze chip is acquired; the temperature coordinates of the calibration points are collected in real time through the high-precision temperature sensor and then quantized through the analog-to-digital converter. According to the method, the density of calibration points in subintervals is dynamically adjusted, nonlinear characteristics of a temperature sensitive area are effectively captured, and the local fitting error between adjacent calibration points is reduced to 0.02 DEG C or below in combination with a cubic Hermite interpolation and residual compensation algorithm. In addition, the local fitting error between adjacent calibration points is reduced to 0.02 DEG C or below through application of a redundancy check storage architecture and an interleaving addressing technology. And the single event upset resistance of the calibration parameters is improved.

The invention relates to an FPGA (Field Programmable Gate Array)-based satellite-borne equipment single event upset resisting system and an implementation method. The system comprises an anti-fuse FPGA chip, an SRAM (Static Random Access Memory) FPGA chip and an FPGA chip, the SRAM type FPGA chip is used for completing signal processing; the three FLASH chips are used for solidifying three identical SRAM (Static Random Access Memory) FPGA programs; the anti-fuse FPGA chip reads backup programs from the three FLASH chips respectively at the same time after the equipment is normally powered on, compares the three backup programs, starts to vote when at least two kinds of data are consistent through comparison, brushes the same data into the SRAM type FPGA chip to complete configuration of the FPGA chip, and refreshes the FPGA chip at regular time at the same time. By adopting the method, the single event upset resistance of the FPGA in the space environment can be enhanced, and the method has the advantages of high stability, low cost and the like.

The invention discloses a single event upset reinforced magnetic random access memory reading circuit, and belongs to the field of nonvolatile memories. Interlocked transistors are added on the basis of a traditional 6T reading circuit, meanwhile, a PMOS tube and an NMOS tube are introduced, and errors caused by the single event upset effect can be effectively corrected. The method has the following advantages that single event effect sensitive nodes are considered, zero upset nodes do not exist in the reinforcement method, meanwhile, 1 upset can be rapidly corrected, the single event upset resistance is higher, and the method can be used for reliable storage of data in the space radiation environment.

The invention discloses a system and a method for testing and analyzing the single event effect of a high-capacity nonvolatile memory. The system comprises an upper computer module, an FPGA (Field Programmable Gate Array) control module and a programmable power supply module. The system is used for testing and analyzing various single event effects of a high-capacity nonvolatile memory chip in a dynamic working mode. And according to the error data read from the memory in the dynamic working mode, presetting error bitmap rules of various single-particle function interruptions in an FPGA test program, carrying out real-time analysis and identification on the various single-particle function interruptions, and discriminating single-particle upset of the memory unit. According to the system, testing and real-time analysis of various complex single event effects of the high-capacity nonvolatile memory can be achieved, then radiation hardening and evaluation can be conducted on the sensitive position of a memory chip, and high pertinence is achieved.

The invention relates to an anti-single event transient and anti-single event upset setting latch, which is characterized in that a setting signal end circuit is re-reinforced and designed, and a setting signal access terminal structure of the setting signal end circuit, which is accessed to a setting latch main body circuit, is correspondingly improved; by means of delay and judgment processing provided by a delay chain A, a delay chain B, an XNOR gate and a three-state phase inverter of a setting signal end circuit, it is ensured that a setting signal can be normally transmitted to a setting redundant circuit formed by a first phase inverter and a second phase inverter when no external transient pulse is input to a setting signal end; two paths of setting signals generated by the setting redundant circuit are respectively accessed to the setting latch main body circuit; when external transient pulse input exists at the setting signal end, the setting signal which is influenced by the transient state and causes an error cannot generate effective output through the three-state inverter, so that the error is filtered out, and the purpose of effectively realizing reinforcing design aiming at the external input transient state of the setting signal end is achieved.

The invention relates to the technical field of chip design, in particular to a test method and system for a chip simulation model. The method comprises the following steps: acquiring chip data, and performing chip circuit logic analysis to obtain circuit logic data; performing signal transmission simulation based on the circuit logic data to obtain signal transmission data; constructing a chip simulation model according to the circuit logic data and the signal transmission data; performing particle bombardment on the chip simulation model to obtain particle data; performing energy spectrum classification based on the particle data to obtain proton data and heavy ion data; performing single event upset fault analysis on the chip simulation model according to the proton data to obtain single event upset data; and performing multi-particle upset fault analysis on the chip simulation model according to the heavy ion data to obtain multi-particle upset fault data. The reliability of the chip in the radiation environment is evaluated and optimized based on the chip design technology, so that the radiation resistance of the chip is improved.

The invention provides an SRAM (Static Random Access Memory) storage unit anti-single particle radiation reinforcement method and system, and relates to the technical field of microelectronics and circuit structure design, a redundant node coupled with a main storage node of an SRAM storage unit is constructed, and the redundant node is used for redundant storage of the logic state of the main storage node; the polarity of a main storage node is reinforced by configuring the main storage node into a circuit structure fully surrounded by a single-type transistor; wherein the redundant node and the main storage node after polarity reinforcement are integrated into a reinforced SRAM (Static Random Access Memory) storage unit. According to the method, circuit-level fusion and collaborative design are carried out on redundancy reinforcement and polarity reinforcement, so that the single event upset resistance of the SRAM unit is improved, and an efficient and enforceable reinforcement design method is provided.

The invention provides a memory error simulation method and device based on a satellite-borne intelligent computing system, a medium and a simulator, and relates to the technical field of satellites. The method comprises the following steps: inputting a deep learning neural network engine into a deep learning reasoning program of a satellite-borne intelligent computing system; executing a deep learning reasoning program to read a process page table; based on the DRAM standard file, the DRAM mapping file and the address mapping relation, determining a memory active area of the deep learning neural network engine in the virtual memory model; performing construction processing on the memory active area, constructing an error injection space represented in a bitmap tree form, and determining an error information injection position in the error injection space according to particle flipping error model information and a Monte Carlo random algorithm; and performing reverse translation processing on the physical address in the virtual memory model, and determining a target virtual address of the deep learning reasoning process. And a single-particle upset memory error and a multi-particle upset memory error caused by space radiation can be effectively simulated.

The invention belongs to the technical field of spaceflight electronic integrated circuits, and particularly relates to a satellite load FPGA configuration data error correction method and system capable of resisting single event upset, in particular to a bit-symbol double-layer error correction method of RS decoding operator error correction based on finite field algebra cascading on the basis of two-out-of-three majority voting logic. Single-particle independent upset and multi-copy common-mode failure can be corrected at the same time, and the problem of traditional TMR error locking is solved. Meanwhile, when configuration data are written into a nonvolatile memory, a cross-sector space staggered and dispersed storage mechanism is introduced, symbols in the same RS code word are separated as far as possible in physical positions, and therefore aggregated physical damage is converted into dispersed symbol-level errors.

The invention discloses an anti-radiation system based on dynamic memory refreshing, which comprises an FPGA (Field Programmable Gate Array), a Flash storage module and a CRC (Cyclic Redundancy Check) module, the FPGA is provided with an internal storage pool and a lookup table updating unit, and the lookup table updating unit periodically reads lookup table data which is stored in the Flash and dynamically updated and stores the lookup table data in the internal storage pool; and replacing expired data or data damaged by single event upset. According to the anti-radiation system based on dynamic memory refreshing, a dynamic memory refreshing mechanism is added on the basis of a plug-in refreshing chip and triple modular redundancy, and an FPGA can dynamically refresh an internal memory pool by reading lookup table data in a plug-in FLASH memory. According to the key technical scheme, a single event upset event in an internal memory pool of the FPGA is rapidly and efficiently processed by combining lookup table cyclic refreshing and CRC verification, the anti-irradiation capacity of a system is improved, and stable operation of the system in an extreme environment is ensured.

The invention provides a single event upset effect-oriented error injection and software fault tolerance system, method and device, relates to the technical field of software reliability processing, and constructs a complete simulation and evaluation framework comprising an error injection module, a processing module and a fault tolerance analysis module. A single event upset error is accurately injected based on a user-defined rule, and the influence of the error on a system operation state is quantified by comparing operation results of a non-error-injection program and an error-injection program. A single event upset error is simulated through instruction-level software error injection, so that the controllability of an error injection process and the repeatability of an experiment are remarkably improved, and dependence on additional hardware equipment is avoided; meanwhile, by establishing a one-time reference operation result, it is avoided that an original program is repeatedly executed in each error injection experiment, the simulation cost is remarkably reduced, and the testing efficiency is improved.

The invention discloses an inter-satellite interconnection routing component radiation hardening method and system, and the method comprises the following steps: obtaining preset radiation hardening configuration parameters in response to a single event upset detection instruction started by a user, the configuration parameters comprising a detection time interval, a detection table item range and a single event upset exception processing strategy; in a system initialization stage, register table entries of a switch chip are backed up through a memory error correction mechanism, a reference table entry backup library is constructed, write operation on the table entries of the switch chip is intercepted during system operation, and the reference table entry backup library is synchronously updated in real time. According to the method, through regular scanning and real-time synchronous backup, efficient detection of single event upset errors is realized, and it is ensured that the system can be found and recovered as soon as possible when upset occurs; a user can set a detection interval, a table item range and a self-defined recovery behavior according to requirements, and extremely high flexibility is provided.

The invention discloses a high-reliability starting method applied to aerospace embedded equipment. The high-reliability starting method comprises the following steps: storing a Linux component and a backup in a FLASH in advance; a correct operating system component is selected in a two-out-of-three mode to be started to ramfs; checking the NAND FLASH and rootfs and application data stored in the NAND FLASH in the ramfs, switching to the rootfs if the checking is successful, and otherwise, entering a repair mode; patrolling the components regularly in an operating system, and replacing error files in a repair mode; compared with other methods, the method has the advantages that the file is verified in the starting process and after starting is completed, the file damage risk caused by single event upset can be avoided, and reliable starting of the Linux operating system is guaranteed.

The invention relates to an anti-single event transient and anti-single event upset reset latch, which can normally provide a reset signal required by a latch circuit when the reset signal end has no external transient pulse input by improving and designing the circuit structure of the reset signal end and introducing reset signal redundancy design into the latch circuit. When an external transient pulse is input at a reset signal end, the influence of the transient state on a subsequent reset signal is eliminated through the delay judgment redundant circuit, so that the influence of the transient state from the reset signal end on the storage state of the reset register is eliminated, and the reset precision of the reset register is improved. The external input transient of the reset signal end is effectively reinforced, and finally the single event transient and single event upset resistance of the reset latch is further improved.

The invention relates to the technical field of software reinforcement, and provides a software reinforcement method for a satellite software system, which comprises the following steps of: identifying the core number of a multi-core CPU (Central Processing Unit) by an application bootstrap program, and starting a plurality of applications to be reinforced according to the core number of the CPU; when a plurality of to-be-reinforced applications are started, determining a master process and one or more slave processes from a plurality of business processes corresponding to the plurality of to-be-reinforced applications by an application bootstrap program, and binding the plurality of to-be-reinforced applications to a plurality of different CPU cores; adding check point functions in the plurality of business processes, wherein input parameters of the check point functions are parameters needing to be compared; and determining whether all the to-be-reinforced applications run normally or not by using the input parameters, and if not, using a corresponding repair method according to the number of the to-be-reinforced applications. Normal operation of the to-be-reinforced application is ensured by adopting corresponding repairing methods according to different conditions, so that the stack data and the global data in the process can be quickly recovered to be normal when single event upset occurs.

Embodiments herein describe a circuit for detecting a single event upset (SEU). The circuit includes a latch including an output node, a first parity node, and a second parity node and correction circuitry configured to correct a single event upset (SEU) at the output node using the first and second parity nodes.

The invention discloses a single event upset resistant self-recovery in-memory computing unit design method based on an SRAM (Static Random Access Memory), and relates to a single event upset resistant self-recovery in-memory computing unit design method. The invention aims to solve the problems that the area and the power consumption are usually increased, the stability is difficult to consider and the high-energy-efficiency design of the in-memory computing architecture cannot be met in the existing radiation hardening design. On the premise of guaranteeing high energy efficiency, through circuit structure and layout design and optimization, comprehensive improvement of single event upset resistance, self-recovery capability and stability is achieved, and the design requirement for high stability of a computing architecture in a space memory is met. The invention belongs to the technical field of integrated circuit design.

The application discloses an improved structure anti-single event upset flip-flop circuit and a flip-flop, wherein the flip-flop circuit comprises a logic input circuit, a first main stage gate circuit, a second main stage gate circuit, a third main stage gate circuit, a fourth main stage gate circuit, a first slave stage gate circuit, a second slave stage gate circuit, a third slave stage gate circuit, a fourth slave stage gate circuit, a main stage latch, a slave stage latch and at least one inverter in an electric circuit connection relationship. The application can solve the technical problem that the level of the prior art is flipped and cannot be recovered when a particle is incident on the circuit in a radiation environment.

The present invention discloses a single-particle upset fault injection method and platform, comprising: copying a module to be tested into a fault injection circuit and a non-fault injection circuit, and connecting a state storage unit between the same timing unit in the fault injection circuit and the non-fault injection circuit; controlling the fault injection circuit and the non-fault injection circuit in a circuit structure unit to operate for a specific number of cycles under the same clock, and saving the logic value of the non-fault injection circuit at this time into the state storage unit; injecting a single-particle upset fault into the fault injection circuit in a target circuit structure unit, and judging whether a fault occurs according to the operating state of the target circuit structure unit; if so, repairing the operating state of the target circuit structure unit according to the logic value in the corresponding state storage unit; otherwise, updating the logic value stored in the state storage unit corresponding to the target circuit structure unit, and performing the next fault injection; the present invention can realize continuous and rapid SEU fault injection and repair.

The invention discloses a fault suppression type high-reliability CNN quantitative perception training method and system, and the method comprises the steps: calculating the occurrence probability of an expected single event upset event according to the type and scale of a CNN network layer; according to the expected single event upset event occurrence probability, random fault generation is carried out in the quantitative perception training simulation integer inference process; extracting a model fault propagation path, analyzing a fault propagation influence mechanism, performing a model fault-tolerant capability node test, finding out a sensitive node of which the model precision oscillation exceeds a preset threshold value, and performing targeted fault generation and training on the sensitive node; according to the model structure, layer-by-layer fault iteration training is carried out, convergence results are obtained, the training result of each convergence is used as a pre-training parameter of next simulation fault training until no sensitive node appears, and the quantification process of the CNN is completed. According to the method, the reliability and robustness of the model in a high-radiation environment are remarkably improved.

An SEU-immune trigger includes a master-level data latch that is transparent in response to a first clock signal state and locked in response to a second clock signal state; a slave-level data latch; and a scan slave latch having an input coupled to a scan output of the slave-level data latch, the scan slave latch being transparent in response to the second clock signal state and locked in response to the first clock signal state. The slave-level data latch includes a switching inverter that is disabled when the slave latch is in a transparent state and enabled when the slave latch is in a locked state with a time delay longer than the SEU time period.

The application discloses a fault-tolerant implementation method of a star sensor storage system against single event upsets, and solves the short board of the existing star sensor storage system against single event upsets and the technical problem that the processor internal FLASH capacity is insufficient to implement triple modular redundancy and the like.The method comprises three parts of power-on loading fault-tolerant reading, external SRAM star table dynamic refreshing and internal FLASH data automatic repairing.The ECC error processing is accurate and efficient, and is suitable for the hardware characteristics.The hardware parameters of 32 bytes corresponding to 10 bits of ECC and 32 byte error positioning granularity are adapted, single-bit error is only recorded and not switched to backup, the data accuracy is guaranteed by relying on hardware error correction, double-bit error is temporarily switched to backup reading, the error correction efficiency and data reading fluency are considered, and the real-time operation requirement of the star sensor is met.The application greatly improves the reliability of the star sensor in long-term operation in orbit, and effectively reduces the failure rate in orbit and operation and maintenance cost.

The present application relates to a kind of device equivalent silicon layer thickness and the acquisition method of single event upset LET threshold, belong to space radiation effect simulation experiment technique and anti-radiation hardening technical field, solve the technical problem that device equivalent silicon layer thickness and single event upset LET threshold are difficult to obtain, its acquisition method includes obtaining average proton energy and LET value and range in silicon;Obtain the relationship curve of device single event upset cross section and average proton energy;Extract the energy upper and lower limit corresponding to the single event upset cross section peak of low-energy proton of device;Based on energy lower limit, the equivalent silicon layer thickness of device is calculated;Based on energy upper limit, the proton range, energy and LET value in the sensitive volume of device are calculated;Based on the proton higher than and closest to energy upper limit, the proton range, energy and LET value in the sensitive volume are calculated;The step of obtaining the LET threshold of device single event upset.The method can realize the accurate acquisition of device equivalent silicon layer thickness and single event upset LET threshold.

The disclosure provides a circuit (700) and method for correcting single event upsets, SEUs, or glitches in electronic circuits. The circuit includes rising and falling edge detection sub-circuits (710, 712) connected to a sequential circuit element output (706) which generate signals if the sequential circuit element output changes logic levels, and comparison sub-circuits (716, 724) which compare the signal from the edge detection sub-circuits with a signal generated on an active edge of a clock signal of the sequential circuit element. The comparison sub-circuits detect an SEU or glitch if their two signals do not coincide. First and second gating sub-circuits (720, 728) permit the outputs of the comparison sub-circuits to asynchronously set or reset the sequential circuit element (702).

The invention discloses a single-particle fault automatic detection and processing method and system, a chip and electronic equipment, and relates to the field of chip detection. And before or when the task instruction is sent to the business unit, configuring the temperature threshold value of each heat source and the power supply information of each power supply domain in the business unit. Respectively comparing the acquired real-time temperature and the real-time parameter of each power domain with a temperature threshold and power information, and determining whether a single-particle fault exists or not; if the single-particle fault exists, fault processing is carried out according to a preset processing method; and if the single-particle fault does not exist, a self-checking instruction is sent to the service unit, so that the service unit performs self-checking. According to the method and the device, two main influences of the single event effect, namely single event upset and single event locking, are solved, the reliability of single event fault checking and processing is high, and a related system built by a common device has relatively good space environment adaptability.

The invention relates to the technical field of integrated circuit design, discloses an anti-radiation SRAM (Static Random Access Memory) storage unit and an integrated circuit board, and aims to solve the problems that the SRAM storage unit in the prior art has many sensitive nodes and cannot realize multi-node overturning self-recovery. When any one main storage node is at a low level, due to the characteristics of the NMOS tube, the main storage node cannot become a sensitive node when the node is bombarded by radiation particles. And the other main storage node is matched with the pull-down tube through the logic retainer and is recovered to the original state through the action of the pull-up tube after single event upset. The width-to-length ratios of the pull-down tubes in the two groups of cross-coupled inverters are greater than those of the pull-up tubes, and when a single event upset event occurs in the redundant storage node, the logic of the main storage node corresponding to the redundant storage node can be kept unchanged through the setting that the width-to-length ratios of the pull-down tubes are greater than those of the pull-up tubes, so that the upset self-recovery of multiple nodes is realized.

The present invention discloses a 14T radiation-hardened SRAM memory circuit based on polarity strengthening technology, which includes six NMOS transistors and eight PMOS transistors. The six NMOS transistors are sequentially denoted as N1 to N6, and the eight PMOS transistors are sequentially denoted as P1 to P8. The PMOS transistors P3 and P4 are cross-coupled, and the PMOS transistors P1 and P2 serve as pull-up transistors, while the NMOS transistors N1, N2, N3, N4 and the PMOS transistors P5 and P6 serve as pull-down transistors. Two main storage nodes Q and QN are respectively connected to the bit lines BL and BLB through the NMOS transistors N5 and N6, and two redundant storage nodes S0 and S1 are respectively connected to the bit lines BL and BLB through the PMOS transistors P7 and P8. This circuit can improve the write speed of the storage cell, reduce the cell power consumption, and enhance the single-event upset (SEU) resistance ability of the cell.

Embodiments herein describe single event upset (SEU) tolerant flip-flop that includes master latch circuitry, slave latch circuitry, and a tristate driver having an input coupled to an output of the master latch circuitry and an output coupled to a first data input of the slave latch circuitry, where the first tristate driver is configured to inhibit charge transfer from the first data input of the slave latch circuitry to the output of the master latch circuitry.

A single-event upset resistant SRAM cell circuit with fast writing of the present invention includes eight NMOS transistors and six PMOS transistors, sequentially denoted as N1 to N8 and P1 to P6. For storage nodes Q and QB, PMOS transistors P1 and P2 serve as pull-up transistors, NMOS transistors N3 and N4 are controlled and reinforced by redundant nodes S0 and S1, and NMOS transistors N1 and N2 are cross-coupled as pull-down transistors; for redundant nodes S0 and S1, PMOS transistors P3 and P4 are cross-coupled as pull-up transistors, NMOS transistors N5 and N6 serve as pull-down transistors, and are controlled and reinforced by storage nodes Q and QB. Storage nodes Q and QB are connected to two bit lines BL and BLB through NMOS transistors N7 and N8, and the on / off of NMOS transistors N7 and N8 is controlled by word line WL. Storage nodes Q and QB are completely surrounded by NMOS transistors, and this structure is called a polarity reinforcement structure. In the present invention, PMOS transistors P5 and P6 control the on / off of the branches where redundant nodes S0 and S1 are located through storage nodes Q and QB, improving the pull-down ability of the redundant nodes and achieving a faster writing speed.

A single event upset (SEU) hardened flip-flop comprises a master latch and a plurality of slave latches, where an output of the master latch is coupled to a respective input of the slave latches. A Muller element which has an input which is coupled to a respective output of the slave latches and an output which is coupled to a bus keeper. The bus keeper maintains a logic level output in presence of the SEU.