2179 results about "Flip-flop" patented technology

The invention relates to the technical field of control and regulation systems, in particular to a photovoltaic module anomaly recognition method based on laser detection, which comprises the following steps: generating a clock signal synchronous with a laser scanning time sequence through a hardware synchronous trigger, and driving a temperature and humidity sensor, a salt mist sensor and an illumination intensity sensor to collect environmental parameters; and constructing a multi-source data set containing the salt crystallization trend and the environmental interference level. And based on a temperature and humidity segmented compensation reflectivity base line, a salt mist mode switching optimization dust retention judgment threshold value, and illumination correlation sensitivity adjustment hot spot detection parameters, dynamic model correction is realized. And a fault database is matched to trigger a grading alarm mechanism, and a decision tree classifier is combined to verify time continuity to generate a diagnosis report. A dynamic detection path is constructed through spiral path planning, a multi-machine contract network protocol and wind disturbance trajectory correction, data feedback is executed to form closed-loop control logic, and the problems of misjudgment and missing detection in high salt mist, temperature change and illumination fluctuation environments are effectively solved.

A system for improving employee engagement and automating the integration of business processes. The system includes: a user interaction module configured to receive multimodal inputs, including natural language text and voice requests from employees via enterprise portals, mobile applications, voice-activated devices, and collaboration platforms, and to generate real-time responses via conversational output channels; a context processor that is operationally coupled with the user interaction module, wherein the context processor stores the interaction history, employee preferences, organizational role metadata, and task results in both short-term and long-term memory and dynamically derives context for controlling responses and initiating workflows; A natural language and intent processor that is communicatively linked to the context processor. The intent engine consists of large language models trained on company-specific lexicons to perform intent detection, entity extraction, ambiguity resolution, and sentiment or urgency classification from employee queries; a workflow orchestration layer in communication with the intent engine and the context processor, wherein the workflow orchestration layer includes a rule-based and AI-powered process execution engine configured to automatically initiate, route, and complete cross-functional business tasks, including approvals, escalations, and compliance checks, with workflows defined using modular templates that include conditional logic and time-based triggers; Webhooks and authentication protocols provide secure interoperability between the workflow orchestration layer and external enterprise platforms; a feedback and learning module that is operationally coupled with the workflow orchestration layer and the natural language understanding engine, wherein the feedback and learning module is configured to analyze task completion rates, response accuracy, latency metrics, and user feedback signals, and to retrain underlying language and workflow models for adaptive improvement in real time; and an administration console with role-based access controls, compliance dashboards, audit trails and interfaces for workflow configuration, whereby the administration console enables authorized personnel to monitor system operations, adjust interaction rules and enforce data protection restrictions across departments.

The invention discloses a UE4-based digital twin model construction system and method, and relates to the technical field of computer vision, and the system comprises a geometric modeling unit which generates three-dimensional model data based on geometric modeling data of a target physical entity, and achieves dynamic LOD rendering level switching through virtualization processing; the real-time data interaction unit is used for analyzing the real-time sensor data flow and generating equipment state data in combination with a transmission operation and maintenance instruction; the simulation engine unit is used for executing rigid body motion and collision simulation based on the equipment state data and outputting a collision event sequence and state transition data by utilizing an event trigger; the machine learning unit is used for training an LSTM (Long Short Term Memory) model based on the collision event sequence and the state transition data, and optimizing state covariance parameters through adaptive Kalman filtering; and the visual interaction unit is used for realizing data synchronization of the command large screen and the mobile terminal through multi-screen collaboration. According to the method, the digital model capable of accurately reflecting physical entity behaviors and characteristics is constructed.

The invention provides a self-adaptive constraint model active mismatch prediction control method based on voltage and current ripple resistance of a power converter in a hybrid energy storage system, and the method comprises the steps: building an island DC micro-grid system model, collecting the voltage and current information of a system, and designing a model prediction control frame of a power loop and a cost function of the model prediction control frame; designing a model predictive control framework of the current loop and a cost function of the model predictive control framework; designing an active model mismatch mechanism to enhance the response capability to dynamic change; determining an optimization problem with a normal value, and designing an adaptive constraint optimization algorithm to dynamically adjust constraint parameters and optimize control performance; and designing a steady-state and dynamic-mode trigger for adapting to the running state of the system. According to the invention, the trajectory tracking precision of the system under dynamic and steady-state working conditions can be significantly improved, current ripples caused by control delay can be effectively eliminated, damage to electrical equipment due to overlarge ripples can be avoided, and the service life of the equipment can be prolonged.

The invention discloses a fault analysis method and device for a switch chip, and relates to the field of computers, and the method comprises the steps: monitoring an error event, and instantly generating an error log containing an error code and a port number when a target link is abnormal; then, through accurate fault mapping, based on an error code mapping table pre-stored in a nonvolatile medium, dynamically converting an original error code into a readable fault description, and in combination with a data packet associated physical position captured by a trigger, realizing fault tracing; through structured storage management, the fault description and the original log are stored in a partitioned mode according to port numbers, and a traceable historical database is formed; and finally, real-time alarm and deep diagnosis are triggered through system collaborative optimization. Therefore, the technical effects of operation and maintenance efficiency rising, fault tracing enhancement and system reliability enhancement are realized, and the technical problem of low fault analysis efficiency of the switch chip in the related technology can be solved.

The invention belongs to the technical field of inspection equipment control systems, and discloses an inspection equipment control system, method and device, and the system comprises a difficulty recognition module, a path density adjustment module, a state monitoring module, a boundary compensation module and a control linkage module. According to the method, a trend included angle is obtained through numerical value change analysis of a track section structure, an angle matching ratio is introduced to realize dynamic adjustment of a path section interval, a three-period sequence is constructed in cooperation with gyroscope data to extract main direction change, disturbance rhythm change is accurately captured, disturbance amplitude is extracted through a minimum interval distance trend, and the disturbance accuracy is improved. A time axis turning position is reconstructed by combining data of a path trigger, a boundary offset reference is positioned, linkage control of the distance between path points and an average path is realized, a processing logic establishes a multi-dimensional linkage relation of path adjustment, disturbance identification and boundary compensation, and path response flexibility and equipment operation stability under environment change are enhanced. And the inspection precision and adaptability in a high-disturbance scene are improved.

The invention relates to the technical field of grain sorting and cleaning, in particular to a multi-modal sensor fusion-based grain quality dynamic grading and stone removal cooperative control method, which comprises the following steps of: 1, synchronously collecting by a multi-modal sensor, and generating a synchronous pulse through a high-speed photoelectric trigger when grains fall, a linear array camera is triggered to collect grain surface morphology sequence images, a near-infrared spectrometer collects an absorbance curve and moisture content data, and a piezoelectric weighing platform collects impact pressure waveforms; step 2, dynamic grading decision making; step 3, generation of collaborative parameters; 4, executing and feedback optimization, and issuing the generated parameters to a vibrating screen, a fan and an inclination angle adjusting mechanism to execute control; and detecting the proportion of residual impurities at a stone removal outlet, and triggering the cascade decision-making model to retrain when the proportion exceeds the limit continuously. Through the design, the grain grading and stone removing efficiency and accuracy are remarkably improved, and high-quality product experience and value-added benefits are provided for users.

In an embodiment, a method comprises: generating a user interface configured to allow selecting a product from a plurality of products that are customizable and displaying the user interface on a display device of a user computer; receiving, via the user interface, a selection of a particular product, from the plurality of products, that require customization; in response to receiving the selection of the particular product, automatically generating a plurality of customization options available for customizing the particular product; receiving one or more triggers of a plurality of triggers, generated based on customization options selected from the plurality of customization options; automatically generating one or more corresponding customization attribute values for the particular product; automatically generating one or more digital representations of the particular product, and displaying the digital representations of the particular product on the display device of the user computer.

The invention discloses an asynchronous micro-pipeline structure based on a'sending-relaying-receiving 'structure, which comprises an asynchronous control component, the asynchronous control component comprises one or more of a sender (Sender), a relay (Relay), a receiver (Receiver) or a relay permission (PmtRelay), and the Sender comprises a trigger, a phase inverter and a delay module; the Relay is composed of an exclusive-OR gate, an XNOR gate, an AND gate, a D trigger, an inverter and a delay module, and is realized based on a Click asynchronous controller; the Receiver comprises a trigger; according to the PmtRelay, a pmt control mechanism is added in a Click controller; the asynchronous control assembly is one of a Fifo, a PmtFifo, a Selector, a Splitter, a WaitMerge and a MutexMerge, and an asynchronous micro pipeline structure is constructed by one or more of the asynchronous control assemblies. According to the asynchronous micro-pipeline structure, fine-grained control is provided, event flow is used for driving control, a unified control chain template is adopted, the design is more direct and simple, the structure pays more attention to delay and generation conditions of event signals, and the design process is more flexible and efficient.

Aspects of the subject technology include receiving a selection of a trigger event, a set of workflows associated with the trigger event, wherein each workflow is assigned a respective priority attribute, and a set of custom expressions, wherein each custom expression corresponds to a respective workflow and specifies one or more conditions associated with the trigger event. Aspects also include receiving an occurrence of the trigger event and, in response to a determination that the trigger event matches a custom expression for at least one workflow, performing a workflow of the set of workflows having a greatest priority and for which the associated respective custom expression is satisfied, wherein performing a workflow includes performing a set of recovery actions. Aspects also include, in response to a determination that the trigger event does not match any of the respective sets of custom expressions, performing a default workflow.

A keyboard key structure comprising a key stem, a contact-based mechanical trigger, and a contactless analog key switch. The key stem is configured to be depressed and move along a linear path over a range of operation. The contact-based mechanical trigger is configured to activate after the key stem is depressed a threshold distance in the range of operation. In response to the contact-based mechanical trigger activating, the contactless analog key switch is configured to detect, at a sample rate, a position of the key stem between the threshold distance and an end of the range of operation after the key stem is depressed. The contact-based mechanical trigger can be a galvanic-type key switch. The contactless analog key switch can be one of an optical key switch, a magnetic key switch, or an inductive key switch.

A multi-modulus divider includes a prescaler and a finite state machine. The prescaler includes a combinational logic circuit programmable to divide a frequency of an input clock signal by a first value or a second value. The multi-modulus divider includes a first flip-flop having a data input coupled to an output of the prescaler and an output coupled to an input of the finite state machine. The multi-modulus divider includes a second flip-flop having a data input coupled to the finite state machine such that the data input is configured to receive a programming signal output by the finite state machine and associated with programming the combinational logic circuit. The multi-modulus divider includes a third flip-flop having a data input coupled to an output of the second flip-flop. The third-flip flop also has an output coupled to the combinational logic circuit.

The invention discloses a predictive maintenance algorithm for transmission equipment, and relates to the technical field of maintenance of the transmission equipment, in particular to a roller conveying system applied to flexible materials, which is characterized by comprising the following steps: S1, arranging position triggers at key transition nodes of a roller conveyor for acquiring timestamps of the materials passing through detection points in real time, generating a unique number and a corresponding time sequence relationship for each material; and S2, standard material passing time is calculated based on the theoretical beat period, the difference between the actual time and the standard period is calculated, and a beat offset set is constructed to reflect the conveying beat deviation of the materials between the adjacent detection points. According to the method, early warning and intelligent regulation and control of flexible material conveying rhythm imbalance are achieved through rhythm offset modeling, abnormal aggregation recognition and root cause diagnosis, compression bandwidth and driving time delay are dynamically adjusted when the imbalance risk occurs, the accumulation risk is effectively relieved, and the system stability, the automation level and the operation efficiency are improved.

The invention relates to the technical field of industrial process control, and discloses a digital twinning-based fermentation process temperature adaptive control system, which comprises a data acquisition and state representation module, a probability generation type digital twinning module, an adaptive risk management module, an opportunity constraint model prediction control module and a model iteration trigger module, according to the method, probability distribution of future states is predicted by constructing probability generation type digital twinning, and the uncertainty of the model is quantified in real time; the system can dynamically adjust the risk tolerance, drives the chance constraint model prediction controller, seeks an optimal control solution on the premise of ensuring the process safety probability, triggers the model adaptive update by means of an online evaluation mechanism, and realizes the optimal control solution on the basis of effectively managing the process uncertainty. The fermentation temperature is subjected to high-performance self-adaptive control considering safety and economy, and the problem that a traditional deterministic model is insufficient in control robustness is solved.

The invention relates to a programmable frequency divider applied to JESD204B / C. The programmable frequency divider comprises a prescaler which realizes 1 / 2 / 4 dynamic frequency division through a closed-loop feedback structure; according to the 12-bit main frequency divider, the duty ratio of odd-even frequency division is controlled by a 11-stage asynchronous CML frequency-halving chain and a separation DFF0 module; the frequency dividing ratio N is equal to DIV Nlt; 11: 0gt; 2, the odd number frequency division duty ratio is automatically adjusted to (N + 1) / 2N; the cascade noise optimization comprises the following steps of: resampling by using an input clock fin through a retiming trigger (RetimeDFF1 / 2); according to the pulse generator, the number K of pulses output by a four-stage counter is equal to Pulsecount; 3: 0gt; a decimal value; and the output mode circuit supports three-mode direct connection. According to the programmable frequency divider, the HBT process CML unit and the emitter follower are adopted for buffering; and the high-precision clock synchronization requirements of JESD204B / C systems such as a 5G base station and a millimeter wave radar can be met.

The invention discloses a dual-mode TDC implementation method and system based on an FPGA, and relates to the technical field of electronic circuits, and the technical key points are as follows: after a dual-mode signal generation circuit receives each STOP pulse, a logic sequence opposite to the last time is immediately output as an effective delay signal, the reset of the last time signal in a time delay chain (TDL) is not required, and the time delay time is shortened; when the logic signal propagated last time does not completely fade, the new reverse logic signal can be independently propagated in the TDL, and the new reverse logic signal and the new reverse logic signal do not interfere with each other; meanwhile, the rising edge of the system clock only updates the state of the main trigger to serve as the logic reference of the next trigger, and an additional reset process is not needed, so that the dead zone time of single measurement is strictly controlled to be a single period corresponding to the system clock, and compared with a double-period dead zone in an existing scheme, the dead zone time is remarkably shortened, and the measurement rate is synchronously doubled; in a high-frequency pulse measurement scene, pulse loss caused by an overlong dead zone can be effectively avoided, and the measurement efficiency is remarkably improved.

An apparatus, including: a first multiplexer including inputs configured to receive an input data signal and a scan signal, and a select input configured to receive shift control signal; a first latch including an input coupled to an output of the first multiplexer, and a complementary (e.g., inverting) clock input configured to receive a clock signal; a second latch including an input coupled to the output of the first multiplexer, and a non-complementary clock input configured to receive the clock signal; and a second multiplexer including inputs coupled to outputs of the first and second latches, respectively, a select input configured to receive the clock signal, and an output configured to generate an output data or scan signal.

The invention provides a self-adaptive threshold calibration zero-crossing detection circuit. The self-adaptive threshold calibration zero-crossing detection circuit comprises a zero-crossing comparator, a phase inverter, a trigger, a dynamic comparator, a counter and a decoder, the input end of the zero-crossing comparator is connected with GND, switch node voltage, an inversion signal of a lower power tube grid control signal and the output end of the decoder, and the output end of the zero-crossing comparator is connected with the input end of the phase inverter; the input end of the phase inverter is connected with the output end of the zero-crossing comparator, and the output end is connected with the input end of the trigger; the input end of the trigger is connected with the output end of the phase inverter and an inversion signal of an upper power tube grid control signal, and the output end of the trigger is connected with the input end of the dynamic comparator; the input end of the dynamic comparator is connected with GND, switch node voltage and the output end of the trigger, and the output end is connected with the input end of the counter; the input end of the counter is connected with the output end of the dynamic comparator, and the output end is connected with the input end of the decoder; the input end of the decoder is connected with the output end of the counter, and the output end is connected with the input end of the zero-crossing comparator. The flip threshold of the zero-cross detection circuit is changed, and when the inductive current zero-cross phenomenon occurs in a DCM type, the reverse inductive current when the lower power tube is turned off is reduced.

A clock domain crossing (CDC) circuit receives a first data. The CDC circuit includes a first buffer and a second buffer. The first buffer includes a single-clock static random-access memory. The second buffer includes a plurality of data flip-flops. Logic coupled to the first buffer and the second buffer can determine that first buffer is not full at a first time. Responsive to the determination that the second buffer is not full at the first time, the processing logic can bypass the first buffer to write the first data to the second buffer according to the first clock domain. The processing logic can provide the first data as output from the second buffer according to the second clock domain.

The invention discloses a true random number generator circuit based on 1T1R and a random number generation method thereof, belongs to the field of information security, and aims to solve the problem that in most true random number generator circuit designs based on volatile memristors, peripheral circuits generally comprise logic gates, triggers and clock signal generators, so that the reliability of the true random number generator circuit is greatly improved. The circuit comprises a memristor, a transistor and a T flip-flop, and the memristor, the transistor and the T flip-flop are connected with the memristor and the T flip-flop respectively. One end of the memristor is connected with an input voltage # imgabs0 #, and the other end of the memristor is connected in series to the drain electrode of the transistor through a first wire; the grid electrode of the transistor is connected to a fixed voltage # imgabs1 #, and the source electrode of the transistor is grounded; a second wire is led out from the first wire connected with the memristor and the transistor and is connected to the clock end of the T trigger, and the cross connection point of the first wire and the second wire is an output node # imgabs2.

A multi-bit linear-feedback shift register (LFSR) counter comprises a plurality of flip-flops serially coupled to one another with a separate flip-flop for each bit of a number of bits of the multi-bit counter, wherein each flip-flop has an individual binary value that, when combined with binary values of the other flip-flops, generates a unique sequence of bits representative of a unique state for the plurality of flip-flops; exclusive-or (XOR) logic between a pair of flip-flops based upon, at least in part, a plurality of taps for a primitive polynomial defined for the number of bits; and a look-up read-only table (LUT) mapping the unique sequence of bits generated by the plurality of flip-flops to a sequential decimal count value based upon, at least in part, an initial unique sequence of bits generated by the plurality of flip-flops.

The invention relates to a KRG system instrument channel test method, a computer storage medium and control equipment. The method comprises the following steps: S10, acquiring test parameters of a to-be-tested instrument channel; s20, a ramp voltage signal is output to a processing calculation module of a to-be-tested instrument channel according to the test parameters and a preset linear formula; s30, acquiring an output end signal of a threshold trigger corresponding to the to-be-tested instrument channel; s40, judging whether the signal at the output end of the threshold trigger jumps or not; s50, when the output end signal jumps, the voltage value of the ramp voltage signal at the jumping moment is recorded as the action voltage; and S60, judging whether the instrument channel to be tested is qualified or not according to the action voltage. According to the invention, the instrument channel to be tested can obtain the ramp voltage signal required by the test through the software program, then the instrument channel is tested, and the method has the advantages of small manual operation amount, low human error risk and high test accuracy.

Provided in the present invention is a method performed by user equipment, and user equipment. The method performed by user equipment is a method, performed by user equipment, for determining address information to which a CSI report belongs or corresponds. The method includes the following steps: carrying, by user equipment, a CSI request trigger in SCI, and scheduling transmission of a PSSCH carrying a TB in the SCI, wherein the TB includes an MAC PDU, and an MAC subheader of the MAC PDU includes address information; receiving, by another user equipment, the SCI, receiving the transmission of the PSSCH according to the information in the SCI, and decoding the TB; and generating, by another user equipment, a CSI report, wherein address information of the CSI report is determined by the address information of the CSI request trigger corresponding to the CSI report.

The invention discloses a multi-modulation-mode power converter and a switching control circuit thereof. The switch control circuit comprises a reset circuit used for generating a reset signal according to a current detection signal representing an inductive current of the power converter and an error signal of a feedback loop of the power converter; the setting circuit is used for generating a setting signal according to the error signal; the RS trigger is used for generating a switch control signal of a switch tube in the power converter according to the reset signal and the set signal; the mode selection circuit is used for comparing the error signal with a switching reference voltage to generate a mode selection signal, and the reset circuit and the setting circuit respond to the mode selection signal to switch internal signal paths respectively, so that the power converter selectively works in one of a PFM mode and a COFT mode. The switch control circuit can adaptively work in one of a PFM mode and a COFT mode according to load conditions, and smooth mode switching can be realized when the COFT mode is switched to the PFM mode.

The invention discloses a transmitter based on a high-speed low-power-consumption data serialization and driving circuit, and the transmitter comprises a low-speed serialization module which is used for serializing 32 paths of input parallel low-speed data into 4 paths under the control of a multi-phase clock signal; the FFE 4-tap generation module is used for performing delay operation on the four paths of data under the control of a clock signal to obtain four groups of tap data; and the high-speed 4: 1 MUX hybrid SST driving module is provided with 2N first slices, the N first slices comprise K slices of PRE taps, L slices of MAIN taps, J slices of POST1 taps and H slices of POST2 taps, and the driving module is used for generating full-rate differential data according to the four groups of tap data and switching signals provided externally and realizing impedance matching of an output end. According to the invention, the number of used triggers can be reduced, full-rate nodes in the circuit are eliminated, the power consumption is reduced, the complexity of simulating the FFE is relatively low, and different channel losses can be compensated.

The invention relates to the technical field of integrated circuits, and provides a self-adaptive frequency modulation and voltage regulation chip control circuit and method, the circuit comprises a time sequence monitoring module which comprises a critical path replication sub-module and a daisy chain delay sub-module which are connected, and the critical path replication sub-module is used for simulating an actual critical data path in a chip; the daisy chain delay sub-module is used for applying a configurable delay amount on a time sequence to the output data signal; the time sequence performance after different time points is simulated; the first trigger is used for transmitting data signals; the sampling trigger module is used for sampling the data signal output by the time sequence monitoring module; the comparison logic module is used for generating a multi-bit time sequence margin indication code according to a comparison result; the time sequence margin indication code is used for adaptively adjusting the working frequency or the working voltage of the chip. According to the invention, through accurate monitoring and self-adaptive adjustment of a chip time sequence, all design margins can be utilized, and the energy utilization efficiency is improved, so that extreme low power consumption is realized.

An integrated circuit includes first bit cells, second bit cells, and clock cells. Each of first bit cells is arranged in one of multiple first cell rows having a first row height. Each of the second bit cells is arranged in one of multiple second cells rows having a second row height different from the first row height. The second bit cells extend to pass the first bit cells in a first direction. The clock cells are arranged in peripheral regions of a multi-bit flip flop cell in the first cell rows. The first and second bit cells and the clock cells are included in the multi-bit flip flop cell.

An electric hair cutting device including a housing having a first end and a second end opposite the first end, a bladeset mounted to the housing at the first end, the bladeset having a stationary blade and a reciprocating blade, an electric motor electrically connected to a power source within the housing, a drive shaft operatively connecting the electric motor to the reciprocating blade, a control module within the housing which controls a rotational speed of the electric motor; and a trigger which sends an actuation signal to the control module based on a partial actuation of the trigger between a minimum actuation and a maximum actuation, the control module adjusting a rotational speed of the electric motor based on the actuation signal. A related charging stand is provided that is compatible with the hair cutting device and features a digital display of device parameters.