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2254 results about "Flip-flop" patented technology

In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to store state information – a bistable multivibrator. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic. Flip-flops and latches are fundamental building blocks of digital electronics systems used in computers, communications, and many other types of systems.

SRAM type FPGA single particle irradiation test system and method

ActiveCN103744014ARefresh is convenient and reliableReliably flip dataElectrical testingCommunication interfacePower flow
The invention provides an SRAM type FPGA single particle irradiation test system and method. The test system comprises a host computer, a current monitoring acquisition plate and a test plate. The current monitoring acquisition plate comprises a current monitoring acquisition FPGA, a current acquisition unit, a power supply module and a first communication interface; the test plate comprises a control processing FPGA, a refreshing chip, an SRAM, a configuration PROM, a storage PROM, a second communication interface and a detected FPGA; the host computer is in charge of flow control and data processing; the current monitoring acquisition plate is in charge of power-on and power-off of the test plate and monitoring and testing of FPGA currents; and the test plate is in charge of processing a command sent by the host computer and performing work such as single particle overturning, single particle function interruption detection and the like. According to the invention, the refreshing chip is utilized to replace some of the reconfiguration modules in a conventional irradiation test system so that a detected chip can be more conveniently and reliably refreshed; and the system and method provided by the invention can realize static and dynamic overturning testing on a trigger, and more reliable trigger overturning data can be obtained by combing the two methods.
Owner:BEIJING MICROELECTRONICS TECH INST +1

Low-power dissipation RS latch unit and low-power dissipation master-slave D flip-flop

InactiveCN101777907ASimple and completely symmetrical structureGood leakage power suppression performanceElectric pulse generatorLogic circuitsHemt circuitsControl theory
The invention discloses a low-power dissipation RS latch unit and a low-power dissipation master-slave D flip-flop, which is characterized in that the low-power dissipation RS latch unit comprises an input driving and synchronizing circuit, a pull-down circuit, a function control circuit, a first phase inverter and a second phase inverter, wherein the first phase inverter and the second phase inverter are mutually overlapped and coupled. The low power dissipation master-slave D flip-flop is composed of an input phase inverter, a clock phase inverter, a first low-power dissipation RS latch unit and a second low-power dissipation RS latch unit, wherein the first low power dissipation RS latch unit and the second low power dissipation RS latch unit have the same inner structure and are cascaded. The low power dissipation master-slave D flip-flop has the advantages that the low-power dissipation RS latch units use three kinds of leaked power consumption lowering technology, i.e. P-type logic technology, function control technology and double-threshold technology, so that the low-power dissipation RS latch units have better leaked power consumption inhibiting performance. The low-power dissipation master-slave D flip-flop has simple and totally symmetrical circuit structure. Compared with the traditional single-threshold transmission gate D trigger circuit, the invention can save 80% of leaked power consumption and 40% of total power consumption in the 90 nm process, so that the invention is suitable to serve as a digital circuit unit to the design of low-power consumption integrated circuits in the deep sub-micron CMOS process.
Owner:NINGBO UNIV

High-precision method and device for measuring interval between positive time and negative time

The invention provides a high-precision method and device for measuring an interval between positive time and negative time. The device comprises a signal shaping and measuring gate extracting unit, a synchronization and interpolation unit, a clock counting unit, a storage unit and a data processing unit, wherein the signal shaping and measuring gate extracting unit, the synchronization and interpolation unit, the clock counting unit, the storage unit and the data processing unit are in connection with one another and in communication with one another. The signal shaping and measuring gate extracting unit conducts comparing and shaping on input signals according to a trigger level, converts measured signals into ECL level signals, and extracts gate signals corresponding to the measured signals through an ECL trigger. The synchronization and interpolation unit samples the two routes of gate signals through a counting clock. By means of the scheme, various types of signal input can be achieved, and the wide input dynamic range can be supported; a channel circuit is obtained through a high-speed ECL device, the channel bandwidth is large, narrow-pulse measurement can be achieved, the minimum measurable pulse width can reach 2.5ns, and the measurement resolution ratio can reach 40ps.
Owner:THE 41ST INST OF CHINA ELECTRONICS TECH GRP

Mobile barcode scanner gun system with mobile tablet device having a mobile Pos and enterprise resource planning application for customer checkout/order fulfillment and real time in store inventory management for retail establishment

A mobile scanner gun system efficiently and reliably processes a retail store purchase and / or performs daily store inventory management functions. The system has a main body portion extending toward a handle portion, the main body portion having a base, side walls, a front wall and a back wall constructed to form an interior cavity, wherein the front wall includes an aperture with a lens recessed therein. The front wall has a trigger member located near the base of the main body. A USB scanner input device is mounted above and in front of the trigger, the scanner having two drivers, including 1) a native device driver and 2) a keyboard input driver, the scanner device being in communication with the trigger for initiating a scan of a barcode. A USB MSR input device is integrated on the short edge of the mobile tablet device (upper receiver) and is used for processing payment card sales transactions through a secured PCI compliant, end to end encrypted bank card processor. The top wall of the main body portion includes an attachment means comprising a base mount universal receiver with rotational coupling means and a specialized universal serial bus wiring harness adapted to interchangeably mount and communicate with a mobile tablet device having a system integrated therein that enables real-time store level inventory management and a fully functioning POS capability for selling merchandise in a retail sales environment. The base mount universal receiver with rotational coupling allows the mobile tablet device to rotate from portrait mode to landscape mode without operational delay of the system.
Owner:RETAIL TECH

Automatic fluid channel screen lock-unlock system

The present invention relates to a screen lock-unlock system for automatically locking and unlocking a screen that is within a fluid channel wherein the screen is rotatable relative to the channel from closed to open. The system includes an actuator comprising a flapper and a trigger, wherein the flapper is rotatably connectable to the back of the screen. The flapper is operably connected to the trigger for moving the trigger. And, the system is further summarized, according to one aspect, as follows. It includes a lock bar wherein the lock bar is rotatably attachable to a screen support structure, the lock bar being rotatable by movement of the trigger. The lock bar intercepts the rearward arc path of a blockable part (such as a flange extending laterally from the screen). The flapper is located and oriented with respect to the closed screen for at least part of the flapper to be rotatable in response to pressure from impact fluid. The trigger is located sufficiently close to the lock bar for rotation of the trigger to move the lock bar in a direction and amount needed for at least part of the lock bar to clear the blockable part, allowing the screen to open in response to pressure against the front of the screen. The screen is rotatable toward a closed position in response to the diminishment of the pressure against the front of the screen. And, the lock bar is biased in a counter-rotation direction (by part of the lock bar and / or another biasing device) to at least help hold the lock bar in and / or return it to a locked position.
Owner:NINO KHALIL IBRAHIM

High-precision TDC based on equivalent segmentation and equivalent measurement method thereof

The invention discloses a high-precision TDC based on equivalent segmentation. A second-order time digital conversion structure of equivalent segmentation based on an FPGA is adopted, and the high-precision TDC comprises a first-order delay ring reduction interpolator, a second-order interpolator based on equivalent segmentation, a triggering pulse generation module, a synchronization module, an integer period counter, a data storage module and a delay line phase-locked oscillator. According to the first-order interpolator, the conversion rate of the TDC is increased with a low measurement resolution ratio, the second-order interpolator is composed of multiple delay ring reduction interpolators connected in parallel, by the adoption of an equivalent segmentation method, the measurement resolution ratio is increased, measurement precision is improved, the triggering pulse generation module is used for generating a starting signal and an ending signal for the TDC, the synchronization module eliminates the semi-stable state effect of a register through multiple trigger structures, the integer period counter is composed of multiple counters based on the principle of the shifting register, and the delay line phase-locked oscillator uses feedback for controlling core voltage of the FPGA to stabilize the measurement result of the TDC. The measurement prevision is high, and the conversion rate is high.
Owner:INNOVATION ACAD FOR PRECISION MEASUREMENT SCI & TECH CAS +1
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