803 results about "Flip-flop" patented technology

The invention discloses a dual-mode TDC implementation method and system based on an FPGA, and relates to the technical field of electronic circuits, and the technical key points are as follows: after a dual-mode signal generation circuit receives each STOP pulse, a logic sequence opposite to the last time is immediately output as an effective delay signal, the reset of the last time signal in a time delay chain (TDL) is not required, and the time delay time is shortened; when the logic signal propagated last time does not completely fade, the new reverse logic signal can be independently propagated in the TDL, and the new reverse logic signal and the new reverse logic signal do not interfere with each other; meanwhile, the rising edge of the system clock only updates the state of the main trigger to serve as the logic reference of the next trigger, and an additional reset process is not needed, so that the dead zone time of single measurement is strictly controlled to be a single period corresponding to the system clock, and compared with a double-period dead zone in an existing scheme, the dead zone time is remarkably shortened, and the measurement rate is synchronously doubled; in a high-frequency pulse measurement scene, pulse loss caused by an overlong dead zone can be effectively avoided, and the measurement efficiency is remarkably improved.

An electric hair cutting device including a housing having a first end and a second end opposite the first end, a bladeset mounted to the housing at the first end, the bladeset having a stationary blade and a reciprocating blade, an electric motor electrically connected to a power source within the housing, a drive shaft operatively connecting the electric motor to the reciprocating blade, a control module within the housing which controls a rotational speed of the electric motor; and a trigger which sends an actuation signal to the control module based on a partial actuation of the trigger between a minimum actuation and a maximum actuation, the control module adjusting a rotational speed of the electric motor based on the actuation signal. A related charging stand is provided that is compatible with the hair cutting device and features a digital display of device parameters.

The invention provides a chip time sequence analysis method and device, and the method comprises the steps: determining the second data path time delay between the corresponding ports of interconnected modules according to the first data path time delay of the corresponding port of each module and the interconnection relation information between the modules under the condition that a plurality of modules are in a target stable state, the interconnection module comprises two modules which are directly connected in the modules; and determining convergence information of the top time sequence of the interconnection modules according to the clock period, the trigger establishment time, the clock uncertainty, the clock skew between the interconnection modules and the second data path time delay. According to the method and the device, the time sequence between the interconnected modules can be quickly analyzed before the top-layer time sequence analysis is executed, and the time sequence analysis efficiency of the top layer of the chip is improved without waiting for all the modules to complete a physical implementation process.

The invention discloses an MEMS resonator low ripple error temperature measurement system based on voltage feedback compensation, and the system comprises a trans-impedance amplifier, an analog-to-digital converter, a frequency detection module, a PI controller, a variable gain amplifier, a Schmitt trigger, a first digital-to-analog converter, a biasing circuit, mode switches S1 and S2, and a voltage feedback compensation loop. The compensation loop comprises an amplitude detection module, a lookup table, a second digital-to-analog converter and an adder; the amplitude detection module receives the digital signal from the analog-to-digital converter and outputs a vibration amplitude signal in real time; the lookup table receives the vibration amplitude signal, inquires and outputs a corresponding digital compensation voltage, and converts the digital compensation voltage into an analog voltage through a second digital-to-analog converter; the adder adds the analog voltage and a fixed bias voltage to generate a dynamic bias voltage and applies the dynamic bias voltage to a drive electrode of the MEMS resonator. According to the system, an amplitude-driving end bias voltage feedback compensation loop is introduced, so that the periodic ripples of the resonant frequency are effectively suppressed.

The invention discloses a method for improving Buck light load efficiency, which can prevent pseudo CCM operation and can keep high light load efficiency even under a large duty ratio, and comprises the following steps: after soft start of a Buck converter is completed, an enable signal at the end of soft start sets an RS trigger U3 to be in an active state, and if an inductive current zero-cross detection trigger signal rises, the RS trigger U3 is in a non-active state, the RS trigger U3 is in a non-active state, and if the inductive current zero-cross detection trigger signal is in a non-active state, the RS trigger U3 is in a non-active state. When the high-end switch and the synchronous low-end switch are switched on, the setting end input of the RS trigger U3 is triggered, a switch starting signal output by the RS trigger U3 is set at the beginning of each switching period, the switch starting signal controls the constant on-time generator to modulate the charging current or capacitance so as to prolong the time of simultaneously switching off the high-end switch and the synchronous low-end switch, and when the synchronous low-end switch is switched on, the synchronous low-end switch is switched off. And the reset end of the RS trigger U3 inputs an output signal of the constant on-time generator to trigger the RS trigger U3 to reset.

A flow control arrangement is provided including a housing seating inlet and outlet conduits is provided. An isolation valve is arranged within the housing and is fluidly coupled to the inlet conduit. A first flow switch with a first shutoff trigger is arranged within the housing and fluidly couples the isolation valve to the outlet conduit. A second flow switch with a second shutoff trigger is arranged outside of the housing and is fluidly separated from the first flow switch. A controller operably connects the first and second flow switches to the isolation valve to close the isolation valve when (a) flow rate of a first fluid traversing the first flow switch is greater than the first shutoff trigger, or (b) flow rate of a second fluid traversing the second flow switch is less than the second shutoff trigger. Semiconductor processing systems and flow control methods are also described.

Devices, systems, and methods are disclosed for customizing audio experiences associated with operation of a ridable device. An electronic device having a processor detects contextual information such as speed, acceleration, ambient noise level, environment type, or location of the ridable device. Sensor data from accelerometers, gyroscopes, microphones, cameras, or positioning systems may be processed to identify these conditions. Based on the detected context, the electronic device determines audio configuration parameters, including selection of audio content, adjustment of volume, blending of tracks, or modification of tempo or pitch. The determined parameters are applied to output audio through one or more speakers of the electronic device, the ridable device, or associated accessories. In some implementations, playback is synchronized with other riders using a common time reference, geo-fence triggers are employed to provide location-specific content, or warning sounds are generated when nearby objects are detected, enhancing both rider enjoyment and environmental awareness.

The invention discloses an adaptive mode switching circuit of a BUCK converter for COT control. The adaptive mode switching circuit comprises a conduction time generation circuit, an OR gate, phase inverters INV1, INV2 and INV3, an NAND gate, an AND gate, RS triggers RS1 and RS2, transistors Mon, MN1, MN2 and MN3, a falling edge delay circuit, a rising edge delay circuit and a zero cross detection circuit. According to the invention, a conduction signal and a zero-cross detection signal are fed back to the conduction time generation circuit, the states of two paths of control signals in a DCM mode and a CCM mode are adaptively adjusted, logic operation is carried out on the control signals through an OR gate, and the conduction time of an upper tube is adaptively adjusted. When the DCM mode is switched to the CCM mode, the CCM control signal serves as a conduction time control signal, and the conduction time of an upper tube is increased; and when the CCM mode is switched to the DCM mode, the DCM control signal is used as a conduction time control signal, and the conduction time of the upper tube is reduced.

A wireless transmit / receive unit (WTRU) may send assistance information to a network element. The assistance information may indicate that the WTRU can use sensor data for mobility. The WTRU may receive conditional PSCell change (CPC) configuration information, for example from the network element. The CPC configuration information may include one or more of a CPC candidate for device mobility, a CPC candidate for external mobility, and / or a trigger for performing CPC based on the assistance information. The WTRU may perform a CPC, for example based on a cell quality of a serving cell being below a threshold. The WTRU may determine whether to use the CPC candidate for device mobility and / or the CPC candidate for external mobility based on the sensor data and the trigger, for example to perform the CPC.

The invention relates to a trigger unit. The trigger unit comprises a first comparison feedback circuit, a first clock gating circuit, a master latch and a slave latch assembly, the first comparison feedback circuit is used for detecting a signal hopping state of an external input signal according to a first output signal output by the output end of the main latch, and generating a corresponding first state feedback signal, so that the first clock gating circuit generates a corresponding first gating clock signal according to the first state feedback signal and a reference clock signal, and sends the first gating clock signal to the second clock gating circuit; under the condition that the first gating clock signal is valid, the main latch is controlled to update the first output signal according to the external input signal; the state switching opportunity of the main latch can be accurately controlled, and unnecessary clock flipping in the trigger and transistor switching activity caused by the unnecessary clock flipping are effectively reduced, so that dynamic power consumption related to a clock network and dynamic power consumption generated by flipping of nodes in a data path are effectively reduced.

A system includes a first sense amplifier having a first data input, a second data input, a clock input configured to receive a first clock signal, a first output, and a second output. The system also includes a second sense amplifier having a first data input, a second data input, a clock input configured to receive a second clock signal, a first output, and a second output. The first data input of the second sense amplifier is coupled to the first data input of the first sense amplifier, and the second data input of the second sense amplifier is coupled to the second data input of the first sense amplifier. The system also includes a set-reset (S-R) latch coupled to the first output and the second output of the first sense amplifier, and coupled to the first output and the second output of the second sense amplifier.

The invention discloses a robot strategy generation method and device, a computer and a storage medium, whether an initial plan generated by a VLM strategy network should be directly executed or not is judged through a confidence trigger, unnecessary reflection is achieved, task execution efficiency is improved, if the confidence is lower than a preset threshold value, an reflection stage is entered, and the task execution efficiency is improved. A plurality of candidate future trajectories guided by a plurality of candidate actions are generated, advantage evaluation is performed on each candidate future trajectory, a more accurate supervision signal is provided, decision robustness is enhanced, an evaluation result is used as feedback of a VLM strategy network, feedback information of all trajectories is aggregated by the VLM strategy network in a decoding stage to correct an initial plan, and the decision robustness is improved. According to the method, the low-quality action planning can be accurately identified and corrected, and the balance of efficiency and performance is realized.

A critical path tracking system for an integrated circuit (IC) is described. The system may include a real critical path with a first set of combinatorial logic receiving data and clock inputs, generating a first output. The system may include a replica critical path with a second set of combinatorial logic replicating the first set, generating a second output. Capture flip-flops (CFFs) may be coupled to paths, capturing the first and second outputs at different points. A programmable delay element may introduce adjustable delays to the second output. A multiplexer may select between the first and delayed outputs for the CFFs, and a comparator may generate a path_failure_signature by comparing the outputs. A control circuit may dynamically adjust the delay settings and the IC's supply voltage based on the path failure signature. A software loop may read the signature, analyze timing margins, and control the circuit.

This disclosure relates to a central control physical button, a central control screen, and a vehicle, belonging to the field of automotive intelligent cockpit technology. The central control physical button includes a mounting base, an electronic control board, and at least one physical button. The electronic control board is mounted on the mounting base and has at least one trigger and a controller. The trigger and controller are signal-connected, and the controller is signal-connected to the central control screen. The physical buttons are mounted on the mounting base and correspond one-to-one with the triggers. When a physical button is pressed, the trigger transmits the triggered signal to the controller. The controller sends a control command corresponding to the physical button to the central control screen to execute the corresponding function of the physical button. The corresponding function of the physical button can be modified by a function customization command received by the central control screen. This disclosure allows for simple and quick use of corresponding functions by pressing the physical button, avoiding the risk of car accidents due to user distraction.

The application relates to a non-volatile D flip-flop circuit. The non-volatile D flip-flop circuit formed by adopting the architecture mode of a latch circuit module, a self-enabled write circuit module, a non-volatile storage unit module, a read circuit module and a multiplexer module has only one working mode, so that the application has the characteristic of simple control timing. The self-enabled write circuit module and the non-volatile storage unit module arranged in the non-volatile D flip-flop circuit can realize real-time backup while reducing energy consumption.

The application discloses an analog-digital conversion circuit and chip, a motor driving device, an electrical equipment, and a vehicle and equipment, wherein the analog-digital conversion circuit comprises an analog signal sampling module, a clock signal generating module and a flip-flop, the analog signal sampling module is used for acquiring an analog signal and generating an analog sampling signal; the clock signal generating module is used for generating a clock signal; a first input end of the flip-flop is connected with an output end of the analog signal sampling module, a second input end of the flip-flop is connected with an output end of the clock signal generating module, and an output end of the flip-flop is connected with a switch control end of the analog signal sampling module; the flip-flop is used for controlling a duty cycle of an output signal according to the clock signal and the analog sampling signal to generate a digital pulse signal. The analog-digital conversion circuit of the embodiment has a wider collection range for the analog signal, and the circuit has a wide application range. The motor driving device, the electrical equipment, the vehicle and the equipment have more stable performances.

An SEU-immune trigger includes a master-level data latch that is transparent in response to a first clock signal state and locked in response to a second clock signal state; a slave-level data latch; and a scan slave latch having an input coupled to a scan output of the slave-level data latch, the scan slave latch being transparent in response to the second clock signal state and locked in response to the first clock signal state. The slave-level data latch includes a switching inverter that is disabled when the slave latch is in a transparent state and enabled when the slave latch is in a locked state with a time delay longer than the SEU time period.

This invention discloses a self-locking circuit and protection system for emergency communication equipment, relating to the field of emergency communication. The self-locking circuit includes: a Schmitt trigger, an RS latch, a magnetic latching relay, a first driver transistor, a second driver transistor, an inverter, and a reset switch. The Schmitt trigger's input receives an abnormal signal and a reference voltage, and its output is connected to the RS latch's set terminal. The RS latch's output is connected to the base of the first driver transistor. The collector of the first driver transistor is connected to the magnetic latching relay's set terminal, and its emitter is grounded. The reset switch's first terminal is grounded, and its second terminal is connected to the RS latch's reset terminal via the inverter. The RS latch's reset terminal is connected to the base of the second driver transistor. The second driver transistor's collector is connected to the magnetic latching relay's reset terminal, and its emitter is grounded. The magnetic latching relay's output is connected to the emergency communication equipment. By implementing this invention, the problem of repeated device restarts in existing software-based communication management is solved, improving the equipment's operational stability.

The invention relates to the technical field of power transmission line operation and maintenance, and discloses an uninterruptible power main material replacement method suitable for a mountainous area rockfall damaged power transmission tower, which comprises the following steps: firstly, establishing a protective bent frame with a mechanical trigger in a dangerous rock area, and linking a tower body locking module through a signal cable to construct an induction linkage defense system; a bypass channel is established by using the hoop lined with the friction coating and the rigid-flexible coupling prestress node, and the damaged main material load is smoothly transferred to the auxiliary main material and then the auxiliary main material is dismantled; then a new main material of the prefabricated micro-channel is installed, epoxy structural adhesive is injected, and gapless connection between the new component and the old component is achieved; and finally, dismantling the temporary facility after the glue solution is cured. Through mechanical linkage defense, friction type lossless connection and a micro-channel glue injection technology, the problems of lack of operation safety early warning, tower damage caused by reinforcement and poor connection anti-vibration performance are solved, and the operation safety without power failure is guaranteed.

Methods, systems, and devices for wireless communications are described. A UE may obtain, via an application program interface (API), an indication of an application type of an application at the UE and information including an indication of performance requirements associated with the application, an indication of a traffic type associated with the application, an indication of whether the performance requirements are being met, an indication of quality of service (QoS) information associated with a packet data unit (PDU) session established for communication by the application, an indication of a network slice associated with the PDU session, an indication of a power consumption of the UE, an indication of whether a power budget of the UE is being met, or any combination thereof. The UE may communicate one or more wireless signals via a subset of multiple antennas of the UE based on the application type or the information.

There is provided mechanisms for triggering uplink PDU duplication from a user equipment. A method is performed by a network node. The method comprises configuring the user equipment with an RLC URLLC mode. According to the RLC URLLC mode the user equipment is configured with an RLC trigger for the user equipment to perform uplink PDU duplication for an URLLC service.

20 25 27 97 96 15 D ec 2 02 5 A B S T R A C T 2 0 2 5 2 7 9 7 9 6 1 5 D e c 2 0 2 5 800 FIG. 8 Displaying, by a graphical user interface of a display device of a gaming device, a primary wagering game comprising a plurality of slot reels 802 Displaying, by the graphical user interface in response to receipt of a wager for the primary wagering game at the gaming device, each slot reel of the plurality of slot reels spinning in a spin direction comprising one of a first direction and a second direction 804 Determining, by a processor circuit based on the spin direction of each slot reel, a sequence of spin directions for the plurality of slot reels 806 Based on the sequence of spin directions comprising a first sequence of spin directions, initiating a bonus game at the gaming device 808 Determining, by the processor circuit, a bonus game result for the bonus game 810 Based on the bonus game result, cause the gaming device to award a bonus game award to a player at the gaming device. 812 12 / 12 802 804 812 20 25 27 97 96 15 D ec 2 02 5 8 0 0 2 0 2 5 2 7 9 7 9 6 1 5 D e c 2 0 2 5 8 0 4 8 0 6 8 0 8 8 1 2

The utility model relates to the technical field of conveying lines, in particular to a conveying line station controller which comprises a circuit board. The circuit board is provided with an MCU, a first output control module which is connected with the MCU and is used for outputting signals to a mechanism of the conveying line, and a second output control module which is connected with the MCU and is used for outputting signals to a warning lamp of the conveying line. The first output control module comprises a first trigger connected with the MCU and a first power switch chip connected with the first trigger. According to the utility model, the first output control module adopts the first trigger and the first power switch chip, so that digital output directly controlled by a NOT gate in a high-low manner is realized, and the problems that a traditional optical coupling control mode probably causes unsmooth conduction, and a mechanism cannot execute or malfunctions due to incomplete turn-off are solved; therefore, the conveying rhythm and accuracy of the conveying line are guaranteed, the production process is prevented from being affected, and production efficiency is guaranteed.

The application discloses a model training process-oriented computing power chip hardware Trojan design method, and relates to the field of integrated circuit security.The method is designed in view of the computing architecture of a GPU, and contains a flip-flop, a finite state machine and a load circuit.The flip-flop identifies the typical characteristics of deep learning training by monitoring the arithmetic instruction intensity and the Warp concurrent activity of the GPU runtime; when the characteristics meet a preset threshold, the finite state machine is triggered, so that the hardware Trojan enters an activated state.The load circuit has two types of designs: the first type is a gradient flipping circuit which interferes with the gradient update direction by modifying the sign bit output by a floating point calculation unit, so that the model cannot converge; the second type is a redundant calculation circuit which consumes computing resources by inserting invalid floating point operations, thereby prolonging the training time.The application designs and triggers the hardware Trojan by utilizing the architecture characteristics of the GPU, has high concealment, and can effectively destroy the accuracy and efficiency of a deep learning training task.

An apparatus includes a first D flip-flop including a first data output, a first negative edge-triggered clock input, and a first reset input, and a second D flip-flop including a second data output, a second negative edge-triggered clock input, and a second reset input. The apparatus includes a logic gate having an output and first and second inputs, the first input of the logic gate coupled to the first data output, and the second input of the logic gate coupled to the second data output, in which the output of the logic gate is configured to be a first clock output of the apparatus. A delay circuit of the apparatus includes an output and input, the output of the delay circuit coupled to the first and second reset inputs, and the input of the delay circuit coupled to the output of the logic gate.

The invention relates to a DICE-based anti-multi-node upset latch, which belongs to the field of anti-radiation reinforcement of integrated circuits and comprises an input circuit, a node holding and restoring circuit, a DICE circuit, a delay circuit and an output circuit. The input circuit consists of two input C unit circuits and is used for controlling signal input; the node holding and restoring circuit, the DICE circuit and the output circuit are used for transmitting and latching data; when the latch is radiated, the latch can tolerate multi-node flipping and restore; the delay circuit is used for recovering multi-node flipping of the DICE and the output circuit by using a delay signal; the multi-node upset resistant latch provided by the invention can realize a single-particle single-node and double-node instantaneous upset self-recovery function, and has the capability of resisting three-node single-particle upset, and meanwhile, the circuit structure is easy to realize.

A device including an inverter circuit, a hysteresis control circuit, and a high-side input level shifter. The inverter circuit having an output and including at least two series connected PMOS transistors connected, at the output, in series to at least two series connected NMOS transistors. The hysteresis control circuit coupled to the output to provide feedback to the at least two series connected PMOS transistors and to the at least two series connected NMOS transistors. The high-side input level shifter connected to gates of the at least two PMOS transistors and configured to shift a low level of an input signal to a higher level and provide the higher level to one or more of the gates of the at least two PMOS transistors.

A system and method for operating a game of chance. A gaming system includes one or more game displays, a user interface, at least one processor running executable instructions related to a game of chance and memory in communication with said at least one processor. The game of chance including a two-part game wherein at least one part of the two-part games includes a video reel game to trigger a second bonus game part including a plurality of free games relating to a progressive award. The second bonus game part includes awarding at least one combination award including a progressive cash or credit award and an award of a plurality of free games.

The utility model relates to the technical field of motors, and particularly discloses a motor based on a Hall sensor and a trigger, which is rigorous and scientific in design, reasonable in hardware structure and configuration and simple in circuit, saves I / O (Input / Output) port resources of an MCU (Microprogrammed Control Unit), and comprises the MCU, a stepping motor, a stepping motor controller and the Hall sensor. A Hall sensor is arranged in a transmission mechanism of the stepping motor, the MCU is in circuit connection with the stepping motor controller, the stepping motor controller is in circuit connection with the stepping motor, the stepping motor is in electric signal connection with the Hall sensor, the Hall sensor is connected with the MCU, and the MCU is connected with the MCU. A corresponding method is adopted to effectively control the motor in real time, the failure rate is low, the function is safe and reliable, and the working efficiency is high.