1435 results about "Flip-flop" patented technology

A system for improving employee engagement and automating the integration of business processes. The system includes: a user interaction module configured to receive multimodal inputs, including natural language text and voice requests from employees via enterprise portals, mobile applications, voice-activated devices, and collaboration platforms, and to generate real-time responses via conversational output channels; a context processor that is operationally coupled with the user interaction module, wherein the context processor stores the interaction history, employee preferences, organizational role metadata, and task results in both short-term and long-term memory and dynamically derives context for controlling responses and initiating workflows; A natural language and intent processor that is communicatively linked to the context processor. The intent engine consists of large language models trained on company-specific lexicons to perform intent detection, entity extraction, ambiguity resolution, and sentiment or urgency classification from employee queries; a workflow orchestration layer in communication with the intent engine and the context processor, wherein the workflow orchestration layer includes a rule-based and AI-powered process execution engine configured to automatically initiate, route, and complete cross-functional business tasks, including approvals, escalations, and compliance checks, with workflows defined using modular templates that include conditional logic and time-based triggers; Webhooks and authentication protocols provide secure interoperability between the workflow orchestration layer and external enterprise platforms; a feedback and learning module that is operationally coupled with the workflow orchestration layer and the natural language understanding engine, wherein the feedback and learning module is configured to analyze task completion rates, response accuracy, latency metrics, and user feedback signals, and to retrain underlying language and workflow models for adaptive improvement in real time; and an administration console with role-based access controls, compliance dashboards, audit trails and interfaces for workflow configuration, whereby the administration console enables authorized personnel to monitor system operations, adjust interaction rules and enforce data protection restrictions across departments.

The invention relates to the technical field of industrial process control, and discloses a digital twinning-based fermentation process temperature adaptive control system, which comprises a data acquisition and state representation module, a probability generation type digital twinning module, an adaptive risk management module, an opportunity constraint model prediction control module and a model iteration trigger module, according to the method, probability distribution of future states is predicted by constructing probability generation type digital twinning, and the uncertainty of the model is quantified in real time; the system can dynamically adjust the risk tolerance, drives the chance constraint model prediction controller, seeks an optimal control solution on the premise of ensuring the process safety probability, triggers the model adaptive update by means of an online evaluation mechanism, and realizes the optimal control solution on the basis of effectively managing the process uncertainty. The fermentation temperature is subjected to high-performance self-adaptive control considering safety and economy, and the problem that a traditional deterministic model is insufficient in control robustness is solved.

The invention discloses a dual-mode TDC implementation method and system based on an FPGA, and relates to the technical field of electronic circuits, and the technical key points are as follows: after a dual-mode signal generation circuit receives each STOP pulse, a logic sequence opposite to the last time is immediately output as an effective delay signal, the reset of the last time signal in a time delay chain (TDL) is not required, and the time delay time is shortened; when the logic signal propagated last time does not completely fade, the new reverse logic signal can be independently propagated in the TDL, and the new reverse logic signal and the new reverse logic signal do not interfere with each other; meanwhile, the rising edge of the system clock only updates the state of the main trigger to serve as the logic reference of the next trigger, and an additional reset process is not needed, so that the dead zone time of single measurement is strictly controlled to be a single period corresponding to the system clock, and compared with a double-period dead zone in an existing scheme, the dead zone time is remarkably shortened, and the measurement rate is synchronously doubled; in a high-frequency pulse measurement scene, pulse loss caused by an overlong dead zone can be effectively avoided, and the measurement efficiency is remarkably improved.

A multi-bit linear-feedback shift register (LFSR) counter comprises a plurality of flip-flops serially coupled to one another with a separate flip-flop for each bit of a number of bits of the multi-bit counter, wherein each flip-flop has an individual binary value that, when combined with binary values of the other flip-flops, generates a unique sequence of bits representative of a unique state for the plurality of flip-flops; exclusive-or (XOR) logic between a pair of flip-flops based upon, at least in part, a plurality of taps for a primitive polynomial defined for the number of bits; and a look-up read-only table (LUT) mapping the unique sequence of bits generated by the plurality of flip-flops to a sequential decimal count value based upon, at least in part, an initial unique sequence of bits generated by the plurality of flip-flops.

The invention discloses a transmitter based on a high-speed low-power-consumption data serialization and driving circuit, and the transmitter comprises a low-speed serialization module which is used for serializing 32 paths of input parallel low-speed data into 4 paths under the control of a multi-phase clock signal; the FFE 4-tap generation module is used for performing delay operation on the four paths of data under the control of a clock signal to obtain four groups of tap data; and the high-speed 4: 1 MUX hybrid SST driving module is provided with 2N first slices, the N first slices comprise K slices of PRE taps, L slices of MAIN taps, J slices of POST1 taps and H slices of POST2 taps, and the driving module is used for generating full-rate differential data according to the four groups of tap data and switching signals provided externally and realizing impedance matching of an output end. According to the invention, the number of used triggers can be reduced, full-rate nodes in the circuit are eliminated, the power consumption is reduced, the complexity of simulating the FFE is relatively low, and different channel losses can be compensated.

The invention relates to the technical field of integrated circuits, and provides a self-adaptive frequency modulation and voltage regulation chip control circuit and method, the circuit comprises a time sequence monitoring module which comprises a critical path replication sub-module and a daisy chain delay sub-module which are connected, and the critical path replication sub-module is used for simulating an actual critical data path in a chip; the daisy chain delay sub-module is used for applying a configurable delay amount on a time sequence to the output data signal; the time sequence performance after different time points is simulated; the first trigger is used for transmitting data signals; the sampling trigger module is used for sampling the data signal output by the time sequence monitoring module; the comparison logic module is used for generating a multi-bit time sequence margin indication code according to a comparison result; the time sequence margin indication code is used for adaptively adjusting the working frequency or the working voltage of the chip. According to the invention, through accurate monitoring and self-adaptive adjustment of a chip time sequence, all design margins can be utilized, and the energy utilization efficiency is improved, so that extreme low power consumption is realized.

An electric hair cutting device including a housing having a first end and a second end opposite the first end, a bladeset mounted to the housing at the first end, the bladeset having a stationary blade and a reciprocating blade, an electric motor electrically connected to a power source within the housing, a drive shaft operatively connecting the electric motor to the reciprocating blade, a control module within the housing which controls a rotational speed of the electric motor; and a trigger which sends an actuation signal to the control module based on a partial actuation of the trigger between a minimum actuation and a maximum actuation, the control module adjusting a rotational speed of the electric motor based on the actuation signal. A related charging stand is provided that is compatible with the hair cutting device and features a digital display of device parameters.

The invention relates to the technical field of electric signal data processing, in particular to a cable life prediction method based on working condition movement. The method comprises the following steps of: sleeving a leakage flux ring on the periphery of a cable shielding layer, wherein a Hall array is arranged in the leakage flux ring; an acoustic emission patch is attached to the surface of the shielding layer; a mechanical trigger is arranged at the joint of the cable drag chain; when the mechanical trigger detects a complete bending stroke every time, the Hall array and the acoustic emission patch are started synchronously, and a magnetic flux leakage pulse amplitude value and an ultrasonic elastic wave energy value of the current stroke number are generated; dividing the magnetic flux leakage pulse amplitude value of the same stroke number by the ultrasonic elastic wave energy value to obtain a broken wire coefficient of the stroke number; and accumulating the broken wire coefficients of the continuous stroke numbers of the cable to form a theoretical accumulated broken wire index. According to the invention, through the magnetic flux leakage and acoustic emission monitoring technology and in combination with the accelerated bending test, accurate quantification and life prediction of the broken wire state of the cable are realized, and finally, the reliability of the whole life cycle management of the cable is improved.

The invention provides a chip time sequence analysis method and device, and the method comprises the steps: determining the second data path time delay between the corresponding ports of interconnected modules according to the first data path time delay of the corresponding port of each module and the interconnection relation information between the modules under the condition that a plurality of modules are in a target stable state, the interconnection module comprises two modules which are directly connected in the modules; and determining convergence information of the top time sequence of the interconnection modules according to the clock period, the trigger establishment time, the clock uncertainty, the clock skew between the interconnection modules and the second data path time delay. According to the method and the device, the time sequence between the interconnected modules can be quickly analyzed before the top-layer time sequence analysis is executed, and the time sequence analysis efficiency of the top layer of the chip is improved without waiting for all the modules to complete a physical implementation process.

The invention discloses an MEMS resonator low ripple error temperature measurement system based on voltage feedback compensation, and the system comprises a trans-impedance amplifier, an analog-to-digital converter, a frequency detection module, a PI controller, a variable gain amplifier, a Schmitt trigger, a first digital-to-analog converter, a biasing circuit, mode switches S1 and S2, and a voltage feedback compensation loop. The compensation loop comprises an amplitude detection module, a lookup table, a second digital-to-analog converter and an adder; the amplitude detection module receives the digital signal from the analog-to-digital converter and outputs a vibration amplitude signal in real time; the lookup table receives the vibration amplitude signal, inquires and outputs a corresponding digital compensation voltage, and converts the digital compensation voltage into an analog voltage through a second digital-to-analog converter; the adder adds the analog voltage and a fixed bias voltage to generate a dynamic bias voltage and applies the dynamic bias voltage to a drive electrode of the MEMS resonator. According to the system, an amplitude-driving end bias voltage feedback compensation loop is introduced, so that the periodic ripples of the resonant frequency are effectively suppressed.

The invention discloses a method for improving Buck light load efficiency, which can prevent pseudo CCM operation and can keep high light load efficiency even under a large duty ratio, and comprises the following steps: after soft start of a Buck converter is completed, an enable signal at the end of soft start sets an RS trigger U3 to be in an active state, and if an inductive current zero-cross detection trigger signal rises, the RS trigger U3 is in a non-active state, the RS trigger U3 is in a non-active state, and if the inductive current zero-cross detection trigger signal is in a non-active state, the RS trigger U3 is in a non-active state. When the high-end switch and the synchronous low-end switch are switched on, the setting end input of the RS trigger U3 is triggered, a switch starting signal output by the RS trigger U3 is set at the beginning of each switching period, the switch starting signal controls the constant on-time generator to modulate the charging current or capacitance so as to prolong the time of simultaneously switching off the high-end switch and the synchronous low-end switch, and when the synchronous low-end switch is switched on, the synchronous low-end switch is switched off. And the reset end of the RS trigger U3 inputs an output signal of the constant on-time generator to trigger the RS trigger U3 to reset.

Systems, methods, devices, and instrumentalities are described herein related to conditional triggers for flight path update indications. A wireless transmit / receive unit (WTRU) may receive configuration information. The configuration information may indicate a trigger condition (e.g., threshold) associated with enabling transmission of a flight path update indication. The WTRU may determine that the threshold associated with enabling transmission of the flight path update indication is satisfied. Based on the threshold being satisfied, the flight path update indication may be transmitted. The WTRU may receive a request to transmit the updated flight path information and transmit the updated flight path information.

The invention relates to the technical field of energy storage Internet of Things and digital twinning, in particular to a digital twinning model data processing method applied to the energy storage Internet of Things, which performs multi-modal data synchronous acquisition through a three-in-one sensor, optimizes storage management through a dynamic cache allocation mechanism, and improves the reliability of data acquisition through the three-in-one sensor. Micro short circuit and voltage unbalance detection is completed through high-frequency harmonic extraction and difference frequency voltage scanning, the event cross trigger establishes a bidirectional feedback mechanism, and the lightweight decision tree verifier outputs a fault code. According to the digital twinborn model data processing method applied to the energy storage Internet of Things, the early detection sensitivity of micro short circuit and voltage imbalance is high, outdated redundant calculation is avoided, parameter configuration is optimized through a periodic diagnosis report, different conditions are flexibly adapted, and support is provided for an intelligent health management system of energy storage equipment.

A flow control arrangement is provided including a housing seating inlet and outlet conduits is provided. An isolation valve is arranged within the housing and is fluidly coupled to the inlet conduit. A first flow switch with a first shutoff trigger is arranged within the housing and fluidly couples the isolation valve to the outlet conduit. A second flow switch with a second shutoff trigger is arranged outside of the housing and is fluidly separated from the first flow switch. A controller operably connects the first and second flow switches to the isolation valve to close the isolation valve when (a) flow rate of a first fluid traversing the first flow switch is greater than the first shutoff trigger, or (b) flow rate of a second fluid traversing the second flow switch is less than the second shutoff trigger. Semiconductor processing systems and flow control methods are also described.

The invention relates to the field of capacitor monitoring, and provides a capacitor quasi-online state monitoring method and system for a wind power converter, and the method comprises the steps: extracting a data slice comprising DC bus voltage, capacitor branch current, housing temperature and output power from a data buffer area; furthermore, output power data is utilized, intelligent screening is carried out through a quasi-steady-state slice trigger, and only effective data with the power average value large enough and the fluctuation small enough are reserved. And for the screened effective data slices, extracting the DC bus voltage and the capacitance branch current, and accurately identifying the voltage, current amplitude and phase information of the main harmonic through fast Fourier transform. Based on the key harmonic data, the complex impedance of the capacitor is calculated, and then the original ESR and capacitance estimation value are calculated. And finally, in combination with the capacitor shell temperature extracted from the same data slice, performing temperature compensation on the original parameters, and outputting a final result capable of truly reflecting the aging state of the capacitor.

Devices, systems, and methods are disclosed for customizing audio experiences associated with operation of a ridable device. An electronic device having a processor detects contextual information such as speed, acceleration, ambient noise level, environment type, or location of the ridable device. Sensor data from accelerometers, gyroscopes, microphones, cameras, or positioning systems may be processed to identify these conditions. Based on the detected context, the electronic device determines audio configuration parameters, including selection of audio content, adjustment of volume, blending of tracks, or modification of tempo or pitch. The determined parameters are applied to output audio through one or more speakers of the electronic device, the ridable device, or associated accessories. In some implementations, playback is synchronized with other riders using a common time reference, geo-fence triggers are employed to provide location-specific content, or warning sounds are generated when nearby objects are detected, enhancing both rider enjoyment and environmental awareness.

The invention discloses an ICPS comprehensive safety control system and method based on GCRA-Light GBM under D-ADETCS, and the system comprises a sampler which carries out the equal-period sampling of the measurement output data of a sensor; the self-adaptive discrete event trigger A is used for transmitting and screening the sampling values and transmitting the data meeting the data transmission condition A through the sensing side communication network; the data reconstruction restorer A is used for restoring system output data subjected to FDI attack on a sensing side, and the restored data is acted by a robust observer and a controller to obtain a control quantity; the self-adaptive discrete event trigger B is used for carrying out transmission screening on the control quantity and transmitting the control quantity meeting a data transmission condition B through an execution side communication network; and the data reconstruction restorer B is used for restoring the control data subjected to the FDI attack on the execution side, maintaining the restored control quantity by using a zero-order retainer, and acting on the controlled object through the executor to complete the integrated security control of the ICPS.

The invention relates to a SERDES channel control binding system and method. Various techniques are provided to configure serializer / deserializer (SerDes) channels in one or more SerDes tetrads into a configurable group using a bound link. A configuration register may configure the SerDes channels into a configurable group. A channel binding control module in each SerDes tetrad may link signals, including control signals, that travel within each configurable group. In order to synchronize the control signals, the channel binding control module may include: one or more flip-flops that introduce a fixed time delay for the control signals traveling between SerDes tetrads; and the tube level matching module introduces variable time delay to match the fixed time delay caused by the trigger. Once synchronized, the control signal reaches different SerDes channels in the configurable group at the same clock cycle.

The invention discloses an adaptive mode switching circuit of a BUCK converter for COT control. The adaptive mode switching circuit comprises a conduction time generation circuit, an OR gate, phase inverters INV1, INV2 and INV3, an NAND gate, an AND gate, RS triggers RS1 and RS2, transistors Mon, MN1, MN2 and MN3, a falling edge delay circuit, a rising edge delay circuit and a zero cross detection circuit. According to the invention, a conduction signal and a zero-cross detection signal are fed back to the conduction time generation circuit, the states of two paths of control signals in a DCM mode and a CCM mode are adaptively adjusted, logic operation is carried out on the control signals through an OR gate, and the conduction time of an upper tube is adaptively adjusted. When the DCM mode is switched to the CCM mode, the CCM control signal serves as a conduction time control signal, and the conduction time of an upper tube is increased; and when the CCM mode is switched to the DCM mode, the DCM control signal is used as a conduction time control signal, and the conduction time of the upper tube is reduced.

The invention provides a low-power-consumption feed-forward equalizer circuit which comprises a grouping processing module which divides tap values of tap coefficients of the feed-forward equalizer circuit into a plurality of groups, each group comprises a plurality of tap values, and a tap combination value needing to be processed by each lookup table module is calculated; the lookup table module is used for storing the tap combination value which is calculated in advance and performing lookup operation according to the bit combination of the input data to generate an intermediate result; the clock gating trigger module is used for enabling a signal tapdata to be equal to 1 when a tap value is updated, completing updating of the tap value output by a register DFF, and closing an input clock of the DFF when the tap value is kept unchanged and the tapdata is equal to 0; the shift accumulation module performs weight shift operation on the intermediate results output by the lookup table module and then accumulates the intermediate results to generate a plurality of groups of tap value processing results; and the result output module outputs a final equalization signal of the feed-forward equalizer circuit. The FFE circuit is realized by converting the multiplier into the LUT table and the adder, and the power consumption of the FFE circuit is greatly reduced while the signal processing performance of the FFE circuit is ensured.

Systems, computer-implemented methods, applications, and user interfaces for providing triggers in a system of record are disclosed. For example, a computer-implemented method may include: receiving, via a first interface for defining custom objects, a custom object definition; automatically generating, based on the custom object definition, one or more second interfaces for defining an automated workflow associated with the custom object; receiving, via the one or more second interfaces, an automated workflow comprising one or more conditions and one or more actions to be performed when the one or more conditions are satisfied; and executing the automated workflow responsive to determining that the one or more conditions are satisfied. The automated workflow can comprise at least one condition or action comprising a creation, read, update, or deletion of a data record associated with the custom object definition.

The invention provides a clock switching circuit, comprising: N clock switch modules, the N clock switch modules performing OR gate operation to obtain clock output; the N clock switch modules respectively and correspondingly input a first clock source to an Nth clock source; the clock switch module comprises a first trigger, a second trigger and a clock latch which are serially coupled in sequence; each clock switch module is correspondingly configured with one sub-synchronous reset module, and only two triggers are configured in one sub-synchronous reset module; and one clock switch module and one corresponding sub-synchronous reset module form a clock switch unit. According to the invention, four triggers are used in one clock switch unit, and the whole clock switching circuit only uses 4 * N triggers, so that the occupied area of the clock switching circuit is reduced; the clock switching circuit only comprises one stage of control logic, so that the delay required for completing clock switching is smaller. When clock switching is carried out, only the two clock sources before switching and after switching need to be enabled, and the unused clock sources can be closed to reduce power consumption.

A wireless transmit / receive unit (WTRU) may send assistance information to a network element. The assistance information may indicate that the WTRU can use sensor data for mobility. The WTRU may receive conditional PSCell change (CPC) configuration information, for example from the network element. The CPC configuration information may include one or more of a CPC candidate for device mobility, a CPC candidate for external mobility, and / or a trigger for performing CPC based on the assistance information. The WTRU may perform a CPC, for example based on a cell quality of a serving cell being below a threshold. The WTRU may determine whether to use the CPC candidate for device mobility and / or the CPC candidate for external mobility based on the sensor data and the trigger, for example to perform the CPC.

The invention discloses a clock synchronization system. The clock synchronization system comprises a trigger group and a frequency divider group, the trigger group comprises N triggers, and the frequency divider group comprises N frequency dividers; the trigger group receives N paths of clock signals and one path of SYNC pulse signal, the N paths of clock signals are respectively transmitted to the N frequency dividers, and the N paths of pulse signals output by the trigger group are respectively transmitted to the N frequency dividers, N is a positive integer greater than 1, through the technical scheme of the invention, the risk of generating a metastable state can be reduced, and the power consumption can be reduced at the same time.

The invention discloses a standard cell library delay test system and a test method thereof, the test system comprises a primary pulse generator, the clock input end of the primary pulse generator receives a test enable signal and generates a start pulse signal; the clock input end of each stage of trigger is connected to the output end of the previous stage of trigger, and the clock input end of the first stage of trigger receives an operation result of a starting pulse signal and an output signal of the last stage of trigger through a logic OR gate; the test system further comprises a feedback control module including a first phase inverter and a logic AND gate, the first phase inverter negates an output signal of any one trigger in the first three stages of the delay chain and then performs logic AND operation with a global reset signal, and a dynamic reset signal is generated and connected to the reset end of the primary pulse generator. According to the technical scheme, the trigger delay chains connected in series in multiple stages and the feedback control module are designed, an additional reference clock path is not needed, and the circuit area is reduced.

The present invention relates to a wearable safety device 99 comprising: a device body 1 adapted to be secured to a user; a local alert system comprising at least one light source 65 and an audible alarm 35; an electronic control unit 51 comprising an alarm trigger and being configured to control the local alert system, wherein the electronic control unit is configured to continuously or repeatedly activate the light source to provide a visual alert, and wherein the electronic control unit is configured, upon actuation of the alarm trigger, to activate the audible alarm. The present invention also relates to a system comprising: a wearable safety device as aforementioned; and a software application for a user device, preferably a smartphone, wherein the software application is configured to broadcast an alert signal: based on a comparison between a planned route input by a user to the software application and data relating to the location of the user device; and / or upon actuation of the alarm trigger.

A flip-flop circuit includes a first memory circuit and a second memory circuit. The flip-flop circuit can be configured to store a first value of the data signal in the first storage circuit in response to a rising edge of the clock signal and a second value of the data signal in the second storage circuit in response to a falling edge of the clock signal during a double edge trigger mode. The flip-flop circuit can be configured to store a third value of the data signal in the first storage circuit and output the third value from the first storage circuit in response to the clock signal during the single-edge trigger mode.

The embodiment of the invention provides a task execution method and device, equipment and a storage medium. The method comprises the steps that a trigger corresponding to an event is determined from at least one pre-configured trigger in response to the fact that the event related to a task occurs, and the at least one trigger is used for triggering calling of an intelligent agent based on a machine learning model; determining agent configuration information for executing the task based on the determined configuration item of the trigger; and executing the task by using the agent based on the agent configuration information and the context information of the event.

A communication apparatus for wirelessly communicating with another communication apparatus, comprising: a transmission unit configured to transmit, to the other communication apparatus, a trigger frame used as a trigger to instruct the other communication apparatus to execute data transmission in a multi-link, wherein the trigger frame includes identification information for identifying another link different from a link in which the trigger frame is transmitted in the multi-link.