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2 results about "Modular exponentiation" patented technology
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Modular exponentiation is a type of exponentiation performed over a modulus. It is useful in computer science, especially in the field of public-key cryptography. The operation of modular exponentiation calculates the remainder when an integer b (the base) raised to the eth power (the exponent), b, is divided by a positive integer m (the modulus). In symbols, given base b, exponent e, and modulus m, the modular exponentiation c is: c = b mod m. From the definition of c, it follows that 0 ≤ c < m.
A public key algorithm reconfigurable circuit
This invention discloses a reconfigurable circuit for public-key cryptography algorithms. This circuit combines coarse / sub-coarse-grained reconfigurable circuits with microcontroller circuits. The sub-coarse-grained reconfigurable unit array employs a reconfigurable multiplier array from a multi-level reconfigurable NTT circuit to support NTT's underlying modular arithmetic. The coarse-grained reconfigurable units, through parameter configuration and data interconnection configuration, are used to implement large integer modular exponentiation and elliptic curve scalar multiplication. Based on the novel multi-level reconfigurable NTT circuit provided in this invention, quantum-resistant cryptographic algorithms can be implemented while also supporting traditional public-key cryptographic algorithms, thus offering advantages such as a small algorithm engine area and high flexibility.
Owner:FUDAN UNIVERSITY
Memory-efficient cryptographic computations in secure communications
PCT designated stageWO2026117674A1Public key for secure communicationDigital data protectionComputer hardwareSecure communication
A computer-implemented method enhances the efficiency and security of cryptographic tasks for modular exponentiation, digital signatures, key generation, and blockchain transaction verification. The method includes receiving a cryptographic task, retrieving a set of operands from memory, decomposing them into smaller parameters to construct multiple cryptographic sub- tasks, allocating non-overlapping memory regions for each sub-task and processes them in parallel. For each sub-task, a pair of variables is initiated in memory, followed by a bit-by-bit iteration through one of the parameters. During this iteration, the variables are updated based on each bit value. Once the iteration is complete, the value of the first variable is stored as an intermediate result in the corresponding memory region. Upon completing all parallel sub-tasks, the device aggregates the intermediate results to produce the final output of the cryptographic task, which is then used to generate verification data for secure communication.
Owner:CROSSBAR INC