6 results about "Modular exponentiation" patented technology

A numerical conversion method for a public key cryptography system includes accumulating a first value by using a first modular addition loop according to the first value for generating a second value after a first predetermined loop count is reached, accumulating the second value by using a second modular addition loop according to the second value for generating a third value after a second predetermined loop count is reached, inputting the third value to a Montgomery modular exponentiation function for generating a Montgomery conversion parameter, and converting a first conversion value in an integer domain into a second conversion value in a Montgomery domain.

The invention provides an anti-side channel attack decryption method and a multi-core system, and the technical scheme of the invention is that a private key at a fixed position in a Paillier algorithm is split into two types of key pairs based on a random number, and the method comprises the steps: splitting an index in the private key into a first private index and a second private index according to the random number, and splitting a coefficient in the private key into a first private coefficient and a second private coefficient according to the random number. And decryption is carried out according to the two secret key pairs obtained dynamically before each time of decryption, so that each time of modular exponentiation and modular multiplication does not have a fixed item, an attacker is difficult to obtain a fixed feature through side channel attack to capture the private key, and the protection effect on the side channel attack can be improved.

This invention discloses a reconfigurable circuit for public-key cryptography algorithms. This circuit combines coarse / sub-coarse-grained reconfigurable circuits with microcontroller circuits. The sub-coarse-grained reconfigurable unit array employs a reconfigurable multiplier array from a multi-level reconfigurable NTT circuit to support NTT's underlying modular arithmetic. The coarse-grained reconfigurable units, through parameter configuration and data interconnection configuration, are used to implement large integer modular exponentiation and elliptic curve scalar multiplication. Based on the novel multi-level reconfigurable NTT circuit provided in this invention, quantum-resistant cryptographic algorithms can be implemented while also supporting traditional public-key cryptographic algorithms, thus offering advantages such as a small algorithm engine area and high flexibility.

The invention relates to the technical field of cryptography hardware acceleration, in particular to a Paillier hardware accelerator based on a distributed multi-core pipeline. The Paillier hardware accelerator comprises a distributed hierarchical multi-core hardware architecture and a Paillier encryption and decryption algorithm executed in the Paillier hardware accelerator, and the distributed hierarchical multi-core hardware architecture splits an encryption and decryption data stream into an assembly line sequentially executed by a pre-processing unit, a distributed modular exponentiation core and a post-processing unit. The modular exponentiation operation of the encryption process of the Paillier encryption and decryption algorithm is converted into modular multiplication and modular addition operation through a simplification mode based on the binomial theorem, so that the encryption and decryption process is adapted to a parallel mechanism of high-digit modular multiplier hardware resource multiplexing and assembly lines in the distributed hierarchical multi-core hardware architecture. The problems of low hardware resource utilization rate, difficulty in time sequence convergence and the like in the prior art are solved, and the performance and the flexibility are remarkably improved.

The invention discloses a digital signature method and terminal equipment, and relates to the technical field of information security, the digital signature method comprises the following steps: executing system parameter determination and key generation operation through a digital signature system, and distributing system parameters and keys; the sending end obtains a to-be-signed message, carries out signature result generation operation, and sends a signature result and the to-be-signed message to the receiving end; and the receiving end executes signature verification judgment operation, outputs a verification result of the to-be-signed message, and sends a retransmission request to the sending end if judging that the to-be-signed message is wrong. According to the method, a random number, a hash function and a linear signature equation are used, confidentiality and randomness of a private key and signature parameters are ensured, the signature length of a signature result is shorter than that of a traditional scheme, the real-time performance of data transmission is improved, arithmetic operation and modular exponentiation operation are mainly adopted as core operation in the signature verification process, complex calculation is avoided, and the signature verification efficiency is improved. And the operation efficiency in a scene in which a large number of digital signature transactions need to be processed is improved.

A computer-implemented method enhances the efficiency and security of cryptographic tasks for modular exponentiation, digital signatures, key generation, and blockchain transaction verification. The method includes receiving a cryptographic task, retrieving a set of operands from memory, decomposing them into smaller parameters to construct multiple cryptographic sub- tasks, allocating non-overlapping memory regions for each sub-task and processes them in parallel. For each sub-task, a pair of variables is initiated in memory, followed by a bit-by-bit iteration through one of the parameters. During this iteration, the variables are updated based on each bit value. Once the iteration is complete, the value of the first variable is stored as an intermediate result in the corresponding memory region. Upon completing all parallel sub-tasks, the device aggregates the intermediate results to produce the final output of the cryptographic task, which is then used to generate verification data for secure communication.