227 results about "Status register" patented technology

The invention provides a DCU-based high-performance sparse stiffness matrix vector multiplication method, which comprises the following steps of: according to a sparse stiffness matrix, dividing a non-zero element into a plurality of calculation unit blocks by rows, pre-loading non-zero element data to an L1 shared memory or a register file through an on-chip shared memory controller of the DCU, a high-bandwidth crossbar switch of the DCU is used for realizing data copying and transmission; starting multi-row fusion execution for a short row of which the row non-zero element is lower than a DCU single-instruction multi-data width threshold value; constructing a wavefront scheduler based on a DCU asynchronous computing engine: binding an independent instruction cache region for each wavefront, and loading a multiply-add operation instruction set in advance through a prefetch instruction queue; a calculation unit state register is established, and when a wavefront scheduler ready signal is triggered, a scalar unit of the DCU is activated to execute calculation; and realizing cross-thread block reduction by adopting a DCU atomic operation accelerator. According to the method, the calculation throughput and the memory bandwidth utilization rate of large-scale structural mechanics stiffness matrix vector multiplication are effectively improved.

The invention provides an SIMT-based neural network processor and a task execution method thereof, and the method comprises the steps that a general processor queries a state register of a coprocessor, and the state register stores the resource condition of the coprocessor; the universal processor completes splitting from a thread block to a thread bundle according to the resource condition, and the universal processor forwards a thread bundle instruction to a thread bundle distributor of the coprocessor; and the thread beam distributor decodes instructions in the thread beams in sequence and schedules the instructions to instruction queues of different calculation cores, and the thread beams sequentially perform thread beam scheduling, instruction emission and instruction execution according to the sequence, so that all calculations of a neural network task are completed in parallel, and a running result of the neural network task is obtained. According to the method, a general processor for task splitting is introduced in front of the thread beam scheduler or a specific compiler is directly used, so that dynamic scheduling of the threads can be realized, and a scheme for dynamically expanding the number of the threads according to data precision becomes a feasible architecture option.

The invention belongs to the field of many-core processor design, and particularly relates to a many-core processor system based on a data flow framework and a task scheduling method.The system comprises a system control node, computing nodes and storage nodes which are connected through an on-chip internet, and each storage node and at least one computing node form a computing cluster; the system control node sends an instruction and data to the storage node through the on-chip internet, and the storage node distributes the data to the computing nodes in the computing cluster; an initialization unit of the computing node monitors a data buffer area of the on-chip internet through a state register, data are moved to a buffer unit, and initialization of a computing core is completed; the scheduling unit is responsible for scheduling a task queue, and transferring data required by a next task to the cache unit in advance through the DMA unit to realize parallel calculation and data transferring; the computing unit executes the computing task, and the data directly flows among different computing nodes, so that the memory access requirement is reduced, and the computing resource utilization rate is improved.

The invention discloses a CAN message priority dynamic arbitration method and system based on event triggering, and the method comprises the steps: obtaining a discrete sampling signal of a CAN node of an engineering vehicle and a state register value of a CAN controller, converting the discrete sampling signal into a working condition data sequence, and obtaining a bus load rate through the state register value; obtaining an event state sequence according to the working condition data sequence; all CAN messages to be sent are constructed into a message data record, and the message data record with event semantics and dynamic priority labels is obtained according to the protocol data unit and the event state sequence; and according to the bus load rate and the event state sequence, sending a message data record with event semantics and dynamic priority annotations by adopting a token bucket mechanism through a three-level priority queue linked with a three-state state machine. According to the invention, the security key message in the system can still be transmitted in time under high load, and the bandwidth occupation and delay jitter caused by the low-priority message are avoided at the same time.

The invention discloses a notch position blade profile tolerance point taking device, system and method, and the method comprises the steps: enabling an actual measurement point cloud to be aligned with a theoretical model through progressive spatial registration, carrying out the initial coarse registration, and dynamically adjusting a root mean square error threshold value and a curvature change rate threshold value based on curvature sensitivity analysis, so as to achieve the self-adaptive segmented interruption control; a three-dimensional Hash mapping engine is constructed to store original point cloud data, an incremental data access mode and an iterative data structure are combined, a historical transformation matrix stack, a B spline control point and an 8-bit state register are included, and data processing integrity and high efficiency are ensured; a genetic algorithm is adopted to optimize segmented B-spline surface fitting, and contours of an air inlet edge and an air outlet edge are synchronously optimized through transverse segmentation and longitudinal segmentation; and finally, composite convergence verification is passed. According to the method, through dynamic threshold regulation and control and a hybrid optimization strategy, the detection precision and the calculation efficiency of the complex curved surface are remarkably improved.

The invention discloses a sparse polynomial multiplication accelerator circuit applied to an HQC algorithm, and belongs to the field of post quantum cryptography algorithm hardware acceleration. Comprising a sparse polynomial non-zero coefficient index register set, a state register set, a multiplication and addition unit, a control state machine and an address generation module. The sparse polynomial non-zero coefficient index register set is used for storing indexes of sparse polynomial non-zero coefficients and providing the indexes for the control state machine, and the control state machine further inputs the obtained indexes to the address generation module; the state register group is used for configuring and representing the working state of the accelerator, storing information of registers and providing information for the address generation module and the control state machine; the address generation module is used for calculating address information and feeding back a result to the control state machine; and the control state machine reads the coefficient of the dense polynomial from the external RAM and inputs the coefficient into the multiplication and addition unit for calculation, and after the multiplication and addition unit completes calculation, the control state machine writes a calculation result into the external RAM.

The invention discloses a task allocation method, device and equipment and a readable storage medium, and the method comprises the steps: obtaining a to-be-processed task from a global task pool, and analyzing a descriptor of the to-be-processed task to obtain priority information and / or dependency information; determining a processing sequence of the to-be-processed tasks by utilizing the priority information and / or the dependency relationship information; obtaining channel load information from a state register for directly accessing the corresponding channel from the memory; and selecting a target channel from the channels by utilizing the channel load information and combining a load balancing strategy, and distributing the to-be-processed tasks to the target channel according to the processing sequence. According to the task allocation method and device, during task allocation, based on at least one of the priority information and the dependency relationship information and the channel load information, load balancing can be dynamically achieved, at least one of the priority and the dependency relationship of the task can be considered, and therefore the reliability of task processing is guaranteed, and the task allocation efficiency is improved. And different task scheduling requirements can be dynamically met.

The invention discloses an embedded SoC-level real-time monitoring and analyzing device. The embedded SoC-level real-time monitoring and analyzing device is composed of a bus comparator, a system event counter and a control register set. The bus comparator collects access signals of an address bus, a data bus and an instruction bus in real time, compares the access signals with a preset matching rule, generates a trigger signal for driving the event state register to record and output an interrupt signal or a debugging signal during matching, and takes the trigger signal as an input event of the system event counter; the system event counter monitors various events generated in the operation process, and when the monitoring result is equal to a preset reference value, a trigger signal is generated; and the control register group configures the matching condition of the bus comparator, sets the counting mode of the system event counter, and reads the comparison state, the event counting result and related monitoring information through the bus interface. According to the method, a configurable event capture mechanism and multiple counting modes are introduced in a hardware level, so that the dependence on software debugging is reduced, and the real-time performance of monitoring and analysis is improved.

The invention relates to the technical field of chip packaging, in particular to a PCIe (peripheral component interface express) equipment function number border crossing prevention method supporting ARI (automatic repeat interface). The hardware layer protection process is as follows: S1-1, hot plugging; s1-2, if it is detected that the equipment declarates to support ARI, the PCIe controller hardware circuit immediately sets an equipment number register to zero; s1-3, only allowing the PCIe controller of the system to read the configuration space unidirectionally during the low level period of the reset signal PERST #; the interception process of the driving layer is as follows: S2-1, in an equipment enumeration stage, an operating system drives to dynamically read an ARI capability register; s2-2, if the equipment declarates to support ARI, forcing an equipment number register to be equal to 0, and releasing an original equipment number bit space for function number expansion; s2-3, border crossing access is blocked; and S2-4, synchronizing the state register. Compared with the prior art, correctness of device function numbers is guaranteed through two dimensions of hardware register state solidification and driver layer access truncation, and'perception-free 'fault tolerance of the PCIe device under ARI / traditional mode switching is achieved for the first time.

A hardware accelerator includes accelerator processing circuitry to perform a delegated task on behalf of a processor; a control interface circuit to exchange control signals with the processor to configure the accelerator processing circuit to perform the delegated task; a fault state register storage device for storing fault state information, the fault state register storage device being readable by the processor based on an accelerator register read request received from the processor via the control interface circuit; and a control circuit to: detect a failure indication received from the processor via the control interface circuit, the failure indication indicating that a failure accelerator triggered memory access request issued to the processor via the control interface circuit and specifying a target virtual address has encountered an address translation failure; and in response to detecting the fault indication, setting fault state information in the fault state register storage device to indicate information about a memory access request triggered by the fault accelerator encountering the address translation fault.

A hardware accelerator comprises accelerator processing circuitry to perform a delegated task on behalf of a processor; control interface circuitry to exchange control signals with the processor to configure the accelerator processing circuitry to perform the delegated task; fault status register storage to store fault status information, the fault status register storage being readable by the processor based on an accelerator register read request received from the processor via the control interface circuitry; and control circuitry to: detect a fault indication received from the processor via the control interface circuitry indicating that a faulting accelerator-triggered memory access request, issued via the control interface circuitry to the processor and specifying a target virtual address, has encountered an address translation fault; and in response to detecting the fault indication, set fault status information in the fault status register storage to indicate information about the faulting accelerator-triggered memory access request that encountered the address translation fault.

Computer-implemented methods and associated hardware for static trusted execution environment for inter-architecture processor program compatibility are disclosed herein. A device (e.g., a Reduced Instruction Set Computing-Five (RISC-V) device), may emulate a static trusted execution environment (e.g., ARM TrustZone) using physical memory protection (PMP). A regular world may have access to only a portion of an address space of the device, while a secure world may have access to the full address space. A secure world identifier (SWID) may be stored in a configuration status register (CSR) only accessible by a mode (e.g., machine mode). When an entry is added to a translation lookaside buffer (TLB), the SWID may be added as part of a tag to differentiate secure world entries from regular world entries.

Providing media power telemetry for virtual machines (VMs) in processor-based devices is disclosed herein. In one exemplary embodiment, a processor-based device provides a controller circuit comprising a power telemetry circuit, and a power management processor. The power telemetry circuit is configured to determine whether a media access request corresponding to a power telemetry event and directed to a media device is detected, and determine whether the media access request matches an event selection filter specified by an event selection control and status register (CSR) corresponding to the power telemetry event. If so, the power telemetry circuit increments a power telemetry counter corresponding to the power telemetry event by a relative power value associated with a media access request type of the media access request. The power management processor determines a power management operation based on the power telemetry counter corresponding to the power telemetry event, and applies the power management operation.

The invention discloses a verification method for a translation lookaside buffer failure instruction, electronic equipment and a computer program product, and is applied to the technical field of memory management of a computer system. A target instruction is inserted and triggered, and the target instruction comprises a TLB failure instruction for the to-be-failed entry; a translation request carrying a target virtual address is sent to a target object, a first translation condition in the process that the target object processes the translation request is obtained, and the target object comprises a translation cache unit or a translation control unit; the target virtual address comprises a virtual address corresponding to the item to be invalid; and determining whether the to-be-invalid item is invalid or not based on the first translation condition. Compared with a mode of verifying the TLB failure instruction by means of a TLB state register, the method is undoubtedly more direct and accurate, and the verification result has higher reliability.

The invention discloses a solid state disk key storage method and system and a storage medium, and belongs to the technical field of solid state disks. The method comprises the steps that a CPU component controls an SM4 component to generate a required medium key, and the medium key is temporarily stored in a register which cannot be read and written by the CPU component in the SM4 component; performing programming operation on the eFlash component through the eFlash controller component, and storing the medium key in an address specified by the key updating area; when the SM4 component detects that a programming operation completion indication signal is in a high level and key programming is successful, the SM4 component resets a medium key temporarily stored in the SM4 component and sets a key programming completion state register and a key programming success state register to be in a high level; and the CPU component performs storage verification, and when the CPU component queries that the secret key programming completion state register and the secret key programming success state register of the SM4 component are both high levels, secret key storage is completed. According to the invention, the medium key and the digital certificate cannot be stored out of the main control chip, so that the security is higher, and the key updating times are not limited.

A processor includes a register file and an execution unit. The execution unit includes a hash circuit including at least a state register, a state update circuit coupled to the state register, and a control circuit. Based on a hash instruction, the hash circuit receives from the register file and buffers within the state register a current state of a message being hashed. The state update circuit performs state update function on contents of the state register, where performing the state update function includes performing a plurality of iterative rounds of processing on contents of the state register and returning a result of each of the plurality of iterative rounds of processing to the state register. Following completion of all of the plurality of iterative rounds of processing, the execution unit stores contents of the state register to the register file as an updated state of the message.

Certain aspects of the present disclosure provide techniques for hardware-based saving and restoring of architecture state information for processing elements (PEs). According to certain aspects, the techniques involve triggering, via at least a first circuit element, saving of architecture state information of at least one processing element (PE) to at least one memory prior to the at least one PE transitioning from a first state to a second state; re-routing, via at least a second circuit element, requests to access the state registers to the architecture state RAM, while the at least one PE is in the second state; and triggering, via the first circuit element, restoration of the architecture state information from the at least one memory to the at least one PE prior to the at least one PE transitioning from the second state to the first state.

The invention relates to a remote stable upgrading method for FPGA firmware, belongs to the technical field of integrated circuits, and solves the problems of low efficiency, high hardware damage risk, poor universality and the like of the existing upgrading scheme. The method comprises the following steps that: an upper computer establishes connection with an FPGA (Field Programmable Gate Array) through a communication interface, and the FPGA enters a communication ready state; a built-in FLASH control module of the FPGA executes an erasing operation on a target storage area of the FLASH memory according to an erasing instruction sent by the upper computer, and the FPGA continuously reads and reports real-time state information of the state register to the upper computer during an erasing period; writing a to-be-upgraded firmware program package into the target area, and powering off and restarting the FPGA; and the restarted FPGA runs the new firmware program written into the target storage area. According to the method, the upgrading efficiency can be improved, the hardware damage risk is reduced, the upgrading cost is reduced, and the universality of the scheme is improved so as to adapt to FPGAs of different types and brands.

The invention discloses a part power-on and power-off state monitoring method, device and equipment and a storage medium, and relates to the technical field of storage, and the method comprises the steps: capturing the power-on and power-off state information of parts in each slot through a hardware interface and a software driver, achieving the real-time full-amount obtaining of the power-on and power-off state information of all slot parts, and improving the reliability of the part power-on and power-off state information. Accurate event recording of the power-on and power-off state of each component is realized by storing the obtained power-on and power-off state information of each component to the preset component power state register. The dynamic rule engine is utilized to automatically perform component anomaly detection, so that the manual inspection frequency is reduced, and the abnormal component can be quickly positioned. The technical problems that the power-on and power-off states of the components in the system cluster cannot be comprehensively mastered, the fault source is difficult to trace, and false alarm or missing alarm is caused are solved, and the technical effects that the power-on and power-off state information of all the slot position components can be fully obtained, accurate event recording of the power-on and power-off states of all the components is achieved, and abnormal components can be rapidly positioned are achieved.

An integrated circuit (IC) device includes a plurality of chiplets including a first device and a second device. A die-to-die (D2D) interconnect link connects between the first device and the second device. A link training and status state machine (LTSSM) of the IC device is configured to operate the degraded D2D interconnect link in a resilient link mode to provide a plurality of enabled lanes and a plurality of disabled lanes. The LTSSM detects a faulty lane among the plurality of enabled lanes, and replaces the faulty lane using a functional lane from the plurality of disabled lanes to maintain the degraded D2D interconnect link.

An apparatus comprises exception return state register storage, and processing circuitry. In response to a guarded control stack (GCS) exception return state push instruction, the processing circuitry obtains exception return state information from the exception return state register storage and push the state information to a GCS data structure. In response to a GCS exception return state pop instruction, the processing circuitry obtains GCS-protected exception return state information from the GCS data structure. In at least one operating state, the processing circuitry detects, in response to an attempt to modify the exception return state information stored in the exception return state register storage, whether an exception return state lock parameter is in a locked state or an unlocked state, and signals a fault when it is in the locked state.

The invention discloses a data handling method and device, a chip, a storage medium and electronic equipment. The data handling method comprises the following steps: in response to a direct memory access controller, receiving a data handling trigger signal from a data node, and handling data between the direct memory access controller and the data node; counting the total data volume of the carried data; and in response to detecting that the receiving state of the direct memory access controller on the data transfer trigger signal is an abnormal state before the total data volume reaches the predetermined data volume, executing a data transfer ending operation. According to the embodiment of the invention, the direct memory access controller is prevented from being in a waiting state all the time, and the central processing unit does not need to continuously poll a state register in the direct memory access controller, so that the overhead of the central processing unit is reduced.

According to the PCIe interface implementation method and device for FPGA high-speed data transmission, a direct memory access mechanism is innovatively designed, and safe and efficient transmission of data is achieved through physical continuous cache region registration and descriptor queue management. A data block organization strategy based on a timestamp is constructed, and a reliable data transmission control system is established in combination with a burst transmission channel and a state tracker. A state register and an interrupt mechanism are introduced, and the integrity and information security of the transmission process are ensured through real-time state monitoring and data synchronization. According to the method, data security is protected, meanwhile, the defects of the traditional technology in the aspects of transmission efficiency, data management, state monitoring and the like are effectively overcome, and the performance and reliability of the PCIe interface are remarkably improved.

System and methods for automatically generating control / status registers (CSR) based on configurations of components in a Network on Chip (NoC) include generating at least one repeatable field group from a plurality of defined fields, each of the plurality of defined fields defining portions of a register and NoC connectivity, generating at least one repeatable multi-register from the at least one repeatable field group, and generating at least one CSR group from the at least one repeatable multi-register, the at least one CSR group generated to be incorporated into a CSR bank. Such systems and methods of generating CSRs provides flexibility for designers / users to optimize the NoC for area consumption, reducing cost and complexity, parameterize configurations of the CSRs, and the like.

The invention discloses a superconducting quantum bit measurement and control waveform real-time generation method, system and equipment, and relates to the technical field of quantum computing, a waveform envelope signal with variable amplitude is read from an envelope memory based on an envelope parameter, a synchronous controller triggers a state register of a finite-state machine to be kept or idle according to a keeping instruction, and the state register of the finite-state machine is kept or idle; outputting a waveform envelope signal with constant amplitude or recovering an idle state; the frequency control word and the phase control word cached by the synchronous controller are loaded into a digital carrier generator, a digital phase signal is synthesized through a phase generation module, and spline interpolation calculation is performed on a cosine function by using a coefficient obtained by looking up a table through the digital phase signal, so that an orthogonal carrier signal is generated; all the waveform envelope signals and the carrier signals are fed back to a modulator to be added and multiplied, and a final measurement and control waveform is generated; the measurement and control waveform real-time generation method can quickly and accurately respond to dynamic adjustment of multiple parameters of the measurement and control waveform by a quantum calculation line.

The invention provides a UCIe-based fault diagnosis and debugging method, a computer readable storage medium and an artificial intelligence chip, and relates to the technical field of chips. The UCIe-based fault diagnosis and debugging method comprises the following steps: carrying out link training between a first core particle and a second core particle; when a state execution error occurs, enabling a first pause state register of the first core particle to stop state jump of the first core particle; enabling a first bypass register of the first core particle to configure a first correction signal stored in the first bypass register; and disabling the first pause state register of the first core particle to continue the state jump of the first core particle. According to the UCIe-based fault diagnosis and debugging method, the computer readable storage medium and the artificial intelligence chip, effective chip debugging and fault diagnosis can be realized, and the post-silicon debugging efficiency can be improved.

The present application relates to an instruction buffer for a nested loop, and a processor. The processor comprises an instruction dispatch unit, a control status register, and a processing engine. The instruction buffer for a nested loop is configured to: acquire an instruction from the instruction dispatch unit; decode the instruction to acquire one or more total loop count indices respectively associated with one or more nested loops in the instruction; acquire from the control status register one or more total loop counts respectively associated with the one or more total loop count indices; and on the basis of the one or more total loop counts respectively associated with the one or more total loop count indices, send the one or more nested loops to the processing engine.

Computer-implemented methods and associated hardware for static trusted execution environment for inter-architecture processor program compatibility are disclosed herein. A device (e.g., RISC-V), may emulate a static trusted execution environment (e.g., ARM TrustZone) using physical memory protection (PMP). A regular world may have access to only a portion of an address space of the device, while a secure world may have access to the full address space. A secure world identifier (SWID) may be a configuration status register (CSR) only accessible by a mode (e.g., machine mode). When an entry is added to a translation lookaside buffer (TLB), the SWID may be added as part of a tag to differentiate secure world entries from regular world entries.

Methods and apparatus to reduce register access latency in split-die SoC designs. The method is implemented on a platform including a legacy socket and one or more non-legacy (NL) sockets comprising split-die System-on-Chips (SoC)s including multiple dielets interconnected with a plurality of Embedded Multi-Die Interconnect Bridges (EMIBs). The dielets include core dielets having cores, cache controllers and memory controllers. The method provides an affinity between a control and status registers (CSRs) memory range for the NL sockets such that CSRs in the memory controllers for multiple core dielets are programmed using transactions forwarded along core-to-cache controller datapaths that avoid crossing EMIBs. In one aspect, a transient map of address ranges is created that includes a respective Sub-NUMA Cluster (SNC) range allocated for the NL sockets, with a range of CSR addresses for accessing CSRs in the memory controllers for the NL sockets being stored in the respective SNC ranges.

A processor includes an instruction decoder configured to provide at least a floating point instruction control signal; performing floating point calculation on a data path; a floating point custom instruction control logic block coupled to the floating point compute data path; a control and status register coupled to the floating point computational data path and the floating point custom instruction control logic block; a first multiplexer configured to provide a floating-point instruction control signal or a custom instruction control signal to the floating-point computational data path based on a state of a selection control signal; and a second multiplexer configured to provide a floating point operand or a custom operand to the floating point computing data path based on a state of the selection control signal. The floating point custom instruction control logic block asserts a select signal while directing the floating point computational data path to assist it in executing custom instructions. The custom instruction may be a floating point exponential function.