151 results about "Status register" patented technology

The invention discloses a CAN message priority dynamic arbitration method and system based on event triggering, and the method comprises the steps: obtaining a discrete sampling signal of a CAN node of an engineering vehicle and a state register value of a CAN controller, converting the discrete sampling signal into a working condition data sequence, and obtaining a bus load rate through the state register value; obtaining an event state sequence according to the working condition data sequence; all CAN messages to be sent are constructed into a message data record, and the message data record with event semantics and dynamic priority labels is obtained according to the protocol data unit and the event state sequence; and according to the bus load rate and the event state sequence, sending a message data record with event semantics and dynamic priority annotations by adopting a token bucket mechanism through a three-level priority queue linked with a three-state state machine. According to the invention, the security key message in the system can still be transmitted in time under high load, and the bandwidth occupation and delay jitter caused by the low-priority message are avoided at the same time.

The invention discloses a task allocation method, device and equipment and a readable storage medium, and the method comprises the steps: obtaining a to-be-processed task from a global task pool, and analyzing a descriptor of the to-be-processed task to obtain priority information and / or dependency information; determining a processing sequence of the to-be-processed tasks by utilizing the priority information and / or the dependency relationship information; obtaining channel load information from a state register for directly accessing the corresponding channel from the memory; and selecting a target channel from the channels by utilizing the channel load information and combining a load balancing strategy, and distributing the to-be-processed tasks to the target channel according to the processing sequence. According to the task allocation method and device, during task allocation, based on at least one of the priority information and the dependency relationship information and the channel load information, load balancing can be dynamically achieved, at least one of the priority and the dependency relationship of the task can be considered, and therefore the reliability of task processing is guaranteed, and the task allocation efficiency is improved. And different task scheduling requirements can be dynamically met.

The invention discloses an embedded SoC-level real-time monitoring and analyzing device. The embedded SoC-level real-time monitoring and analyzing device is composed of a bus comparator, a system event counter and a control register set. The bus comparator collects access signals of an address bus, a data bus and an instruction bus in real time, compares the access signals with a preset matching rule, generates a trigger signal for driving the event state register to record and output an interrupt signal or a debugging signal during matching, and takes the trigger signal as an input event of the system event counter; the system event counter monitors various events generated in the operation process, and when the monitoring result is equal to a preset reference value, a trigger signal is generated; and the control register group configures the matching condition of the bus comparator, sets the counting mode of the system event counter, and reads the comparison state, the event counting result and related monitoring information through the bus interface. According to the method, a configurable event capture mechanism and multiple counting modes are introduced in a hardware level, so that the dependence on software debugging is reduced, and the real-time performance of monitoring and analysis is improved.

The invention relates to the technical field of chip packaging, in particular to a PCIe (peripheral component interface express) equipment function number border crossing prevention method supporting ARI (automatic repeat interface). The hardware layer protection process is as follows: S1-1, hot plugging; s1-2, if it is detected that the equipment declarates to support ARI, the PCIe controller hardware circuit immediately sets an equipment number register to zero; s1-3, only allowing the PCIe controller of the system to read the configuration space unidirectionally during the low level period of the reset signal PERST #; the interception process of the driving layer is as follows: S2-1, in an equipment enumeration stage, an operating system drives to dynamically read an ARI capability register; s2-2, if the equipment declarates to support ARI, forcing an equipment number register to be equal to 0, and releasing an original equipment number bit space for function number expansion; s2-3, border crossing access is blocked; and S2-4, synchronizing the state register. Compared with the prior art, correctness of device function numbers is guaranteed through two dimensions of hardware register state solidification and driver layer access truncation, and'perception-free 'fault tolerance of the PCIe device under ARI / traditional mode switching is achieved for the first time.

A hardware accelerator includes accelerator processing circuitry to perform a delegated task on behalf of a processor; a control interface circuit to exchange control signals with the processor to configure the accelerator processing circuit to perform the delegated task; a fault state register storage device for storing fault state information, the fault state register storage device being readable by the processor based on an accelerator register read request received from the processor via the control interface circuit; and a control circuit to: detect a failure indication received from the processor via the control interface circuit, the failure indication indicating that a failure accelerator triggered memory access request issued to the processor via the control interface circuit and specifying a target virtual address has encountered an address translation failure; and in response to detecting the fault indication, setting fault state information in the fault state register storage device to indicate information about a memory access request triggered by the fault accelerator encountering the address translation fault.

A hardware accelerator comprises accelerator processing circuitry to perform a delegated task on behalf of a processor; control interface circuitry to exchange control signals with the processor to configure the accelerator processing circuitry to perform the delegated task; fault status register storage to store fault status information, the fault status register storage being readable by the processor based on an accelerator register read request received from the processor via the control interface circuitry; and control circuitry to: detect a fault indication received from the processor via the control interface circuitry indicating that a faulting accelerator-triggered memory access request, issued via the control interface circuitry to the processor and specifying a target virtual address, has encountered an address translation fault; and in response to detecting the fault indication, set fault status information in the fault status register storage to indicate information about the faulting accelerator-triggered memory access request that encountered the address translation fault.

Computer-implemented methods and associated hardware for static trusted execution environment for inter-architecture processor program compatibility are disclosed herein. A device (e.g., a Reduced Instruction Set Computing-Five (RISC-V) device), may emulate a static trusted execution environment (e.g., ARM TrustZone) using physical memory protection (PMP). A regular world may have access to only a portion of an address space of the device, while a secure world may have access to the full address space. A secure world identifier (SWID) may be stored in a configuration status register (CSR) only accessible by a mode (e.g., machine mode). When an entry is added to a translation lookaside buffer (TLB), the SWID may be added as part of a tag to differentiate secure world entries from regular world entries.

The invention discloses a solid state disk key storage method and system and a storage medium, and belongs to the technical field of solid state disks. The method comprises the steps that a CPU component controls an SM4 component to generate a required medium key, and the medium key is temporarily stored in a register which cannot be read and written by the CPU component in the SM4 component; performing programming operation on the eFlash component through the eFlash controller component, and storing the medium key in an address specified by the key updating area; when the SM4 component detects that a programming operation completion indication signal is in a high level and key programming is successful, the SM4 component resets a medium key temporarily stored in the SM4 component and sets a key programming completion state register and a key programming success state register to be in a high level; and the CPU component performs storage verification, and when the CPU component queries that the secret key programming completion state register and the secret key programming success state register of the SM4 component are both high levels, secret key storage is completed. According to the invention, the medium key and the digital certificate cannot be stored out of the main control chip, so that the security is higher, and the key updating times are not limited.

Certain aspects of the present disclosure provide techniques for hardware-based saving and restoring of architecture state information for processing elements (PEs). According to certain aspects, the techniques involve triggering, via at least a first circuit element, saving of architecture state information of at least one processing element (PE) to at least one memory prior to the at least one PE transitioning from a first state to a second state; re-routing, via at least a second circuit element, requests to access the state registers to the architecture state RAM, while the at least one PE is in the second state; and triggering, via the first circuit element, restoration of the architecture state information from the at least one memory to the at least one PE prior to the at least one PE transitioning from the second state to the first state.

The invention relates to a remote stable upgrading method for FPGA firmware, belongs to the technical field of integrated circuits, and solves the problems of low efficiency, high hardware damage risk, poor universality and the like of the existing upgrading scheme. The method comprises the following steps that: an upper computer establishes connection with an FPGA (Field Programmable Gate Array) through a communication interface, and the FPGA enters a communication ready state; a built-in FLASH control module of the FPGA executes an erasing operation on a target storage area of the FLASH memory according to an erasing instruction sent by the upper computer, and the FPGA continuously reads and reports real-time state information of the state register to the upper computer during an erasing period; writing a to-be-upgraded firmware program package into the target area, and powering off and restarting the FPGA; and the restarted FPGA runs the new firmware program written into the target storage area. According to the method, the upgrading efficiency can be improved, the hardware damage risk is reduced, the upgrading cost is reduced, and the universality of the scheme is improved so as to adapt to FPGAs of different types and brands.

An integrated circuit (IC) device includes a plurality of chiplets including a first device and a second device. A die-to-die (D2D) interconnect link connects between the first device and the second device. A link training and status state machine (LTSSM) of the IC device is configured to operate the degraded D2D interconnect link in a resilient link mode to provide a plurality of enabled lanes and a plurality of disabled lanes. The LTSSM detects a faulty lane among the plurality of enabled lanes, and replaces the faulty lane using a functional lane from the plurality of disabled lanes to maintain the degraded D2D interconnect link.

System and methods for automatically generating control / status registers (CSR) based on configurations of components in a Network on Chip (NoC) include generating at least one repeatable field group from a plurality of defined fields, each of the plurality of defined fields defining portions of a register and NoC connectivity, generating at least one repeatable multi-register from the at least one repeatable field group, and generating at least one CSR group from the at least one repeatable multi-register, the at least one CSR group generated to be incorporated into a CSR bank. Such systems and methods of generating CSRs provides flexibility for designers / users to optimize the NoC for area consumption, reducing cost and complexity, parameterize configurations of the CSRs, and the like.

The invention provides a UCIe-based fault diagnosis and debugging method, a computer readable storage medium and an artificial intelligence chip, and relates to the technical field of chips. The UCIe-based fault diagnosis and debugging method comprises the following steps: carrying out link training between a first core particle and a second core particle; when a state execution error occurs, enabling a first pause state register of the first core particle to stop state jump of the first core particle; enabling a first bypass register of the first core particle to configure a first correction signal stored in the first bypass register; and disabling the first pause state register of the first core particle to continue the state jump of the first core particle. According to the UCIe-based fault diagnosis and debugging method, the computer readable storage medium and the artificial intelligence chip, effective chip debugging and fault diagnosis can be realized, and the post-silicon debugging efficiency can be improved.

The present application relates to an instruction buffer for a nested loop, and a processor. The processor comprises an instruction dispatch unit, a control status register, and a processing engine. The instruction buffer for a nested loop is configured to: acquire an instruction from the instruction dispatch unit; decode the instruction to acquire one or more total loop count indices respectively associated with one or more nested loops in the instruction; acquire from the control status register one or more total loop counts respectively associated with the one or more total loop count indices; and on the basis of the one or more total loop counts respectively associated with the one or more total loop count indices, send the one or more nested loops to the processing engine.

The invention discloses a PLC (Programmable Logic Controller) power failure data retention system based on a Linux memory mapping technology. The PLC power failure data retention system comprises a hardware subsystem and a software subsystem, the hardware subsystem comprises a CPU module for running a real-time Linux operating system; the power failure detection module is used for monitoring the voltage of an external power supply and triggering hardware interruption; the super capacitor power supply module is used for providing backup power after power failure; and the EMMC storage module is used for storing PLC key data. The software subsystem comprises a memory mapping driving module for mapping a physical space of the EMMC storage module to a system space to form a shared memory mapping area; the synchronization guarantee module is used for realizing lock-free synchronous access control by operating a state register; and the power failure control module responds to hardware interruption to start a data synchronization process. According to the system, lock-free synchronous access control between a user mode and a kernel mode is achieved through atomic bit flipping and exclusive-OR logic, it is ensured that a complete data block is synchronized to an EMMC storage module, the reliability problem of power-down data retention of a PLC system is solved, and the data synchronization efficiency and the system stability are improved.

Systems, methods, and apparatus for a memory system supporting low latency multi-cycle queue (MCQ) functionality. In a first aspect, a method performed by a host memory controller in a flash memory system includes storing response information as an entry in a completion queue based on a response received from a memory system coupled to a host device. The method includes updating an entry in a completion queue pointer register corresponding to the completion queue based on storage of the response information at the completion queue. The method includes clearing an entry in a complete queue interrupt state (CQIS) register, and issuing an MCQ event specific interrupt (ESI) to a processor core of the host device after clearing the entry in the CQIS register.

Systems or methods of the present disclosure may provide for analyzing or monitoring one or more frequencies of one or more clocks. For example, a clock analysis system includes a control register that stores a frequency indication for a first clock, and an edge counter and a window counter that count respective numbers of edges of the first clock and a second clock within a particular window. The clock analysis system also includes a status register that stores indications of the number of edges from the edge counter and the window counter. The clock analysis system further includes an application processor that determines a ratio between the number of edges of the first clock and the number of edges of the second clock, determines a frequency of the first clock based on the ratio, and transmits an indication of the frequency to a peripheral device for display.

Disclosed is an integrated circuit, IC (1), for switching regulation of switch mode drivers (2) of various driver topologies is provided. The IC (1) comprises a state machine (11) including a finite plurality of states (Sx). A quantity of the plurality of states (Sx) is adaptable to a designated driver topology (21) of the various driver topologies. A behavior of the plurality of states (Sx) is adaptable to the designated driver topology (21) via respective state registers (111) in terms of: at least one action (1111) being executed in the respective state, and at least one transition from the respective state to a subsequent state of the plurality of states (Sx) according to an associated stimulus. Its general suitability for various driver topologies renders the IC future-proof and long-lived.

The invention relates to a method and a device for managing LLC (Logical Link Control) resources. There is provided a method for managing LLC resources, comprising: receiving a memory mapping request from user mode software, the memory mapping request requesting to map a virtual memory address of the user mode software to a physical address of an LLC SRAM block; in response to the memory mapping request, allocating at least one LLC SRAM block from an LLC SRAM resource pool, where the LLC SRAM resource pool is a storage resource dynamically configured in an SRAM mode by configuring a first control state register in the LLC; establishing mapping from a virtual memory address of the user mode software to a physical address of the allocated LLC SRAM block, and configuring a page table item attribute of the mapping as a non-cache mode; and enabling the allocated LLC SRAM block by a second control state register.

The invention provides a DMA (Direct Memory Access) controller, a control method and a bridging chip. The controller comprises a PCIe (Peripheral Component Interconnect Express) splitting and combining processing module, a WDMA processing module, a control and state register, a doorbell processing module and a RapidIO splitting and combining processing module, the PCIe splitting and combining processing module is connected with the WDMA processing module and the control and state register; and the RapidIO splitting and combining processing module is connected with the WDMA processing module and the doorbell processing module. The WDMA processing module is used for reading to-be-sent data on the PCIe side, assembling a RapidIO write request according to the descriptor information, and sending the RapidIO write request to an opposite side device connected with the RapidIO controller; the control and state register is used for controlling behaviors of the WDMA processing module and storing necessary information; and the doorbell processing module is used for generating and sending a doorbell data packet and processing doorbell response. According to the scheme, the doorbell is automatically triggered after hardware finishes data migration, so that a plurality of links of software processing are omitted, the speed is higher, and the burden of a CPU (Central Processing Unit) is relieved.

Providing media power telemetry for virtual machines (VMs) in processor-based devices is disclosed herein. In one exemplary embodiment, a processor-based device provides a controller circuit comprising a power telemetry circuit, and a power management processor. The power telemetry circuit is configured to determine whether a media access request corresponding to a power telemetry event and directed to a media device is detected, and determine whether the media access request matches an event selection filter specified by an event selection control and status register (CSR) corresponding to the power telemetry event. If so, the power telemetry circuit increments a power telemetry counter corresponding to the power telemetry event by a relative power value associated with a media access request type of the media access request. The power management processor determines a power management operation based on the power telemetry counter corresponding to the power telemetry event, and applies the power management operation.

The application relates to an inter-cluster multi-task dynamic scheduling controller and method based on a reconfigurable computing array, which comprises a task sliding window unit configured to extract task information from a task queue to form a sliding window; a state register unit configured to receive and store real-time state information fed back by a plurality of reconfigurable array clusters; a scheduling control unit connected with the task sliding window unit and the state register unit respectively and configured to generate a scheduling decision according to the task information in the sliding window and the real-time state information of each reconfigurable array cluster; and a task distribution unit connected with the scheduling control unit and configured to receive a task instruction to be issued and the scheduling decision, modify a cluster addressing field in the task instruction according to target cluster information in the scheduling decision, and issue the modified task instruction to the reconfigurable array cluster indicated by the target cluster information, so as to solve the problem of waste of computing resources in the prior art.

Computer systems, service processing methods, and chips are provided in this disclosure. In one implementation, a computer system comprises an interrupt status register, a permission management register, a processor, a target storage space, and a memory storing programming instructions for execution by the processor to: set a flag corresponding to the first interrupt in the interrupt status register to a first interrupt flag and a flag corresponding to the first interrupt in the permission management register to a first call flag, wherein the first interrupt flag and the first call flag indicate whether access to the target storage space is allowed, determine whether to allow the processor to access the target storage space, and obtain first information in the target storage space in a TEE mode if determining that the processor is allowed to access the target storage space; and execute the target service based on the first information.

This application relates to dynamic status register arrays. An apparatus can include one or more memory dies coupled with a data bus. The apparatus can further include a controller coupled with each of the plurality of memory dies via the data bus, the controller configured to transmit a first command associated with a first operation to a first memory die. The first command can be an operation (e.g., the first operation) associated with an allocation of a queue slot of a status store associated with at least the first memory die. The controller can further transmit a second command to the first memory die to request a status of the first operation. The controller can receive the status of the first operation via a channel (e.g., a first channel) of the data bus based on the allocated queue slot of the status store.

An electronic device includes a debug port providing a communications interface for debugging purposes, a plurality of processing unit access ports, an authentication interface circuit configured to authenticate the external device, and a further access port coupled between the debug port and the authentication interface circuit. The further access port is configured to be in an open state in which communications are relayed between the debug port and the authentication interface circuit. The authentication interface circuit has registers including a status register capable of being read by the external device via the debug port and the further access port, the status register being configured to store an indication of the open or closed state of each of the processing unit access ports.

Aspects of the disclosure are directed to a side sideband interface (SSBI). The SSBI is a die-to-die (D2D) interface configured for various protocols to enable cross-die communication with higher robustness and flexibility and lower cost. The SSBI includes a control status register (CSR) wrapper containing the CSRs for configuring and monitoring the SSBI, a protocol handler for converting the various protocols both to and from a standard streaming interface as well as performing arbitration, and a link layer for performing serialization and deserialization of data as well as flow control management and error detection.

A low-area hardware architecture to execute the ASCON cipher suite and resist side-channel attacks that have a co-processor having controllers, register file, a permutation operably configured to receive input from a multiplexor structure and execute ASCON permutation, an ASCON state register that can be optionally removed and substituted by the register layer inside the permutation unit, and XOR logic gates that are operably configured to receive input from the register file and the permutation unit and provide input to the multiplexor structure.

The invention discloses a demodulation reference signal sequence generation method and device, equipment, a medium and a product. The method comprises the following steps: determining a current signal index and a current time slot index, and determining a current index number according to the current signal index and the current time slot index; querying a predetermined register data table according to the current index number, and determining a current first state register value and a current second state register value; according to the method, iterative calculation is performed according to the current value of the first state register and the current value of the second state register to obtain a preset number of pseudo-random sequence values, and the demodulation reference signal sequence is generated according to the preset number of pseudo-random sequence values, so that the problem of computing resource waste in the demodulation reference signal sequence generation process is solved, and the demodulation reference signal sequence generation efficiency is improved. The register data table is generated in advance, the first state register value and the second state register value are stored through the register data table, the state register value is rapidly obtained, multiple iterations are not needed, computing resources are saved, and the sequence generation speed is increased.

The application relates to the fields of integrated circuits and chip design, and provides a customized logic circuit and design method for peripheral interfaces, which comprises a clock generation module for generating clock signals required by different peripheral interface IPs according to a main clock signal; a synchronous reset module for generating reset signals required by different peripheral interface IPs according to a main reset signal; a self-defined register read-write module for connecting detection signals of the peripheral interface IPs to a state register, reading the state register through a bus, connecting control signals of the peripheral interface IPs to a to-be-configured register, and performing a configuration operation on the register inside the peripheral interface IP through the bus; and a parity check module for generating parity check codes on data links at outputs and inputs of the peripheral interface, and comparing the parity check codes. The application can save a chip design period and accelerate the integration time of a high-speed peripheral interface IP of an SoC chip.

Certain aspects of the present disclosure provide techniques for hardware-based saving and restoring of architecture state information for processing elements (PEs). According to certain aspects, the techniques involve triggering, via at least a first circuit element, saving of architecture state information of at least one processing element (PE) to at least one memory prior to the at least one PE transitioning from a first state to a second state; re-routing, via at least a second circuit element, requests to access the state registers to the architecture state RAM, while the at least one PE is in the second state; and triggering, via the first circuit element, restoration of the architecture state information from the at least one memory to the at least one PE prior to the at least one PE transitioning from the second state to the first state.