371 results about "Status register" patented technology

The invention relates to the technical field of servers, and discloses a method for executing a hot removal operation, a hot plug system, equipment, a medium and a product, which are used for acquiring target link identification information, target state indication information and position information of a target universal input / output interface unit. And determining a target output pin according to the identification information of the target communication link and the position information of the target general input / output interface unit. And changing the signal state of the level signal of the target output pin according to the target state indication information, and outputting the level signal to the target system control interruption pin. And when the target central processing unit is the main central processing unit, changing the numerical value in the target system control interrupt state register according to the signal state of the level signal. And when it is detected that the numerical value is the first preset numerical value, executing a heat removal operation on the target equipment. According to the method and the device, the hot removal operation of all types of peripheral interconnection component equipment can be realized, and the influence on the operation service of the server can be avoided.

The invention provides a DCU-based high-performance sparse stiffness matrix vector multiplication method, which comprises the following steps of: according to a sparse stiffness matrix, dividing a non-zero element into a plurality of calculation unit blocks by rows, pre-loading non-zero element data to an L1 shared memory or a register file through an on-chip shared memory controller of the DCU, a high-bandwidth crossbar switch of the DCU is used for realizing data copying and transmission; starting multi-row fusion execution for a short row of which the row non-zero element is lower than a DCU single-instruction multi-data width threshold value; constructing a wavefront scheduler based on a DCU asynchronous computing engine: binding an independent instruction cache region for each wavefront, and loading a multiply-add operation instruction set in advance through a prefetch instruction queue; a calculation unit state register is established, and when a wavefront scheduler ready signal is triggered, a scalar unit of the DCU is activated to execute calculation; and realizing cross-thread block reduction by adopting a DCU atomic operation accelerator. According to the method, the calculation throughput and the memory bandwidth utilization rate of large-scale structural mechanics stiffness matrix vector multiplication are effectively improved.

The invention discloses a hot plug control method, a hot plug system, a medium and a program product, and relates to the technical field of servers. A substrate management controller sends interrupt signal state information to a peripheral interconnection component slot corresponding to a target device based on an obtained trigger instruction of the target device; and the central processing unit determines a status bit numerical value of the interrupt status register based on the interrupt signal status information, and controls the target equipment to be in a hot plug state based on the status bit numerical value of the interrupt status register. Therefore, the hot plug state of the PCI device is controlled, the problem that the PCI device is replaced by manual physical disassembly after the server is shut down and powered off, and the service operation of the server is affected is solved, and the operation and maintenance cost of the server is reduced. Besides, interrupt signal state information sent to the peripheral interconnection component slot is regulated and controlled by using the substrate management controller, a general input and output chip does not need to be introduced, and the cost is reduced.

The invention provides an SIMT-based neural network processor and a task execution method thereof, and the method comprises the steps that a general processor queries a state register of a coprocessor, and the state register stores the resource condition of the coprocessor; the universal processor completes splitting from a thread block to a thread bundle according to the resource condition, and the universal processor forwards a thread bundle instruction to a thread bundle distributor of the coprocessor; and the thread beam distributor decodes instructions in the thread beams in sequence and schedules the instructions to instruction queues of different calculation cores, and the thread beams sequentially perform thread beam scheduling, instruction emission and instruction execution according to the sequence, so that all calculations of a neural network task are completed in parallel, and a running result of the neural network task is obtained. According to the method, a general processor for task splitting is introduced in front of the thread beam scheduler or a specific compiler is directly used, so that dynamic scheduling of the threads can be realized, and a scheme for dynamically expanding the number of the threads according to data precision becomes a feasible architecture option.

The embodiment of the invention discloses a test control method and device of a memory, a chip, equipment and a storage medium, the method is applied to a system control processor SCP, and the method comprises the following steps: responding to a starting operation of a system on chip of the chip, and starting the SCP; after a second-level boot loader of the SCP is executed, if it is detected that the power-on state register information is power-on starting information, whether memory self-test MBIST needs to be carried out in current starting or not is determined on the basis of test running field information in the nonvolatile memory; if MBIST needs to be carried out on the current starting, locking configuration of the test clock frequency is carried out on the phase-locked loop, and when locking succeeds, based on configured test link information, the MBIST device is controlled to carry out self-test on a target memory of the chip. Through the technical scheme of the embodiment of the invention, the memory test in the chip can be effectively controlled, so that the test resources are saved, and the memory test flexibility is improved.

The invention discloses an exception handling method and device for an embedded system, equipment and a storage medium, and relates to the technical field of embedding. The method comprises the steps of determining a current operation mode of a target processor according to a program state register of the target processor under the condition that abnormal codes appear in the operation process of the target processor in a target embedded system; according to the program state register, switching the current operation mode into a target operation mode, and obtaining a stack pointer value of a stack pointer register of the target processor in the target operation mode; and determining a target function address of a target function to which the abnormal code belongs and a call chain of the target function according to the stack pointer value. According to the technical scheme, the target function address is determined according to the stack pointer register, and before the target function address is determined, the target processor is switched to the target operation module and the interrupt is closed, so that interruption in the exception handling process can be effectively avoided, and the exception handling reliability can be improved.

The invention belongs to the field of many-core processor design, and particularly relates to a many-core processor system based on a data flow framework and a task scheduling method.The system comprises a system control node, computing nodes and storage nodes which are connected through an on-chip internet, and each storage node and at least one computing node form a computing cluster; the system control node sends an instruction and data to the storage node through the on-chip internet, and the storage node distributes the data to the computing nodes in the computing cluster; an initialization unit of the computing node monitors a data buffer area of the on-chip internet through a state register, data are moved to a buffer unit, and initialization of a computing core is completed; the scheduling unit is responsible for scheduling a task queue, and transferring data required by a next task to the cache unit in advance through the DMA unit to realize parallel calculation and data transferring; the computing unit executes the computing task, and the data directly flows among different computing nodes, so that the memory access requirement is reduced, and the computing resource utilization rate is improved.

The invention discloses a CAN message priority dynamic arbitration method and system based on event triggering, and the method comprises the steps: obtaining a discrete sampling signal of a CAN node of an engineering vehicle and a state register value of a CAN controller, converting the discrete sampling signal into a working condition data sequence, and obtaining a bus load rate through the state register value; obtaining an event state sequence according to the working condition data sequence; all CAN messages to be sent are constructed into a message data record, and the message data record with event semantics and dynamic priority labels is obtained according to the protocol data unit and the event state sequence; and according to the bus load rate and the event state sequence, sending a message data record with event semantics and dynamic priority annotations by adopting a token bucket mechanism through a three-level priority queue linked with a three-state state machine. According to the invention, the security key message in the system can still be transmitted in time under high load, and the bandwidth occupation and delay jitter caused by the low-priority message are avoided at the same time.

The invention discloses a notch position blade profile tolerance point taking device, system and method, and the method comprises the steps: enabling an actual measurement point cloud to be aligned with a theoretical model through progressive spatial registration, carrying out the initial coarse registration, and dynamically adjusting a root mean square error threshold value and a curvature change rate threshold value based on curvature sensitivity analysis, so as to achieve the self-adaptive segmented interruption control; a three-dimensional Hash mapping engine is constructed to store original point cloud data, an incremental data access mode and an iterative data structure are combined, a historical transformation matrix stack, a B spline control point and an 8-bit state register are included, and data processing integrity and high efficiency are ensured; a genetic algorithm is adopted to optimize segmented B-spline surface fitting, and contours of an air inlet edge and an air outlet edge are synchronously optimized through transverse segmentation and longitudinal segmentation; and finally, composite convergence verification is passed. According to the method, through dynamic threshold regulation and control and a hybrid optimization strategy, the detection precision and the calculation efficiency of the complex curved surface are remarkably improved.

The invention discloses a method for deploying a regular expression based on P4 in an intelligent network card / DPU. The method specifically comprises the following steps that the regular expression defined by a user is compiled into a finite-state machine; a matching table structure and a state register are defined in the P4 program and used for storing a state conversion rule of the regular expression, and a current matching state is recorded; and mapping a matching logic and a state register defined by the P4 into a hardware module of the intelligent network card / DPU, and realizing high-speed state conversion and matching by utilizing the parallel processing capability of the intelligent network card / DPU. According to the method for realizing regular expression matching based on P4 in the intelligent network card or the DPU, the regular expression is converted into the finite-state machine, and the programmability and the hardware acceleration capability of the P4 language are combined, so that the network flow detection and analysis efficiency is greatly improved, and the network flow detection and analysis efficiency is improved. And an effective solution is provided for next-generation network security and performance optimization.

The invention discloses a communication data security protection method and system based on an HSM module. Relates to the field of data security transmission, and aims to realize a high-security, high-performance and high-reliability data protection scheme, the method comprises the following steps: S1, an application processor is connected with an HSM module through a system bus, and the HSM module comprises a configuration register, a state register and a data register; s2, loading an SDK (Software Development Kit) by the application processor, wherein the SDK provides an application program interface for interacting with the HSM module; s3, receiving data to be encrypted, and transmitting the data to the HSM module through the API; s4, in the HSM module, initializing a state register, configuring an encryption mode, encrypting the data, and storing the encrypted data in a data register; and S5, the encrypted data is returned through the API. The method is suitable for secure data transmission in the fields of Internet of Things, cloud computing and the like, and an innovative solution is provided for sensitive information protection.

The invention discloses a sparse polynomial multiplication accelerator circuit applied to an HQC algorithm, and belongs to the field of post quantum cryptography algorithm hardware acceleration. Comprising a sparse polynomial non-zero coefficient index register set, a state register set, a multiplication and addition unit, a control state machine and an address generation module. The sparse polynomial non-zero coefficient index register set is used for storing indexes of sparse polynomial non-zero coefficients and providing the indexes for the control state machine, and the control state machine further inputs the obtained indexes to the address generation module; the state register group is used for configuring and representing the working state of the accelerator, storing information of registers and providing information for the address generation module and the control state machine; the address generation module is used for calculating address information and feeding back a result to the control state machine; and the control state machine reads the coefficient of the dense polynomial from the external RAM and inputs the coefficient into the multiplication and addition unit for calculation, and after the multiplication and addition unit completes calculation, the control state machine writes a calculation result into the external RAM.

The invention provides a realization device, a server and a realization method for hot removal of expansion equipment, and the method comprises the steps: responding to the starting of the server, and detecting a set value of an interrupt control option corresponding to each expansion slot by a basic input / output system; in response to the fact that the set value of the interrupt control option is detected to be enabled, setting a state value of a target pin of a universal input / output chip matched with the target expansion slot as a first preset value to trigger system interrupt; in response to the detection that the server enters the operating system, the operating system analyzes a target interrupt state register corresponding to the target expansion slot in the power management configuration protocol; if the target interrupt state register is a first preset value, triggering to execute a hot removal operation on the accessed target extension equipment. On the basis of physical connection between the GPIO chip and the interrupt signal line of the expansion slot, hot removal of the expansion equipment under an operating system is realized, the range of the equipment capable of being hot removed is expanded, and the reliability and the stability of a server are improved.

The invention discloses a data reading method based on an interrupt signal, a terminal, equipment and a storage medium, and the method comprises the steps that a vehicle-mounted controller executes a preset interrupt processing flow after receiving a preparation completion signal sent by an inertial measurement chip, and the preparation completion signal is an interrupt signal used for triggering the interrupt processing flow; the interrupt processing flow comprises the following steps: sending a data reading instruction to the inertial measurement chip, so that the inertial measurement chip feeds back currently stored synchronous measurement data; receiving synchronous measurement data; analyzing the received synchronous measurement data to obtain motion state data and storing the motion state data; and sending a reading and clearing instruction to the inertial measurement chip, so that an interrupt state register in the inertial measurement chip is cleared. According to the scheme, the real-time performance of acquiring the data from the inertial measurement chip can be improved.

The invention discloses a task allocation method, device and equipment and a readable storage medium, and the method comprises the steps: obtaining a to-be-processed task from a global task pool, and analyzing a descriptor of the to-be-processed task to obtain priority information and / or dependency information; determining a processing sequence of the to-be-processed tasks by utilizing the priority information and / or the dependency relationship information; obtaining channel load information from a state register for directly accessing the corresponding channel from the memory; and selecting a target channel from the channels by utilizing the channel load information and combining a load balancing strategy, and distributing the to-be-processed tasks to the target channel according to the processing sequence. According to the task allocation method and device, during task allocation, based on at least one of the priority information and the dependency relationship information and the channel load information, load balancing can be dynamically achieved, at least one of the priority and the dependency relationship of the task can be considered, and therefore the reliability of task processing is guaranteed, and the task allocation efficiency is improved. And different task scheduling requirements can be dynamically met.

The invention discloses an embedded SoC-level real-time monitoring and analyzing device. The embedded SoC-level real-time monitoring and analyzing device is composed of a bus comparator, a system event counter and a control register set. The bus comparator collects access signals of an address bus, a data bus and an instruction bus in real time, compares the access signals with a preset matching rule, generates a trigger signal for driving the event state register to record and output an interrupt signal or a debugging signal during matching, and takes the trigger signal as an input event of the system event counter; the system event counter monitors various events generated in the operation process, and when the monitoring result is equal to a preset reference value, a trigger signal is generated; and the control register group configures the matching condition of the bus comparator, sets the counting mode of the system event counter, and reads the comparison state, the event counting result and related monitoring information through the bus interface. According to the method, a configurable event capture mechanism and multiple counting modes are introduced in a hardware level, so that the dependence on software debugging is reduced, and the real-time performance of monitoring and analysis is improved.

The invention relates to the technical field of chip packaging, in particular to a PCIe (peripheral component interface express) equipment function number border crossing prevention method supporting ARI (automatic repeat interface). The hardware layer protection process is as follows: S1-1, hot plugging; s1-2, if it is detected that the equipment declarates to support ARI, the PCIe controller hardware circuit immediately sets an equipment number register to zero; s1-3, only allowing the PCIe controller of the system to read the configuration space unidirectionally during the low level period of the reset signal PERST #; the interception process of the driving layer is as follows: S2-1, in an equipment enumeration stage, an operating system drives to dynamically read an ARI capability register; s2-2, if the equipment declarates to support ARI, forcing an equipment number register to be equal to 0, and releasing an original equipment number bit space for function number expansion; s2-3, border crossing access is blocked; and S2-4, synchronizing the state register. Compared with the prior art, correctness of device function numbers is guaranteed through two dimensions of hardware register state solidification and driver layer access truncation, and'perception-free 'fault tolerance of the PCIe device under ARI / traditional mode switching is achieved for the first time.

A hardware accelerator includes accelerator processing circuitry to perform a delegated task on behalf of a processor; a control interface circuit to exchange control signals with the processor to configure the accelerator processing circuit to perform the delegated task; a fault state register storage device for storing fault state information, the fault state register storage device being readable by the processor based on an accelerator register read request received from the processor via the control interface circuit; and a control circuit to: detect a failure indication received from the processor via the control interface circuit, the failure indication indicating that a failure accelerator triggered memory access request issued to the processor via the control interface circuit and specifying a target virtual address has encountered an address translation failure; and in response to detecting the fault indication, setting fault state information in the fault state register storage device to indicate information about a memory access request triggered by the fault accelerator encountering the address translation fault.

An error correction code (ECC) test system and method are provided that test ECC logic for faults, preferably at power on before a workload is being processed. If the ECC logic fails the test, preferably an interrupt is issued indicating that the ECC logic is faulty and the corresponding ECC fault signature is reported in a status register of the system as part of a consolidated system report.

The invention belongs to the field of communication network fault detection, and particularly discloses an Ethernet physical layer line connection fault detection and positioning method and system, a storage medium and a product, and the method comprises the steps that a master station of the Ethernet sends Ethernet frames containing sequential addressing bits, each slave station processes the Ethernet frames in sequence according to a connection sequence, and the Ethernet frames are processed by the slave stations; meanwhile, sequentially addressing bits are progressively increased; each slave station detects a PHY chip clock frequency and a state register of the network port in real time; and when any slave station detects that the clock frequency of the PHY chip of the network port is reduced below a preset threshold value or the state register is link-down, judging that a disconnection fault occurs, returning the Ethernet frame to the master station from the network port of the corresponding slave station, and judging a disconnection position by the master station according to a sequential addressing bit of the received Ethernet frame. According to the method, the reliability and the response speed of disconnection detection are improved, disconnection detection can be triggered after the physical layer is disconnected under the condition of hybrid network topology communication, the disconnection position is positioned, and a network topology structure is reformed.

Systems, apparatuses, and methods related to a hypervisor status register in a computer processor are described. For example, a memory coupled to the computer processor can store instructions of routines of predefined, non-hierarchical domains. The computer processor can store a value in the hypervisor status register during a power up process of the computer system. The value stored in the hypervisor status register that identifies whether or not an operating hypervisor is present in the computer system. The computer processor can configure its operations (e.g., address translation) based on the value stored in the hypervisor status register.

A hardware accelerator comprises accelerator processing circuitry to perform a delegated task on behalf of a processor; control interface circuitry to exchange control signals with the processor to configure the accelerator processing circuitry to perform the delegated task; fault status register storage to store fault status information, the fault status register storage being readable by the processor based on an accelerator register read request received from the processor via the control interface circuitry; and control circuitry to: detect a fault indication received from the processor via the control interface circuitry indicating that a faulting accelerator-triggered memory access request, issued via the control interface circuitry to the processor and specifying a target virtual address, has encountered an address translation fault; and in response to detecting the fault indication, set fault status information in the fault status register storage to indicate information about the faulting accelerator-triggered memory access request that encountered the address translation fault.

Computer-implemented methods and associated hardware for static trusted execution environment for inter-architecture processor program compatibility are disclosed herein. A device (e.g., a Reduced Instruction Set Computing-Five (RISC-V) device), may emulate a static trusted execution environment (e.g., ARM TrustZone) using physical memory protection (PMP). A regular world may have access to only a portion of an address space of the device, while a secure world may have access to the full address space. A secure world identifier (SWID) may be stored in a configuration status register (CSR) only accessible by a mode (e.g., machine mode). When an entry is added to a translation lookaside buffer (TLB), the SWID may be added as part of a tag to differentiate secure world entries from regular world entries.

Providing media power telemetry for virtual machines (VMs) in processor-based devices is disclosed herein. In one exemplary embodiment, a processor-based device provides a controller circuit comprising a power telemetry circuit, and a power management processor. The power telemetry circuit is configured to determine whether a media access request corresponding to a power telemetry event and directed to a media device is detected, and determine whether the media access request matches an event selection filter specified by an event selection control and status register (CSR) corresponding to the power telemetry event. If so, the power telemetry circuit increments a power telemetry counter corresponding to the power telemetry event by a relative power value associated with a media access request type of the media access request. The power management processor determines a power management operation based on the power telemetry counter corresponding to the power telemetry event, and applies the power management operation.

The invention discloses a multi-task monitoring method of an embedded system, the embedded system and embedded equipment, relates to the technical field of embedded systems, and solves the technical problem that the operation of the embedded system is affected due to the fact that abnormal conditions of the system are difficult to find reliably. The method comprises the following steps: respectively setting a task state register and a maximum blocking timeout time register for a plurality of tasks; the method comprises the following steps of: dividing tasks into blocked tasks and non-blocked tasks, and performing state setting on a task state register and a maximum blocking timeout time register of each task; obtaining a task state register and a maximum blocking timeout time register of a blocking task and a non-blocking task; and judging whether each task is scheduled and operated or not, if so, clearing and resetting the task, and otherwise, restarting the task or resetting the embedded system for the task. According to the method, the abnormity of the non-blocking task and the abnormity of the blocking task can be monitored, the abnormal condition of the system can be conveniently and reliably found, and the reliability and the self-healing capability of the system are improved.

The invention discloses an instruction-driven coprocessor architecture design method for an in-memory computing platform of a high-performance magnetic memory. The instruction-driven coprocessor architecture design method comprises the following steps of: switching a magnetic memory into a normal mode or an in-memory computing mode by writing a corresponding operation code into a state register OP; the normal mode is used for the read-write function of a normal memory, and the in-memory calculation mode provides the function that the magnetic memory serves as a calculation unit; when the magnetic memory is used as a computing unit, the operation of in-memory computing consists of two memory access instructions, namely, an in-memory computing activation instruction and an in-memory computing address transmission instruction; the in-memory calculation activation instruction is used for activating an in-memory mode of the memory, and the in-memory calculation address transmission instruction is used for providing necessary control signals for in-memory calculation. On the premise that a memory protocol and an instruction set architecture are not changed, memory access and calculation instructions can be distinguished through the memory circuit with the changeable state, and the high-reliability, low-power-consumption and high-parallelism in-memory calculation architecture based on the magnetic memory is achieved.

A processor includes a register file and an execution unit. The execution unit includes a hash circuit including at least a state register, a state update circuit coupled to the state register, and a control circuit. Based on the hash instruction, the hash circuit receives a current state of the hash message from the register file and buffers the current state within the state register. The state update circuit executes a state update function on the content of the state register, where executing the state update function includes executing a plurality of iterative processing rounds on the content of the state register, and returning a result of each of the plurality of iterative processing rounds to the state register. The execution unit stores the content of the state register to the register file as an updated state of the message after completion of an iterative processing round of all of the plurality of iterative processing rounds.

A memory device includes CRC (cyclic redundance check) circuitry to detect CRC errors in write transactions. The CRC circuitry computes CRC for a data block to compare with CRC bits that were computed and sent by the memory controller. The memory device records the pass / fail status of write transactions in an error status register readable by the memory controller. The memory device can trigger the ALERT_n signal in response to an error.

Various embodiments of the present disclosure relate to the conditional execution of program code. In an example embodiment, a system including instruction fetch circuitry, decoder circuitry, and multi-condition branch circuitry is provided. The instruction fetch circuitry is configured to fetch a multi-condition branch instruction (MCBI) from memory. The MCBI identifies multiple status registers and multiple branch destinations. The multiple status registers of the MCBI are representative of registers which hold results of multiple condition evaluations, such that each status register corresponds to a different one of the multiple condition evaluations. Similarly, the multiple branch destinations of the MCBI also correspond to a different one of the multiple condition evaluations. The instruction fetch circuitry provides the MCBI to the decoder circuitry. In response, the decoder circuitry is configured to cause the multi-condition branch circuitry to execute the multi-condition branch instruction.

The embodiment of the invention relates to the technical field of integrated circuits, in particular to a system-level verification method and test system for an RISC-V reconfigurable multi-core processor chip, and the method comprises the steps: firstly, verifying a hardware state; the hardware state comprises core configuration of the reconfigurable multi-core processor, internal storage, interruption, states of a plurality of cores and configuration of a control state register; then, verifying the basic software; the verification of the basic software comprises the following steps of: lightening a chip of the reconfigurable multi-core processor, starting an operating system, and verifying bottom-layer driving software and a board-level support package; and finally, verifying cooperative work of the upper software and the multi-core chip software and hardware system. According to the system-level verification method provided by the embodiment of the invention, verification of a system-level peripheral scheme and verification of basic software adaptation are carried out on the RISC-V reconfigurable multi-core processor chip by simulating related hardware peripherals, and compatibility and continuous optimization between software and hardware are ensured.