29 results about "Status register" patented technology

The present application relates to an instruction buffer for a nested loop, and a processor. The processor comprises an instruction dispatch unit, a control status register, and a processing engine. The instruction buffer for a nested loop is configured to: acquire an instruction from the instruction dispatch unit; decode the instruction to acquire one or more total loop count indices respectively associated with one or more nested loops in the instruction; acquire from the control status register one or more total loop counts respectively associated with the one or more total loop count indices; and on the basis of the one or more total loop counts respectively associated with the one or more total loop count indices, send the one or more nested loops to the processing engine.

The application relates to an inter-cluster multi-task dynamic scheduling controller and method based on a reconfigurable computing array, which comprises a task sliding window unit configured to extract task information from a task queue to form a sliding window; a state register unit configured to receive and store real-time state information fed back by a plurality of reconfigurable array clusters; a scheduling control unit connected with the task sliding window unit and the state register unit respectively and configured to generate a scheduling decision according to the task information in the sliding window and the real-time state information of each reconfigurable array cluster; and a task distribution unit connected with the scheduling control unit and configured to receive a task instruction to be issued and the scheduling decision, modify a cluster addressing field in the task instruction according to target cluster information in the scheduling decision, and issue the modified task instruction to the reconfigurable array cluster indicated by the target cluster information, so as to solve the problem of waste of computing resources in the prior art.

Computer systems, service processing methods, and chips are provided in this disclosure. In one implementation, a computer system comprises an interrupt status register, a permission management register, a processor, a target storage space, and a memory storing programming instructions for execution by the processor to: set a flag corresponding to the first interrupt in the interrupt status register to a first interrupt flag and a flag corresponding to the first interrupt in the permission management register to a first call flag, wherein the first interrupt flag and the first call flag indicate whether access to the target storage space is allowed, determine whether to allow the processor to access the target storage space, and obtain first information in the target storage space in a TEE mode if determining that the processor is allowed to access the target storage space; and execute the target service based on the first information.

A low-area hardware architecture to execute the ASCON cipher suite and resist side-channel attacks that have a co-processor having controllers, register file, a permutation operably configured to receive input from a multiplexor structure and execute ASCON permutation, an ASCON state register that can be optionally removed and substituted by the register layer inside the permutation unit, and XOR logic gates that are operably configured to receive input from the register file and the permutation unit and provide input to the multiplexor structure.

A system and method for detecting abnormal program sequences on a memory device. In some examples, a timing process is initiated by either starting a timer or recording an initial timer value from the timer. A status register of the memory device is checked in response to initiating the timing process to determine whether the memory device is in a busy state corresponding to performing the program operation. The timer is stopped or a current timer value is recorded from the timer in response to determining that the memory device is not in the busy state. A determination is made to determine an elapsed time of the timer since being started or based on the initial and current timer values to provide a checked operation time. The checked operation time and the defined operation time are evaluated to determine whether the program sequence for implementing the program operation was abnormal.

This invention proposes a service-oriented architecture (SOA) braking system, braking method, computer program product, and vehicle. The braking system includes a controller, a state machine, and a brake actuator. The state machine is used to acquire SOA braking information sent by an external controller, switch the braking state corresponding to the SOA braking information, and store the braking control quantity in the SOA braking information into a state register corresponding to the braking state. The controller is used to read the braking control quantity stored in the corresponding state register according to the braking state indicated by the state machine, and generate a corresponding braking command based on the braking control quantity. The brake actuator is used to perform braking operations based on the braking command.

This invention discloses a multi-source sensing data fusion and event reasoning method based on edge computing and knowledge graphs, relating to the field of remote monitoring technology. The method includes the following steps: Step 1, synchronous acquisition of multi-source sensing data; Step 2, location semantic mapping and appliance operating status identification; Step 3, the edge gateway constructs a set of current observation facts based on the current functional area number, current area dwell time, appliance status register content, and the time interval to which the current timestamp belongs, determining the current event type and current event level; Step 4, the cloud server performs incremental updates to the home scene event knowledge graph based on event feedback records and distributes the updates to the edge gateway. This invention achieves three-dimensional fusion sensing of location information, electricity consumption behavior, and temporal context, possessing advantages such as strong privacy protection, good interpretability, and a response measure that matches the level of risk.

This application provides a method and apparatus for smoothing port failures. The method includes receiving a link state interruption event; reading the link state register of the physical layer chip that generated the link state interruption event; reading the fault type and the physical port where the link interruption occurred from the link state register; determining the fault type as a local link interruption, setting the logical operating state of the physical port to "off", clearing all Layer 2 MAC forwarding table entries with the physical port as the outgoing port, and updating the Layer 3 forwarding information base (FIB) table entry of the Layer 3 interface to which the physical port belongs; or, determining the fault type as a remote link interruption, recording at least the physical layer chip, the physical port, and its current detection count, and starting a software delay timer. This application is applicable to various IP networks and FTTR networks.

The serial bus data autonomous analysis controller belongs to the field of digital circuits. On the basis of the UART protocol IP core, the data autonomous analysis state machine is designed according to the serial bus data ICD. The serial bus data autonomous analysis controller controls the data autonomous analysis state machine to realize the switching of six states by periodically inquiring the state register and the data register of the UART protocol IP core, and simultaneously analyzes the serial data according to the bus data ICD and stores the serial data in the designated space for the processor to read. The data autonomous analysis state machine is designed according to the bus data ICD to solve the problem of large time cost of the processor in analyzing the serial data, realizes the autonomous analysis of the serial data, reduces the time cost of the processor in analyzing the serial data, significantly improves the processor efficiency, and can be widely applied to the industrial field.

An operating method of a processor includes: setting, according to a setting of a control and status register (CSR) included in a core, a designated register as a streaming pointer for transmitting and receiving data to and from a streaming accelerator, wherein the designated register is included in a general-purpose register file according to an instruction set architecture (ISA) of the core; and based on an instruction for the core either being a memory read instruction having the streaming pointer as a source register or being a memory write instruction having the streaming pointer as a destination register, performing either the memory read instruction or the memory write instruction by accessing an input first in first out (FIFO) buffer or an output FIFO buffer of the streaming accelerator.

A serial cipher register differential discriminator based on residual networks includes the following steps: 1) Dataset generation: For serial cipher algorithms, training samples containing fixed differences (label 1) and random differences (label 0) are generated. The data is loaded into the state register using the key and initialization vector, and after a warm-up round, concatenated input data of length 2M is generated; 2) Feature extraction and preprocessing: Linear transformation and batch normalization are performed using embedding layers to reshape the data into a format suitable for convolutional processing, and initial features are extracted using a 1D convolutional neural network; 3) Residual network architecture: Multi-layer residual blocks are designed, employing different dilation rates (2 for odd positions and 1 for even positions) to capture multi-scale contextual information, supporting 1-10 configurable residual blocks; 4) Classification prediction: Binary classification is achieved through adaptive average pooling, fully connected layers, and the Softmax activation function, with a threshold of 0.51 used to determine true differences and random differences.

The application discloses a multi-protocol streaming data code-free automatic identification and adaptive storage method, which is based on three indexes of feature code matching degree, CRC check confidence and channel quality factor for multi-protocol automatic identification through joint determination, and simultaneously outputs a protocol attribute label; the adaptive plug-in generation is generated through code-free rule configuration and template engine driving based on a Web visual platform; software adaptation of information exchange between a flow control subunit and a thread scheduling subunit through a shared state register; threefold verification with cross-layer quality feedback, wherein downstream error modes are fed back to upstream interception in advance through a feedback channel, and a global scheduler dynamically adjusts batch size according to a pass rate; multi-dimensional layered storage based on linkage of the protocol attribute label, wherein a migration score is determined by comprehensively considering time length, access frequency and protocol attributes. The application is suitable for reliable identification, efficient processing and differentiated storage of multi-protocol streaming data in an industrial scene.

This invention discloses a hardware circuit supporting SM3 encryption, relating to the field of information security cryptography. It includes a register configuration component, an initialization and update component, and an SM3 hash calculation component integrated at the top layer of the chip and interconnected in pairs. The register configuration component includes a message register, an IV value setting register, a status register, a hash result register, and an SM3 control register. The register configuration component is connected to the CPU via a CPU_IF interface, through which the CPU performs read and write operations on each register. The initialization and update component receives the message data to be encrypted from the message register and the IV value from the IV value setting register, packages the received IV value as the initial IV value and the message data to be encrypted, and forwards it to the SM3 hash calculation component. The SM3 hash calculation component calculates the hash value based on the message data and the IV value, performs endianness conversion, and sends the hash result back to the hash result register. This invention enhances the overall security and computational speed of the chip system.

Methods and apparatuses are provided that can establish data links with greater bandwidths within die-to-die interconnect architectures. In one example, a system-on-a-chip (SoC) includes an error status register, a plurality of data ports for a data link, and a processor electrically coupled to the error status register and to the plurality of data ports. The processor can receive error data from the error status register and, based on the error data, can determine a portion of the plurality of data ports that are error free. Further, the processor can determine a bandwidth for the data link based on the portion of the plurality of data ports that are error free. Further, the processor can initiate a link negotiation process to establish the link with another device based on the link width value and the portion of the plurality of data ports that are error free.

This invention discloses a low-resource AES encryption system and method based on heterogeneous computing, belonging to the field of information security hardware acceleration technology. Based on the traditional AES algorithm, a fixed-round multiplexing control module and an external dedicated XOR circuit are introduced. The fixed-round multiplexing control module sequentially executes SubBytes and ShiftRows transformations within the FPGA. By employing in-round operation multiplexing and state register sharing, high-level reuse of logic resources is achieved, significantly reducing the FPGA's lookup table usage. By decomposing the MixColumns operation into a two-stage pipeline structure of internal FPGA xtime transformation and external XOR circuit, and using an external 74LVC574 register to synchronize the data path in real time, precise matching of computational latency and area optimization are achieved. This system implements secure and reliable AES encryption with limited hardware resources. Combined with a dynamic masking mechanism, effective protection of intermediate states is achieved, significantly enhancing the system's resistance to side-channel attacks and reducing hardware costs and resource overhead while ensuring throughput.

A processing device (20) has a processor (200) including a plurality of delay push processor registers (214) and a processor register control circuit (220, 222, 224, 226, 228). The processor register control circuit (220, 222, 224, 226, 228) includes a plurality of status registers (226), each status register (226) corresponding to a respective different delay push register (214). The processor register control circuit (220, 222, 224, 226, 228) is configured to detect a write of a new value to a register (214) in the delay push registers (214) and determine whether a status register (226) of the delay push register (214) has a first value indicating an unsaved state of the delay push register (214). The processor control circuit (220, 222, 224, 226, 228) is configured, when the status register (226) has the first value, to read a current value from the delay push register (214) before completion of the write of the new value to the delay push register (214), write the current value to a memory (202), and set the status register (226) of the delay push register (214) to a second value indicating a saved state of the delay push register (214).

The application discloses a BIOS offline recovery method based on U disk control, and aims to solve the problem that a system cannot be started due to BIOS damage. The method comprises the following steps: after a micro control unit detects BIOS startup timeout, the micro control unit controls a power indicator to flicker to prompt an exception, and adjusts a detection frequency through an SPI response stability evaluation model; when the SPI response is stable and a U disk is connected, a BIOS recovery image stream in a compressed format is read from the U disk, and a cache area is divided according to image header metadata; a data test packet is sent to a BIOS Flash ROM to evaluate data loading performance, and the size of a data block after decompression is determined; in the decompression and writing process, a synchronization delay parameter is calculated according to a chip response timestamp sequence, and a writing delay interval is dynamically adjusted; finally, after a file checksum is matched and a state register returns a writing completion signal, system reset is triggered to complete recovery. The application realizes the offline and automatic recovery of BIOS, and improves stability and efficiency.

This invention discloses a data prefetching method, product, device, and medium based on multiple memory access patterns, relating to the field of computer architecture technology. The method includes: monitoring for L2 cache memory access miss events in the processor; if the miss status register hits the event, splitting the miss address to obtain the base address of the spatial region and the offset address within the region. When the program counter pattern training table hits the base address, stride and spatiotemporal pattern training is performed on the offset address to obtain a fixed stride, space / time related access pattern. Valid memory access patterns are filtered by confidence level and stored in the corresponding LLC pattern table, with an index recorded in the prefetch pattern record table. Subsequently, based on the memory access miss event and index information, the target pattern is read from the corresponding pattern table to calculate the prefetch address, generate a request, and execute the prefetch. Through this scheme, it is possible to adapt to multiple scenarios and accurately identify memory access patterns for more precise data prefetching.

The present application provides an apparatus and method for implementing hot removal of an expansion device, and a server. The method comprises: in response to server startup, a basic input / output system detecting a setting value of an interrupt control option corresponding to each expansion slot; in response to detecting that the setting value of an interrupt control option is enabled, setting a state value of a target pin of a general-purpose input / output chip matching a target expansion slot to a first preset value to trigger a system interrupt; in response to detecting that a server has entered an operating system, the operating system parsing a target interrupt status register in a power management configuration protocol and corresponding to the target expansion slot; and when the target interrupt status register is at the first preset value, triggering the execution of a hot removal operation on a connected target expansion device.

A fault detection system includes a state register, an error detection code (EDC) register, logic circuitry, an EDC generator, and an EDC checker. The state and EDC registers store first reference data and first checksum data, respectively. The logic circuitry executes a logic function based on the first reference data to iteratively generate second reference data that is different from the first reference data, and updates the first reference data of the state register with the second reference data of one iteration. The EDC generator iteratively generates second checksum data based on the iteratively generated second reference data and updates the first checksum data of the EDC register with the second checksum data of one iteration. The EDC checker detects a fault in the IC based on the updated first reference data and the updated first checksum data.

The application provides a method, device, terminal and medium for optimizing a fault diagnosis log collection process, and belongs to the technical field of server log collection.The method steps are as follows: S1.BMC pre-maintains a mapping file of a mapping relationship between device asset information and a state register; S2.BMC records downtime after detecting a set error register, informs an ACD tool to collect state register information, and records a collection completion time; S3.BMC informs a BAFI tool to analyze fault device information and error type information, records an analysis completion time after the analysis is completed, and records and informs a user to collect fault diagnosis logs when the fault device information is located.The application realizes accurate acquisition of the time used in each stage in a fault diagnosis process, a simple and fast fault analysis process, and can prompt after the analysis is completed and realize separate collection of fault diagnosis logs.

The application provides a terminal device charging mode switching control method and device, equipment and storage medium, the method is applied to the terminal device with charging input and reverse power supply function, the terminal includes application processor, microcontroller and notification control circuit connected with both, the circuit is provided with first and second two notification channels, respectively connecting the non-maskable interrupt pin and general pin of application processor. In the above method, the microcontroller is responsible for the device type and working mode identification when the external device is connected; when the first type of emergency event is identified, the non-maskable wake-up interrupt signal is sent to the application processor through the first channel, and the application processor is forced to wake up for processing; when the second type of ordinary state event is identified, the state update signal is sent to the application processor through the second channel, and the signal only updates the state register without triggering the interrupt to wake up the application processor in sleep.

This application provides a method, apparatus, device, and storage medium for self-destruction of NOR flash chip data, applied in the field of non-volatile memory device technology. By configuring a mode status bit in the volatile status register of the non-volatile memory device, and based on the actual destruction mode indicated by the mode status bit, upon receiving a self-destruct trigger command, data erasure operations are preferentially performed on a predefined priority destruction area. Subsequently, an erasure control signal is generated for the remaining areas for subsequent erasure. After all erasure operations are completed, the non-volatile memory device is placed in a shielded and locked state. In this state, the read interface responds to read requests by outputting preset mask data, and the device is prohibited from executing the normal boot process. This method has the advantage of preventing any form of data recovery and chip reuse, greatly improving the data security of the NOR flash chip and effectively resisting the risks of physical attacks and information leakage.

The embodiment of the application discloses a processor chip and a register state value acquisition method, relates to the technical field of integrated circuits, and is invented to improve the accuracy of analyzing the change of the processor chip system in the whole process of the processor chip problem and to improve the performance of the processor chip. The processor chip comprises a control unit configured to configure the identification of a target state register and a comparison mode; a state value acquisition unit connected with the control unit; the state value acquisition unit is configured to acquire the state value in the target state register at multiple time points in sequence according to the identification of the target state register; a comparison unit connected with the control unit and the state value acquisition unit respectively, configured to determine whether to send the state value at the multiple time points to a first-in first-out storage unit in sequence according to the comparison mode; and a first-in first-out storage unit connected with the comparison unit, configured to receive the state value sent by the comparison unit and store the state value. The application is suitable for processing data.

The application discloses a storage body self-test system and method with extensible programming, which comprises the following steps: a CPU is connected to a configurable storage body test controller through a CPU configuration interface and a configuration bus for bidirectional transmission of configuration instructions and parameters; the configurable storage body test controller is connected to each group of SRAM and ROM through a storage body access bus; test results of the measured storage body are written into a state register through an internal bus, and the state register is connected to a CPU data reading port for output; a fault signal output end of the configurable storage body test controller is connected to an interrupt module, and the interrupt module sends an interrupt request to the CPU; and an ATE test multiplexing interface reserved in the configurable storage body test controller is directly connected to MBIST logic of chip factory test for multiplexing. The method is implemented based on the system. The application has the advantages of simple principle, lower cost, better responsiveness, stronger compatibility, wider application range and the like.

This invention relates to the field of industrial data acquisition and edge network technology, and discloses a data acquisition method for an automatic grease-adding system based on edge computing. This method establishes a node mapping table in the edge control unit, generates a global interlocking signal by comparing the real-time current of the main circuit with a threshold, and dynamically switches the polling frequency of the underlying bus. When the value of the underlying status register deviates from the interlocking signal, a time window anti-jitter mechanism based on time difference is introduced to filter out missynchronization caused by physical transmission delay. Furthermore, the edge unit implements read-write decoupling; read requests achieve a through-response based on the mapping table, and write requests are stored in a write buffer queue after acceptance evaluation. When the interlocking signal undergoes a state switch due to a physical abrupt change, the system forcibly locks the queue and suspends writing, prioritizing high-frequency status polling. This invention effectively eliminates read-write collisions caused by network latency, thereby improving the data consistency and operational security of the system under complex operating conditions.

This invention discloses a method for remote hardware debugging and analysis of a server, relating to the field of server hardware management. The method includes: connecting the hardware signal to be debugged and analyzed in the server to a CPLD (Content Processing LD) and mapping it to a hardware status register array; establishing a communication connection between the BMC (Browser Control Center) and the CPLD via a first communication bus and sending a hardware status query configuration command to the CPLD; obtaining the hardware signal level status stored in the corresponding hardware status register from the CPLD via the first communication bus according to the query mode; and presenting the obtained level status through a web interface for remote debugging and analysis. This application solves the problems of existing server hardware signal debugging, such as the inability to remotely implement the process and the difficulty in efficiently acquiring multiple signals in batches and performing long-term continuous analysis. It achieves the effects of remote debugging and monitoring of server hardware signals, efficient batch acquisition of multiple hardware signals, and support for long-term continuous sampling and backtracking analysis.

A low-area hardware architecture to execute the ASCON cipher suite and resist side-channel attacks that have a co-processor having controllers, register file, a permutation operably configured to receive input from a multiplexor structure and execute ASCON permutation, an ASCON state register that can be optionally removed and substituted by the register layer inside the permutation unit, and XOR logic gates that are operably configured to receive input from the register file and the permutation unit and provide input to the multiplexor structure.

This invention relates to the field of industrial control security and discloses an industrial control vulnerability repair system based on dynamic node upgrades. The system includes: a data flow parsing unit that acquires the scan cycle status register data of the industrial control node; a patch segmentation unit that parses the target vulnerability function to extract security patch instruction blocks and decomposes the security patch instruction blocks into instruction fragments carrying timing dependency attributes; a timing scheduling unit that identifies the communication idle window period at the end of the control loop and calculates the remaining residence time; and a memory mapping takeover unit that, when the remaining residence time meets the processing time quota, loads the instruction fragments into a reserved memory isolation area and modifies the entry address pointer of the target vulnerability function. This invention utilizes a fragmented injection mechanism to eliminate the interference of vulnerability repair on the continuity of industrial control services, avoids control interruptions caused by restart upgrades, and ensures the steady-state operation of production processes in harsh industrial environments.